1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
9 #include <linux/iopoll.h>
10
11 #include "dsi_phy.h"
12 #include "dsi.xml.h"
13 #include "dsi_phy_10nm.xml.h"
14
15 /*
16 * DSI PLL 10nm - clock diagram (eg: DSI0):
17 *
18 * dsi0_pll_out_div_clk dsi0_pll_bit_clk
19 * | |
20 * | |
21 * +---------+ | +----------+ | +----+
22 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
23 * +---------+ | +----------+ | +----+
24 * | |
25 * | | dsi0_pll_by_2_bit_clk
26 * | | |
27 * | | +----+ | |\ dsi0_pclk_mux
28 * | |--| /2 |--o--| \ |
29 * | | +----+ | \ | +---------+
30 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
31 * |------------------------------| / +---------+
32 * | +-----+ | /
33 * -----------| /4? |--o----------|/
34 * +-----+ | |
35 * | |dsiclk_sel
36 * |
37 * dsi0_pll_post_out_div_clk
38 */
39
40 #define VCO_REF_CLK_RATE 19200000
41 #define FRAC_BITS 18
42
43 /* v3.0.0 10nm implementation that requires the old timings settings */
44 #define DSI_PHY_10NM_QUIRK_OLD_TIMINGS BIT(0)
45
46 struct dsi_pll_config {
47 bool enable_ssc;
48 bool ssc_center;
49 u32 ssc_freq;
50 u32 ssc_offset;
51 u32 ssc_adj_per;
52
53 /* out */
54 u32 pll_prop_gain_rate;
55 u32 decimal_div_start;
56 u32 frac_div_start;
57 u32 pll_clock_inverters;
58 u32 ssc_stepsize;
59 u32 ssc_div_per;
60 };
61
62 struct pll_10nm_cached_state {
63 unsigned long vco_rate;
64 u8 bit_clk_div;
65 u8 pix_clk_div;
66 u8 pll_out_div;
67 u8 pll_mux;
68 };
69
70 struct dsi_pll_10nm {
71 struct clk_hw clk_hw;
72
73 struct msm_dsi_phy *phy;
74
75 u64 vco_current_rate;
76
77 /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
78 spinlock_t postdiv_lock;
79
80 struct pll_10nm_cached_state cached_state;
81
82 struct dsi_pll_10nm *slave;
83 };
84
85 #define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, clk_hw)
86
87 /**
88 * struct dsi_phy_10nm_tuning_cfg - Holds 10nm PHY tuning config parameters.
89 * @rescode_offset_top: Offset for pull-up legs rescode.
90 * @rescode_offset_bot: Offset for pull-down legs rescode.
91 * @vreg_ctrl: vreg ctrl to drive LDO level
92 */
93 struct dsi_phy_10nm_tuning_cfg {
94 u8 rescode_offset_top[DSI_LANE_MAX];
95 u8 rescode_offset_bot[DSI_LANE_MAX];
96 u8 vreg_ctrl;
97 };
98
99 /*
100 * Global list of private DSI PLL struct pointers. We need this for bonded DSI
101 * mode, where the master PLL's clk_ops needs access the slave's private data
102 */
103 static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX];
104
dsi_pll_setup_config(struct dsi_pll_config * config)105 static void dsi_pll_setup_config(struct dsi_pll_config *config)
106 {
107 config->ssc_freq = 31500;
108 config->ssc_offset = 5000;
109 config->ssc_adj_per = 2;
110
111 config->enable_ssc = false;
112 config->ssc_center = false;
113 }
114
dsi_pll_calc_dec_frac(struct dsi_pll_10nm * pll,struct dsi_pll_config * config)115 static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
116 {
117 u64 fref = VCO_REF_CLK_RATE;
118 u64 pll_freq;
119 u64 divider;
120 u64 dec, dec_multiple;
121 u32 frac;
122 u64 multiplier;
123
124 pll_freq = pll->vco_current_rate;
125
126 divider = fref * 2;
127
128 multiplier = 1 << FRAC_BITS;
129 dec_multiple = div_u64(pll_freq * multiplier, divider);
130 dec = div_u64_rem(dec_multiple, multiplier, &frac);
131
132 if (pll_freq <= 1900000000UL)
133 config->pll_prop_gain_rate = 8;
134 else if (pll_freq <= 3000000000UL)
135 config->pll_prop_gain_rate = 10;
136 else
137 config->pll_prop_gain_rate = 12;
138 if (pll_freq < 1100000000UL)
139 config->pll_clock_inverters = 8;
140 else
141 config->pll_clock_inverters = 0;
142
143 config->decimal_div_start = dec;
144 config->frac_div_start = frac;
145 }
146
147 #define SSC_CENTER BIT(0)
148 #define SSC_EN BIT(1)
149
dsi_pll_calc_ssc(struct dsi_pll_10nm * pll,struct dsi_pll_config * config)150 static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
151 {
152 u32 ssc_per;
153 u32 ssc_mod;
154 u64 ssc_step_size;
155 u64 frac;
156
157 if (!config->enable_ssc) {
158 DBG("SSC not enabled\n");
159 return;
160 }
161
162 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1;
163 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
164 ssc_per -= ssc_mod;
165
166 frac = config->frac_div_start;
167 ssc_step_size = config->decimal_div_start;
168 ssc_step_size *= (1 << FRAC_BITS);
169 ssc_step_size += frac;
170 ssc_step_size *= config->ssc_offset;
171 ssc_step_size *= (config->ssc_adj_per + 1);
172 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
173 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
174
175 config->ssc_div_per = ssc_per;
176 config->ssc_stepsize = ssc_step_size;
177
178 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
179 config->decimal_div_start, frac, FRAC_BITS);
180 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
181 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
182 }
183
dsi_pll_ssc_commit(struct dsi_pll_10nm * pll,struct dsi_pll_config * config)184 static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
185 {
186 void __iomem *base = pll->phy->pll_base;
187
188 if (config->enable_ssc) {
189 pr_debug("SSC is enabled\n");
190
191 writel(config->ssc_stepsize & 0xff,
192 base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1);
193 writel(config->ssc_stepsize >> 8,
194 base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1);
195 writel(config->ssc_div_per & 0xff,
196 base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1);
197 writel(config->ssc_div_per >> 8,
198 base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1);
199 writel(config->ssc_adj_per & 0xff,
200 base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1);
201 writel(config->ssc_adj_per >> 8,
202 base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1);
203 writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0),
204 base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL);
205 }
206 }
207
dsi_pll_config_hzindep_reg(struct dsi_pll_10nm * pll)208 static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
209 {
210 void __iomem *base = pll->phy->pll_base;
211
212 writel(0x80, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE);
213 writel(0x03, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO);
214 writel(0x00, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE);
215 writel(0x00, base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER);
216 writel(0x4e, base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER);
217 writel(0x40, base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS);
218 writel(0xba, base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE);
219 writel(0x0c, base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE);
220 writel(0x00, base + REG_DSI_10nm_PHY_PLL_OUTDIV);
221 writel(0x00, base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE);
222 writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO);
223 writel(0x08, base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1);
224 writel(0xc0, base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1);
225 writel(0xfa, base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1);
226 writel(0x4c, base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1);
227 writel(0x80, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE);
228 writel(0x29, base + REG_DSI_10nm_PHY_PLL_PFILT);
229 writel(0x3f, base + REG_DSI_10nm_PHY_PLL_IFILT);
230 }
231
dsi_pll_commit(struct dsi_pll_10nm * pll,struct dsi_pll_config * config)232 static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config)
233 {
234 void __iomem *base = pll->phy->pll_base;
235
236 writel(0x12, base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE);
237 writel(config->decimal_div_start,
238 base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
239 writel(config->frac_div_start & 0xff,
240 base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
241 writel((config->frac_div_start & 0xff00) >> 8,
242 base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1);
243 writel((config->frac_div_start & 0x30000) >> 16,
244 base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1);
245 writel(64, base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1);
246 writel(0x06, base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY);
247 writel(0x10, base + REG_DSI_10nm_PHY_PLL_CMODE);
248 writel(config->pll_clock_inverters, base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS);
249 }
250
dsi_pll_10nm_vco_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)251 static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
252 unsigned long parent_rate)
253 {
254 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
255 struct dsi_pll_config config;
256
257 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->phy->id, rate,
258 parent_rate);
259
260 pll_10nm->vco_current_rate = rate;
261
262 dsi_pll_setup_config(&config);
263
264 dsi_pll_calc_dec_frac(pll_10nm, &config);
265
266 dsi_pll_calc_ssc(pll_10nm, &config);
267
268 dsi_pll_commit(pll_10nm, &config);
269
270 dsi_pll_config_hzindep_reg(pll_10nm);
271
272 dsi_pll_ssc_commit(pll_10nm, &config);
273
274 /* flush, ensure all register writes are done*/
275 wmb();
276
277 return 0;
278 }
279
dsi_pll_10nm_lock_status(struct dsi_pll_10nm * pll)280 static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
281 {
282 struct device *dev = &pll->phy->pdev->dev;
283 int rc;
284 u32 status = 0;
285 u32 const delay_us = 100;
286 u32 const timeout_us = 5000;
287
288 rc = readl_poll_timeout_atomic(pll->phy->pll_base +
289 REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE,
290 status,
291 ((status & BIT(0)) > 0),
292 delay_us,
293 timeout_us);
294 if (rc)
295 DRM_DEV_ERROR(dev, "DSI PLL(%d) lock failed, status=0x%08x\n",
296 pll->phy->id, status);
297
298 return rc;
299 }
300
dsi_pll_disable_pll_bias(struct dsi_pll_10nm * pll)301 static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
302 {
303 u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
304
305 writel(0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
306 writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
307 ndelay(250);
308 }
309
dsi_pll_enable_pll_bias(struct dsi_pll_10nm * pll)310 static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
311 {
312 u32 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
313
314 writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CTRL_0);
315 writel(0xc0, pll->phy->pll_base + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES);
316 ndelay(250);
317 }
318
dsi_pll_disable_global_clk(struct dsi_pll_10nm * pll)319 static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
320 {
321 u32 data;
322
323 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
324 writel(data & ~BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
325 }
326
dsi_pll_enable_global_clk(struct dsi_pll_10nm * pll)327 static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
328 {
329 u32 data;
330
331 data = readl(pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
332 writel(data | BIT(5), pll->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
333 }
334
dsi_pll_10nm_vco_prepare(struct clk_hw * hw)335 static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
336 {
337 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
338 struct device *dev = &pll_10nm->phy->pdev->dev;
339 int rc;
340
341 dsi_pll_enable_pll_bias(pll_10nm);
342 if (pll_10nm->slave)
343 dsi_pll_enable_pll_bias(pll_10nm->slave);
344
345 rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
346 if (rc) {
347 DRM_DEV_ERROR(dev, "vco_set_rate failed, rc=%d\n", rc);
348 return rc;
349 }
350
351 /* Start PLL */
352 writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
353
354 /*
355 * ensure all PLL configurations are written prior to checking
356 * for PLL lock.
357 */
358 wmb();
359
360 /* Check for PLL lock */
361 rc = dsi_pll_10nm_lock_status(pll_10nm);
362 if (rc) {
363 DRM_DEV_ERROR(dev, "PLL(%d) lock failed\n", pll_10nm->phy->id);
364 goto error;
365 }
366
367 pll_10nm->phy->pll_on = true;
368
369 dsi_pll_enable_global_clk(pll_10nm);
370 if (pll_10nm->slave)
371 dsi_pll_enable_global_clk(pll_10nm->slave);
372
373 writel(0x01, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
374 if (pll_10nm->slave)
375 writel(0x01, pll_10nm->slave->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
376
377 error:
378 return rc;
379 }
380
dsi_pll_disable_sub(struct dsi_pll_10nm * pll)381 static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
382 {
383 writel(0, pll->phy->base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
384 dsi_pll_disable_pll_bias(pll);
385 }
386
dsi_pll_10nm_vco_unprepare(struct clk_hw * hw)387 static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
388 {
389 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
390
391 /*
392 * To avoid any stray glitches while abruptly powering down the PLL
393 * make sure to gate the clock using the clock enable bit before
394 * powering down the PLL
395 */
396 dsi_pll_disable_global_clk(pll_10nm);
397 writel(0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
398 dsi_pll_disable_sub(pll_10nm);
399 if (pll_10nm->slave) {
400 dsi_pll_disable_global_clk(pll_10nm->slave);
401 dsi_pll_disable_sub(pll_10nm->slave);
402 }
403 /* flush, ensure all register writes are done */
404 wmb();
405 pll_10nm->phy->pll_on = false;
406 }
407
dsi_pll_10nm_vco_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)408 static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
409 unsigned long parent_rate)
410 {
411 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
412 void __iomem *base = pll_10nm->phy->pll_base;
413 u64 ref_clk = VCO_REF_CLK_RATE;
414 u64 vco_rate = 0x0;
415 u64 multiplier;
416 u32 frac;
417 u32 dec;
418 u64 pll_freq, tmp64;
419
420 dec = readl(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
421 dec &= 0xff;
422
423 frac = readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
424 frac |= ((readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
425 0xff) << 8);
426 frac |= ((readl(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
427 0x3) << 16);
428
429 /*
430 * TODO:
431 * 1. Assumes prescaler is disabled
432 */
433 multiplier = 1 << FRAC_BITS;
434 pll_freq = dec * (ref_clk * 2);
435 tmp64 = (ref_clk * 2 * frac);
436 pll_freq += div_u64(tmp64, multiplier);
437
438 vco_rate = pll_freq;
439 pll_10nm->vco_current_rate = vco_rate;
440
441 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
442 pll_10nm->phy->id, (unsigned long)vco_rate, dec, frac);
443
444 return (unsigned long)vco_rate;
445 }
446
dsi_pll_10nm_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)447 static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
448 unsigned long rate, unsigned long *parent_rate)
449 {
450 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
451
452 if (rate < pll_10nm->phy->cfg->min_pll_rate)
453 return pll_10nm->phy->cfg->min_pll_rate;
454 else if (rate > pll_10nm->phy->cfg->max_pll_rate)
455 return pll_10nm->phy->cfg->max_pll_rate;
456 else
457 return rate;
458 }
459
460 static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
461 .round_rate = dsi_pll_10nm_clk_round_rate,
462 .set_rate = dsi_pll_10nm_vco_set_rate,
463 .recalc_rate = dsi_pll_10nm_vco_recalc_rate,
464 .prepare = dsi_pll_10nm_vco_prepare,
465 .unprepare = dsi_pll_10nm_vco_unprepare,
466 };
467
468 /*
469 * PLL Callbacks
470 */
471
dsi_10nm_pll_save_state(struct msm_dsi_phy * phy)472 static void dsi_10nm_pll_save_state(struct msm_dsi_phy *phy)
473 {
474 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
475 struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
476 void __iomem *phy_base = pll_10nm->phy->base;
477 u32 cmn_clk_cfg0, cmn_clk_cfg1;
478
479 cached->pll_out_div = readl(pll_10nm->phy->pll_base +
480 REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
481 cached->pll_out_div &= 0x3;
482
483 cmn_clk_cfg0 = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
484 cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
485 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
486
487 cmn_clk_cfg1 = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
488 cached->pll_mux = cmn_clk_cfg1 & 0x3;
489
490 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
491 pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
492 cached->pix_clk_div, cached->pll_mux);
493 }
494
dsi_10nm_pll_restore_state(struct msm_dsi_phy * phy)495 static int dsi_10nm_pll_restore_state(struct msm_dsi_phy *phy)
496 {
497 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
498 struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
499 void __iomem *phy_base = pll_10nm->phy->base;
500 u32 val;
501 int ret;
502
503 val = readl(pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
504 val &= ~0x3;
505 val |= cached->pll_out_div;
506 writel(val, pll_10nm->phy->pll_base + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
507
508 writel(cached->bit_clk_div | (cached->pix_clk_div << 4),
509 phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
510
511 val = readl(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
512 val &= ~0x3;
513 val |= cached->pll_mux;
514 writel(val, phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
515
516 ret = dsi_pll_10nm_vco_set_rate(phy->vco_hw,
517 pll_10nm->vco_current_rate,
518 VCO_REF_CLK_RATE);
519 if (ret) {
520 DRM_DEV_ERROR(&pll_10nm->phy->pdev->dev,
521 "restore vco rate failed. ret=%d\n", ret);
522 return ret;
523 }
524
525 DBG("DSI PLL%d", pll_10nm->phy->id);
526
527 return 0;
528 }
529
dsi_10nm_set_usecase(struct msm_dsi_phy * phy)530 static int dsi_10nm_set_usecase(struct msm_dsi_phy *phy)
531 {
532 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(phy->vco_hw);
533 void __iomem *base = phy->base;
534 u32 data = 0x0; /* internal PLL */
535
536 DBG("DSI PLL%d", pll_10nm->phy->id);
537
538 switch (phy->usecase) {
539 case MSM_DSI_PHY_STANDALONE:
540 break;
541 case MSM_DSI_PHY_MASTER:
542 pll_10nm->slave = pll_10nm_list[(pll_10nm->phy->id + 1) % DSI_MAX];
543 break;
544 case MSM_DSI_PHY_SLAVE:
545 data = 0x1; /* external PLL */
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 /* set PLL src */
552 writel(data << 2, base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
553
554 return 0;
555 }
556
557 /*
558 * The post dividers and mux clocks are created using the standard divider and
559 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
560 * state to follow the master PLL's divider/mux state. Therefore, we don't
561 * require special clock ops that also configure the slave PLL registers
562 */
pll_10nm_register(struct dsi_pll_10nm * pll_10nm,struct clk_hw ** provided_clocks)563 static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **provided_clocks)
564 {
565 char clk_name[32];
566 struct clk_init_data vco_init = {
567 .parent_data = &(const struct clk_parent_data) {
568 .fw_name = "ref",
569 },
570 .num_parents = 1,
571 .name = clk_name,
572 .flags = CLK_IGNORE_UNUSED,
573 .ops = &clk_ops_dsi_pll_10nm_vco,
574 };
575 struct device *dev = &pll_10nm->phy->pdev->dev;
576 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit;
577 struct clk_hw *pll_post_out_div, *pclk_mux;
578 int ret;
579
580 DBG("DSI%d", pll_10nm->phy->id);
581
582 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id);
583 pll_10nm->clk_hw.init = &vco_init;
584
585 ret = devm_clk_hw_register(dev, &pll_10nm->clk_hw);
586 if (ret)
587 return ret;
588
589 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_10nm->phy->id);
590
591 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
592 &pll_10nm->clk_hw, CLK_SET_RATE_PARENT,
593 pll_10nm->phy->pll_base +
594 REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
595 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
596 if (IS_ERR(pll_out_div)) {
597 ret = PTR_ERR(pll_out_div);
598 goto fail;
599 }
600
601 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_10nm->phy->id);
602
603 /* BIT CLK: DIV_CTRL_3_0 */
604 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name,
605 pll_out_div, CLK_SET_RATE_PARENT,
606 pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
607 0, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);
608 if (IS_ERR(pll_bit)) {
609 ret = PTR_ERR(pll_bit);
610 goto fail;
611 }
612
613 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id);
614
615 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
616 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name,
617 pll_bit, CLK_SET_RATE_PARENT, 1, 8);
618 if (IS_ERR(hw)) {
619 ret = PTR_ERR(hw);
620 goto fail;
621 }
622
623 provided_clocks[DSI_BYTE_PLL_CLK] = hw;
624
625 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id);
626
627 pll_by_2_bit = devm_clk_hw_register_fixed_factor_parent_hw(dev,
628 clk_name, pll_bit, 0, 1, 2);
629 if (IS_ERR(pll_by_2_bit)) {
630 ret = PTR_ERR(pll_by_2_bit);
631 goto fail;
632 }
633
634 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_post_out_div_clk", pll_10nm->phy->id);
635
636 pll_post_out_div = devm_clk_hw_register_fixed_factor_parent_hw(dev,
637 clk_name, pll_out_div, 0, 1, 4);
638 if (IS_ERR(pll_post_out_div)) {
639 ret = PTR_ERR(pll_post_out_div);
640 goto fail;
641 }
642
643 snprintf(clk_name, sizeof(clk_name), "dsi%d_pclk_mux", pll_10nm->phy->id);
644
645 pclk_mux = devm_clk_hw_register_mux_parent_hws(dev, clk_name,
646 ((const struct clk_hw *[]){
647 pll_bit,
648 pll_by_2_bit,
649 pll_out_div,
650 pll_post_out_div,
651 }), 4, 0, pll_10nm->phy->base +
652 REG_DSI_10nm_PHY_CMN_CLK_CFG1, 0, 2, 0, NULL);
653 if (IS_ERR(pclk_mux)) {
654 ret = PTR_ERR(pclk_mux);
655 goto fail;
656 }
657
658 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_dsiclk", pll_10nm->phy->id);
659
660 /* PIX CLK DIV : DIV_CTRL_7_4*/
661 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, pclk_mux,
662 0, pll_10nm->phy->base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
663 4, 4, CLK_DIVIDER_ONE_BASED, &pll_10nm->postdiv_lock);
664 if (IS_ERR(hw)) {
665 ret = PTR_ERR(hw);
666 goto fail;
667 }
668
669 provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
670
671 return 0;
672
673 fail:
674
675 return ret;
676 }
677
dsi_pll_10nm_init(struct msm_dsi_phy * phy)678 static int dsi_pll_10nm_init(struct msm_dsi_phy *phy)
679 {
680 struct platform_device *pdev = phy->pdev;
681 struct dsi_pll_10nm *pll_10nm;
682 int ret;
683
684 pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
685 if (!pll_10nm)
686 return -ENOMEM;
687
688 DBG("DSI PLL%d", phy->id);
689
690 pll_10nm_list[phy->id] = pll_10nm;
691
692 spin_lock_init(&pll_10nm->postdiv_lock);
693
694 pll_10nm->phy = phy;
695
696 ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws);
697 if (ret) {
698 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
699 return ret;
700 }
701
702 phy->vco_hw = &pll_10nm->clk_hw;
703
704 /* TODO: Remove this when we have proper display handover support */
705 msm_dsi_phy_pll_save_state(phy);
706
707 return 0;
708 }
709
dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy * phy)710 static int dsi_phy_hw_v3_0_is_pll_on(struct msm_dsi_phy *phy)
711 {
712 void __iomem *base = phy->base;
713 u32 data = 0;
714
715 data = readl(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
716 mb(); /* make sure read happened */
717
718 return (data & BIT(0));
719 }
720
dsi_phy_hw_v3_0_config_lpcdrx(struct msm_dsi_phy * phy,bool enable)721 static void dsi_phy_hw_v3_0_config_lpcdrx(struct msm_dsi_phy *phy, bool enable)
722 {
723 void __iomem *lane_base = phy->lane_base;
724 int phy_lane_0 = 0; /* TODO: Support all lane swap configs */
725
726 /*
727 * LPRX and CDRX need to enabled only for physical data lane
728 * corresponding to the logical data lane 0
729 */
730 if (enable)
731 writel(0x3, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0));
732 else
733 writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(phy_lane_0));
734 }
735
dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy * phy)736 static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
737 {
738 int i;
739 u8 tx_dctrl[] = { 0x00, 0x00, 0x00, 0x04, 0x01 };
740 void __iomem *lane_base = phy->lane_base;
741 struct dsi_phy_10nm_tuning_cfg *tuning_cfg = phy->tuning_cfg;
742
743 if (phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)
744 tx_dctrl[3] = 0x02;
745
746 /* Strength ctrl settings */
747 for (i = 0; i < 5; i++) {
748 writel(0x55, lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i));
749 /*
750 * Disable LPRX and CDRX for all lanes. And later on, it will
751 * be only enabled for the physical data lane corresponding
752 * to the logical data lane 0
753 */
754 writel(0, lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i));
755 writel(0x0, lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i));
756 writel(0x88, lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i));
757 }
758
759 dsi_phy_hw_v3_0_config_lpcdrx(phy, true);
760
761 /* other settings */
762 for (i = 0; i < 5; i++) {
763 writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG0(i));
764 writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG1(i));
765 writel(0, lane_base + REG_DSI_10nm_PHY_LN_CFG2(i));
766 writel(i == 4 ? 0x80 : 0x0, lane_base + REG_DSI_10nm_PHY_LN_CFG3(i));
767
768 /* platform specific dsi phy drive strength adjustment */
769 writel(tuning_cfg->rescode_offset_top[i],
770 lane_base + REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(i));
771 writel(tuning_cfg->rescode_offset_bot[i],
772 lane_base + REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(i));
773
774 writel(tx_dctrl[i],
775 lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i));
776 }
777
778 if (!(phy->cfg->quirks & DSI_PHY_10NM_QUIRK_OLD_TIMINGS)) {
779 /* Toggle BIT 0 to release freeze I/0 */
780 writel(0x05, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3));
781 writel(0x04, lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3));
782 }
783 }
784
dsi_10nm_phy_enable(struct msm_dsi_phy * phy,struct msm_dsi_phy_clk_request * clk_req)785 static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy,
786 struct msm_dsi_phy_clk_request *clk_req)
787 {
788 int ret;
789 u32 status;
790 u32 const delay_us = 5;
791 u32 const timeout_us = 1000;
792 struct msm_dsi_dphy_timing *timing = &phy->timing;
793 void __iomem *base = phy->base;
794 struct dsi_phy_10nm_tuning_cfg *tuning_cfg = phy->tuning_cfg;
795 u32 data;
796
797 DBG("");
798
799 if (msm_dsi_dphy_timing_calc_v3(timing, clk_req)) {
800 DRM_DEV_ERROR(&phy->pdev->dev,
801 "%s: D-PHY timing calculation failed\n", __func__);
802 return -EINVAL;
803 }
804
805 if (dsi_phy_hw_v3_0_is_pll_on(phy))
806 pr_warn("PLL turned on before configuring PHY\n");
807
808 /* wait for REFGEN READY */
809 ret = readl_poll_timeout_atomic(base + REG_DSI_10nm_PHY_CMN_PHY_STATUS,
810 status, (status & BIT(0)),
811 delay_us, timeout_us);
812 if (ret) {
813 pr_err("Ref gen not ready. Aborting\n");
814 return -EINVAL;
815 }
816
817 /* de-assert digital and pll power down */
818 data = BIT(6) | BIT(5);
819 writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
820
821 /* Assert PLL core reset */
822 writel(0x00, base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL);
823
824 /* turn off resync FIFO */
825 writel(0x00, base + REG_DSI_10nm_PHY_CMN_RBUF_CTRL);
826
827 /* Select MS1 byte-clk */
828 writel(0x10, base + REG_DSI_10nm_PHY_CMN_GLBL_CTRL);
829
830 /* Enable LDO with platform specific drive level/amplitude adjustment */
831 writel(tuning_cfg->vreg_ctrl, base + REG_DSI_10nm_PHY_CMN_VREG_CTRL);
832
833 /* Configure PHY lane swap (TODO: we need to calculate this) */
834 writel(0x21, base + REG_DSI_10nm_PHY_CMN_LANE_CFG0);
835 writel(0x84, base + REG_DSI_10nm_PHY_CMN_LANE_CFG1);
836
837 /* DSI PHY timings */
838 writel(timing->hs_halfbyte_en, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0);
839 writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1);
840 writel(timing->clk_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2);
841 writel(timing->clk_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3);
842 writel(timing->hs_exit, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4);
843 writel(timing->hs_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5);
844 writel(timing->hs_prepare, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6);
845 writel(timing->hs_trail, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7);
846 writel(timing->hs_rqst, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8);
847 writel(timing->ta_go | (timing->ta_sure << 3), base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9);
848 writel(timing->ta_get, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10);
849 writel(0x00, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11);
850
851 /* Remove power down from all blocks */
852 writel(0x7f, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
853
854 /* power up lanes */
855 data = readl(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
856
857 /* TODO: only power up lanes that are used */
858 data |= 0x1F;
859 writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
860 writel(0x1F, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0);
861
862 /* Select full-rate mode */
863 writel(0x40, base + REG_DSI_10nm_PHY_CMN_CTRL_2);
864
865 ret = dsi_10nm_set_usecase(phy);
866 if (ret) {
867 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
868 __func__, ret);
869 return ret;
870 }
871
872 /* DSI lane settings */
873 dsi_phy_hw_v3_0_lane_settings(phy);
874
875 DBG("DSI%d PHY enabled", phy->id);
876
877 return 0;
878 }
879
dsi_10nm_phy_disable(struct msm_dsi_phy * phy)880 static void dsi_10nm_phy_disable(struct msm_dsi_phy *phy)
881 {
882 void __iomem *base = phy->base;
883 u32 data;
884
885 DBG("");
886
887 if (dsi_phy_hw_v3_0_is_pll_on(phy))
888 pr_warn("Turning OFF PHY while PLL is on\n");
889
890 dsi_phy_hw_v3_0_config_lpcdrx(phy, false);
891 data = readl(base + REG_DSI_10nm_PHY_CMN_CTRL_0);
892
893 /* disable all lanes */
894 data &= ~0x1F;
895 writel(data, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
896 writel(0, base + REG_DSI_10nm_PHY_CMN_LANE_CTRL0);
897
898 /* Turn off all PHY blocks */
899 writel(0x00, base + REG_DSI_10nm_PHY_CMN_CTRL_0);
900 /* make sure phy is turned off */
901 wmb();
902
903 DBG("DSI%d PHY disabled", phy->id);
904 }
905
dsi_10nm_phy_parse_dt(struct msm_dsi_phy * phy)906 static int dsi_10nm_phy_parse_dt(struct msm_dsi_phy *phy)
907 {
908 struct device *dev = &phy->pdev->dev;
909 struct dsi_phy_10nm_tuning_cfg *tuning_cfg;
910 s8 offset_top[DSI_LANE_MAX] = { 0 }; /* No offset */
911 s8 offset_bot[DSI_LANE_MAX] = { 0 }; /* No offset */
912 u32 ldo_level = 400; /* 400mV */
913 u8 level;
914 int ret, i;
915
916 tuning_cfg = devm_kzalloc(dev, sizeof(*tuning_cfg), GFP_KERNEL);
917 if (!tuning_cfg)
918 return -ENOMEM;
919
920 /* Drive strength adjustment parameters */
921 ret = of_property_read_u8_array(dev->of_node, "qcom,phy-rescode-offset-top",
922 offset_top, DSI_LANE_MAX);
923 if (ret && ret != -EINVAL) {
924 DRM_DEV_ERROR(dev, "failed to parse qcom,phy-rescode-offset-top, %d\n", ret);
925 return ret;
926 }
927
928 for (i = 0; i < DSI_LANE_MAX; i++) {
929 if (offset_top[i] < -32 || offset_top[i] > 31) {
930 DRM_DEV_ERROR(dev,
931 "qcom,phy-rescode-offset-top value %d is not in range [-32..31]\n",
932 offset_top[i]);
933 return -EINVAL;
934 }
935 tuning_cfg->rescode_offset_top[i] = 0x3f & offset_top[i];
936 }
937
938 ret = of_property_read_u8_array(dev->of_node, "qcom,phy-rescode-offset-bot",
939 offset_bot, DSI_LANE_MAX);
940 if (ret && ret != -EINVAL) {
941 DRM_DEV_ERROR(dev, "failed to parse qcom,phy-rescode-offset-bot, %d\n", ret);
942 return ret;
943 }
944
945 for (i = 0; i < DSI_LANE_MAX; i++) {
946 if (offset_bot[i] < -32 || offset_bot[i] > 31) {
947 DRM_DEV_ERROR(dev,
948 "qcom,phy-rescode-offset-bot value %d is not in range [-32..31]\n",
949 offset_bot[i]);
950 return -EINVAL;
951 }
952 tuning_cfg->rescode_offset_bot[i] = 0x3f & offset_bot[i];
953 }
954
955 /* Drive level/amplitude adjustment parameters */
956 ret = of_property_read_u32(dev->of_node, "qcom,phy-drive-ldo-level", &ldo_level);
957 if (ret && ret != -EINVAL) {
958 DRM_DEV_ERROR(dev, "failed to parse qcom,phy-drive-ldo-level, %d\n", ret);
959 return ret;
960 }
961
962 switch (ldo_level) {
963 case 375:
964 level = 0;
965 break;
966 case 400:
967 level = 1;
968 break;
969 case 425:
970 level = 2;
971 break;
972 case 450:
973 level = 3;
974 break;
975 case 475:
976 level = 4;
977 break;
978 case 500:
979 level = 5;
980 break;
981 default:
982 DRM_DEV_ERROR(dev, "qcom,phy-drive-ldo-level %d is not supported\n", ldo_level);
983 return -EINVAL;
984 }
985 tuning_cfg->vreg_ctrl = 0x58 | (0x7 & level);
986
987 phy->tuning_cfg = tuning_cfg;
988
989 return 0;
990 }
991
992 static const struct regulator_bulk_data dsi_phy_10nm_regulators[] = {
993 { .supply = "vdds", .init_load_uA = 36000 },
994 };
995
996 const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
997 .has_phy_lane = true,
998 .regulator_data = dsi_phy_10nm_regulators,
999 .num_regulators = ARRAY_SIZE(dsi_phy_10nm_regulators),
1000 .ops = {
1001 .enable = dsi_10nm_phy_enable,
1002 .disable = dsi_10nm_phy_disable,
1003 .pll_init = dsi_pll_10nm_init,
1004 .save_pll_state = dsi_10nm_pll_save_state,
1005 .restore_pll_state = dsi_10nm_pll_restore_state,
1006 .parse_dt_properties = dsi_10nm_phy_parse_dt,
1007 },
1008 .min_pll_rate = 1000000000UL,
1009 .max_pll_rate = 3500000000UL,
1010 .io_start = { 0xae94400, 0xae96400 },
1011 .num_dsi_phy = 2,
1012 };
1013
1014 const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
1015 .has_phy_lane = true,
1016 .regulator_data = dsi_phy_10nm_regulators,
1017 .num_regulators = ARRAY_SIZE(dsi_phy_10nm_regulators),
1018 .ops = {
1019 .enable = dsi_10nm_phy_enable,
1020 .disable = dsi_10nm_phy_disable,
1021 .pll_init = dsi_pll_10nm_init,
1022 .save_pll_state = dsi_10nm_pll_save_state,
1023 .restore_pll_state = dsi_10nm_pll_restore_state,
1024 .parse_dt_properties = dsi_10nm_phy_parse_dt,
1025 },
1026 .min_pll_rate = 1000000000UL,
1027 .max_pll_rate = 3500000000UL,
1028 .io_start = { 0xc994400, 0xc996400 },
1029 .num_dsi_phy = 2,
1030 .quirks = DSI_PHY_10NM_QUIRK_OLD_TIMINGS,
1031 };
1032