1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef _A6XX_CRASH_DUMP_H_
8 #define _A6XX_CRASH_DUMP_H_
9 
10 #include "a6xx.xml.h"
11 
12 #define A6XX_NUM_CONTEXTS 2
13 #define A6XX_NUM_SHADER_BANKS 3
14 
15 static const u32 a6xx_gras_cluster[] = {
16 	0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
17 	0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
18 	0x8400, 0x840b,
19 };
20 
21 static const u32 a6xx_ps_cluster_rac[] = {
22 	0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
23 	0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
24 	0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
25 	0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 };
27 
28 static const u32 a6xx_ps_cluster_rbp[] = {
29 	0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
30 	0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 };
32 
33 static const u32 a6xx_ps_cluster[] = {
34 	0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
35 };
36 
37 static const u32 a6xx_fe_cluster[] = {
38 	0x9300, 0x9306, 0x9800, 0x9806, 0x9b00, 0x9b07, 0xa000, 0xa009,
39 	0xa00e, 0xa0ef, 0xa0f8, 0xa0f8,
40 };
41 
42 static const u32 a660_fe_cluster[] = {
43 	0x9807, 0x9807,
44 };
45 
46 static const u32 a6xx_pc_vs_cluster[] = {
47 	0x9100, 0x9108, 0x9300, 0x9306, 0x9980, 0x9981, 0x9b00, 0x9b07,
48 };
49 
50 #define CLUSTER_FE	0
51 #define CLUSTER_SP_VS	1
52 #define CLUSTER_PC_VS	2
53 #define CLUSTER_GRAS	3
54 #define CLUSTER_SP_PS	4
55 #define CLUSTER_PS	5
56 #define CLUSTER_VPC_PS	6
57 #define CLUSTER_NONE    7
58 
59 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
60 	{ .id = _id, .name = #_id,\
61 		.registers = _reg, \
62 		.count = ARRAY_SIZE(_reg), \
63 		.sel_reg = _sel_reg, .sel_val = _sel_val }
64 
65 static const struct a6xx_cluster {
66 	u32 id;
67 	const char *name;
68 	const u32 *registers;
69 	size_t count;
70 	u32 sel_reg;
71 	u32 sel_val;
72 } a6xx_clusters[] = {
73 	CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
74 	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
75 	CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
76 	CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
77 	CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
78 	CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
79 	CLUSTER(CLUSTER_FE, a660_fe_cluster, 0, 0),
80 };
81 
82 static const u32 a6xx_sp_vs_hlsq_cluster[] = {
83 	0xb800, 0xb803, 0xb820, 0xb822,
84 };
85 
86 static const u32 a6xx_sp_vs_sp_cluster[] = {
87 	0xa800, 0xa824, 0xa830, 0xa83c, 0xa840, 0xa864, 0xa870, 0xa895,
88 	0xa8a0, 0xa8af, 0xa8c0, 0xa8c3,
89 };
90 
91 static const u32 a6xx_hlsq_duplicate_cluster[] = {
92 	0xbb10, 0xbb11, 0xbb20, 0xbb29,
93 };
94 
95 static const u32 a6xx_hlsq_2d_duplicate_cluster[] = {
96 	0xbd80, 0xbd80,
97 };
98 
99 static const u32 a6xx_sp_duplicate_cluster[] = {
100 	0xab00, 0xab00, 0xab04, 0xab05, 0xab10, 0xab1b, 0xab20, 0xab20,
101 };
102 
103 static const u32 a6xx_tp_duplicate_cluster[] = {
104 	0xb300, 0xb307, 0xb309, 0xb309, 0xb380, 0xb382,
105 };
106 
107 static const u32 a6xx_sp_ps_hlsq_cluster[] = {
108 	0xb980, 0xb980, 0xb982, 0xb987, 0xb990, 0xb99b, 0xb9a0, 0xb9a2,
109 	0xb9c0, 0xb9c9,
110 };
111 
112 static const u32 a6xx_sp_ps_hlsq_2d_cluster[] = {
113 	0xbd80, 0xbd80,
114 };
115 
116 static const u32 a6xx_sp_ps_sp_cluster[] = {
117 	0xa980, 0xa9a8, 0xa9b0, 0xa9bc, 0xa9d0, 0xa9d3, 0xa9e0, 0xa9f3,
118 	0xaa00, 0xaa00, 0xaa30, 0xaa31, 0xaaf2, 0xaaf2,
119 };
120 
121 static const u32 a6xx_sp_ps_sp_2d_cluster[] = {
122 	0xacc0, 0xacc0,
123 };
124 
125 static const u32 a6xx_sp_ps_tp_cluster[] = {
126 	0xb180, 0xb183, 0xb190, 0xb191,
127 };
128 
129 static const u32 a6xx_sp_ps_tp_2d_cluster[] = {
130 	0xb4c0, 0xb4d1,
131 };
132 
133 #define CLUSTER_DBGAHB(_id, _base, _type, _reg) \
134 	{ .name = #_id, .statetype = _type, .base = _base, \
135 		.registers = _reg, .count = ARRAY_SIZE(_reg) }
136 
137 static const struct a6xx_dbgahb_cluster {
138 	const char *name;
139 	u32 statetype;
140 	u32 base;
141 	const u32 *registers;
142 	size_t count;
143 } a6xx_dbgahb_clusters[] = {
144 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_sp_vs_hlsq_cluster),
145 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_vs_sp_cluster),
146 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002e000, 0x41, a6xx_hlsq_duplicate_cluster),
147 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002f000, 0x45, a6xx_hlsq_2d_duplicate_cluster),
148 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002a000, 0x21, a6xx_sp_duplicate_cluster),
149 	CLUSTER_DBGAHB(CLUSTER_SP_VS, 0x0002c000, 0x1, a6xx_tp_duplicate_cluster),
150 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_sp_ps_hlsq_cluster),
151 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002f000, 0x46, a6xx_sp_ps_hlsq_2d_cluster),
152 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_ps_sp_cluster),
153 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002b000, 0x26, a6xx_sp_ps_sp_2d_cluster),
154 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_sp_ps_tp_cluster),
155 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002d000, 0x6, a6xx_sp_ps_tp_2d_cluster),
156 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002e000, 0x42, a6xx_hlsq_duplicate_cluster),
157 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002a000, 0x22, a6xx_sp_duplicate_cluster),
158 	CLUSTER_DBGAHB(CLUSTER_SP_PS, 0x0002c000, 0x2, a6xx_tp_duplicate_cluster),
159 };
160 
161 static const u32 a6xx_hlsq_registers[] = {
162 	0xbe00, 0xbe01, 0xbe04, 0xbe05, 0xbe08, 0xbe09, 0xbe10, 0xbe15,
163 	0xbe20, 0xbe23,
164 };
165 
166 static const u32 a6xx_sp_registers[] = {
167 	0xae00, 0xae04, 0xae0c, 0xae0c, 0xae0f, 0xae2b, 0xae30, 0xae32,
168 	0xae35, 0xae35, 0xae3a, 0xae3f, 0xae50, 0xae52,
169 };
170 
171 static const u32 a6xx_tp_registers[] = {
172 	0xb600, 0xb601, 0xb604, 0xb605, 0xb610, 0xb61b, 0xb620, 0xb623,
173 };
174 
175 struct a6xx_registers {
176 	const u32 *registers;
177 	size_t count;
178 	u32 val0;
179 	u32 val1;
180 };
181 
182 #define HLSQ_DBG_REGS(_base, _type, _array) \
183 	{ .val0 = _base, .val1 = _type, .registers = _array, \
184 		.count = ARRAY_SIZE(_array), }
185 
186 static const struct a6xx_registers a6xx_hlsq_reglist[] = {
187 	HLSQ_DBG_REGS(0x0002F800, 0x40, a6xx_hlsq_registers),
188 	HLSQ_DBG_REGS(0x0002B800, 0x20, a6xx_sp_registers),
189 	HLSQ_DBG_REGS(0x0002D800, 0x0, a6xx_tp_registers),
190 };
191 
192 #define SHADER(_type, _size) \
193 	{ .type = _type, .name = #_type, .size = _size }
194 
195 static const struct a6xx_shader_block {
196 	const char *name;
197 	u32 type;
198 	u32 size;
199 } a6xx_shader_blocks[] = {
200 	SHADER(A6XX_TP0_TMO_DATA, 0x200),
201 	SHADER(A6XX_TP0_SMO_DATA, 0x80),
202 	SHADER(A6XX_TP0_MIPMAP_BASE_DATA, 0x3c0),
203 	SHADER(A6XX_TP1_TMO_DATA, 0x200),
204 	SHADER(A6XX_TP1_SMO_DATA, 0x80),
205 	SHADER(A6XX_TP1_MIPMAP_BASE_DATA, 0x3c0),
206 	SHADER(A6XX_SP_INST_DATA, 0x800),
207 	SHADER(A6XX_SP_LB_0_DATA, 0x800),
208 	SHADER(A6XX_SP_LB_1_DATA, 0x800),
209 	SHADER(A6XX_SP_LB_2_DATA, 0x800),
210 	SHADER(A6XX_SP_LB_3_DATA, 0x800),
211 	SHADER(A6XX_SP_LB_4_DATA, 0x800),
212 	SHADER(A6XX_SP_LB_5_DATA, 0x200),
213 	SHADER(A6XX_SP_CB_BINDLESS_DATA, 0x800),
214 	SHADER(A6XX_SP_CB_LEGACY_DATA, 0x280),
215 	SHADER(A6XX_SP_UAV_DATA, 0x80),
216 	SHADER(A6XX_SP_INST_TAG, 0x80),
217 	SHADER(A6XX_SP_CB_BINDLESS_TAG, 0x80),
218 	SHADER(A6XX_SP_TMO_UMO_TAG, 0x80),
219 	SHADER(A6XX_SP_SMO_TAG, 0x80),
220 	SHADER(A6XX_SP_STATE_DATA, 0x3f),
221 	SHADER(A6XX_HLSQ_CHUNK_CVS_RAM, 0x1c0),
222 	SHADER(A6XX_HLSQ_CHUNK_CPS_RAM, 0x280),
223 	SHADER(A6XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40),
224 	SHADER(A6XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40),
225 	SHADER(A6XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x4),
226 	SHADER(A6XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x4),
227 	SHADER(A6XX_HLSQ_CVS_MISC_RAM, 0x1c0),
228 	SHADER(A6XX_HLSQ_CPS_MISC_RAM, 0x580),
229 	SHADER(A6XX_HLSQ_INST_RAM, 0x800),
230 	SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM, 0x800),
231 	SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM, 0x800),
232 	SHADER(A6XX_HLSQ_CVS_MISC_RAM_TAG, 0x8),
233 	SHADER(A6XX_HLSQ_CPS_MISC_RAM_TAG, 0x4),
234 	SHADER(A6XX_HLSQ_INST_RAM_TAG, 0x80),
235 	SHADER(A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0xc),
236 	SHADER(A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10),
237 	SHADER(A6XX_HLSQ_PWR_REST_RAM, 0x28),
238 	SHADER(A6XX_HLSQ_PWR_REST_TAG, 0x14),
239 	SHADER(A6XX_HLSQ_DATAPATH_META, 0x40),
240 	SHADER(A6XX_HLSQ_FRONTEND_META, 0x40),
241 	SHADER(A6XX_HLSQ_INDIRECT_META, 0x40),
242 	SHADER(A6XX_SP_LB_6_DATA, 0x200),
243 	SHADER(A6XX_SP_LB_7_DATA, 0x200),
244 	SHADER(A6XX_HLSQ_INST_RAM_1, 0x200),
245 };
246 
247 static const u32 a6xx_rb_rac_registers[] = {
248 	0x8e04, 0x8e05, 0x8e07, 0x8e08, 0x8e10, 0x8e1c, 0x8e20, 0x8e25,
249 	0x8e28, 0x8e28, 0x8e2c, 0x8e2f, 0x8e50, 0x8e52,
250 };
251 
252 static const u32 a6xx_rb_rbp_registers[] = {
253 	0x8e01, 0x8e01, 0x8e0c, 0x8e0c, 0x8e3b, 0x8e3e, 0x8e40, 0x8e43,
254 	0x8e53, 0x8e5f, 0x8e70, 0x8e77,
255 };
256 
257 static const u32 a6xx_registers[] = {
258 	/* RBBM */
259 	0x0000, 0x0002, 0x0010, 0x0010, 0x0012, 0x0012, 0x0018, 0x001b,
260 	0x001e, 0x0032, 0x0038, 0x003c, 0x0042, 0x0042, 0x0044, 0x0044,
261 	0x0047, 0x0047, 0x0056, 0x0056, 0x00ad, 0x00ae, 0x00b0, 0x00fb,
262 	0x0100, 0x011d, 0x0200, 0x020d, 0x0218, 0x023d, 0x0400, 0x04f9,
263 	0x0500, 0x0500, 0x0505, 0x050b, 0x050e, 0x0511, 0x0533, 0x0533,
264 	0x0540, 0x0555,
265 	/* CP */
266 	0x0800, 0x0808, 0x0810, 0x0813, 0x0820, 0x0821, 0x0823, 0x0824,
267 	0x0826, 0x0827, 0x0830, 0x0833, 0x0840, 0x0845, 0x084f, 0x086f,
268 	0x0880, 0x088a, 0x08a0, 0x08ab, 0x08c0, 0x08c4, 0x08d0, 0x08dd,
269 	0x08f0, 0x08f3, 0x0900, 0x0903, 0x0908, 0x0911, 0x0928, 0x093e,
270 	0x0942, 0x094d, 0x0980, 0x0984, 0x098d, 0x0996, 0x0998, 0x099e,
271 	0x09a0, 0x09a6, 0x09a8, 0x09ae, 0x09b0, 0x09b1, 0x09c2, 0x09c8,
272 	0x0a00, 0x0a03,
273 	/* VSC */
274 	0x0c00, 0x0c04, 0x0c06, 0x0c06, 0x0c10, 0x0cd9, 0x0e00, 0x0e0e,
275 	/* UCHE */
276 	0x0e10, 0x0e13, 0x0e17, 0x0e19, 0x0e1c, 0x0e2b, 0x0e30, 0x0e32,
277 	0x0e38, 0x0e39,
278 	/* GRAS */
279 	0x8600, 0x8601, 0x8610, 0x861b, 0x8620, 0x8620, 0x8628, 0x862b,
280 	0x8630, 0x8637,
281 	/* VPC */
282 	0x9600, 0x9604, 0x9624, 0x9637,
283 	/* PC */
284 	0x9e00, 0x9e01, 0x9e03, 0x9e0e, 0x9e11, 0x9e16, 0x9e19, 0x9e19,
285 	0x9e1c, 0x9e1c, 0x9e20, 0x9e23, 0x9e30, 0x9e31, 0x9e34, 0x9e34,
286 	0x9e70, 0x9e72, 0x9e78, 0x9e79, 0x9e80, 0x9fff,
287 	/* VFD */
288 	0xa600, 0xa601, 0xa603, 0xa603, 0xa60a, 0xa60a, 0xa610, 0xa617,
289 	0xa630, 0xa630,
290 	/* HLSQ */
291 	0xd002, 0xd003,
292 };
293 
294 static const u32 a660_registers[] = {
295 	/* UCHE */
296 	0x0e3c, 0x0e3c,
297 };
298 
299 #define REGS(_array, _sel_reg, _sel_val) \
300 	{ .registers = _array, .count = ARRAY_SIZE(_array), \
301 		.val0 = _sel_reg, .val1 = _sel_val }
302 
303 static const struct a6xx_registers a6xx_reglist[] = {
304 	REGS(a6xx_registers, 0, 0),
305 	REGS(a660_registers, 0, 0),
306 	REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307 	REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
308 };
309 
310 static const u32 a6xx_ahb_registers[] = {
311 	/* RBBM_STATUS - RBBM_STATUS3 */
312 	0x210, 0x213,
313 	/* CP_STATUS_1 */
314 	0x825, 0x825,
315 };
316 
317 static const u32 a6xx_vbif_registers[] = {
318 	0x3000, 0x3007, 0x300c, 0x3014, 0x3018, 0x302d, 0x3030, 0x3031,
319 	0x3034, 0x3036, 0x303c, 0x303d, 0x3040, 0x3040, 0x3042, 0x3042,
320 	0x3049, 0x3049, 0x3058, 0x3058, 0x305a, 0x3061, 0x3064, 0x3068,
321 	0x306c, 0x306d, 0x3080, 0x3088, 0x308b, 0x308c, 0x3090, 0x3094,
322 	0x3098, 0x3098, 0x309c, 0x309c, 0x30c0, 0x30c0, 0x30c8, 0x30c8,
323 	0x30d0, 0x30d0, 0x30d8, 0x30d8, 0x30e0, 0x30e0, 0x3100, 0x3100,
324 	0x3108, 0x3108, 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120,
325 	0x3124, 0x3125, 0x3129, 0x3129, 0x3131, 0x3131, 0x3154, 0x3154,
326 	0x3156, 0x3156, 0x3158, 0x3158, 0x315a, 0x315a, 0x315c, 0x315c,
327 	0x315e, 0x315e, 0x3160, 0x3160, 0x3162, 0x3162, 0x340c, 0x340c,
328 	0x3410, 0x3410, 0x3800, 0x3801,
329 };
330 
331 static const u32 a6xx_gbif_registers[] = {
332 	0x3C00, 0X3C0B, 0X3C40, 0X3C47, 0X3CC0, 0X3CD1, 0xE3A, 0xE3A,
333 };
334 
335 static const struct a6xx_registers a6xx_ahb_reglist =
336 	REGS(a6xx_ahb_registers, 0, 0);
337 
338 static const struct a6xx_registers a6xx_vbif_reglist =
339 			REGS(a6xx_vbif_registers, 0, 0);
340 
341 static const struct a6xx_registers a6xx_gbif_reglist =
342 			REGS(a6xx_gbif_registers, 0, 0);
343 
344 static const u32 a6xx_gmu_gx_registers[] = {
345 	/* GMU GX */
346 	0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
347 	0x001e, 0x001e, 0x0020, 0x0023, 0x0026, 0x0026, 0x0028, 0x002b,
348 	0x002e, 0x002e, 0x0030, 0x0033, 0x0036, 0x0036, 0x0038, 0x003b,
349 	0x003e, 0x003e, 0x0040, 0x0043, 0x0046, 0x0046, 0x0080, 0x0084,
350 	0x0100, 0x012b, 0x0140, 0x0140,
351 };
352 
353 static const u32 a6xx_gmu_cx_registers[] = {
354 	/* GMU CX */
355 	0x4c00, 0x4c07, 0x4c10, 0x4c12, 0x4d00, 0x4d00, 0x4d07, 0x4d0a,
356 	0x5000, 0x5004, 0x5007, 0x5008, 0x500b, 0x500c, 0x500f, 0x501c,
357 	0x5024, 0x502a, 0x502d, 0x5030, 0x5040, 0x5053, 0x5087, 0x5089,
358 	0x50a0, 0x50a2, 0x50a4, 0x50af, 0x50c0, 0x50c3, 0x50d0, 0x50d0,
359 	0x50e4, 0x50e4, 0x50e8, 0x50ec, 0x5100, 0x5103, 0x5140, 0x5140,
360 	0x5142, 0x5144, 0x514c, 0x514d, 0x514f, 0x5151, 0x5154, 0x5154,
361 	0x5157, 0x5158, 0x515d, 0x515d, 0x5162, 0x5162, 0x5164, 0x5165,
362 	0x5180, 0x5186, 0x5190, 0x519e, 0x51c0, 0x51c0, 0x51c5, 0x51cc,
363 	0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
364 	/* GMU AO */
365 	0x9300, 0x9316, 0x9400, 0x9400,
366 };
367 
368 static const u32 a6xx_gmu_gpucc_registers[] = {
369 	/* GPU CC */
370 	0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
371 	0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
372 	0x9c42, 0x9c49, 0x9c58, 0x9c5a, 0x9d40, 0x9d5e, 0xa000, 0xa002,
373 	0xa400, 0xa402, 0xac00, 0xac02, 0xb000, 0xb002, 0xb400, 0xb402,
374 	0xb800, 0xb802,
375 	/* GPU CC ACD */
376 	0xbc00, 0xbc16, 0xbc20, 0xbc27,
377 };
378 
379 static const u32 a621_gmu_gpucc_registers[] = {
380 	/* GPU CC */
381 	0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,
382 	0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,
383 	0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,
384 	0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,
385 	0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,
386 	0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,
387 	0xbe20, 0xbe2d,
388 };
389 
390 static const u32 a6xx_gmu_cx_rscc_registers[] = {
391 	/* GPU RSCC */
392 	0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,
393 	0x034c, 0x0387, 0x03ec, 0x03ef, 0x03f4, 0x042f, 0x0494, 0x0497,
394 	0x049c, 0x04d7, 0x053c, 0x053f, 0x0544, 0x057f,
395 };
396 
397 static const struct a6xx_registers a6xx_gmu_reglist[] = {
398 	REGS(a6xx_gmu_cx_registers, 0, 0),
399 	REGS(a6xx_gmu_cx_rscc_registers, 0, 0),
400 	REGS(a6xx_gmu_gx_registers, 0, 0),
401 };
402 
403 static const struct a6xx_registers a6xx_gpucc_reg = REGS(a6xx_gmu_gpucc_registers, 0, 0);
404 static const struct a6xx_registers a621_gpucc_reg = REGS(a621_gmu_gpucc_registers, 0, 0);
405 
406 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
407 static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
408 
409 struct a6xx_indexed_registers {
410 	const char *name;
411 	u32 addr;
412 	u32 data;
413 	u32 count;
414 	u32 (*count_fn)(struct msm_gpu *gpu);
415 };
416 
417 static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
418 	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
419 		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
420 	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
421 		REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
422 	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
423 		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
424 	{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
425 		REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
426 };
427 
428 static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
429 	{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
430 		REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
431 	{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
432 		REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL },
433 	{ "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
434 		REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL },
435 	{ "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
436 		REG_A7XX_CP_BV_SQE_STAT_DATA, 0x33, NULL },
437 	{ "CP_BV_DRAW_STATE_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
438 		REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x100, NULL },
439 	{ "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
440 		REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x8000, NULL },
441 	{ "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
442 		REG_A7XX_CP_SQE_AC_STAT_DATA, 0x33, NULL },
443 	{ "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
444 		REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x100, NULL },
445 	{ "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
446 		REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x8000, NULL },
447 	{ "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
448 		REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x40, NULL },
449 	{ "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
450 		REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
451 };
452 
453 static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
454 	"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
455 		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
456 };
457 
458 static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
459 	{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
460 		REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
461 	{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
462 		REG_A7XX_CP_BV_MEM_POOL_DBG_DATA, 0x2100, NULL },
463 };
464 
465 #define DEBUGBUS(_id, _count) { .id = _id, .name = #_id, .count = _count }
466 
467 static const struct a6xx_debugbus_block {
468 	const char *name;
469 	u32 id;
470 	u32 count;
471 } a6xx_debugbus_blocks[] = {
472 	DEBUGBUS(A6XX_DBGBUS_CP, 0x100),
473 	DEBUGBUS(A6XX_DBGBUS_RBBM, 0x100),
474 	DEBUGBUS(A6XX_DBGBUS_HLSQ, 0x100),
475 	DEBUGBUS(A6XX_DBGBUS_UCHE, 0x100),
476 	DEBUGBUS(A6XX_DBGBUS_DPM, 0x100),
477 	DEBUGBUS(A6XX_DBGBUS_TESS, 0x100),
478 	DEBUGBUS(A6XX_DBGBUS_PC, 0x100),
479 	DEBUGBUS(A6XX_DBGBUS_VFDP, 0x100),
480 	DEBUGBUS(A6XX_DBGBUS_VPC, 0x100),
481 	DEBUGBUS(A6XX_DBGBUS_TSE, 0x100),
482 	DEBUGBUS(A6XX_DBGBUS_RAS, 0x100),
483 	DEBUGBUS(A6XX_DBGBUS_VSC, 0x100),
484 	DEBUGBUS(A6XX_DBGBUS_COM, 0x100),
485 	DEBUGBUS(A6XX_DBGBUS_LRZ, 0x100),
486 	DEBUGBUS(A6XX_DBGBUS_A2D, 0x100),
487 	DEBUGBUS(A6XX_DBGBUS_CCUFCHE, 0x100),
488 	DEBUGBUS(A6XX_DBGBUS_RBP, 0x100),
489 	DEBUGBUS(A6XX_DBGBUS_DCS, 0x100),
490 	DEBUGBUS(A6XX_DBGBUS_DBGC, 0x100),
491 	DEBUGBUS(A6XX_DBGBUS_GMU_GX, 0x100),
492 	DEBUGBUS(A6XX_DBGBUS_TPFCHE, 0x100),
493 	DEBUGBUS(A6XX_DBGBUS_GPC, 0x100),
494 	DEBUGBUS(A6XX_DBGBUS_LARC, 0x100),
495 	DEBUGBUS(A6XX_DBGBUS_HLSQ_SPTP, 0x100),
496 	DEBUGBUS(A6XX_DBGBUS_RB_0, 0x100),
497 	DEBUGBUS(A6XX_DBGBUS_RB_1, 0x100),
498 	DEBUGBUS(A6XX_DBGBUS_UCHE_WRAPPER, 0x100),
499 	DEBUGBUS(A6XX_DBGBUS_CCU_0, 0x100),
500 	DEBUGBUS(A6XX_DBGBUS_CCU_1, 0x100),
501 	DEBUGBUS(A6XX_DBGBUS_VFD_0, 0x100),
502 	DEBUGBUS(A6XX_DBGBUS_VFD_1, 0x100),
503 	DEBUGBUS(A6XX_DBGBUS_VFD_2, 0x100),
504 	DEBUGBUS(A6XX_DBGBUS_VFD_3, 0x100),
505 	DEBUGBUS(A6XX_DBGBUS_SP_0, 0x100),
506 	DEBUGBUS(A6XX_DBGBUS_SP_1, 0x100),
507 	DEBUGBUS(A6XX_DBGBUS_TPL1_0, 0x100),
508 	DEBUGBUS(A6XX_DBGBUS_TPL1_1, 0x100),
509 	DEBUGBUS(A6XX_DBGBUS_TPL1_2, 0x100),
510 	DEBUGBUS(A6XX_DBGBUS_TPL1_3, 0x100),
511 };
512 
513 static const struct a6xx_debugbus_block a6xx_gbif_debugbus_block =
514 			DEBUGBUS(A6XX_DBGBUS_VBIF, 0x100);
515 
516 static const struct a6xx_debugbus_block a6xx_cx_debugbus_blocks[] = {
517 	DEBUGBUS(A6XX_DBGBUS_GMU_CX, 0x100),
518 	DEBUGBUS(A6XX_DBGBUS_CX, 0x100),
519 };
520 
521 static const struct a6xx_debugbus_block a650_debugbus_blocks[] = {
522 	DEBUGBUS(A6XX_DBGBUS_RB_2, 0x100),
523 	DEBUGBUS(A6XX_DBGBUS_CCU_2, 0x100),
524 	DEBUGBUS(A6XX_DBGBUS_VFD_4, 0x100),
525 	DEBUGBUS(A6XX_DBGBUS_VFD_5, 0x100),
526 	DEBUGBUS(A6XX_DBGBUS_SP_2, 0x100),
527 	DEBUGBUS(A6XX_DBGBUS_TPL1_4, 0x100),
528 	DEBUGBUS(A6XX_DBGBUS_TPL1_5, 0x100),
529 	DEBUGBUS(A6XX_DBGBUS_SPTP_0, 0x100),
530 	DEBUGBUS(A6XX_DBGBUS_SPTP_1, 0x100),
531 	DEBUGBUS(A6XX_DBGBUS_SPTP_2, 0x100),
532 	DEBUGBUS(A6XX_DBGBUS_SPTP_3, 0x100),
533 	DEBUGBUS(A6XX_DBGBUS_SPTP_4, 0x100),
534 	DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
535 };
536 
537 static const u32 a7xx_gbif_debugbus_blocks[] = {
538 	A7XX_DBGBUS_GBIF_CX,
539 	A7XX_DBGBUS_GBIF_GX,
540 };
541 
542 static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = {
543 	DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100),
544 	DEBUGBUS(A7XX_DBGBUS_CX, 0x100),
545 	DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
546 };
547 
548 #define STATE_NON_CONTEXT 0
549 #define STATE_TOGGLE_CTXT 1
550 #define STATE_FORCE_CTXT_0 2
551 #define STATE_FORCE_CTXT_1 3
552 
553 struct gen7_sel_reg {
554 	unsigned int host_reg;
555 	unsigned int cd_reg;
556 	unsigned int val;
557 };
558 
559 struct gen7_cluster_registers {
560 	/* cluster_id: Cluster identifier */
561 	int cluster_id;
562 	/* pipe_id: Pipe Identifier */
563 	int pipe_id;
564 	/* context_id: one of STATE_ that identifies the context to dump */
565 	int context_id;
566 	/* regs: Pointer to an array of register pairs */
567 	const u32 *regs;
568 	/* sel: Pointer to a selector register to write before reading */
569 	const struct gen7_sel_reg *sel;
570 };
571 
572 struct gen7_sptp_cluster_registers {
573 	/* cluster_id: Cluster identifier */
574 	enum a7xx_cluster cluster_id;
575 	/* statetype: SP block state type for the cluster */
576 	enum a7xx_statetype_id statetype;
577 	/* pipe_id: Pipe identifier */
578 	enum a7xx_pipe pipe_id;
579 	/* context_id: Context identifier */
580 	int context_id;
581 	/* location_id: Location identifier */
582 	enum a7xx_state_location location_id;
583 	/* regs: Pointer to the list of register pairs to read */
584 	const u32 *regs;
585 	/* regbase: Dword offset of the register block in the GPu register space */
586 	unsigned int regbase;
587 };
588 
589 struct gen7_shader_block {
590 	/* statetype: Type identifer for the block */
591 	u32 statetype;
592 	/* size: Size of the block (in dwords) */
593 	u32 size;
594 	/* num_sps: The SP id to dump */
595 	u32 num_sps;
596 	/* num_usptps: The number of USPTPs to dump */;
597 	u32 num_usptps;
598 	/* pipe_id: Pipe identifier for the block data  */
599 	u32 pipeid;
600 	/* location: Location identifer for the block data */
601 	u32 location;
602 };
603 
604 struct gen7_reg_list {
605 	const u32 *regs;
606 	const struct gen7_sel_reg *sel;
607 };
608 
609 /* adreno_gen7_x_y_snapshot.h defines which debugbus blocks a given family has, but the
610  * list of debugbus blocks is global on a7xx.
611  */
612 
613 #define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count },
614 static const struct a6xx_debugbus_block a7xx_debugbus_blocks[] = {
615 	A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_0, 0x100)
616 	A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_1, 0x100)
617 	A7XX_DEBUGBUS(A7XX_DBGBUS_RBBM, 0x100)
618 	A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100)
619 	A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100)
620 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ, 0x100)
621 	A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_0, 0x100)
622 	A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_1, 0x100)
623 	A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BR, 0x100)
624 	A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BV, 0x100)
625 	A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BR, 0x100)
626 	A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BV, 0x100)
627 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BR, 0x100)
628 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BV, 0x100)
629 	A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BR, 0x100)
630 	A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BV, 0x100)
631 	A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BR, 0x100)
632 	A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BV, 0x100)
633 	A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BR, 0x100)
634 	A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BV, 0x100)
635 	A7XX_DEBUGBUS(A7XX_DBGBUS_VSC, 0x100)
636 	A7XX_DEBUGBUS(A7XX_DBGBUS_COM_0, 0x100)
637 	A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BR, 0x100)
638 	A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BV, 0x100)
639 	A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_0, 0x100)
640 	A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_1, 0x100)
641 	A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_GX, 0x100)
642 	A7XX_DEBUGBUS(A7XX_DBGBUS_DBGC, 0x100)
643 	A7XX_DEBUGBUS(A7XX_DBGBUS_CX, 0x100)
644 	A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100)
645 	A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BR, 0x100)
646 	A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BV, 0x100)
647 	A7XX_DEBUGBUS(A7XX_DBGBUS_LARC, 0x100)
648 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_SPTP, 0x100)
649 	A7XX_DEBUGBUS(A7XX_DBGBUS_RB_0, 0x100)
650 	A7XX_DEBUGBUS(A7XX_DBGBUS_RB_1, 0x100)
651 	A7XX_DEBUGBUS(A7XX_DBGBUS_RB_2, 0x100)
652 	A7XX_DEBUGBUS(A7XX_DBGBUS_RB_3, 0x100)
653 	A7XX_DEBUGBUS(A7XX_DBGBUS_RB_4, 0x100)
654 	A7XX_DEBUGBUS(A7XX_DBGBUS_RB_5, 0x100)
655 	A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_WRAPPER, 0x100)
656 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_0, 0x100)
657 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_1, 0x100)
658 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_2, 0x100)
659 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_3, 0x100)
660 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_4, 0x100)
661 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_5, 0x100)
662 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_0, 0x100)
663 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_1, 0x100)
664 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_2, 0x100)
665 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_3, 0x100)
666 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_4, 0x100)
667 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_5, 0x100)
668 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_6, 0x100)
669 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_7, 0x100)
670 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_0, 0x100)
671 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_1, 0x100)
672 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_2, 0x100)
673 	A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_3, 0x100)
674 	A7XX_DEBUGBUS(A7XX_DBGBUS_USP_0, 0x100)
675 	A7XX_DEBUGBUS(A7XX_DBGBUS_USP_1, 0x100)
676 	A7XX_DEBUGBUS(A7XX_DBGBUS_USP_2, 0x100)
677 	A7XX_DEBUGBUS(A7XX_DBGBUS_USP_3, 0x100)
678 	A7XX_DEBUGBUS(A7XX_DBGBUS_USP_4, 0x100)
679 	A7XX_DEBUGBUS(A7XX_DBGBUS_USP_5, 0x100)
680 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_0, 0x100)
681 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_1, 0x100)
682 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_2, 0x100)
683 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_3, 0x100)
684 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_4, 0x100)
685 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_5, 0x100)
686 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_6, 0x100)
687 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_7, 0x100)
688 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_8, 0x100)
689 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_9, 0x100)
690 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_10, 0x100)
691 	A7XX_DEBUGBUS(A7XX_DBGBUS_TP_11, 0x100)
692 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_0, 0x100)
693 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_1, 0x100)
694 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_2, 0x100)
695 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_3, 0x100)
696 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_4, 0x100)
697 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_5, 0x100)
698 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_6, 0x100)
699 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_7, 0x100)
700 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_8, 0x100)
701 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_9, 0x100)
702 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_10, 0x100)
703 	A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_11, 0x100)
704 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_0, 0x100)
705 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_1, 0x100)
706 	A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_2, 0x100)
707 	A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_0, 0x100)
708 	A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_1, 0x100)
709 	A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_2, 0x100)
710 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_0, 0x100)
711 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_1, 0x100)
712 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_2, 0x100)
713 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_3, 0x100)
714 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_4, 0x100)
715 	A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_5, 0x100)
716 	A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_0, 0x100)
717 	A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_1, 0x100)
718 	A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_2, 0x100)
719 	A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_SUBCORE, 0x100)
720 	A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_CORE, 0x100)
721 };
722 
723 #define A7XX_NAME(enumval) [enumval] = #enumval
724 static const char *a7xx_statetype_names[] = {
725 	A7XX_NAME(A7XX_TP0_NCTX_REG),
726 	A7XX_NAME(A7XX_TP0_CTX0_3D_CVS_REG),
727 	A7XX_NAME(A7XX_TP0_CTX0_3D_CPS_REG),
728 	A7XX_NAME(A7XX_TP0_CTX1_3D_CVS_REG),
729 	A7XX_NAME(A7XX_TP0_CTX1_3D_CPS_REG),
730 	A7XX_NAME(A7XX_TP0_CTX2_3D_CPS_REG),
731 	A7XX_NAME(A7XX_TP0_CTX3_3D_CPS_REG),
732 	A7XX_NAME(A7XX_TP0_TMO_DATA),
733 	A7XX_NAME(A7XX_TP0_SMO_DATA),
734 	A7XX_NAME(A7XX_TP0_MIPMAP_BASE_DATA),
735 	A7XX_NAME(A7XX_SP_NCTX_REG),
736 	A7XX_NAME(A7XX_SP_CTX0_3D_CVS_REG),
737 	A7XX_NAME(A7XX_SP_CTX0_3D_CPS_REG),
738 	A7XX_NAME(A7XX_SP_CTX1_3D_CVS_REG),
739 	A7XX_NAME(A7XX_SP_CTX1_3D_CPS_REG),
740 	A7XX_NAME(A7XX_SP_CTX2_3D_CPS_REG),
741 	A7XX_NAME(A7XX_SP_CTX3_3D_CPS_REG),
742 	A7XX_NAME(A7XX_SP_INST_DATA),
743 	A7XX_NAME(A7XX_SP_INST_DATA_1),
744 	A7XX_NAME(A7XX_SP_LB_0_DATA),
745 	A7XX_NAME(A7XX_SP_LB_1_DATA),
746 	A7XX_NAME(A7XX_SP_LB_2_DATA),
747 	A7XX_NAME(A7XX_SP_LB_3_DATA),
748 	A7XX_NAME(A7XX_SP_LB_4_DATA),
749 	A7XX_NAME(A7XX_SP_LB_5_DATA),
750 	A7XX_NAME(A7XX_SP_LB_6_DATA),
751 	A7XX_NAME(A7XX_SP_LB_7_DATA),
752 	A7XX_NAME(A7XX_SP_CB_RAM),
753 	A7XX_NAME(A7XX_SP_LB_13_DATA),
754 	A7XX_NAME(A7XX_SP_LB_14_DATA),
755 	A7XX_NAME(A7XX_SP_INST_TAG),
756 	A7XX_NAME(A7XX_SP_INST_DATA_2),
757 	A7XX_NAME(A7XX_SP_TMO_TAG),
758 	A7XX_NAME(A7XX_SP_SMO_TAG),
759 	A7XX_NAME(A7XX_SP_STATE_DATA),
760 	A7XX_NAME(A7XX_SP_HWAVE_RAM),
761 	A7XX_NAME(A7XX_SP_L0_INST_BUF),
762 	A7XX_NAME(A7XX_SP_LB_8_DATA),
763 	A7XX_NAME(A7XX_SP_LB_9_DATA),
764 	A7XX_NAME(A7XX_SP_LB_10_DATA),
765 	A7XX_NAME(A7XX_SP_LB_11_DATA),
766 	A7XX_NAME(A7XX_SP_LB_12_DATA),
767 	A7XX_NAME(A7XX_HLSQ_DATAPATH_DSTR_META),
768 	A7XX_NAME(A7XX_HLSQ_L2STC_TAG_RAM),
769 	A7XX_NAME(A7XX_HLSQ_L2STC_INFO_CMD),
770 	A7XX_NAME(A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG),
771 	A7XX_NAME(A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG),
772 	A7XX_NAME(A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM),
773 	A7XX_NAME(A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM),
774 	A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM),
775 	A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM),
776 	A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM_TAG),
777 	A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM_TAG),
778 	A7XX_NAME(A7XX_HLSQ_ICB_CVS_CB_BASE_TAG),
779 	A7XX_NAME(A7XX_HLSQ_ICB_CPS_CB_BASE_TAG),
780 	A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM),
781 	A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM),
782 	A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_1),
783 	A7XX_NAME(A7XX_HLSQ_INST_RAM),
784 	A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM),
785 	A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM),
786 	A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM_TAG),
787 	A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_TAG),
788 	A7XX_NAME(A7XX_HLSQ_INST_RAM_TAG),
789 	A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG),
790 	A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG),
791 	A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM),
792 	A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG),
793 	A7XX_NAME(A7XX_HLSQ_INST_RAM_1),
794 	A7XX_NAME(A7XX_HLSQ_STPROC_META),
795 	A7XX_NAME(A7XX_HLSQ_BV_BE_META),
796 	A7XX_NAME(A7XX_HLSQ_INST_RAM_2),
797 	A7XX_NAME(A7XX_HLSQ_DATAPATH_META),
798 	A7XX_NAME(A7XX_HLSQ_FRONTEND_META),
799 	A7XX_NAME(A7XX_HLSQ_INDIRECT_META),
800 	A7XX_NAME(A7XX_HLSQ_BACKEND_META),
801 };
802 
803 static const char *a7xx_pipe_names[] = {
804 	A7XX_NAME(A7XX_PIPE_NONE),
805 	A7XX_NAME(A7XX_PIPE_BR),
806 	A7XX_NAME(A7XX_PIPE_BV),
807 	A7XX_NAME(A7XX_PIPE_LPAC),
808 };
809 
810 static const char *a7xx_cluster_names[] = {
811 	A7XX_NAME(A7XX_CLUSTER_NONE),
812 	A7XX_NAME(A7XX_CLUSTER_FE),
813 	A7XX_NAME(A7XX_CLUSTER_SP_VS),
814 	A7XX_NAME(A7XX_CLUSTER_PC_VS),
815 	A7XX_NAME(A7XX_CLUSTER_GRAS),
816 	A7XX_NAME(A7XX_CLUSTER_SP_PS),
817 	A7XX_NAME(A7XX_CLUSTER_VPC_PS),
818 	A7XX_NAME(A7XX_CLUSTER_PS),
819 };
820 
821 #endif
822