1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5 #include "msm_gem.h"
6 #include "msm_mmu.h"
7 #include "msm_gpu_trace.h"
8 #include "a6xx_gpu.h"
9 #include "a6xx_gmu.xml.h"
10
11 #include <linux/bitfield.h>
12 #include <linux/devfreq.h>
13 #include <linux/firmware/qcom/qcom_scm.h>
14 #include <linux/pm_domain.h>
15 #include <linux/soc/qcom/llcc-qcom.h>
16
17 #define GPU_PAS_ID 13
18
_a6xx_check_idle(struct msm_gpu * gpu)19 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
20 {
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
22 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
23
24 /* Check that the GMU is idle */
25 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu))
26 return false;
27
28 /* Check tha the CX master is idle */
29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
30 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
31 return false;
32
33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
34 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
35 }
36
a6xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring)37 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
38 {
39 /* wait for CP to drain ringbuffer: */
40 if (!adreno_idle(gpu, ring))
41 return false;
42
43 if (spin_until(_a6xx_check_idle(gpu))) {
44 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
45 gpu->name, __builtin_return_address(0),
46 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
48 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
49 gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
50 return false;
51 }
52
53 return true;
54 }
55
update_shadow_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring)56 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
57 {
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
59 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
60
61 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
63 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
66 }
67 }
68
a6xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring)69 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
70 {
71 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
72 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
73 uint32_t wptr;
74 unsigned long flags;
75
76 update_shadow_rptr(gpu, ring);
77
78 spin_lock_irqsave(&ring->preempt_lock, flags);
79
80 /* Copy the shadow to the actual register */
81 ring->cur = ring->next;
82
83 /* Make sure to wrap wptr if we need to */
84 wptr = get_wptr(ring);
85
86 /* Update HW if this is the current ring and we are not in preempt*/
87 if (!a6xx_in_preempt(a6xx_gpu)) {
88 if (a6xx_gpu->cur_ring == ring)
89 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
90 else
91 ring->restore_wptr = true;
92 } else {
93 ring->restore_wptr = true;
94 }
95
96 spin_unlock_irqrestore(&ring->preempt_lock, flags);
97 }
98
get_stats_counter(struct msm_ringbuffer * ring,u32 counter,u64 iova)99 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
100 u64 iova)
101 {
102 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
103 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
104 CP_REG_TO_MEM_0_CNT(2) |
105 CP_REG_TO_MEM_0_64B);
106 OUT_RING(ring, lower_32_bits(iova));
107 OUT_RING(ring, upper_32_bits(iova));
108 }
109
a6xx_set_pagetable(struct a6xx_gpu * a6xx_gpu,struct msm_ringbuffer * ring,struct msm_gem_submit * submit)110 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
111 struct msm_ringbuffer *ring, struct msm_gem_submit *submit)
112 {
113 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
114 struct msm_file_private *ctx = submit->queue->ctx;
115 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
116 phys_addr_t ttbr;
117 u32 asid;
118 u64 memptr = rbmemptr(ring, ttbr0);
119
120 if (ctx->seqno == ring->cur_ctx_seqno)
121 return;
122
123 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
124 return;
125
126 if (adreno_gpu->info->family >= ADRENO_7XX_GEN1) {
127 /* Wait for previous submit to complete before continuing: */
128 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4);
129 OUT_RING(ring, 0);
130 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
131 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
132 OUT_RING(ring, submit->seqno - 1);
133 }
134
135 if (!sysprof) {
136 if (!adreno_is_a7xx(adreno_gpu)) {
137 /* Turn off protected mode to write to special registers */
138 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
139 OUT_RING(ring, 0);
140 }
141
142 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
143 OUT_RING(ring, 1);
144 }
145
146 /* Execute the table update */
147 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
148 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
149
150 OUT_RING(ring,
151 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
152 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
153 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
154 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
155
156 /*
157 * Write the new TTBR0 to the memstore. This is good for debugging.
158 * Needed for preemption
159 */
160 OUT_PKT7(ring, CP_MEM_WRITE, 5);
161 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
162 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
163 OUT_RING(ring, lower_32_bits(ttbr));
164 OUT_RING(ring, upper_32_bits(ttbr));
165 OUT_RING(ring, ctx->seqno);
166
167 /*
168 * Sync both threads after switching pagetables and enable BR only
169 * to make sure BV doesn't race ahead while BR is still switching
170 * pagetables.
171 */
172 if (adreno_is_a7xx(&a6xx_gpu->base)) {
173 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
174 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
175 }
176
177 /*
178 * And finally, trigger a uche flush to be sure there isn't anything
179 * lingering in that part of the GPU
180 */
181
182 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
183 OUT_RING(ring, CACHE_INVALIDATE);
184
185 if (!sysprof) {
186 /*
187 * Wait for SRAM clear after the pgtable update, so the
188 * two can happen in parallel:
189 */
190 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
191 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));
192 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO(
193 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS));
194 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0));
195 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));
196 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));
197 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));
198
199 if (!adreno_is_a7xx(adreno_gpu)) {
200 /* Re-enable protected mode: */
201 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
202 OUT_RING(ring, 1);
203 }
204 }
205 }
206
a6xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)207 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
208 {
209 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
210 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
211 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
212 struct msm_ringbuffer *ring = submit->ring;
213 unsigned int i, ibs = 0;
214
215 a6xx_set_pagetable(a6xx_gpu, ring, submit);
216
217 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
218 rbmemptr_stats(ring, index, cpcycles_start));
219
220 /*
221 * For PM4 the GMU register offsets are calculated from the base of the
222 * GPU registers so we need to add 0x1a800 to the register value on A630
223 * to get the right value from PM4.
224 */
225 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
226 rbmemptr_stats(ring, index, alwayson_start));
227
228 /* Invalidate CCU depth and color */
229 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
230 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
231
232 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
233 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
234
235 /* Submit the commands */
236 for (i = 0; i < submit->nr_cmds; i++) {
237 switch (submit->cmd[i].type) {
238 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
239 break;
240 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
241 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno)
242 break;
243 fallthrough;
244 case MSM_SUBMIT_CMD_BUF:
245 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
246 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
247 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
248 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size));
249 ibs++;
250 break;
251 }
252
253 /*
254 * Periodically update shadow-wptr if needed, so that we
255 * can see partial progress of submits with large # of
256 * cmds.. otherwise we could needlessly stall waiting for
257 * ringbuffer state, simply due to looking at a shadow
258 * rptr value that has not been updated
259 */
260 if ((ibs % 32) == 0)
261 update_shadow_rptr(gpu, ring);
262 }
263
264 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
265 rbmemptr_stats(ring, index, cpcycles_end));
266 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
267 rbmemptr_stats(ring, index, alwayson_end));
268
269 /* Write the fence to the scratch register */
270 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
271 OUT_RING(ring, submit->seqno);
272
273 /*
274 * Execute a CACHE_FLUSH_TS event. This will ensure that the
275 * timestamp is written to the memory and then triggers the interrupt
276 */
277 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
278 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
279 CP_EVENT_WRITE_0_IRQ);
280 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
281 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
282 OUT_RING(ring, submit->seqno);
283
284 trace_msm_gpu_submit_flush(submit,
285 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER));
286
287 a6xx_flush(gpu, ring);
288 }
289
a6xx_emit_set_pseudo_reg(struct msm_ringbuffer * ring,struct a6xx_gpu * a6xx_gpu,struct msm_gpu_submitqueue * queue)290 static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring,
291 struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue)
292 {
293 u64 preempt_postamble;
294
295 OUT_PKT7(ring, CP_SET_PSEUDO_REG, 12);
296
297 OUT_RING(ring, SMMU_INFO);
298 /* don't save SMMU, we write the record from the kernel instead */
299 OUT_RING(ring, 0);
300 OUT_RING(ring, 0);
301
302 /* privileged and non secure buffer save */
303 OUT_RING(ring, NON_SECURE_SAVE_ADDR);
304 OUT_RING(ring, lower_32_bits(
305 a6xx_gpu->preempt_iova[ring->id]));
306 OUT_RING(ring, upper_32_bits(
307 a6xx_gpu->preempt_iova[ring->id]));
308
309 /* user context buffer save, seems to be unnused by fw */
310 OUT_RING(ring, NON_PRIV_SAVE_ADDR);
311 OUT_RING(ring, 0);
312 OUT_RING(ring, 0);
313
314 OUT_RING(ring, COUNTER);
315 /* seems OK to set to 0 to disable it */
316 OUT_RING(ring, 0);
317 OUT_RING(ring, 0);
318
319 /* Emit postamble to clear perfcounters */
320 preempt_postamble = a6xx_gpu->preempt_postamble_iova;
321
322 OUT_PKT7(ring, CP_SET_AMBLE, 3);
323 OUT_RING(ring, lower_32_bits(preempt_postamble));
324 OUT_RING(ring, upper_32_bits(preempt_postamble));
325 OUT_RING(ring, CP_SET_AMBLE_2_DWORDS(
326 a6xx_gpu->preempt_postamble_len) |
327 CP_SET_AMBLE_2_TYPE(KMD_AMBLE_TYPE));
328 }
329
a7xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)330 static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
331 {
332 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
333 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
334 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
335 struct msm_ringbuffer *ring = submit->ring;
336 unsigned int i, ibs = 0;
337
338 /*
339 * Toggle concurrent binning for pagetable switch and set the thread to
340 * BR since only it can execute the pagetable switch packets.
341 */
342 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
343 OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
344
345 a6xx_set_pagetable(a6xx_gpu, ring, submit);
346
347 /*
348 * If preemption is enabled, then set the pseudo register for the save
349 * sequence
350 */
351 if (gpu->nr_rings > 1)
352 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, submit->queue);
353
354 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
355 rbmemptr_stats(ring, index, cpcycles_start));
356 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
357 rbmemptr_stats(ring, index, alwayson_start));
358
359 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
360 OUT_RING(ring, CP_SET_THREAD_BOTH);
361
362 OUT_PKT7(ring, CP_SET_MARKER, 1);
363 OUT_RING(ring, 0x101); /* IFPC disable */
364
365 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) {
366 OUT_PKT7(ring, CP_SET_MARKER, 1);
367 OUT_RING(ring, 0x00d); /* IB1LIST start */
368 }
369
370 /* Submit the commands */
371 for (i = 0; i < submit->nr_cmds; i++) {
372 switch (submit->cmd[i].type) {
373 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
374 break;
375 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
376 if (ring->cur_ctx_seqno == submit->queue->ctx->seqno)
377 break;
378 fallthrough;
379 case MSM_SUBMIT_CMD_BUF:
380 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
381 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
382 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
383 OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size));
384 ibs++;
385 break;
386 }
387
388 /*
389 * Periodically update shadow-wptr if needed, so that we
390 * can see partial progress of submits with large # of
391 * cmds.. otherwise we could needlessly stall waiting for
392 * ringbuffer state, simply due to looking at a shadow
393 * rptr value that has not been updated
394 */
395 if ((ibs % 32) == 0)
396 update_shadow_rptr(gpu, ring);
397 }
398
399 if (submit->queue->flags & MSM_SUBMITQUEUE_ALLOW_PREEMPT) {
400 OUT_PKT7(ring, CP_SET_MARKER, 1);
401 OUT_RING(ring, 0x00e); /* IB1LIST end */
402 }
403
404 get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
405 rbmemptr_stats(ring, index, cpcycles_end));
406 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
407 rbmemptr_stats(ring, index, alwayson_end));
408
409 /* Write the fence to the scratch register */
410 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
411 OUT_RING(ring, submit->seqno);
412
413 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
414 OUT_RING(ring, CP_SET_THREAD_BR);
415
416 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
417 OUT_RING(ring, CCU_INVALIDATE_DEPTH);
418
419 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
420 OUT_RING(ring, CCU_INVALIDATE_COLOR);
421
422 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
423 OUT_RING(ring, CP_SET_THREAD_BV);
424
425 /*
426 * Make sure the timestamp is committed once BV pipe is
427 * completely done with this submission.
428 */
429 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
430 OUT_RING(ring, CACHE_CLEAN | BIT(27));
431 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence)));
432 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence)));
433 OUT_RING(ring, submit->seqno);
434
435 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
436 OUT_RING(ring, CP_SET_THREAD_BR);
437
438 /*
439 * This makes sure that BR doesn't race ahead and commit
440 * timestamp to memstore while BV is still processing
441 * this submission.
442 */
443 OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4);
444 OUT_RING(ring, 0);
445 OUT_RING(ring, lower_32_bits(rbmemptr(ring, bv_fence)));
446 OUT_RING(ring, upper_32_bits(rbmemptr(ring, bv_fence)));
447 OUT_RING(ring, submit->seqno);
448
449 a6xx_gpu->last_seqno[ring->id] = submit->seqno;
450
451 /* write the ringbuffer timestamp */
452 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
453 OUT_RING(ring, CACHE_CLEAN | CP_EVENT_WRITE_0_IRQ | BIT(27));
454 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
455 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
456 OUT_RING(ring, submit->seqno);
457
458 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
459 OUT_RING(ring, CP_SET_THREAD_BOTH);
460
461 OUT_PKT7(ring, CP_SET_MARKER, 1);
462 OUT_RING(ring, 0x100); /* IFPC enable */
463
464 /* If preemption is enabled */
465 if (gpu->nr_rings > 1) {
466 /* Yield the floor on command completion */
467 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4);
468
469 /*
470 * If dword[2:1] are non zero, they specify an address for
471 * the CP to write the value of dword[3] to on preemption
472 * complete. Write 0 to skip the write
473 */
474 OUT_RING(ring, 0x00);
475 OUT_RING(ring, 0x00);
476 /* Data value - not used if the address above is 0 */
477 OUT_RING(ring, 0x01);
478 /* generate interrupt on preemption completion */
479 OUT_RING(ring, 0x00);
480 }
481
482
483 trace_msm_gpu_submit_flush(submit,
484 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER));
485
486 a6xx_flush(gpu, ring);
487
488 /* Check to see if we need to start preemption */
489 a6xx_preempt_trigger(gpu);
490 }
491
a6xx_set_hwcg(struct msm_gpu * gpu,bool state)492 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
493 {
494 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
495 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
496 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
497 const struct adreno_reglist *reg;
498 unsigned int i;
499 u32 cgc_delay, cgc_hyst;
500 u32 val, clock_cntl_on;
501
502 if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
503 return;
504
505 if (adreno_is_a630(adreno_gpu))
506 clock_cntl_on = 0x8aa8aa02;
507 else if (adreno_is_a610(adreno_gpu))
508 clock_cntl_on = 0xaaa8aa82;
509 else if (adreno_is_a702(adreno_gpu))
510 clock_cntl_on = 0xaaaaaa82;
511 else
512 clock_cntl_on = 0x8aa8aa82;
513
514 cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
515 cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
516
517 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
518 state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
519 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
520 state ? cgc_delay : 0);
521 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
522 state ? cgc_hyst : 0);
523
524 if (!adreno_gpu->info->a6xx->hwcg) {
525 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);
526 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0);
527
528 if (state) {
529 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1);
530
531 if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val,
532 val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) {
533 dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n");
534 return;
535 }
536
537 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0);
538 }
539
540 return;
541 }
542
543 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
544
545 /* Don't re-program the registers if they are already correct */
546 if ((!state && !val) || (state && (val == clock_cntl_on)))
547 return;
548
549 /* Disable SP clock before programming HWCG registers */
550 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
551 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
552
553 for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++)
554 gpu_write(gpu, reg->offset, state ? reg->value : 0);
555
556 /* Enable SP clock */
557 if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
558 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
559
560 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
561 }
562
a6xx_set_cp_protect(struct msm_gpu * gpu)563 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
564 {
565 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
566 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect;
567 unsigned i;
568
569 /*
570 * Enable access protection to privileged registers, fault on an access
571 * protect violation and select the last span to protect from the start
572 * address all the way to the end of the register address space
573 */
574 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL,
575 A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN |
576 A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN |
577 A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE);
578
579 for (i = 0; i < protect->count - 1; i++) {
580 /* Intentionally skip writing to some registers */
581 if (protect->regs[i])
582 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), protect->regs[i]);
583 }
584 /* last CP_PROTECT to have "infinite" length on the last entry */
585 gpu_write(gpu, REG_A6XX_CP_PROTECT(protect->count_max - 1), protect->regs[i]);
586 }
587
a6xx_calc_ubwc_config(struct adreno_gpu * gpu)588 static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
589 {
590 gpu->ubwc_config.rgb565_predicator = 0;
591 gpu->ubwc_config.uavflagprd_inv = 0;
592 gpu->ubwc_config.min_acc_len = 0;
593 gpu->ubwc_config.ubwc_swizzle = 0x6;
594 gpu->ubwc_config.macrotile_mode = 0;
595 gpu->ubwc_config.highest_bank_bit = 15;
596
597 if (adreno_is_a610(gpu)) {
598 gpu->ubwc_config.highest_bank_bit = 13;
599 gpu->ubwc_config.min_acc_len = 1;
600 gpu->ubwc_config.ubwc_swizzle = 0x7;
601 }
602
603 if (adreno_is_a618(gpu))
604 gpu->ubwc_config.highest_bank_bit = 14;
605
606 if (adreno_is_a619(gpu))
607 /* TODO: Should be 14 but causes corruption at e.g. 1920x1200 on DP */
608 gpu->ubwc_config.highest_bank_bit = 13;
609
610 if (adreno_is_a619_holi(gpu))
611 gpu->ubwc_config.highest_bank_bit = 13;
612
613 if (adreno_is_a621(gpu)) {
614 gpu->ubwc_config.highest_bank_bit = 13;
615 gpu->ubwc_config.amsbc = 1;
616 gpu->ubwc_config.uavflagprd_inv = 2;
617 }
618
619 if (adreno_is_a623(gpu)) {
620 gpu->ubwc_config.highest_bank_bit = 16;
621 gpu->ubwc_config.amsbc = 1;
622 gpu->ubwc_config.rgb565_predicator = 1;
623 gpu->ubwc_config.uavflagprd_inv = 2;
624 gpu->ubwc_config.macrotile_mode = 1;
625 }
626
627 if (adreno_is_a640_family(gpu))
628 gpu->ubwc_config.amsbc = 1;
629
630 if (adreno_is_a680(gpu))
631 gpu->ubwc_config.macrotile_mode = 1;
632
633 if (adreno_is_a650(gpu) ||
634 adreno_is_a660(gpu) ||
635 adreno_is_a690(gpu) ||
636 adreno_is_a730(gpu) ||
637 adreno_is_a740_family(gpu)) {
638 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
639 gpu->ubwc_config.highest_bank_bit = 16;
640 gpu->ubwc_config.amsbc = 1;
641 gpu->ubwc_config.rgb565_predicator = 1;
642 gpu->ubwc_config.uavflagprd_inv = 2;
643 gpu->ubwc_config.macrotile_mode = 1;
644 }
645
646 if (adreno_is_a663(gpu)) {
647 gpu->ubwc_config.highest_bank_bit = 13;
648 gpu->ubwc_config.amsbc = 1;
649 gpu->ubwc_config.rgb565_predicator = 1;
650 gpu->ubwc_config.uavflagprd_inv = 2;
651 gpu->ubwc_config.macrotile_mode = 1;
652 gpu->ubwc_config.ubwc_swizzle = 0x4;
653 }
654
655 if (adreno_is_7c3(gpu)) {
656 gpu->ubwc_config.highest_bank_bit = 14;
657 gpu->ubwc_config.amsbc = 1;
658 gpu->ubwc_config.rgb565_predicator = 1;
659 gpu->ubwc_config.uavflagprd_inv = 2;
660 gpu->ubwc_config.macrotile_mode = 1;
661 }
662
663 if (adreno_is_a702(gpu)) {
664 gpu->ubwc_config.highest_bank_bit = 14;
665 gpu->ubwc_config.min_acc_len = 1;
666 }
667 }
668
a6xx_set_ubwc_config(struct msm_gpu * gpu)669 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
670 {
671 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
672 /*
673 * We subtract 13 from the highest bank bit (13 is the minimum value
674 * allowed by hw) and write the lowest two bits of the remaining value
675 * as hbb_lo and the one above it as hbb_hi to the hardware.
676 */
677 BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
678 u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
679 u32 hbb_hi = hbb >> 2;
680 u32 hbb_lo = hbb & 3;
681 u32 ubwc_mode = adreno_gpu->ubwc_config.ubwc_swizzle & 1;
682 u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
683
684 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
685 level2_swizzling_dis << 12 |
686 adreno_gpu->ubwc_config.rgb565_predicator << 11 |
687 hbb_hi << 10 | adreno_gpu->ubwc_config.amsbc << 4 |
688 adreno_gpu->ubwc_config.min_acc_len << 3 |
689 hbb_lo << 1 | ubwc_mode);
690
691 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
692 level2_swizzling_dis << 6 | hbb_hi << 4 |
693 adreno_gpu->ubwc_config.min_acc_len << 3 |
694 hbb_lo << 1 | ubwc_mode);
695
696 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
697 level2_swizzling_dis << 12 | hbb_hi << 10 |
698 adreno_gpu->ubwc_config.uavflagprd_inv << 4 |
699 adreno_gpu->ubwc_config.min_acc_len << 3 |
700 hbb_lo << 1 | ubwc_mode);
701
702 if (adreno_is_a7xx(adreno_gpu))
703 gpu_write(gpu, REG_A7XX_GRAS_NC_MODE_CNTL,
704 FIELD_PREP(GENMASK(8, 5), hbb_lo));
705
706 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
707 adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21);
708
709 gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
710 adreno_gpu->ubwc_config.macrotile_mode);
711 }
712
a7xx_patch_pwrup_reglist(struct msm_gpu * gpu)713 static void a7xx_patch_pwrup_reglist(struct msm_gpu *gpu)
714 {
715 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
716 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
717 const struct adreno_reglist_list *reglist;
718 void *ptr = a6xx_gpu->pwrup_reglist_ptr;
719 struct cpu_gpu_lock *lock = ptr;
720 u32 *dest = (u32 *)&lock->regs[0];
721 int i;
722
723 reglist = adreno_gpu->info->a6xx->pwrup_reglist;
724
725 lock->gpu_req = lock->cpu_req = lock->turn = 0;
726 lock->ifpc_list_len = 0;
727 lock->preemption_list_len = reglist->count;
728
729 /*
730 * For each entry in each of the lists, write the offset and the current
731 * register value into the GPU buffer
732 */
733 for (i = 0; i < reglist->count; i++) {
734 *dest++ = reglist->regs[i];
735 *dest++ = gpu_read(gpu, reglist->regs[i]);
736 }
737
738 /*
739 * The overall register list is composed of
740 * 1. Static IFPC-only registers
741 * 2. Static IFPC + preemption registers
742 * 3. Dynamic IFPC + preemption registers (ex: perfcounter selects)
743 *
744 * The first two lists are static. Size of these lists are stored as
745 * number of pairs in ifpc_list_len and preemption_list_len
746 * respectively. With concurrent binning, Some of the perfcounter
747 * registers being virtualized, CP needs to know the pipe id to program
748 * the aperture inorder to restore the same. Thus, third list is a
749 * dynamic list with triplets as
750 * (<aperture, shifted 12 bits> <address> <data>), and the length is
751 * stored as number for triplets in dynamic_list_len.
752 */
753 lock->dynamic_list_len = 0;
754 }
755
a7xx_preempt_start(struct msm_gpu * gpu)756 static int a7xx_preempt_start(struct msm_gpu *gpu)
757 {
758 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
759 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
760 struct msm_ringbuffer *ring = gpu->rb[0];
761
762 if (gpu->nr_rings <= 1)
763 return 0;
764
765 /* Turn CP protection off */
766 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
767 OUT_RING(ring, 0);
768
769 a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL);
770
771 /* Yield the floor on command completion */
772 OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4);
773 OUT_RING(ring, 0x00);
774 OUT_RING(ring, 0x00);
775 OUT_RING(ring, 0x00);
776 /* Generate interrupt on preemption completion */
777 OUT_RING(ring, 0x00);
778
779 a6xx_flush(gpu, ring);
780
781 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
782 }
783
a6xx_cp_init(struct msm_gpu * gpu)784 static int a6xx_cp_init(struct msm_gpu *gpu)
785 {
786 struct msm_ringbuffer *ring = gpu->rb[0];
787
788 OUT_PKT7(ring, CP_ME_INIT, 8);
789
790 OUT_RING(ring, 0x0000002f);
791
792 /* Enable multiple hardware contexts */
793 OUT_RING(ring, 0x00000003);
794
795 /* Enable error detection */
796 OUT_RING(ring, 0x20000000);
797
798 /* Don't enable header dump */
799 OUT_RING(ring, 0x00000000);
800 OUT_RING(ring, 0x00000000);
801
802 /* No workarounds enabled */
803 OUT_RING(ring, 0x00000000);
804
805 /* Pad rest of the cmds with 0's */
806 OUT_RING(ring, 0x00000000);
807 OUT_RING(ring, 0x00000000);
808
809 a6xx_flush(gpu, ring);
810 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
811 }
812
a7xx_cp_init(struct msm_gpu * gpu)813 static int a7xx_cp_init(struct msm_gpu *gpu)
814 {
815 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
816 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
817 struct msm_ringbuffer *ring = gpu->rb[0];
818 u32 mask;
819
820 /* Disable concurrent binning before sending CP init */
821 OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
822 OUT_RING(ring, BIT(27));
823
824 OUT_PKT7(ring, CP_ME_INIT, 7);
825
826 /* Use multiple HW contexts */
827 mask = BIT(0);
828
829 /* Enable error detection */
830 mask |= BIT(1);
831
832 /* Set default reset state */
833 mask |= BIT(3);
834
835 /* Disable save/restore of performance counters across preemption */
836 mask |= BIT(6);
837
838 /* Enable the register init list with the spinlock */
839 mask |= BIT(8);
840
841 OUT_RING(ring, mask);
842
843 /* Enable multiple hardware contexts */
844 OUT_RING(ring, 0x00000003);
845
846 /* Enable error detection */
847 OUT_RING(ring, 0x20000000);
848
849 /* Operation mode mask */
850 OUT_RING(ring, 0x00000002);
851
852 /* *Don't* send a power up reg list for concurrent binning (TODO) */
853 /* Lo address */
854 OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova));
855 /* Hi address */
856 OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova));
857 /* BIT(31) set => read the regs from the list */
858 OUT_RING(ring, BIT(31));
859
860 a6xx_flush(gpu, ring);
861 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
862 }
863
864 /*
865 * Check that the microcode version is new enough to include several key
866 * security fixes. Return true if the ucode is safe.
867 */
a6xx_ucode_check_version(struct a6xx_gpu * a6xx_gpu,struct drm_gem_object * obj)868 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
869 struct drm_gem_object *obj)
870 {
871 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
872 struct msm_gpu *gpu = &adreno_gpu->base;
873 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE];
874 u32 *buf = msm_gem_get_vaddr(obj);
875 bool ret = false;
876
877 if (IS_ERR(buf))
878 return false;
879
880 /* A7xx is safe! */
881 if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu))
882 return true;
883
884 /*
885 * Targets up to a640 (a618, a630 and a640) need to check for a
886 * microcode version that is patched to support the whereami opcode or
887 * one that is new enough to include it by default.
888 *
889 * a650 tier targets don't need whereami but still need to be
890 * equal to or newer than 0.95 for other security fixes
891 *
892 * a660 targets have all the critical security fixes from the start
893 */
894 if (!strcmp(sqe_name, "a630_sqe.fw")) {
895 /*
896 * If the lowest nibble is 0xa that is an indication that this
897 * microcode has been patched. The actual version is in dword
898 * [3] but we only care about the patchlevel which is the lowest
899 * nibble of dword [3]
900 *
901 * Otherwise check that the firmware is greater than or equal
902 * to 1.90 which was the first version that had this fix built
903 * in
904 */
905 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) ||
906 (buf[0] & 0xfff) >= 0x190) {
907 a6xx_gpu->has_whereami = true;
908 ret = true;
909 goto out;
910 }
911
912 DRM_DEV_ERROR(&gpu->pdev->dev,
913 "a630 SQE ucode is too old. Have version %x need at least %x\n",
914 buf[0] & 0xfff, 0x190);
915 } else if (!strcmp(sqe_name, "a650_sqe.fw")) {
916 if ((buf[0] & 0xfff) >= 0x095) {
917 ret = true;
918 goto out;
919 }
920
921 DRM_DEV_ERROR(&gpu->pdev->dev,
922 "a650 SQE ucode is too old. Have version %x need at least %x\n",
923 buf[0] & 0xfff, 0x095);
924 } else if (!strcmp(sqe_name, "a660_sqe.fw")) {
925 ret = true;
926 } else {
927 DRM_DEV_ERROR(&gpu->pdev->dev,
928 "unknown GPU, add it to a6xx_ucode_check_version()!!\n");
929 }
930 out:
931 msm_gem_put_vaddr(obj);
932 return ret;
933 }
934
a6xx_ucode_load(struct msm_gpu * gpu)935 static int a6xx_ucode_load(struct msm_gpu *gpu)
936 {
937 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
938 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
939
940 if (!a6xx_gpu->sqe_bo) {
941 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
942 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
943
944 if (IS_ERR(a6xx_gpu->sqe_bo)) {
945 int ret = PTR_ERR(a6xx_gpu->sqe_bo);
946
947 a6xx_gpu->sqe_bo = NULL;
948 DRM_DEV_ERROR(&gpu->pdev->dev,
949 "Could not allocate SQE ucode: %d\n", ret);
950
951 return ret;
952 }
953
954 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
955 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
956 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
957 drm_gem_object_put(a6xx_gpu->sqe_bo);
958
959 a6xx_gpu->sqe_bo = NULL;
960 return -EPERM;
961 }
962 }
963
964 /*
965 * Expanded APRIV and targets that support WHERE_AM_I both need a
966 * privileged buffer to store the RPTR shadow
967 */
968 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) &&
969 !a6xx_gpu->shadow_bo) {
970 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
971 sizeof(u32) * gpu->nr_rings,
972 MSM_BO_WC | MSM_BO_MAP_PRIV,
973 gpu->aspace, &a6xx_gpu->shadow_bo,
974 &a6xx_gpu->shadow_iova);
975
976 if (IS_ERR(a6xx_gpu->shadow))
977 return PTR_ERR(a6xx_gpu->shadow);
978
979 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow");
980 }
981
982 a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE,
983 MSM_BO_WC | MSM_BO_MAP_PRIV,
984 gpu->aspace, &a6xx_gpu->pwrup_reglist_bo,
985 &a6xx_gpu->pwrup_reglist_iova);
986
987 if (IS_ERR(a6xx_gpu->pwrup_reglist_ptr))
988 return PTR_ERR(a6xx_gpu->pwrup_reglist_ptr);
989
990 msm_gem_object_set_name(a6xx_gpu->pwrup_reglist_bo, "pwrup_reglist");
991
992 return 0;
993 }
994
a6xx_zap_shader_init(struct msm_gpu * gpu)995 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
996 {
997 static bool loaded;
998 int ret;
999
1000 if (loaded)
1001 return 0;
1002
1003 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
1004
1005 loaded = !ret;
1006 return ret;
1007 }
1008
1009 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
1010 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
1011 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
1012 A6XX_RBBM_INT_0_MASK_CP_IB2 | \
1013 A6XX_RBBM_INT_0_MASK_CP_IB1 | \
1014 A6XX_RBBM_INT_0_MASK_CP_RB | \
1015 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
1016 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
1017 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
1018 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
1019 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
1020
1021 #define A7XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
1022 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
1023 A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR | \
1024 A6XX_RBBM_INT_0_MASK_CP_SW | \
1025 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
1026 A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT | \
1027 A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS | \
1028 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
1029 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
1030 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
1031 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
1032 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
1033 A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
1034 A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
1035
1036 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
1037 A6XX_CP_APRIV_CNTL_RBFETCH | \
1038 A6XX_CP_APRIV_CNTL_RBPRIVLEVEL | \
1039 A6XX_CP_APRIV_CNTL_RBRPWB)
1040
1041 #define A7XX_BR_APRIVMASK (A7XX_APRIV_MASK | \
1042 A6XX_CP_APRIV_CNTL_CDREAD | \
1043 A6XX_CP_APRIV_CNTL_CDWRITE)
1044
hw_init(struct msm_gpu * gpu)1045 static int hw_init(struct msm_gpu *gpu)
1046 {
1047 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1048 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1049 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1050 u64 gmem_range_min;
1051 unsigned int i;
1052 int ret;
1053
1054 if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1055 /* Make sure the GMU keeps the GPU on while we set it up */
1056 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
1057 if (ret)
1058 return ret;
1059 }
1060
1061 /* Clear GBIF halt in case GX domain was not collapsed */
1062 if (adreno_is_a619_holi(adreno_gpu)) {
1063 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
1064 gpu_read(gpu, REG_A6XX_GBIF_HALT);
1065
1066 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0);
1067 gpu_read(gpu, REG_A6XX_RBBM_GPR0_CNTL);
1068 } else if (a6xx_has_gbif(adreno_gpu)) {
1069 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);
1070 gpu_read(gpu, REG_A6XX_GBIF_HALT);
1071
1072 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
1073 gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT);
1074 }
1075
1076 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
1077
1078 if (adreno_is_a619_holi(adreno_gpu))
1079 a6xx_sptprac_enable(gmu);
1080
1081 /*
1082 * Disable the trusted memory range - we don't actually supported secure
1083 * memory rendering at this point in time and we don't want to block off
1084 * part of the virtual memory space.
1085 */
1086 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000);
1087 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
1088
1089 if (!adreno_is_a7xx(adreno_gpu)) {
1090 /* Turn on 64 bit addressing for all blocks */
1091 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
1092 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
1093 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
1094 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
1095 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
1096 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
1097 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
1098 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
1099 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
1100 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
1101 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
1102 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
1103 }
1104
1105 /* enable hardware clockgating */
1106 a6xx_set_hwcg(gpu, true);
1107
1108 /* VBIF/GBIF start*/
1109 if (adreno_is_a610_family(adreno_gpu) ||
1110 adreno_is_a640_family(adreno_gpu) ||
1111 adreno_is_a650_family(adreno_gpu) ||
1112 adreno_is_a7xx(adreno_gpu)) {
1113 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
1114 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
1115 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
1116 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1117 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
1118 adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3);
1119 } else {
1120 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
1121 }
1122
1123 if (adreno_is_a630(adreno_gpu))
1124 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
1125
1126 if (adreno_is_a7xx(adreno_gpu))
1127 gpu_write(gpu, REG_A6XX_UCHE_GBIF_GX_CONFIG, 0x10240e0);
1128
1129 /* Make all blocks contribute to the GPU BUSY perf counter */
1130 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
1131
1132 /* Disable L2 bypass in the UCHE */
1133 if (adreno_is_a7xx(adreno_gpu)) {
1134 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base);
1135 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);
1136 } else {
1137 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0);
1138 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base);
1139 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base);
1140 }
1141
1142 if (!(adreno_is_a650_family(adreno_gpu) ||
1143 adreno_is_a702(adreno_gpu) ||
1144 adreno_is_a730(adreno_gpu))) {
1145 gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M;
1146
1147 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
1148 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min);
1149
1150 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX,
1151 gmem_range_min + adreno_gpu->info->gmem - 1);
1152 }
1153
1154 if (adreno_is_a7xx(adreno_gpu))
1155 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, BIT(23));
1156 else {
1157 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
1158 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
1159 }
1160
1161 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {
1162 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1163 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
1164 } else if (adreno_is_a610_family(adreno_gpu)) {
1165 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);
1166 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);
1167 } else if (!adreno_is_a7xx(adreno_gpu)) {
1168 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
1169 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
1170 }
1171
1172 if (adreno_is_a660_family(adreno_gpu))
1173 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
1174
1175 /* Setting the mem pool size */
1176 if (adreno_is_a610(adreno_gpu)) {
1177 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
1178 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
1179 } else if (adreno_is_a702(adreno_gpu)) {
1180 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64);
1181 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63);
1182 } else if (!adreno_is_a7xx(adreno_gpu))
1183 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
1184
1185
1186 /* Set the default primFifo threshold values */
1187 if (adreno_gpu->info->a6xx->prim_fifo_threshold)
1188 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL,
1189 adreno_gpu->info->a6xx->prim_fifo_threshold);
1190
1191 /* Set the AHB default slave response to "ERROR" */
1192 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
1193
1194 /* Turn on performance counters */
1195 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
1196
1197 if (adreno_is_a7xx(adreno_gpu)) {
1198 /* Turn on the IFPC counter (countable 4 on XOCLK4) */
1199 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1,
1200 FIELD_PREP(GENMASK(7, 0), 0x4));
1201 }
1202
1203 /* Select CP0 to always count cycles */
1204 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
1205
1206 a6xx_set_ubwc_config(gpu);
1207
1208 /* Enable fault detection */
1209 if (adreno_is_a730(adreno_gpu) ||
1210 adreno_is_a740_family(adreno_gpu))
1211 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
1212 else if (adreno_is_a690(adreno_gpu))
1213 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff);
1214 else if (adreno_is_a619(adreno_gpu))
1215 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff);
1216 else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
1217 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff);
1218 else
1219 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff);
1220
1221 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, BIT(7) | 0x1);
1222
1223 /* Set weights for bicubic filtering */
1224 if (adreno_is_a650_family(adreno_gpu) || adreno_is_x185(adreno_gpu)) {
1225 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
1226 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
1227 0x3fe05ff4);
1228 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
1229 0x3fa0ebee);
1230 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
1231 0x3f5193ed);
1232 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
1233 0x3f0243f0);
1234 }
1235
1236 /* Set up the CX GMU counter 0 to count busy ticks */
1237 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
1238
1239 /* Enable the power counter */
1240 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5));
1241 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
1242
1243 /* Protect registers from the CP */
1244 a6xx_set_cp_protect(gpu);
1245
1246 if (adreno_is_a660_family(adreno_gpu)) {
1247 if (adreno_is_a690(adreno_gpu))
1248 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x00028801);
1249 else
1250 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
1251 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
1252 } else if (adreno_is_a702(adreno_gpu)) {
1253 /* Something to do with the HLSQ cluster */
1254 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24));
1255 }
1256
1257 if (adreno_is_a690(adreno_gpu))
1258 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x90);
1259 /* Set dualQ + disable afull for A660 GPU */
1260 else if (adreno_is_a660(adreno_gpu) || adreno_is_a663(adreno_gpu))
1261 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
1262 else if (adreno_is_a7xx(adreno_gpu))
1263 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG,
1264 FIELD_PREP(GENMASK(19, 16), 6) |
1265 FIELD_PREP(GENMASK(15, 12), 6) |
1266 FIELD_PREP(GENMASK(11, 8), 9) |
1267 BIT(3) | BIT(2) |
1268 FIELD_PREP(GENMASK(1, 0), 2));
1269
1270 /* Enable expanded apriv for targets that support it */
1271 if (gpu->hw_apriv) {
1272 if (adreno_is_a7xx(adreno_gpu)) {
1273 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1274 A7XX_BR_APRIVMASK);
1275 gpu_write(gpu, REG_A7XX_CP_BV_APRIV_CNTL,
1276 A7XX_APRIV_MASK);
1277 gpu_write(gpu, REG_A7XX_CP_LPAC_APRIV_CNTL,
1278 A7XX_APRIV_MASK);
1279 } else
1280 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1281 BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1));
1282 }
1283
1284 if (adreno_is_a750(adreno_gpu)) {
1285 /* Disable ubwc merged UFC request feature */
1286 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19));
1287
1288 /* Enable TP flaghint and other performance settings */
1289 gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700);
1290 } else if (adreno_is_a7xx(adreno_gpu)) {
1291 /* Disable non-ubwc read reqs from passing write reqs */
1292 gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11));
1293 }
1294
1295 /* Enable interrupts */
1296 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK,
1297 adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);
1298
1299 ret = adreno_hw_init(gpu);
1300 if (ret)
1301 goto out;
1302
1303 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova);
1304
1305 /* Set the ringbuffer address */
1306 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova);
1307
1308 /* Targets that support extended APRIV can use the RPTR shadow from
1309 * hardware but all the other ones need to disable the feature. Targets
1310 * that support the WHERE_AM_I opcode can use that instead
1311 */
1312 if (adreno_gpu->base.hw_apriv)
1313 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
1314 else
1315 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
1316 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
1317
1318 /* Configure the RPTR shadow if needed: */
1319 if (a6xx_gpu->shadow_bo) {
1320 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR,
1321 shadowptr(a6xx_gpu, gpu->rb[0]));
1322 for (unsigned int i = 0; i < gpu->nr_rings; i++)
1323 a6xx_gpu->shadow[i] = 0;
1324 }
1325
1326 /* ..which means "always" on A7xx, also for BV shadow */
1327 if (adreno_is_a7xx(adreno_gpu)) {
1328 gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR,
1329 rbmemptr(gpu->rb[0], bv_rptr));
1330 }
1331
1332 a6xx_preempt_hw_init(gpu);
1333
1334 /* Always come up on rb 0 */
1335 a6xx_gpu->cur_ring = gpu->rb[0];
1336
1337 for (i = 0; i < gpu->nr_rings; i++)
1338 gpu->rb[i]->cur_ctx_seqno = 0;
1339
1340 /* Enable the SQE_to start the CP engine */
1341 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
1342
1343 if (adreno_is_a7xx(adreno_gpu) && !a6xx_gpu->pwrup_reglist_emitted) {
1344 a7xx_patch_pwrup_reglist(gpu);
1345 a6xx_gpu->pwrup_reglist_emitted = true;
1346 }
1347
1348 ret = adreno_is_a7xx(adreno_gpu) ? a7xx_cp_init(gpu) : a6xx_cp_init(gpu);
1349 if (ret)
1350 goto out;
1351
1352 /*
1353 * Try to load a zap shader into the secure world. If successful
1354 * we can use the CP to switch out of secure mode. If not then we
1355 * have no resource but to try to switch ourselves out manually. If we
1356 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
1357 * be blocked and a permissions violation will soon follow.
1358 */
1359 ret = a6xx_zap_shader_init(gpu);
1360 if (!ret) {
1361 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
1362 OUT_RING(gpu->rb[0], 0x00000000);
1363
1364 a6xx_flush(gpu, gpu->rb[0]);
1365 if (!a6xx_idle(gpu, gpu->rb[0]))
1366 return -EINVAL;
1367 } else if (ret == -ENODEV) {
1368 /*
1369 * This device does not use zap shader (but print a warning
1370 * just in case someone got their dt wrong.. hopefully they
1371 * have a debug UART to realize the error of their ways...
1372 * if you mess this up you are about to crash horribly)
1373 */
1374 dev_warn_once(gpu->dev->dev,
1375 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
1376 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
1377 ret = 0;
1378 } else {
1379 return ret;
1380 }
1381
1382 out:
1383 if (adreno_has_gmu_wrapper(adreno_gpu))
1384 return ret;
1385
1386 /* Last step - yield the ringbuffer */
1387 a7xx_preempt_start(gpu);
1388
1389 /*
1390 * Tell the GMU that we are done touching the GPU and it can start power
1391 * management
1392 */
1393 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
1394
1395 if (a6xx_gpu->gmu.legacy) {
1396 /* Take the GMU out of its special boot mode */
1397 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
1398 }
1399
1400 return ret;
1401 }
1402
a6xx_hw_init(struct msm_gpu * gpu)1403 static int a6xx_hw_init(struct msm_gpu *gpu)
1404 {
1405 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1406 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1407 int ret;
1408
1409 mutex_lock(&a6xx_gpu->gmu.lock);
1410 ret = hw_init(gpu);
1411 mutex_unlock(&a6xx_gpu->gmu.lock);
1412
1413 return ret;
1414 }
1415
a6xx_dump(struct msm_gpu * gpu)1416 static void a6xx_dump(struct msm_gpu *gpu)
1417 {
1418 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n",
1419 gpu_read(gpu, REG_A6XX_RBBM_STATUS));
1420 adreno_dump(gpu);
1421 }
1422
a6xx_recover(struct msm_gpu * gpu)1423 static void a6xx_recover(struct msm_gpu *gpu)
1424 {
1425 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1426 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1427 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1428 int i, active_submits;
1429
1430 adreno_dump_info(gpu);
1431
1432 for (i = 0; i < 8; i++)
1433 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
1434 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
1435
1436 if (hang_debug)
1437 a6xx_dump(gpu);
1438
1439 /*
1440 * To handle recovery specific sequences during the rpm suspend we are
1441 * about to trigger
1442 */
1443 a6xx_gpu->hung = true;
1444
1445 /* Halt SQE first */
1446 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
1447
1448 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev);
1449
1450 /* active_submit won't change until we make a submission */
1451 mutex_lock(&gpu->active_lock);
1452 active_submits = gpu->active_submits;
1453
1454 /*
1455 * Temporarily clear active_submits count to silence a WARN() in the
1456 * runtime suspend cb
1457 */
1458 gpu->active_submits = 0;
1459
1460 if (adreno_has_gmu_wrapper(adreno_gpu)) {
1461 /* Drain the outstanding traffic on memory buses */
1462 a6xx_bus_clear_pending_transactions(adreno_gpu, true);
1463
1464 /* Reset the GPU to a clean state */
1465 a6xx_gpu_sw_reset(gpu, true);
1466 a6xx_gpu_sw_reset(gpu, false);
1467 }
1468
1469 reinit_completion(&gmu->pd_gate);
1470 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb);
1471 dev_pm_genpd_synced_poweroff(gmu->cxpd);
1472
1473 /* Drop the rpm refcount from active submits */
1474 if (active_submits)
1475 pm_runtime_put(&gpu->pdev->dev);
1476
1477 /* And the final one from recover worker */
1478 pm_runtime_put_sync(&gpu->pdev->dev);
1479
1480 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000)))
1481 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n");
1482
1483 dev_pm_genpd_remove_notifier(gmu->cxpd);
1484
1485 pm_runtime_use_autosuspend(&gpu->pdev->dev);
1486
1487 if (active_submits)
1488 pm_runtime_get(&gpu->pdev->dev);
1489
1490 pm_runtime_get_sync(&gpu->pdev->dev);
1491
1492 gpu->active_submits = active_submits;
1493 mutex_unlock(&gpu->active_lock);
1494
1495 msm_gpu_hw_init(gpu);
1496 a6xx_gpu->hung = false;
1497 }
1498
a6xx_uche_fault_block(struct msm_gpu * gpu,u32 mid)1499 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
1500 {
1501 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1502 static const char *uche_clients[7] = {
1503 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
1504 };
1505 u32 val;
1506
1507 if (adreno_is_a7xx(adreno_gpu)) {
1508 if (mid != 1 && mid != 2 && mid != 3 && mid != 8)
1509 return "UNKNOWN";
1510 } else {
1511 if (mid < 1 || mid > 3)
1512 return "UNKNOWN";
1513 }
1514
1515 /*
1516 * The source of the data depends on the mid ID read from FSYNR1.
1517 * and the client ID read from the UCHE block
1518 */
1519 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
1520
1521 if (adreno_is_a7xx(adreno_gpu)) {
1522 /* Bit 3 for mid=3 indicates BR or BV */
1523 static const char *uche_clients_a7xx[16] = {
1524 "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC",
1525 "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP",
1526 "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC",
1527 "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP",
1528 };
1529
1530 /* LPAC has the same clients as BR and BV, but because it is
1531 * compute-only some of them do not exist and there are holes
1532 * in the array.
1533 */
1534 static const char *uche_clients_lpac_a7xx[8] = {
1535 "-", "LPAC_SP", "-", "-",
1536 "LPAC_HLSQ", "-", "-", "LPAC_TP",
1537 };
1538
1539 val &= GENMASK(6, 0);
1540
1541 /* mid=3 refers to BR or BV */
1542 if (mid == 3) {
1543 if (val < ARRAY_SIZE(uche_clients_a7xx))
1544 return uche_clients_a7xx[val];
1545 else
1546 return "UCHE";
1547 }
1548
1549 /* mid=8 refers to LPAC */
1550 if (mid == 8) {
1551 if (val < ARRAY_SIZE(uche_clients_lpac_a7xx))
1552 return uche_clients_lpac_a7xx[val];
1553 else
1554 return "UCHE_LPAC";
1555 }
1556
1557 /* mid=2 is a catchall for everything else in LPAC */
1558 if (mid == 2)
1559 return "UCHE_LPAC";
1560
1561 /* mid=1 is a catchall for everything else in BR/BV */
1562 return "UCHE";
1563 } else if (adreno_is_a660_family(adreno_gpu)) {
1564 static const char *uche_clients_a660[8] = {
1565 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP",
1566 };
1567
1568 static const char *uche_clients_a660_not[8] = {
1569 "not VFD", "not SP", "not VSC", "not VPC",
1570 "not HLSQ", "not PC", "not LRZ", "not TP",
1571 };
1572
1573 val &= GENMASK(6, 0);
1574
1575 if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660))
1576 return uche_clients_a660[val];
1577
1578 if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not))
1579 return uche_clients_a660_not[val];
1580
1581 return "UCHE";
1582 } else {
1583 /* mid = 3 is most precise and refers to only one block per client */
1584 if (mid == 3)
1585 return uche_clients[val & 7];
1586
1587 /* For mid=2 the source is TP or VFD except when the client id is 0 */
1588 if (mid == 2)
1589 return ((val & 7) == 0) ? "TP" : "TP|VFD";
1590
1591 /* For mid=1 just return "UCHE" as a catchall for everything else */
1592 return "UCHE";
1593 }
1594 }
1595
a6xx_fault_block(struct msm_gpu * gpu,u32 id)1596 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
1597 {
1598 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1599
1600 if (id == 0)
1601 return "CP";
1602 else if (id == 4)
1603 return "CCU";
1604 else if (id == 6)
1605 return "CDP Prefetch";
1606 else if (id == 7)
1607 return "GMU";
1608 else if (id == 5 && adreno_is_a7xx(adreno_gpu))
1609 return "Flag cache";
1610
1611 return a6xx_uche_fault_block(gpu, id);
1612 }
1613
a6xx_fault_handler(void * arg,unsigned long iova,int flags,void * data)1614 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
1615 {
1616 struct msm_gpu *gpu = arg;
1617 struct adreno_smmu_fault_info *info = data;
1618 const char *block = "unknown";
1619
1620 u32 scratch[] = {
1621 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1622 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1623 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1624 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),
1625 };
1626
1627 if (info)
1628 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
1629
1630 return adreno_fault_handler(gpu, iova, flags, info, block, scratch);
1631 }
1632
a6xx_cp_hw_err_irq(struct msm_gpu * gpu)1633 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
1634 {
1635 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
1636
1637 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
1638 u32 val;
1639
1640 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1641 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
1642 dev_err_ratelimited(&gpu->pdev->dev,
1643 "CP | opcode error | possible opcode=0x%8.8X\n",
1644 val);
1645 }
1646
1647 if (status & A6XX_CP_INT_CP_UCODE_ERROR)
1648 dev_err_ratelimited(&gpu->pdev->dev,
1649 "CP ucode error interrupt\n");
1650
1651 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
1652 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
1653 gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
1654
1655 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
1656 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1657
1658 dev_err_ratelimited(&gpu->pdev->dev,
1659 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1660 val & (1 << 20) ? "READ" : "WRITE",
1661 (val & 0x3ffff), val);
1662 }
1663
1664 if (status & A6XX_CP_INT_CP_AHB_ERROR && !adreno_is_a7xx(to_adreno_gpu(gpu)))
1665 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1666
1667 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1668 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1669
1670 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1671 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1672
1673 }
1674
a6xx_fault_detect_irq(struct msm_gpu * gpu)1675 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1676 {
1677 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1678 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1679 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1680
1681 /*
1682 * If stalled on SMMU fault, we could trip the GPU's hang detection,
1683 * but the fault handler will trigger the devcore dump, and we want
1684 * to otherwise resume normally rather than killing the submit, so
1685 * just bail.
1686 */
1687 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
1688 return;
1689
1690 /*
1691 * Force the GPU to stay on until after we finish
1692 * collecting information
1693 */
1694 if (!adreno_has_gmu_wrapper(adreno_gpu))
1695 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1696
1697 DRM_DEV_ERROR(&gpu->pdev->dev,
1698 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1699 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0,
1700 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1701 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1702 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1703 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
1704 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1705 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
1706 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1707
1708 /* Turn off the hangcheck timer to keep it from bothering us */
1709 timer_delete(&gpu->hangcheck_timer);
1710
1711 kthread_queue_work(gpu->worker, &gpu->recover_work);
1712 }
1713
a7xx_sw_fuse_violation_irq(struct msm_gpu * gpu)1714 static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
1715 {
1716 u32 status;
1717
1718 status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
1719 gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
1720
1721 dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
1722
1723 /*
1724 * Ignore FASTBLEND violations, because the HW will silently fall back
1725 * to legacy blending.
1726 */
1727 if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
1728 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
1729 timer_delete(&gpu->hangcheck_timer);
1730
1731 kthread_queue_work(gpu->worker, &gpu->recover_work);
1732 }
1733 }
1734
a6xx_irq(struct msm_gpu * gpu)1735 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1736 {
1737 struct msm_drm_private *priv = gpu->dev->dev_private;
1738 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1739
1740 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1741
1742 if (priv->disable_err_irq)
1743 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
1744
1745 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1746 a6xx_fault_detect_irq(gpu);
1747
1748 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1749 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1750
1751 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1752 a6xx_cp_hw_err_irq(gpu);
1753
1754 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1755 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1756
1757 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1758 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1759
1760 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1761 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1762
1763 if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
1764 a7xx_sw_fuse_violation_irq(gpu);
1765
1766 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) {
1767 msm_gpu_retire(gpu);
1768 a6xx_preempt_trigger(gpu);
1769 }
1770
1771 if (status & A6XX_RBBM_INT_0_MASK_CP_SW)
1772 a6xx_preempt_irq(gpu);
1773
1774 return IRQ_HANDLED;
1775 }
1776
a6xx_llc_deactivate(struct a6xx_gpu * a6xx_gpu)1777 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
1778 {
1779 llcc_slice_deactivate(a6xx_gpu->llc_slice);
1780 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
1781 }
1782
a6xx_llc_activate(struct a6xx_gpu * a6xx_gpu)1783 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1784 {
1785 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1786 struct msm_gpu *gpu = &adreno_gpu->base;
1787 u32 cntl1_regval = 0;
1788
1789 if (IS_ERR(a6xx_gpu->llc_mmio))
1790 return;
1791
1792 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1793 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1794
1795 gpu_scid &= 0x1f;
1796 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
1797 (gpu_scid << 15) | (gpu_scid << 20);
1798
1799 /* On A660, the SCID programming for UCHE traffic is done in
1800 * A6XX_GBIF_SCACHE_CNTL0[14:10]
1801 */
1802 if (adreno_is_a660_family(adreno_gpu))
1803 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
1804 (1 << 8), (gpu_scid << 10) | (1 << 8));
1805 }
1806
1807 /*
1808 * For targets with a MMU500, activate the slice but don't program the
1809 * register. The XBL will take care of that.
1810 */
1811 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
1812 if (!a6xx_gpu->have_mmu500) {
1813 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
1814
1815 gpuhtw_scid &= 0x1f;
1816 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
1817 }
1818 }
1819
1820 if (!cntl1_regval)
1821 return;
1822
1823 /*
1824 * Program the slice IDs for the various GPU blocks and GPU MMU
1825 * pagetables
1826 */
1827 if (!a6xx_gpu->have_mmu500) {
1828 a6xx_llc_write(a6xx_gpu,
1829 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
1830
1831 /*
1832 * Program cacheability overrides to not allocate cache
1833 * lines on a write miss
1834 */
1835 a6xx_llc_rmw(a6xx_gpu,
1836 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
1837 return;
1838 }
1839
1840 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
1841 }
1842
a7xx_llc_activate(struct a6xx_gpu * a6xx_gpu)1843 static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1844 {
1845 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1846 struct msm_gpu *gpu = &adreno_gpu->base;
1847
1848 if (IS_ERR(a6xx_gpu->llc_mmio))
1849 return;
1850
1851 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1852 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1853
1854 gpu_scid &= GENMASK(4, 0);
1855
1856 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL1,
1857 FIELD_PREP(GENMASK(29, 25), gpu_scid) |
1858 FIELD_PREP(GENMASK(24, 20), gpu_scid) |
1859 FIELD_PREP(GENMASK(19, 15), gpu_scid) |
1860 FIELD_PREP(GENMASK(14, 10), gpu_scid) |
1861 FIELD_PREP(GENMASK(9, 5), gpu_scid) |
1862 FIELD_PREP(GENMASK(4, 0), gpu_scid));
1863
1864 gpu_write(gpu, REG_A6XX_GBIF_SCACHE_CNTL0,
1865 FIELD_PREP(GENMASK(14, 10), gpu_scid) |
1866 BIT(8));
1867 }
1868
1869 llcc_slice_activate(a6xx_gpu->htw_llc_slice);
1870 }
1871
a6xx_llc_slices_destroy(struct a6xx_gpu * a6xx_gpu)1872 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
1873 {
1874 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
1875 if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
1876 return;
1877
1878 llcc_slice_putd(a6xx_gpu->llc_slice);
1879 llcc_slice_putd(a6xx_gpu->htw_llc_slice);
1880 }
1881
a6xx_llc_slices_init(struct platform_device * pdev,struct a6xx_gpu * a6xx_gpu,bool is_a7xx)1882 static void a6xx_llc_slices_init(struct platform_device *pdev,
1883 struct a6xx_gpu *a6xx_gpu, bool is_a7xx)
1884 {
1885 struct device_node *phandle;
1886
1887 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
1888 if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
1889 return;
1890
1891 /*
1892 * There is a different programming path for A6xx targets with an
1893 * mmu500 attached, so detect if that is the case
1894 */
1895 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
1896 a6xx_gpu->have_mmu500 = (phandle &&
1897 of_device_is_compatible(phandle, "arm,mmu-500"));
1898 of_node_put(phandle);
1899
1900 if (is_a7xx || !a6xx_gpu->have_mmu500)
1901 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem");
1902 else
1903 a6xx_gpu->llc_mmio = NULL;
1904
1905 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1906 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1907
1908 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1909 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
1910 }
1911
a7xx_cx_mem_init(struct a6xx_gpu * a6xx_gpu)1912 static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
1913 {
1914 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1915 struct msm_gpu *gpu = &adreno_gpu->base;
1916 u32 fuse_val;
1917 int ret;
1918
1919 if (adreno_is_a750(adreno_gpu)) {
1920 /*
1921 * Assume that if qcom scm isn't available, that whatever
1922 * replacement allows writing the fuse register ourselves.
1923 * Users of alternative firmware need to make sure this
1924 * register is writeable or indicate that it's not somehow.
1925 * Print a warning because if you mess this up you're about to
1926 * crash horribly.
1927 */
1928 if (!qcom_scm_is_available()) {
1929 dev_warn_once(gpu->dev->dev,
1930 "SCM is not available, poking fuse register\n");
1931 a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
1932 A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
1933 A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
1934 A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
1935 adreno_gpu->has_ray_tracing = true;
1936 return 0;
1937 }
1938
1939 ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ |
1940 QCOM_SCM_GPU_TSENSE_EN_REQ);
1941 if (ret)
1942 return ret;
1943
1944 /*
1945 * On a750 raytracing may be disabled by the firmware, find out
1946 * whether that's the case. The scm call above sets the fuse
1947 * register.
1948 */
1949 fuse_val = a6xx_llc_read(a6xx_gpu,
1950 REG_A7XX_CX_MISC_SW_FUSE_VALUE);
1951 adreno_gpu->has_ray_tracing =
1952 !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
1953 } else if (adreno_is_a740(adreno_gpu)) {
1954 /* Raytracing is always enabled on a740 */
1955 adreno_gpu->has_ray_tracing = true;
1956 }
1957
1958 return 0;
1959 }
1960
1961
1962 #define GBIF_CLIENT_HALT_MASK BIT(0)
1963 #define GBIF_ARB_HALT_MASK BIT(1)
1964 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0)
1965 #define VBIF_RESET_ACK_MASK 0xF0
1966 #define GPR0_GBIF_HALT_REQUEST 0x1E0
1967
a6xx_bus_clear_pending_transactions(struct adreno_gpu * adreno_gpu,bool gx_off)1968 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off)
1969 {
1970 struct msm_gpu *gpu = &adreno_gpu->base;
1971
1972 if (adreno_is_a619_holi(adreno_gpu)) {
1973 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST);
1974 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &
1975 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK);
1976 } else if (!a6xx_has_gbif(adreno_gpu)) {
1977 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK);
1978 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
1979 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK);
1980 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1981
1982 return;
1983 }
1984
1985 if (gx_off) {
1986 /* Halt the gx side of GBIF */
1987 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
1988 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
1989 }
1990
1991 /* Halt new client requests on GBIF */
1992 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1993 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1994 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1995
1996 /* Halt all AXI requests on GBIF */
1997 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1998 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1999 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
2000
2001 /* The GBIF halt needs to be explicitly cleared */
2002 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
2003 }
2004
a6xx_gpu_sw_reset(struct msm_gpu * gpu,bool assert)2005 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert)
2006 {
2007 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */
2008 if (adreno_is_a610(to_adreno_gpu(gpu)))
2009 return;
2010
2011 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert);
2012 /* Perform a bogus read and add a brief delay to ensure ordering. */
2013 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD);
2014 udelay(1);
2015
2016 /* The reset line needs to be asserted for at least 100 us */
2017 if (assert)
2018 udelay(100);
2019 }
2020
a6xx_gmu_pm_resume(struct msm_gpu * gpu)2021 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu)
2022 {
2023 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2024 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2025 int ret;
2026
2027 gpu->needs_hw_init = true;
2028
2029 trace_msm_gpu_resume(0);
2030
2031 mutex_lock(&a6xx_gpu->gmu.lock);
2032 ret = a6xx_gmu_resume(a6xx_gpu);
2033 mutex_unlock(&a6xx_gpu->gmu.lock);
2034 if (ret)
2035 return ret;
2036
2037 msm_devfreq_resume(gpu);
2038
2039 adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu);
2040
2041 return ret;
2042 }
2043
a6xx_pm_resume(struct msm_gpu * gpu)2044 static int a6xx_pm_resume(struct msm_gpu *gpu)
2045 {
2046 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2047 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2048 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2049 unsigned long freq = gpu->fast_rate;
2050 struct dev_pm_opp *opp;
2051 int ret;
2052
2053 gpu->needs_hw_init = true;
2054
2055 trace_msm_gpu_resume(0);
2056
2057 mutex_lock(&a6xx_gpu->gmu.lock);
2058
2059 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq);
2060 if (IS_ERR(opp)) {
2061 ret = PTR_ERR(opp);
2062 goto err_set_opp;
2063 }
2064 dev_pm_opp_put(opp);
2065
2066 /* Set the core clock and bus bw, having VDD scaling in mind */
2067 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
2068
2069 pm_runtime_resume_and_get(gmu->dev);
2070 pm_runtime_resume_and_get(gmu->gxpd);
2071
2072 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
2073 if (ret)
2074 goto err_bulk_clk;
2075
2076 if (adreno_is_a619_holi(adreno_gpu))
2077 a6xx_sptprac_enable(gmu);
2078
2079 /* If anything goes south, tear the GPU down piece by piece.. */
2080 if (ret) {
2081 err_bulk_clk:
2082 pm_runtime_put(gmu->gxpd);
2083 pm_runtime_put(gmu->dev);
2084 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
2085 }
2086 err_set_opp:
2087 mutex_unlock(&a6xx_gpu->gmu.lock);
2088
2089 if (!ret)
2090 msm_devfreq_resume(gpu);
2091
2092 return ret;
2093 }
2094
a6xx_gmu_pm_suspend(struct msm_gpu * gpu)2095 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu)
2096 {
2097 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2098 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2099 int i, ret;
2100
2101 trace_msm_gpu_suspend(0);
2102
2103 a6xx_llc_deactivate(a6xx_gpu);
2104
2105 msm_devfreq_suspend(gpu);
2106
2107 mutex_lock(&a6xx_gpu->gmu.lock);
2108 ret = a6xx_gmu_stop(a6xx_gpu);
2109 mutex_unlock(&a6xx_gpu->gmu.lock);
2110 if (ret)
2111 return ret;
2112
2113 if (a6xx_gpu->shadow_bo)
2114 for (i = 0; i < gpu->nr_rings; i++)
2115 a6xx_gpu->shadow[i] = 0;
2116
2117 gpu->suspend_count++;
2118
2119 return 0;
2120 }
2121
a6xx_pm_suspend(struct msm_gpu * gpu)2122 static int a6xx_pm_suspend(struct msm_gpu *gpu)
2123 {
2124 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2125 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2126 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
2127 int i;
2128
2129 trace_msm_gpu_suspend(0);
2130
2131 msm_devfreq_suspend(gpu);
2132
2133 mutex_lock(&a6xx_gpu->gmu.lock);
2134
2135 /* Drain the outstanding traffic on memory buses */
2136 a6xx_bus_clear_pending_transactions(adreno_gpu, true);
2137
2138 if (adreno_is_a619_holi(adreno_gpu))
2139 a6xx_sptprac_disable(gmu);
2140
2141 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
2142
2143 pm_runtime_put_sync(gmu->gxpd);
2144 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
2145 pm_runtime_put_sync(gmu->dev);
2146
2147 mutex_unlock(&a6xx_gpu->gmu.lock);
2148
2149 if (a6xx_gpu->shadow_bo)
2150 for (i = 0; i < gpu->nr_rings; i++)
2151 a6xx_gpu->shadow[i] = 0;
2152
2153 gpu->suspend_count++;
2154
2155 return 0;
2156 }
2157
a6xx_gmu_get_timestamp(struct msm_gpu * gpu,uint64_t * value)2158 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
2159 {
2160 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2161 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2162
2163 mutex_lock(&a6xx_gpu->gmu.lock);
2164
2165 /* Force the GPU power on so we can read this register */
2166 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
2167
2168 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
2169
2170 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
2171
2172 mutex_unlock(&a6xx_gpu->gmu.lock);
2173
2174 return 0;
2175 }
2176
a6xx_get_timestamp(struct msm_gpu * gpu,uint64_t * value)2177 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
2178 {
2179 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
2180 return 0;
2181 }
2182
a6xx_active_ring(struct msm_gpu * gpu)2183 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
2184 {
2185 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2186 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2187
2188 return a6xx_gpu->cur_ring;
2189 }
2190
a6xx_destroy(struct msm_gpu * gpu)2191 static void a6xx_destroy(struct msm_gpu *gpu)
2192 {
2193 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2194 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2195
2196 if (a6xx_gpu->sqe_bo) {
2197 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
2198 drm_gem_object_put(a6xx_gpu->sqe_bo);
2199 }
2200
2201 if (a6xx_gpu->shadow_bo) {
2202 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
2203 drm_gem_object_put(a6xx_gpu->shadow_bo);
2204 }
2205
2206 a6xx_llc_slices_destroy(a6xx_gpu);
2207
2208 a6xx_gmu_remove(a6xx_gpu);
2209
2210 adreno_gpu_cleanup(adreno_gpu);
2211
2212 kfree(a6xx_gpu);
2213 }
2214
a6xx_gpu_busy(struct msm_gpu * gpu,unsigned long * out_sample_rate)2215 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
2216 {
2217 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2218 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2219 u64 busy_cycles;
2220
2221 /* 19.2MHz */
2222 *out_sample_rate = 19200000;
2223
2224 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
2225 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
2226 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
2227
2228 return busy_cycles;
2229 }
2230
a6xx_gpu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp,bool suspended)2231 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
2232 bool suspended)
2233 {
2234 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2235 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2236
2237 mutex_lock(&a6xx_gpu->gmu.lock);
2238 a6xx_gmu_set_freq(gpu, opp, suspended);
2239 mutex_unlock(&a6xx_gpu->gmu.lock);
2240 }
2241
2242 static struct msm_gem_address_space *
a6xx_create_address_space(struct msm_gpu * gpu,struct platform_device * pdev)2243 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
2244 {
2245 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2246 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2247 unsigned long quirks = 0;
2248
2249 /*
2250 * This allows GPU to set the bus attributes required to use system
2251 * cache on behalf of the iommu page table walker.
2252 */
2253 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) &&
2254 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY))
2255 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
2256
2257 return adreno_iommu_create_address_space(gpu, pdev, quirks);
2258 }
2259
2260 static struct msm_gem_address_space *
a6xx_create_private_address_space(struct msm_gpu * gpu)2261 a6xx_create_private_address_space(struct msm_gpu *gpu)
2262 {
2263 struct msm_mmu *mmu;
2264
2265 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
2266
2267 if (IS_ERR(mmu))
2268 return ERR_CAST(mmu);
2269
2270 return msm_gem_address_space_create(mmu,
2271 "gpu", 0x100000000ULL,
2272 adreno_private_address_space_size(gpu));
2273 }
2274
a6xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring)2275 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
2276 {
2277 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
2278 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
2279
2280 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
2281 return a6xx_gpu->shadow[ring->id];
2282
2283 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
2284 }
2285
a6xx_progress(struct msm_gpu * gpu,struct msm_ringbuffer * ring)2286 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
2287 {
2288 struct msm_cp_state cp_state = {
2289 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
2290 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
2291 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
2292 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE),
2293 };
2294 bool progress;
2295
2296 /*
2297 * Adjust the remaining data to account for what has already been
2298 * fetched from memory, but not yet consumed by the SQE.
2299 *
2300 * This is not *technically* correct, the amount buffered could
2301 * exceed the IB size due to hw prefetching ahead, but:
2302 *
2303 * (1) We aren't trying to find the exact position, just whether
2304 * progress has been made
2305 * (2) The CP_REG_TO_MEM at the end of a submit should be enough
2306 * to prevent prefetching into an unrelated submit. (And
2307 * either way, at some point the ROQ will be full.)
2308 */
2309 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16;
2310 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16;
2311
2312 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state));
2313
2314 ring->last_cp_state = cp_state;
2315
2316 return progress;
2317 }
2318
fuse_to_supp_hw(const struct adreno_info * info,u32 fuse)2319 static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
2320 {
2321 if (!info->speedbins)
2322 return UINT_MAX;
2323
2324 for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++)
2325 if (info->speedbins[i].fuse == fuse)
2326 return BIT(info->speedbins[i].speedbin);
2327
2328 return UINT_MAX;
2329 }
2330
a6xx_set_supported_hw(struct device * dev,const struct adreno_info * info)2331 static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
2332 {
2333 u32 supp_hw;
2334 u32 speedbin;
2335 int ret;
2336
2337 ret = adreno_read_speedbin(dev, &speedbin);
2338 /*
2339 * -ENOENT means that the platform doesn't support speedbin which is
2340 * fine
2341 */
2342 if (ret == -ENOENT) {
2343 return 0;
2344 } else if (ret) {
2345 dev_err_probe(dev, ret,
2346 "failed to read speed-bin. Some OPPs may not be supported by hardware\n");
2347 return ret;
2348 }
2349
2350 supp_hw = fuse_to_supp_hw(info, speedbin);
2351
2352 if (supp_hw == UINT_MAX) {
2353 DRM_DEV_ERROR(dev,
2354 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
2355 speedbin);
2356 supp_hw = BIT(0); /* Default */
2357 }
2358
2359 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
2360 if (ret)
2361 return ret;
2362
2363 return 0;
2364 }
2365
2366 static const struct adreno_gpu_funcs funcs = {
2367 .base = {
2368 .get_param = adreno_get_param,
2369 .set_param = adreno_set_param,
2370 .hw_init = a6xx_hw_init,
2371 .ucode_load = a6xx_ucode_load,
2372 .pm_suspend = a6xx_gmu_pm_suspend,
2373 .pm_resume = a6xx_gmu_pm_resume,
2374 .recover = a6xx_recover,
2375 .submit = a6xx_submit,
2376 .active_ring = a6xx_active_ring,
2377 .irq = a6xx_irq,
2378 .destroy = a6xx_destroy,
2379 #if defined(CONFIG_DRM_MSM_GPU_STATE)
2380 .show = a6xx_show,
2381 #endif
2382 .gpu_busy = a6xx_gpu_busy,
2383 .gpu_get_freq = a6xx_gmu_get_freq,
2384 .gpu_set_freq = a6xx_gpu_set_freq,
2385 #if defined(CONFIG_DRM_MSM_GPU_STATE)
2386 .gpu_state_get = a6xx_gpu_state_get,
2387 .gpu_state_put = a6xx_gpu_state_put,
2388 #endif
2389 .create_address_space = a6xx_create_address_space,
2390 .create_private_address_space = a6xx_create_private_address_space,
2391 .get_rptr = a6xx_get_rptr,
2392 .progress = a6xx_progress,
2393 },
2394 .get_timestamp = a6xx_gmu_get_timestamp,
2395 };
2396
2397 static const struct adreno_gpu_funcs funcs_gmuwrapper = {
2398 .base = {
2399 .get_param = adreno_get_param,
2400 .set_param = adreno_set_param,
2401 .hw_init = a6xx_hw_init,
2402 .ucode_load = a6xx_ucode_load,
2403 .pm_suspend = a6xx_pm_suspend,
2404 .pm_resume = a6xx_pm_resume,
2405 .recover = a6xx_recover,
2406 .submit = a6xx_submit,
2407 .active_ring = a6xx_active_ring,
2408 .irq = a6xx_irq,
2409 .destroy = a6xx_destroy,
2410 #if defined(CONFIG_DRM_MSM_GPU_STATE)
2411 .show = a6xx_show,
2412 #endif
2413 .gpu_busy = a6xx_gpu_busy,
2414 #if defined(CONFIG_DRM_MSM_GPU_STATE)
2415 .gpu_state_get = a6xx_gpu_state_get,
2416 .gpu_state_put = a6xx_gpu_state_put,
2417 #endif
2418 .create_address_space = a6xx_create_address_space,
2419 .create_private_address_space = a6xx_create_private_address_space,
2420 .get_rptr = a6xx_get_rptr,
2421 .progress = a6xx_progress,
2422 },
2423 .get_timestamp = a6xx_get_timestamp,
2424 };
2425
2426 static const struct adreno_gpu_funcs funcs_a7xx = {
2427 .base = {
2428 .get_param = adreno_get_param,
2429 .set_param = adreno_set_param,
2430 .hw_init = a6xx_hw_init,
2431 .ucode_load = a6xx_ucode_load,
2432 .pm_suspend = a6xx_gmu_pm_suspend,
2433 .pm_resume = a6xx_gmu_pm_resume,
2434 .recover = a6xx_recover,
2435 .submit = a7xx_submit,
2436 .active_ring = a6xx_active_ring,
2437 .irq = a6xx_irq,
2438 .destroy = a6xx_destroy,
2439 #if defined(CONFIG_DRM_MSM_GPU_STATE)
2440 .show = a6xx_show,
2441 #endif
2442 .gpu_busy = a6xx_gpu_busy,
2443 .gpu_get_freq = a6xx_gmu_get_freq,
2444 .gpu_set_freq = a6xx_gpu_set_freq,
2445 #if defined(CONFIG_DRM_MSM_GPU_STATE)
2446 .gpu_state_get = a6xx_gpu_state_get,
2447 .gpu_state_put = a6xx_gpu_state_put,
2448 #endif
2449 .create_address_space = a6xx_create_address_space,
2450 .create_private_address_space = a6xx_create_private_address_space,
2451 .get_rptr = a6xx_get_rptr,
2452 .progress = a6xx_progress,
2453 },
2454 .get_timestamp = a6xx_gmu_get_timestamp,
2455 };
2456
a6xx_gpu_init(struct drm_device * dev)2457 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
2458 {
2459 struct msm_drm_private *priv = dev->dev_private;
2460 struct platform_device *pdev = priv->gpu_pdev;
2461 struct adreno_platform_config *config = pdev->dev.platform_data;
2462 struct device_node *node;
2463 struct a6xx_gpu *a6xx_gpu;
2464 struct adreno_gpu *adreno_gpu;
2465 struct msm_gpu *gpu;
2466 extern int enable_preemption;
2467 bool is_a7xx;
2468 int ret;
2469
2470 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
2471 if (!a6xx_gpu)
2472 return ERR_PTR(-ENOMEM);
2473
2474 adreno_gpu = &a6xx_gpu->base;
2475 gpu = &adreno_gpu->base;
2476
2477 mutex_init(&a6xx_gpu->gmu.lock);
2478
2479 adreno_gpu->registers = NULL;
2480
2481 /* Check if there is a GMU phandle and set it up */
2482 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
2483 /* FIXME: How do we gracefully handle this? */
2484 BUG_ON(!node);
2485
2486 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
2487
2488 adreno_gpu->base.hw_apriv =
2489 !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
2490
2491 /* gpu->info only gets assigned in adreno_gpu_init() */
2492 is_a7xx = config->info->family == ADRENO_7XX_GEN1 ||
2493 config->info->family == ADRENO_7XX_GEN2 ||
2494 config->info->family == ADRENO_7XX_GEN3;
2495
2496 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
2497
2498 ret = a6xx_set_supported_hw(&pdev->dev, config->info);
2499 if (ret) {
2500 a6xx_llc_slices_destroy(a6xx_gpu);
2501 kfree(a6xx_gpu);
2502 return ERR_PTR(ret);
2503 }
2504
2505 if ((enable_preemption == 1) || (enable_preemption == -1 &&
2506 (config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
2507 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4);
2508 else if (is_a7xx)
2509 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1);
2510 else if (adreno_has_gmu_wrapper(adreno_gpu))
2511 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1);
2512 else
2513 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
2514 if (ret) {
2515 a6xx_destroy(&(a6xx_gpu->base.base));
2516 return ERR_PTR(ret);
2517 }
2518
2519 /*
2520 * For now only clamp to idle freq for devices where this is known not
2521 * to cause power supply issues:
2522 */
2523 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu))
2524 priv->gpu_clamp_to_idle = true;
2525
2526 if (adreno_has_gmu_wrapper(adreno_gpu))
2527 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node);
2528 else
2529 ret = a6xx_gmu_init(a6xx_gpu, node);
2530 of_node_put(node);
2531 if (ret) {
2532 a6xx_destroy(&(a6xx_gpu->base.base));
2533 return ERR_PTR(ret);
2534 }
2535
2536 if (adreno_is_a7xx(adreno_gpu)) {
2537 ret = a7xx_cx_mem_init(a6xx_gpu);
2538 if (ret) {
2539 a6xx_destroy(&(a6xx_gpu->base.base));
2540 return ERR_PTR(ret);
2541 }
2542 }
2543
2544 adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
2545
2546 if (gpu->aspace)
2547 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
2548 a6xx_fault_handler);
2549
2550 a6xx_calc_ubwc_config(adreno_gpu);
2551 /* Set up the preemption specific bits and pieces for each ringbuffer */
2552 a6xx_preempt_init(gpu);
2553
2554 return gpu;
2555 }
2556