1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2016 BayLibre, SAS
4  * Author: Neil Armstrong <narmstrong@baylibre.com>
5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6  */
7 
8 #include <linux/export.h>
9 
10 #include <drm/drm_print.h>
11 
12 #include "meson_drv.h"
13 #include "meson_vclk.h"
14 
15 /**
16  * DOC: Video Clocks
17  *
18  * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
19  * We handle the following encodings :
20  *
21  * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
22  * - HDMI Pixel Clocks generation
23  *
24  * What is missing :
25  *
26  * - Genenate Pixel clocks for 2K/4K 10bit formats
27  *
28  * Clock generator scheme :
29  *
30  * .. code::
31  *
32  *    __________   _________            _____
33  *   |          | |         |          |     |--ENCI
34  *   | HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL
35  *   |__________| |_________| \        | MUX |--ENCP
36  *                             --VCLK2-|     |--VDAC
37  *                                     |_____|--HDMI-TX
38  *
39  * Final clocks can take input for either VCLK or VCLK2, but
40  * VCLK is the preferred path for HDMI clocking and VCLK2 is the
41  * preferred path for CVBS VDAC clocking.
42  *
43  * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
44  *
45  * The PLL_DIV can achieve an additional fractional dividing like
46  * 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
47  */
48 
49 /* HHI Registers */
50 #define HHI_VID_PLL_CLK_DIV	0x1a0 /* 0x68 offset in data sheet */
51 #define VID_PLL_EN		BIT(19)
52 #define VID_PLL_BYPASS		BIT(18)
53 #define VID_PLL_PRESET		BIT(15)
54 #define HHI_VIID_CLK_DIV	0x128 /* 0x4a offset in data sheet */
55 #define VCLK2_DIV_MASK		0xff
56 #define VCLK2_DIV_EN		BIT(16)
57 #define VCLK2_DIV_RESET		BIT(17)
58 #define CTS_VDAC_SEL_MASK	(0xf << 28)
59 #define CTS_VDAC_SEL_SHIFT	28
60 #define HHI_VIID_CLK_CNTL	0x12c /* 0x4b offset in data sheet */
61 #define VCLK2_EN		BIT(19)
62 #define VCLK2_SEL_MASK		(0x7 << 16)
63 #define VCLK2_SEL_SHIFT		16
64 #define VCLK2_SOFT_RESET	BIT(15)
65 #define VCLK2_DIV1_EN		BIT(0)
66 #define HHI_VID_CLK_DIV		0x164 /* 0x59 offset in data sheet */
67 #define VCLK_DIV_MASK		0xff
68 #define VCLK_DIV_EN		BIT(16)
69 #define VCLK_DIV_RESET		BIT(17)
70 #define CTS_ENCP_SEL_MASK	(0xf << 24)
71 #define CTS_ENCP_SEL_SHIFT	24
72 #define CTS_ENCI_SEL_MASK	(0xf << 28)
73 #define CTS_ENCI_SEL_SHIFT	28
74 #define HHI_VID_CLK_CNTL	0x17c /* 0x5f offset in data sheet */
75 #define VCLK_EN			BIT(19)
76 #define VCLK_SEL_MASK		(0x7 << 16)
77 #define VCLK_SEL_SHIFT		16
78 #define VCLK_SOFT_RESET		BIT(15)
79 #define VCLK_DIV1_EN		BIT(0)
80 #define VCLK_DIV2_EN		BIT(1)
81 #define VCLK_DIV4_EN		BIT(2)
82 #define VCLK_DIV6_EN		BIT(3)
83 #define VCLK_DIV12_EN		BIT(4)
84 #define HHI_VID_CLK_CNTL2	0x194 /* 0x65 offset in data sheet */
85 #define CTS_ENCI_EN		BIT(0)
86 #define CTS_ENCP_EN		BIT(2)
87 #define CTS_VDAC_EN		BIT(4)
88 #define HDMI_TX_PIXEL_EN	BIT(5)
89 #define HHI_HDMI_CLK_CNTL	0x1cc /* 0x73 offset in data sheet */
90 #define HDMI_TX_PIXEL_SEL_MASK	(0xf << 16)
91 #define HDMI_TX_PIXEL_SEL_SHIFT	16
92 #define CTS_HDMI_SYS_SEL_MASK	(0x7 << 9)
93 #define CTS_HDMI_SYS_DIV_MASK	(0x7f)
94 #define CTS_HDMI_SYS_EN		BIT(8)
95 
96 #define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
97 #define HHI_VDAC_CNTL1		0x2F8 /* 0xbe offset in data sheet */
98 
99 #define HHI_HDMI_PLL_CNTL	0x320 /* 0xc8 offset in data sheet */
100 #define HHI_HDMI_PLL_CNTL_EN	BIT(30)
101 #define HHI_HDMI_PLL_CNTL2	0x324 /* 0xc9 offset in data sheet */
102 #define HHI_HDMI_PLL_CNTL3	0x328 /* 0xca offset in data sheet */
103 #define HHI_HDMI_PLL_CNTL4	0x32C /* 0xcb offset in data sheet */
104 #define HHI_HDMI_PLL_CNTL5	0x330 /* 0xcc offset in data sheet */
105 #define HHI_HDMI_PLL_CNTL6	0x334 /* 0xcd offset in data sheet */
106 #define HHI_HDMI_PLL_CNTL7	0x338 /* 0xce offset in data sheet */
107 
108 #define HDMI_PLL_RESET		BIT(28)
109 #define HDMI_PLL_RESET_G12A	BIT(29)
110 #define HDMI_PLL_LOCK		BIT(31)
111 #define HDMI_PLL_LOCK_G12A	(3 << 30)
112 
113 #define PIXEL_FREQ_1000_1001(_freq)	\
114 	DIV_ROUND_CLOSEST_ULL((_freq) * 1000ULL, 1001ULL)
115 #define PHY_FREQ_1000_1001(_freq)	\
116 	(PIXEL_FREQ_1000_1001(DIV_ROUND_DOWN_ULL(_freq, 10ULL)) * 10)
117 
118 /* VID PLL Dividers */
119 enum {
120 	VID_PLL_DIV_1 = 0,
121 	VID_PLL_DIV_2,
122 	VID_PLL_DIV_2p5,
123 	VID_PLL_DIV_3,
124 	VID_PLL_DIV_3p5,
125 	VID_PLL_DIV_3p75,
126 	VID_PLL_DIV_4,
127 	VID_PLL_DIV_5,
128 	VID_PLL_DIV_6,
129 	VID_PLL_DIV_6p25,
130 	VID_PLL_DIV_7,
131 	VID_PLL_DIV_7p5,
132 	VID_PLL_DIV_12,
133 	VID_PLL_DIV_14,
134 	VID_PLL_DIV_15,
135 };
136 
meson_vid_pll_set(struct meson_drm * priv,unsigned int div)137 static void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
138 {
139 	unsigned int shift_val = 0;
140 	unsigned int shift_sel = 0;
141 
142 	/* Disable vid_pll output clock */
143 	regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
144 	regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
145 
146 	switch (div) {
147 	case VID_PLL_DIV_2:
148 		shift_val = 0x0aaa;
149 		shift_sel = 0;
150 		break;
151 	case VID_PLL_DIV_2p5:
152 		shift_val = 0x5294;
153 		shift_sel = 2;
154 		break;
155 	case VID_PLL_DIV_3:
156 		shift_val = 0x0db6;
157 		shift_sel = 0;
158 		break;
159 	case VID_PLL_DIV_3p5:
160 		shift_val = 0x36cc;
161 		shift_sel = 1;
162 		break;
163 	case VID_PLL_DIV_3p75:
164 		shift_val = 0x6666;
165 		shift_sel = 2;
166 		break;
167 	case VID_PLL_DIV_4:
168 		shift_val = 0x0ccc;
169 		shift_sel = 0;
170 		break;
171 	case VID_PLL_DIV_5:
172 		shift_val = 0x739c;
173 		shift_sel = 2;
174 		break;
175 	case VID_PLL_DIV_6:
176 		shift_val = 0x0e38;
177 		shift_sel = 0;
178 		break;
179 	case VID_PLL_DIV_6p25:
180 		shift_val = 0x0000;
181 		shift_sel = 3;
182 		break;
183 	case VID_PLL_DIV_7:
184 		shift_val = 0x3c78;
185 		shift_sel = 1;
186 		break;
187 	case VID_PLL_DIV_7p5:
188 		shift_val = 0x78f0;
189 		shift_sel = 2;
190 		break;
191 	case VID_PLL_DIV_12:
192 		shift_val = 0x0fc0;
193 		shift_sel = 0;
194 		break;
195 	case VID_PLL_DIV_14:
196 		shift_val = 0x3f80;
197 		shift_sel = 1;
198 		break;
199 	case VID_PLL_DIV_15:
200 		shift_val = 0x7f80;
201 		shift_sel = 2;
202 		break;
203 	}
204 
205 	if (div == VID_PLL_DIV_1)
206 		/* Enable vid_pll bypass to HDMI pll */
207 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
208 				   VID_PLL_BYPASS, VID_PLL_BYPASS);
209 	else {
210 		/* Disable Bypass */
211 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
212 				   VID_PLL_BYPASS, 0);
213 		/* Clear sel */
214 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
215 				   3 << 16, 0);
216 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
217 				   VID_PLL_PRESET, 0);
218 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
219 				   0x7fff, 0);
220 
221 		/* Setup sel and val */
222 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
223 				   3 << 16, shift_sel << 16);
224 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
225 				   VID_PLL_PRESET, VID_PLL_PRESET);
226 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
227 				   0x7fff, shift_val);
228 
229 		regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
230 				   VID_PLL_PRESET, 0);
231 	}
232 
233 	/* Enable the vid_pll output clock */
234 	regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
235 				VID_PLL_EN, VID_PLL_EN);
236 }
237 
238 /*
239  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
240  *
241  * TOFIX: Refactor into table to also handle HDMI frequency and paths
242  */
meson_venci_cvbs_clock_config(struct meson_drm * priv)243 static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
244 {
245 	unsigned int val;
246 
247 	/* Setup PLL to output 1.485GHz */
248 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
249 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
250 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
251 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
252 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
253 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
254 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
255 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
256 
257 		/* Poll for lock bit */
258 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
259 					 (val & HDMI_PLL_LOCK), 10, 0);
260 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
261 		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
262 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
263 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
264 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
265 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
266 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
267 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
268 
269 		/* Reset PLL */
270 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
271 					HDMI_PLL_RESET, HDMI_PLL_RESET);
272 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
273 					HDMI_PLL_RESET, 0);
274 
275 		/* Poll for lock bit */
276 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
277 					 (val & HDMI_PLL_LOCK), 10, 0);
278 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
279 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
280 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);
281 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
282 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
283 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
284 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
285 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000);
286 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
287 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
288 
289 		/* Poll for lock bit */
290 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
291 			((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
292 			10, 0);
293 	}
294 
295 	/* Disable VCLK2 */
296 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
297 
298 	/* Setup vid_pll to /1 */
299 	meson_vid_pll_set(priv, VID_PLL_DIV_1);
300 
301 	/* Setup the VCLK2 divider value to achieve 27MHz */
302 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
303 				VCLK2_DIV_MASK, (55 - 1));
304 
305 	/* select vid_pll for vclk2 */
306 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
307 		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
308 					VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
309 	else
310 		regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
311 					VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
312 
313 	/* enable vclk2 gate */
314 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
315 
316 	/* select vclk_div1 for enci */
317 	regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
318 				CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
319 	/* select vclk_div1 for vdac */
320 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
321 				CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
322 
323 	/* release vclk2_div_reset and enable vclk2_div */
324 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
325 				VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
326 
327 	/* enable vclk2_div1 gate */
328 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
329 				VCLK2_DIV1_EN, VCLK2_DIV1_EN);
330 
331 	/* reset vclk2 */
332 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
333 				VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
334 	regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
335 				VCLK2_SOFT_RESET, 0);
336 
337 	/* enable enci_clk */
338 	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
339 				CTS_ENCI_EN, CTS_ENCI_EN);
340 	/* enable vdac_clk */
341 	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
342 				CTS_VDAC_EN, CTS_VDAC_EN);
343 }
344 
345 enum {
346 /* PLL	O1 O2 O3 VP DV     EN TX */
347 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
348 	MESON_VCLK_HDMI_ENCI_54000 = 0,
349 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
350 	MESON_VCLK_HDMI_DDR_54000,
351 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
352 	MESON_VCLK_HDMI_DDR_148500,
353 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
354 	MESON_VCLK_HDMI_74250,
355 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
356 	MESON_VCLK_HDMI_148500,
357 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
358 	MESON_VCLK_HDMI_297000,
359 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
360 	MESON_VCLK_HDMI_594000,
361 /* 2970 /1 /1 /1 /5 /1  => /1 /2 */
362 	MESON_VCLK_HDMI_594000_YUV420,
363 };
364 
365 struct meson_vclk_params {
366 	unsigned long long pll_freq;
367 	unsigned long long phy_freq;
368 	unsigned long long vclk_freq;
369 	unsigned long long venc_freq;
370 	unsigned long long pixel_freq;
371 	unsigned int pll_od1;
372 	unsigned int pll_od2;
373 	unsigned int pll_od3;
374 	unsigned int vid_pll_div;
375 	unsigned int vclk_div;
376 } params[] = {
377 	[MESON_VCLK_HDMI_ENCI_54000] = {
378 		.pll_freq = 4320000000,
379 		.phy_freq = 270000000,
380 		.vclk_freq = 54000000,
381 		.venc_freq = 54000000,
382 		.pixel_freq = 54000000,
383 		.pll_od1 = 4,
384 		.pll_od2 = 4,
385 		.pll_od3 = 1,
386 		.vid_pll_div = VID_PLL_DIV_5,
387 		.vclk_div = 1,
388 	},
389 	[MESON_VCLK_HDMI_DDR_54000] = {
390 		.pll_freq = 4320000000,
391 		.phy_freq = 270000000,
392 		.vclk_freq = 54000000,
393 		.venc_freq = 54000000,
394 		.pixel_freq = 27000000,
395 		.pll_od1 = 4,
396 		.pll_od2 = 4,
397 		.pll_od3 = 1,
398 		.vid_pll_div = VID_PLL_DIV_5,
399 		.vclk_div = 1,
400 	},
401 	[MESON_VCLK_HDMI_DDR_148500] = {
402 		.pll_freq = 2970000000,
403 		.phy_freq = 742500000,
404 		.vclk_freq = 148500000,
405 		.venc_freq = 148500000,
406 		.pixel_freq = 74250000,
407 		.pll_od1 = 4,
408 		.pll_od2 = 1,
409 		.pll_od3 = 1,
410 		.vid_pll_div = VID_PLL_DIV_5,
411 		.vclk_div = 1,
412 	},
413 	[MESON_VCLK_HDMI_74250] = {
414 		.pll_freq = 2970000000,
415 		.phy_freq = 742500000,
416 		.vclk_freq = 74250000,
417 		.venc_freq = 74250000,
418 		.pixel_freq = 74250000,
419 		.pll_od1 = 2,
420 		.pll_od2 = 2,
421 		.pll_od3 = 2,
422 		.vid_pll_div = VID_PLL_DIV_5,
423 		.vclk_div = 1,
424 	},
425 	[MESON_VCLK_HDMI_148500] = {
426 		.pll_freq = 2970000000,
427 		.phy_freq = 1485000000,
428 		.vclk_freq = 148500000,
429 		.venc_freq = 148500000,
430 		.pixel_freq = 148500000,
431 		.pll_od1 = 1,
432 		.pll_od2 = 2,
433 		.pll_od3 = 2,
434 		.vid_pll_div = VID_PLL_DIV_5,
435 		.vclk_div = 1,
436 	},
437 	[MESON_VCLK_HDMI_297000] = {
438 		.pll_freq = 5940000000,
439 		.phy_freq = 2970000000,
440 		.venc_freq = 297000000,
441 		.vclk_freq = 297000000,
442 		.pixel_freq = 297000000,
443 		.pll_od1 = 2,
444 		.pll_od2 = 1,
445 		.pll_od3 = 1,
446 		.vid_pll_div = VID_PLL_DIV_5,
447 		.vclk_div = 2,
448 	},
449 	[MESON_VCLK_HDMI_594000] = {
450 		.pll_freq = 5940000000,
451 		.phy_freq = 5940000000,
452 		.venc_freq = 594000000,
453 		.vclk_freq = 594000000,
454 		.pixel_freq = 594000000,
455 		.pll_od1 = 1,
456 		.pll_od2 = 1,
457 		.pll_od3 = 2,
458 		.vid_pll_div = VID_PLL_DIV_5,
459 		.vclk_div = 1,
460 	},
461 	[MESON_VCLK_HDMI_594000_YUV420] = {
462 		.pll_freq = 5940000000,
463 		.phy_freq = 2970000000,
464 		.venc_freq = 594000000,
465 		.vclk_freq = 594000000,
466 		.pixel_freq = 297000000,
467 		.pll_od1 = 2,
468 		.pll_od2 = 1,
469 		.pll_od3 = 1,
470 		.vid_pll_div = VID_PLL_DIV_5,
471 		.vclk_div = 1,
472 	},
473 	{ /* sentinel */ },
474 };
475 
pll_od_to_reg(unsigned int od)476 static inline unsigned int pll_od_to_reg(unsigned int od)
477 {
478 	switch (od) {
479 	case 1:
480 		return 0;
481 	case 2:
482 		return 1;
483 	case 4:
484 		return 2;
485 	case 8:
486 		return 3;
487 	}
488 
489 	/* Invalid */
490 	return 0;
491 }
492 
meson_hdmi_pll_set_params(struct meson_drm * priv,unsigned int m,unsigned int frac,unsigned int od1,unsigned int od2,unsigned int od3)493 static void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
494 				      unsigned int frac, unsigned int od1,
495 				      unsigned int od2, unsigned int od3)
496 {
497 	unsigned int val;
498 
499 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
500 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
501 		if (frac)
502 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
503 				     0x00004000 | frac);
504 		else
505 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
506 				     0x00000000);
507 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
508 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
509 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
510 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
511 
512 		/* Enable and unreset */
513 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
514 				   0x7 << 28, HHI_HDMI_PLL_CNTL_EN);
515 
516 		/* Poll for lock bit */
517 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
518 					 val, (val & HDMI_PLL_LOCK), 10, 0);
519 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
520 		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
521 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
522 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
523 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
524 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
525 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
526 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
527 
528 		/* Reset PLL */
529 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
530 				HDMI_PLL_RESET, HDMI_PLL_RESET);
531 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
532 				HDMI_PLL_RESET, 0);
533 
534 		/* Poll for lock bit */
535 		regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
536 				(val & HDMI_PLL_LOCK), 10, 0);
537 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
538 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
539 
540 		/* Enable and reset */
541 		/* TODO: add specific macro for g12a here */
542 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
543 				   0x3 << 28, 0x3 << 28);
544 
545 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
546 		regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
547 
548 		/* G12A HDMI PLL Needs specific parameters for 5.4GHz */
549 		if (m >= 0xf7) {
550 			if (frac < 0x10000) {
551 				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
552 							0x6a685c00);
553 				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
554 							0x11551293);
555 			} else {
556 				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
557 							0xea68dc00);
558 				regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
559 							0x65771290);
560 			}
561 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
562 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
563 		} else {
564 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
565 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
566 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
567 			regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
568 		}
569 
570 		do {
571 			/* Reset PLL */
572 			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
573 					HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
574 
575 			/* UN-Reset PLL */
576 			regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
577 					HDMI_PLL_RESET_G12A, 0);
578 
579 			/* Poll for lock bits */
580 			if (!regmap_read_poll_timeout(priv->hhi,
581 						      HHI_HDMI_PLL_CNTL, val,
582 						      ((val & HDMI_PLL_LOCK_G12A)
583 						        == HDMI_PLL_LOCK_G12A),
584 						      10, 100))
585 				break;
586 		} while(1);
587 	}
588 
589 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
590 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
591 				3 << 16, pll_od_to_reg(od1) << 16);
592 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
593 		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
594 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
595 				3 << 21, pll_od_to_reg(od1) << 21);
596 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
597 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
598 				3 << 16, pll_od_to_reg(od1) << 16);
599 
600 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
601 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
602 				3 << 22, pll_od_to_reg(od2) << 22);
603 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
604 		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
605 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
606 				3 << 23, pll_od_to_reg(od2) << 23);
607 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
608 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
609 				3 << 18, pll_od_to_reg(od2) << 18);
610 
611 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
612 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
613 				3 << 18, pll_od_to_reg(od3) << 18);
614 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
615 		 meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
616 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
617 				3 << 19, pll_od_to_reg(od3) << 19);
618 	else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
619 		regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
620 				3 << 20, pll_od_to_reg(od3) << 20);
621 }
622 
623 #define XTAL_FREQ (24 * 1000 * 1000)
624 
meson_hdmi_pll_get_m(struct meson_drm * priv,unsigned long long pll_freq)625 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
626 					 unsigned long long pll_freq)
627 {
628 	/* The GXBB PLL has a /2 pre-multiplier */
629 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
630 		pll_freq = DIV_ROUND_DOWN_ULL(pll_freq, 2);
631 
632 	return DIV_ROUND_DOWN_ULL(pll_freq, XTAL_FREQ);
633 }
634 
635 #define HDMI_FRAC_MAX_GXBB	4096
636 #define HDMI_FRAC_MAX_GXL	1024
637 #define HDMI_FRAC_MAX_G12A	131072
638 
meson_hdmi_pll_get_frac(struct meson_drm * priv,unsigned int m,unsigned long long pll_freq)639 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
640 					    unsigned int m,
641 					    unsigned long long pll_freq)
642 {
643 	unsigned long long parent_freq = XTAL_FREQ;
644 	unsigned int frac_max = HDMI_FRAC_MAX_GXL;
645 	unsigned int frac_m;
646 	unsigned int frac;
647 	u32 remainder;
648 
649 	/* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
650 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
651 		frac_max = HDMI_FRAC_MAX_GXBB;
652 		parent_freq *= 2;
653 	}
654 
655 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
656 		frac_max = HDMI_FRAC_MAX_G12A;
657 
658 	/* We can have a perfect match !*/
659 	if (div_u64_rem(pll_freq, m, &remainder) == parent_freq &&
660 	    remainder == 0)
661 		return 0;
662 
663 	frac = mul_u64_u64_div_u64(pll_freq, frac_max, parent_freq);
664 	frac_m = m * frac_max;
665 	if (frac_m > frac)
666 		return frac_max;
667 	frac -= frac_m;
668 
669 	return min((u16)frac, (u16)(frac_max - 1));
670 }
671 
meson_hdmi_pll_validate_params(struct meson_drm * priv,unsigned long long m,unsigned int frac)672 static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
673 					   unsigned long long m,
674 					   unsigned int frac)
675 {
676 	if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
677 		/* Empiric supported min/max dividers */
678 		if (m < 53 || m > 123)
679 			return false;
680 		if (frac >= HDMI_FRAC_MAX_GXBB)
681 			return false;
682 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
683 		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
684 		/* Empiric supported min/max dividers */
685 		if (m < 106 || m > 247)
686 			return false;
687 		if (frac >= HDMI_FRAC_MAX_GXL)
688 			return false;
689 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
690 		/* Empiric supported min/max dividers */
691 		if (m < 106 || m > 247)
692 			return false;
693 		if (frac >= HDMI_FRAC_MAX_G12A)
694 			return false;
695 	}
696 
697 	return true;
698 }
699 
meson_hdmi_pll_find_params(struct meson_drm * priv,unsigned long long freq,unsigned int * m,unsigned int * frac,unsigned int * od)700 static bool meson_hdmi_pll_find_params(struct meson_drm *priv,
701 				       unsigned long long freq,
702 				       unsigned int *m,
703 				       unsigned int *frac,
704 				       unsigned int *od)
705 {
706 	/* Cycle from /16 to /2 */
707 	for (*od = 16 ; *od > 1 ; *od >>= 1) {
708 		*m = meson_hdmi_pll_get_m(priv, freq * *od);
709 		if (!*m)
710 			continue;
711 		*frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
712 
713 		DRM_DEBUG_DRIVER("PLL params for %lluHz: m=%x frac=%x od=%d\n",
714 				 freq, *m, *frac, *od);
715 
716 		if (meson_hdmi_pll_validate_params(priv, *m, *frac))
717 			return true;
718 	}
719 
720 	return false;
721 }
722 
723 /* pll_freq is the frequency after the OD dividers */
724 enum drm_mode_status
meson_vclk_dmt_supported_freq(struct meson_drm * priv,unsigned long long freq)725 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned long long freq)
726 {
727 	unsigned int od, m, frac;
728 
729 	/* In DMT mode, path after PLL is always /10 */
730 	freq *= 10;
731 
732 	/* Check against soc revision/package limits */
733 	if (priv->limits) {
734 		if (priv->limits->max_hdmi_phy_freq &&
735 		    freq > priv->limits->max_hdmi_phy_freq)
736 			return MODE_CLOCK_HIGH;
737 	}
738 
739 	if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
740 		return MODE_OK;
741 
742 	return MODE_CLOCK_RANGE;
743 }
744 EXPORT_SYMBOL_GPL(meson_vclk_dmt_supported_freq);
745 
746 /* pll_freq is the frequency after the OD dividers */
meson_hdmi_pll_generic_set(struct meson_drm * priv,unsigned long long pll_freq)747 static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
748 				       unsigned long long pll_freq)
749 {
750 	unsigned int od, m, frac, od1, od2, od3;
751 
752 	if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
753 		/* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */
754 		od3 = 1;
755 		if (od < 4) {
756 			od1 = 2;
757 			od2 = 1;
758 		} else {
759 			od2 = od / 4;
760 			od1 = od / od2;
761 		}
762 
763 		DRM_DEBUG_DRIVER("PLL params for %lluHz: m=%x frac=%x od=%d/%d/%d\n",
764 				 pll_freq, m, frac, od1, od2, od3);
765 
766 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
767 
768 		return;
769 	}
770 
771 	DRM_ERROR("Fatal, unable to find parameters for PLL freq %lluHz\n",
772 		  pll_freq);
773 }
774 
775 enum drm_mode_status
meson_vclk_vic_supported_freq(struct meson_drm * priv,unsigned long long phy_freq,unsigned long long vclk_freq)776 meson_vclk_vic_supported_freq(struct meson_drm *priv,
777 			      unsigned long long phy_freq,
778 			      unsigned long long vclk_freq)
779 {
780 	int i;
781 
782 	DRM_DEBUG_DRIVER("phy_freq = %lluHz vclk_freq = %lluHz\n",
783 			 phy_freq, vclk_freq);
784 
785 	/* Check against soc revision/package limits */
786 	if (priv->limits) {
787 		if (priv->limits->max_hdmi_phy_freq &&
788 		    phy_freq > priv->limits->max_hdmi_phy_freq)
789 			return MODE_CLOCK_HIGH;
790 	}
791 
792 	for (i = 0 ; params[i].pixel_freq ; ++i) {
793 		DRM_DEBUG_DRIVER("i = %d pixel_freq = %lluHz alt = %lluHz\n",
794 				 i, params[i].pixel_freq,
795 				 PIXEL_FREQ_1000_1001(params[i].pixel_freq));
796 		DRM_DEBUG_DRIVER("i = %d phy_freq = %lluHz alt = %lluHz\n",
797 				 i, params[i].phy_freq,
798 				 PHY_FREQ_1000_1001(params[i].phy_freq));
799 		/* Match strict frequency */
800 		if (phy_freq == params[i].phy_freq &&
801 		    vclk_freq == params[i].vclk_freq)
802 			return MODE_OK;
803 		/* Match 1000/1001 variant */
804 		if (phy_freq == PHY_FREQ_1000_1001(params[i].phy_freq) &&
805 		    vclk_freq == PIXEL_FREQ_1000_1001(params[i].vclk_freq))
806 			return MODE_OK;
807 	}
808 
809 	return MODE_CLOCK_RANGE;
810 }
811 EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq);
812 
meson_vclk_set(struct meson_drm * priv,unsigned long long pll_base_freq,unsigned int od1,unsigned int od2,unsigned int od3,unsigned int vid_pll_div,unsigned int vclk_div,unsigned int hdmi_tx_div,unsigned int venc_div,bool hdmi_use_enci,bool vic_alternate_clock)813 static void meson_vclk_set(struct meson_drm *priv,
814 			   unsigned long long pll_base_freq, unsigned int od1,
815 			   unsigned int od2, unsigned int od3,
816 			   unsigned int vid_pll_div, unsigned int vclk_div,
817 			   unsigned int hdmi_tx_div, unsigned int venc_div,
818 			   bool hdmi_use_enci, bool vic_alternate_clock)
819 {
820 	unsigned int m = 0, frac = 0;
821 
822 	/* Set HDMI-TX sys clock */
823 	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
824 			   CTS_HDMI_SYS_SEL_MASK, 0);
825 	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
826 			   CTS_HDMI_SYS_DIV_MASK, 0);
827 	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
828 			   CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
829 
830 	/* Set HDMI PLL rate */
831 	if (!od1 && !od2 && !od3) {
832 		meson_hdmi_pll_generic_set(priv, pll_base_freq);
833 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
834 		switch (pll_base_freq) {
835 		case 2970000000:
836 			m = 0x3d;
837 			frac = vic_alternate_clock ? 0xd02 : 0xe00;
838 			break;
839 		case 4320000000:
840 			m = vic_alternate_clock ? 0x59 : 0x5a;
841 			frac = vic_alternate_clock ? 0xe8f : 0;
842 			break;
843 		case 5940000000:
844 			m = 0x7b;
845 			frac = vic_alternate_clock ? 0xa05 : 0xc00;
846 			break;
847 		}
848 
849 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
850 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
851 		   meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
852 		switch (pll_base_freq) {
853 		case 2970000000:
854 			m = 0x7b;
855 			frac = vic_alternate_clock ? 0x281 : 0x300;
856 			break;
857 		case 4320000000:
858 			m = vic_alternate_clock ? 0xb3 : 0xb4;
859 			frac = vic_alternate_clock ? 0x347 : 0;
860 			break;
861 		case 5940000000:
862 			m = 0xf7;
863 			frac = vic_alternate_clock ? 0x102 : 0x200;
864 			break;
865 		}
866 
867 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
868 	} else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
869 		switch (pll_base_freq) {
870 		case 2970000000:
871 			m = 0x7b;
872 			frac = vic_alternate_clock ? 0x140b4 : 0x18000;
873 			break;
874 		case 4320000000:
875 			m = vic_alternate_clock ? 0xb3 : 0xb4;
876 			frac = vic_alternate_clock ? 0x1a3ee : 0;
877 			break;
878 		case 5940000000:
879 			m = 0xf7;
880 			frac = vic_alternate_clock ? 0x8148 : 0x10000;
881 			break;
882 		}
883 
884 		meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
885 	}
886 
887 	/* Setup vid_pll divider */
888 	meson_vid_pll_set(priv, vid_pll_div);
889 
890 	/* Set VCLK div */
891 	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
892 			   VCLK_SEL_MASK, 0);
893 	regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
894 			   VCLK_DIV_MASK, vclk_div - 1);
895 
896 	/* Set HDMI-TX source */
897 	switch (hdmi_tx_div) {
898 	case 1:
899 		/* enable vclk_div1 gate */
900 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
901 				   VCLK_DIV1_EN, VCLK_DIV1_EN);
902 
903 		/* select vclk_div1 for HDMI-TX */
904 		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
905 				   HDMI_TX_PIXEL_SEL_MASK, 0);
906 		break;
907 	case 2:
908 		/* enable vclk_div2 gate */
909 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
910 				   VCLK_DIV2_EN, VCLK_DIV2_EN);
911 
912 		/* select vclk_div2 for HDMI-TX */
913 		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
914 			HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
915 		break;
916 	case 4:
917 		/* enable vclk_div4 gate */
918 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
919 				   VCLK_DIV4_EN, VCLK_DIV4_EN);
920 
921 		/* select vclk_div4 for HDMI-TX */
922 		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
923 			HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
924 		break;
925 	case 6:
926 		/* enable vclk_div6 gate */
927 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
928 				   VCLK_DIV6_EN, VCLK_DIV6_EN);
929 
930 		/* select vclk_div6 for HDMI-TX */
931 		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
932 			HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
933 		break;
934 	case 12:
935 		/* enable vclk_div12 gate */
936 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
937 				   VCLK_DIV12_EN, VCLK_DIV12_EN);
938 
939 		/* select vclk_div12 for HDMI-TX */
940 		regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
941 			HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
942 		break;
943 	}
944 	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
945 				   HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
946 
947 	/* Set ENCI/ENCP Source */
948 	switch (venc_div) {
949 	case 1:
950 		/* enable vclk_div1 gate */
951 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
952 				   VCLK_DIV1_EN, VCLK_DIV1_EN);
953 
954 		if (hdmi_use_enci)
955 			/* select vclk_div1 for enci */
956 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
957 					   CTS_ENCI_SEL_MASK, 0);
958 		else
959 			/* select vclk_div1 for encp */
960 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
961 					   CTS_ENCP_SEL_MASK, 0);
962 		break;
963 	case 2:
964 		/* enable vclk_div2 gate */
965 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
966 				   VCLK_DIV2_EN, VCLK_DIV2_EN);
967 
968 		if (hdmi_use_enci)
969 			/* select vclk_div2 for enci */
970 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
971 				CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
972 		else
973 			/* select vclk_div2 for encp */
974 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
975 				CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
976 		break;
977 	case 4:
978 		/* enable vclk_div4 gate */
979 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
980 				   VCLK_DIV4_EN, VCLK_DIV4_EN);
981 
982 		if (hdmi_use_enci)
983 			/* select vclk_div4 for enci */
984 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
985 				CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
986 		else
987 			/* select vclk_div4 for encp */
988 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
989 				CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
990 		break;
991 	case 6:
992 		/* enable vclk_div6 gate */
993 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
994 				   VCLK_DIV6_EN, VCLK_DIV6_EN);
995 
996 		if (hdmi_use_enci)
997 			/* select vclk_div6 for enci */
998 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
999 				CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
1000 		else
1001 			/* select vclk_div6 for encp */
1002 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
1003 				CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
1004 		break;
1005 	case 12:
1006 		/* enable vclk_div12 gate */
1007 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
1008 				   VCLK_DIV12_EN, VCLK_DIV12_EN);
1009 
1010 		if (hdmi_use_enci)
1011 			/* select vclk_div12 for enci */
1012 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
1013 				CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
1014 		else
1015 			/* select vclk_div12 for encp */
1016 			regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
1017 				CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
1018 		break;
1019 	}
1020 
1021 	if (hdmi_use_enci)
1022 		/* Enable ENCI clock gate */
1023 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
1024 				   CTS_ENCI_EN, CTS_ENCI_EN);
1025 	else
1026 		/* Enable ENCP clock gate */
1027 		regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
1028 				   CTS_ENCP_EN, CTS_ENCP_EN);
1029 
1030 	regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
1031 }
1032 
meson_vclk_setup(struct meson_drm * priv,unsigned int target,unsigned long long phy_freq,unsigned long long vclk_freq,unsigned long long venc_freq,unsigned long long dac_freq,bool hdmi_use_enci)1033 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
1034 		      unsigned long long phy_freq, unsigned long long vclk_freq,
1035 		      unsigned long long venc_freq, unsigned long long dac_freq,
1036 		      bool hdmi_use_enci)
1037 {
1038 	bool vic_alternate_clock = false;
1039 	unsigned long long freq;
1040 	unsigned long long hdmi_tx_div;
1041 	unsigned long long venc_div;
1042 
1043 	if (target == MESON_VCLK_TARGET_CVBS) {
1044 		meson_venci_cvbs_clock_config(priv);
1045 		return;
1046 	} else if (target == MESON_VCLK_TARGET_DMT) {
1047 		/*
1048 		 * The DMT clock path is fixed after the PLL:
1049 		 * - automatic PLL freq + OD management
1050 		 * - vid_pll_div = VID_PLL_DIV_5
1051 		 * - vclk_div = 2
1052 		 * - hdmi_tx_div = 1
1053 		 * - venc_div = 1
1054 		 * - encp encoder
1055 		 */
1056 		meson_vclk_set(priv, phy_freq, 0, 0, 0,
1057 			       VID_PLL_DIV_5, 2, 1, 1, false, false);
1058 		return;
1059 	}
1060 
1061 	hdmi_tx_div = DIV_ROUND_DOWN_ULL(vclk_freq, dac_freq);
1062 
1063 	if (hdmi_tx_div == 0) {
1064 		pr_err("Fatal Error, invalid HDMI-TX freq %lluHz\n",
1065 		       dac_freq);
1066 		return;
1067 	}
1068 
1069 	venc_div = DIV_ROUND_DOWN_ULL(vclk_freq, venc_freq);
1070 
1071 	if (venc_div == 0) {
1072 		pr_err("Fatal Error, invalid HDMI venc freq %lluHz\n",
1073 		       venc_freq);
1074 		return;
1075 	}
1076 
1077 	for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
1078 		if ((phy_freq == params[freq].phy_freq ||
1079 		     phy_freq == PHY_FREQ_1000_1001(params[freq].phy_freq)) &&
1080 		    (vclk_freq == params[freq].vclk_freq ||
1081 		     vclk_freq == PIXEL_FREQ_1000_1001(params[freq].vclk_freq))) {
1082 			if (vclk_freq != params[freq].vclk_freq)
1083 				vic_alternate_clock = true;
1084 			else
1085 				vic_alternate_clock = false;
1086 
1087 			if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
1088 			    !hdmi_use_enci)
1089 				continue;
1090 
1091 			if (freq == MESON_VCLK_HDMI_DDR_54000 &&
1092 			    hdmi_use_enci)
1093 				continue;
1094 
1095 			if (freq == MESON_VCLK_HDMI_DDR_148500 &&
1096 			    dac_freq == vclk_freq)
1097 				continue;
1098 
1099 			if (freq == MESON_VCLK_HDMI_148500 &&
1100 			    dac_freq != vclk_freq)
1101 				continue;
1102 			break;
1103 		}
1104 	}
1105 
1106 	if (!params[freq].pixel_freq) {
1107 		pr_err("Fatal Error, invalid HDMI vclk freq %lluHz\n",
1108 		       vclk_freq);
1109 		return;
1110 	}
1111 
1112 	meson_vclk_set(priv, params[freq].pll_freq,
1113 		       params[freq].pll_od1, params[freq].pll_od2,
1114 		       params[freq].pll_od3, params[freq].vid_pll_div,
1115 		       params[freq].vclk_div, hdmi_tx_div, venc_div,
1116 		       hdmi_use_enci, vic_alternate_clock);
1117 }
1118 EXPORT_SYMBOL_GPL(meson_vclk_setup);
1119