1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7 #include <linux/component.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/dma-mapping.h>
14
15 #include <drm/clients/drm_client_setup.h>
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fbdev_dma.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_ioctl.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_vblank.h>
27
28 #include "mtk_crtc.h"
29 #include "mtk_ddp_comp.h"
30 #include "mtk_disp_drv.h"
31 #include "mtk_drm_drv.h"
32 #include "mtk_gem.h"
33
34 #define DRIVER_NAME "mediatek"
35 #define DRIVER_DESC "Mediatek SoC DRM"
36 #define DRIVER_MAJOR 1
37 #define DRIVER_MINOR 0
38
39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
41 };
42
43 static struct drm_framebuffer *
mtk_drm_mode_fb_create(struct drm_device * dev,struct drm_file * file,const struct drm_mode_fb_cmd2 * cmd)44 mtk_drm_mode_fb_create(struct drm_device *dev,
45 struct drm_file *file,
46 const struct drm_mode_fb_cmd2 *cmd)
47 {
48 const struct drm_format_info *info = drm_get_format_info(dev, cmd);
49
50 if (info->num_planes != 1)
51 return ERR_PTR(-EINVAL);
52
53 return drm_gem_fb_create(dev, file, cmd);
54 }
55
56 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
57 .fb_create = mtk_drm_mode_fb_create,
58 .atomic_check = drm_atomic_helper_check,
59 .atomic_commit = drm_atomic_helper_commit,
60 };
61
62 static const unsigned int mt2701_mtk_ddp_main[] = {
63 DDP_COMPONENT_OVL0,
64 DDP_COMPONENT_RDMA0,
65 DDP_COMPONENT_COLOR0,
66 DDP_COMPONENT_BLS,
67 DDP_COMPONENT_DSI0,
68 };
69
70 static const unsigned int mt2701_mtk_ddp_ext[] = {
71 DDP_COMPONENT_RDMA1,
72 DDP_COMPONENT_DPI0,
73 };
74
75 static const unsigned int mt7623_mtk_ddp_main[] = {
76 DDP_COMPONENT_OVL0,
77 DDP_COMPONENT_RDMA0,
78 DDP_COMPONENT_COLOR0,
79 DDP_COMPONENT_BLS,
80 DDP_COMPONENT_DPI0,
81 };
82
83 static const unsigned int mt7623_mtk_ddp_ext[] = {
84 DDP_COMPONENT_RDMA1,
85 DDP_COMPONENT_DSI0,
86 };
87
88 static const unsigned int mt2712_mtk_ddp_main[] = {
89 DDP_COMPONENT_OVL0,
90 DDP_COMPONENT_COLOR0,
91 DDP_COMPONENT_AAL0,
92 DDP_COMPONENT_OD0,
93 DDP_COMPONENT_RDMA0,
94 DDP_COMPONENT_DPI0,
95 DDP_COMPONENT_PWM0,
96 };
97
98 static const unsigned int mt2712_mtk_ddp_ext[] = {
99 DDP_COMPONENT_OVL1,
100 DDP_COMPONENT_COLOR1,
101 DDP_COMPONENT_AAL1,
102 DDP_COMPONENT_OD1,
103 DDP_COMPONENT_RDMA1,
104 DDP_COMPONENT_DPI1,
105 DDP_COMPONENT_PWM1,
106 };
107
108 static const unsigned int mt2712_mtk_ddp_third[] = {
109 DDP_COMPONENT_RDMA2,
110 DDP_COMPONENT_DSI3,
111 DDP_COMPONENT_PWM2,
112 };
113
114 static unsigned int mt8167_mtk_ddp_main[] = {
115 DDP_COMPONENT_OVL0,
116 DDP_COMPONENT_COLOR0,
117 DDP_COMPONENT_CCORR,
118 DDP_COMPONENT_AAL0,
119 DDP_COMPONENT_GAMMA,
120 DDP_COMPONENT_DITHER0,
121 DDP_COMPONENT_RDMA0,
122 DDP_COMPONENT_DSI0,
123 };
124
125 static const unsigned int mt8173_mtk_ddp_main[] = {
126 DDP_COMPONENT_OVL0,
127 DDP_COMPONENT_COLOR0,
128 DDP_COMPONENT_AAL0,
129 DDP_COMPONENT_OD0,
130 DDP_COMPONENT_RDMA0,
131 DDP_COMPONENT_UFOE,
132 DDP_COMPONENT_DSI0,
133 DDP_COMPONENT_PWM0,
134 };
135
136 static const unsigned int mt8173_mtk_ddp_ext[] = {
137 DDP_COMPONENT_OVL1,
138 DDP_COMPONENT_COLOR1,
139 DDP_COMPONENT_GAMMA,
140 DDP_COMPONENT_RDMA1,
141 DDP_COMPONENT_DPI0,
142 };
143
144 static const unsigned int mt8183_mtk_ddp_main[] = {
145 DDP_COMPONENT_OVL0,
146 DDP_COMPONENT_OVL_2L0,
147 DDP_COMPONENT_RDMA0,
148 DDP_COMPONENT_COLOR0,
149 DDP_COMPONENT_CCORR,
150 DDP_COMPONENT_AAL0,
151 DDP_COMPONENT_GAMMA,
152 DDP_COMPONENT_DITHER0,
153 DDP_COMPONENT_DSI0,
154 };
155
156 static const unsigned int mt8183_mtk_ddp_ext[] = {
157 DDP_COMPONENT_OVL_2L1,
158 DDP_COMPONENT_RDMA1,
159 DDP_COMPONENT_DPI0,
160 };
161
162 static const unsigned int mt8186_mtk_ddp_main[] = {
163 DDP_COMPONENT_OVL0,
164 DDP_COMPONENT_RDMA0,
165 DDP_COMPONENT_COLOR0,
166 DDP_COMPONENT_CCORR,
167 DDP_COMPONENT_AAL0,
168 DDP_COMPONENT_GAMMA,
169 DDP_COMPONENT_POSTMASK0,
170 DDP_COMPONENT_DITHER0,
171 DDP_COMPONENT_DSI0,
172 };
173
174 static const unsigned int mt8186_mtk_ddp_ext[] = {
175 DDP_COMPONENT_OVL_2L0,
176 DDP_COMPONENT_RDMA1,
177 DDP_COMPONENT_DPI0,
178 };
179
180 static const unsigned int mt8188_mtk_ddp_main[] = {
181 DDP_COMPONENT_OVL0,
182 DDP_COMPONENT_RDMA0,
183 DDP_COMPONENT_COLOR0,
184 DDP_COMPONENT_CCORR,
185 DDP_COMPONENT_AAL0,
186 DDP_COMPONENT_GAMMA,
187 DDP_COMPONENT_POSTMASK0,
188 DDP_COMPONENT_DITHER0,
189 };
190
191 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
192 {0, DDP_COMPONENT_DP_INTF0},
193 {0, DDP_COMPONENT_DSI0},
194 };
195
196 static const unsigned int mt8192_mtk_ddp_main[] = {
197 DDP_COMPONENT_OVL0,
198 DDP_COMPONENT_OVL_2L0,
199 DDP_COMPONENT_RDMA0,
200 DDP_COMPONENT_COLOR0,
201 DDP_COMPONENT_CCORR,
202 DDP_COMPONENT_AAL0,
203 DDP_COMPONENT_GAMMA,
204 DDP_COMPONENT_POSTMASK0,
205 DDP_COMPONENT_DITHER0,
206 DDP_COMPONENT_DSI0,
207 };
208
209 static const unsigned int mt8192_mtk_ddp_ext[] = {
210 DDP_COMPONENT_OVL_2L2,
211 DDP_COMPONENT_RDMA4,
212 DDP_COMPONENT_DPI0,
213 };
214
215 static const unsigned int mt8195_mtk_ddp_main[] = {
216 DDP_COMPONENT_OVL0,
217 DDP_COMPONENT_RDMA0,
218 DDP_COMPONENT_COLOR0,
219 DDP_COMPONENT_CCORR,
220 DDP_COMPONENT_AAL0,
221 DDP_COMPONENT_GAMMA,
222 DDP_COMPONENT_DITHER0,
223 DDP_COMPONENT_DSC0,
224 DDP_COMPONENT_MERGE0,
225 DDP_COMPONENT_DP_INTF0,
226 };
227
228 static const unsigned int mt8195_mtk_ddp_ext[] = {
229 DDP_COMPONENT_DRM_OVL_ADAPTOR,
230 DDP_COMPONENT_MERGE5,
231 DDP_COMPONENT_DP_INTF1,
232 };
233
234 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
235 .main_path = mt2701_mtk_ddp_main,
236 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
237 .ext_path = mt2701_mtk_ddp_ext,
238 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
239 .shadow_register = true,
240 .mmsys_dev_num = 1,
241 };
242
243 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
244 .main_path = mt7623_mtk_ddp_main,
245 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
246 .ext_path = mt7623_mtk_ddp_ext,
247 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
248 .shadow_register = true,
249 .mmsys_dev_num = 1,
250 };
251
252 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
253 .main_path = mt2712_mtk_ddp_main,
254 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
255 .ext_path = mt2712_mtk_ddp_ext,
256 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
257 .third_path = mt2712_mtk_ddp_third,
258 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
259 .mmsys_dev_num = 1,
260 };
261
262 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
263 .main_path = mt8167_mtk_ddp_main,
264 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
265 .mmsys_dev_num = 1,
266 };
267
268 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
269 .main_path = mt8173_mtk_ddp_main,
270 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
271 .ext_path = mt8173_mtk_ddp_ext,
272 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
273 .mmsys_dev_num = 1,
274 };
275
276 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
277 .main_path = mt8183_mtk_ddp_main,
278 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
279 .ext_path = mt8183_mtk_ddp_ext,
280 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
281 .mmsys_dev_num = 1,
282 };
283
284 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
285 .main_path = mt8186_mtk_ddp_main,
286 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
287 .ext_path = mt8186_mtk_ddp_ext,
288 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
289 .mmsys_dev_num = 1,
290 };
291
292 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
293 .main_path = mt8188_mtk_ddp_main,
294 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
295 .conn_routes = mt8188_mtk_ddp_main_routes,
296 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
297 .mmsys_dev_num = 2,
298 .max_width = 8191,
299 .min_width = 1,
300 .min_height = 1,
301 };
302
303 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
304 .main_path = mt8192_mtk_ddp_main,
305 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
306 .ext_path = mt8192_mtk_ddp_ext,
307 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
308 .mmsys_dev_num = 1,
309 };
310
311 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
312 .main_path = mt8195_mtk_ddp_main,
313 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
314 .mmsys_dev_num = 2,
315 .max_width = 8191,
316 .min_width = 1,
317 .min_height = 1,
318 };
319
320 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
321 .ext_path = mt8195_mtk_ddp_ext,
322 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
323 .mmsys_id = 1,
324 .mmsys_dev_num = 2,
325 .max_width = 8191,
326 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
327 .min_height = 1,
328 };
329
330 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
331 .mmsys_dev_num = 1,
332 };
333
334 static const struct of_device_id mtk_drm_of_ids[] = {
335 { .compatible = "mediatek,mt2701-mmsys",
336 .data = &mt2701_mmsys_driver_data},
337 { .compatible = "mediatek,mt7623-mmsys",
338 .data = &mt7623_mmsys_driver_data},
339 { .compatible = "mediatek,mt2712-mmsys",
340 .data = &mt2712_mmsys_driver_data},
341 { .compatible = "mediatek,mt8167-mmsys",
342 .data = &mt8167_mmsys_driver_data},
343 { .compatible = "mediatek,mt8173-mmsys",
344 .data = &mt8173_mmsys_driver_data},
345 { .compatible = "mediatek,mt8183-mmsys",
346 .data = &mt8183_mmsys_driver_data},
347 { .compatible = "mediatek,mt8186-mmsys",
348 .data = &mt8186_mmsys_driver_data},
349 { .compatible = "mediatek,mt8188-vdosys0",
350 .data = &mt8188_vdosys0_driver_data},
351 { .compatible = "mediatek,mt8188-vdosys1",
352 .data = &mt8195_vdosys1_driver_data},
353 { .compatible = "mediatek,mt8192-mmsys",
354 .data = &mt8192_mmsys_driver_data},
355 { .compatible = "mediatek,mt8195-mmsys",
356 .data = &mt8195_vdosys0_driver_data},
357 { .compatible = "mediatek,mt8195-vdosys0",
358 .data = &mt8195_vdosys0_driver_data},
359 { .compatible = "mediatek,mt8195-vdosys1",
360 .data = &mt8195_vdosys1_driver_data},
361 { .compatible = "mediatek,mt8365-mmsys",
362 .data = &mt8365_mmsys_driver_data},
363 { }
364 };
365 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
366
mtk_drm_match(struct device * dev,const void * data)367 static int mtk_drm_match(struct device *dev, const void *data)
368 {
369 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
370 return true;
371 return false;
372 }
373
mtk_drm_get_all_drm_priv(struct device * dev)374 static bool mtk_drm_get_all_drm_priv(struct device *dev)
375 {
376 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
377 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
378 struct mtk_drm_private *temp_drm_priv;
379 struct device_node *phandle = dev->parent->of_node;
380 const struct of_device_id *of_id;
381 struct device_node *node;
382 struct device *drm_dev;
383 unsigned int cnt = 0;
384 int i, j;
385
386 for_each_child_of_node(phandle->parent, node) {
387 struct platform_device *pdev;
388
389 of_id = of_match_node(mtk_drm_of_ids, node);
390 if (!of_id)
391 continue;
392
393 pdev = of_find_device_by_node(node);
394 if (!pdev)
395 continue;
396
397 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
398 if (!drm_dev)
399 continue;
400
401 temp_drm_priv = dev_get_drvdata(drm_dev);
402 if (!temp_drm_priv)
403 continue;
404
405 if (temp_drm_priv->data->main_len)
406 all_drm_priv[CRTC_MAIN] = temp_drm_priv;
407 else if (temp_drm_priv->data->ext_len)
408 all_drm_priv[CRTC_EXT] = temp_drm_priv;
409 else if (temp_drm_priv->data->third_len)
410 all_drm_priv[CRTC_THIRD] = temp_drm_priv;
411
412 if (temp_drm_priv->mtk_drm_bound)
413 cnt++;
414
415 if (cnt == MAX_CRTC) {
416 of_node_put(node);
417 break;
418 }
419 }
420
421 if (drm_priv->data->mmsys_dev_num == cnt) {
422 for (i = 0; i < cnt; i++)
423 for (j = 0; j < cnt; j++)
424 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
425
426 return true;
427 }
428
429 return false;
430 }
431
mtk_drm_find_mmsys_comp(struct mtk_drm_private * private,int comp_id)432 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
433 {
434 const struct mtk_mmsys_driver_data *drv_data = private->data;
435 int i;
436
437 if (drv_data->main_path)
438 for (i = 0; i < drv_data->main_len; i++)
439 if (drv_data->main_path[i] == comp_id)
440 return true;
441
442 if (drv_data->ext_path)
443 for (i = 0; i < drv_data->ext_len; i++)
444 if (drv_data->ext_path[i] == comp_id)
445 return true;
446
447 if (drv_data->third_path)
448 for (i = 0; i < drv_data->third_len; i++)
449 if (drv_data->third_path[i] == comp_id)
450 return true;
451
452 if (drv_data->num_conn_routes)
453 for (i = 0; i < drv_data->num_conn_routes; i++)
454 if (drv_data->conn_routes[i].route_ddp == comp_id)
455 return true;
456
457 return false;
458 }
459
mtk_drm_kms_init(struct drm_device * drm)460 static int mtk_drm_kms_init(struct drm_device *drm)
461 {
462 struct mtk_drm_private *private = drm->dev_private;
463 struct mtk_drm_private *priv_n;
464 struct device *dma_dev = NULL;
465 struct drm_crtc *crtc;
466 int ret, i, j;
467
468 if (drm_firmware_drivers_only())
469 return -ENODEV;
470
471 ret = drmm_mode_config_init(drm);
472 if (ret)
473 goto put_mutex_dev;
474
475 drm->mode_config.min_width = 64;
476 drm->mode_config.min_height = 64;
477
478 /*
479 * set max width and height as default value(4096x4096).
480 * this value would be used to check framebuffer size limitation
481 * at drm_mode_addfb().
482 */
483 drm->mode_config.max_width = 4096;
484 drm->mode_config.max_height = 4096;
485 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
486 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
487
488 for (i = 0; i < private->data->mmsys_dev_num; i++) {
489 drm->dev_private = private->all_drm_private[i];
490 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
491 if (ret)
492 goto put_mutex_dev;
493 }
494
495 /*
496 * Ensure internal panels are at the top of the connector list before
497 * crtc creation.
498 */
499 drm_helper_move_panel_connectors_to_head(drm);
500
501 /*
502 * 1. We currently support two fixed data streams, each optional,
503 * and each statically assigned to a crtc:
504 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
505 * 2. For multi mmsys architecture, crtc path data are located in
506 * different drm private data structures. Loop through crtc index to
507 * create crtc from the main path and then ext_path and finally the
508 * third path.
509 */
510 for (i = 0; i < MAX_CRTC; i++) {
511 for (j = 0; j < private->data->mmsys_dev_num; j++) {
512 priv_n = private->all_drm_private[j];
513
514 if (priv_n->data->max_width)
515 drm->mode_config.max_width = priv_n->data->max_width;
516
517 if (priv_n->data->min_width)
518 drm->mode_config.min_width = priv_n->data->min_width;
519
520 if (priv_n->data->min_height)
521 drm->mode_config.min_height = priv_n->data->min_height;
522
523 if (i == CRTC_MAIN && priv_n->data->main_len) {
524 ret = mtk_crtc_create(drm, priv_n->data->main_path,
525 priv_n->data->main_len, j,
526 priv_n->data->conn_routes,
527 priv_n->data->num_conn_routes);
528 if (ret)
529 goto err_component_unbind;
530
531 continue;
532 } else if (i == CRTC_EXT && priv_n->data->ext_len) {
533 ret = mtk_crtc_create(drm, priv_n->data->ext_path,
534 priv_n->data->ext_len, j, NULL, 0);
535 if (ret)
536 goto err_component_unbind;
537
538 continue;
539 } else if (i == CRTC_THIRD && priv_n->data->third_len) {
540 ret = mtk_crtc_create(drm, priv_n->data->third_path,
541 priv_n->data->third_len, j, NULL, 0);
542 if (ret)
543 goto err_component_unbind;
544
545 continue;
546 }
547 }
548 }
549
550 /* IGT will check if the cursor size is configured */
551 drm->mode_config.cursor_width = 512;
552 drm->mode_config.cursor_height = 512;
553
554 /* Use OVL device for all DMA memory allocations */
555 crtc = drm_crtc_from_index(drm, 0);
556 if (crtc)
557 dma_dev = mtk_crtc_dma_dev_get(crtc);
558 if (!dma_dev) {
559 ret = -ENODEV;
560 dev_err(drm->dev, "Need at least one OVL device\n");
561 goto err_component_unbind;
562 }
563
564 for (i = 0; i < private->data->mmsys_dev_num; i++)
565 private->all_drm_private[i]->dma_dev = dma_dev;
566
567 /*
568 * Configure the DMA segment size to make sure we get contiguous IOVA
569 * when importing PRIME buffers.
570 */
571 dma_set_max_seg_size(dma_dev, UINT_MAX);
572
573 ret = drm_vblank_init(drm, MAX_CRTC);
574 if (ret < 0)
575 goto err_component_unbind;
576
577 drm_kms_helper_poll_init(drm);
578 drm_mode_config_reset(drm);
579
580 return 0;
581
582 err_component_unbind:
583 for (i = 0; i < private->data->mmsys_dev_num; i++)
584 component_unbind_all(private->all_drm_private[i]->dev, drm);
585 put_mutex_dev:
586 for (i = 0; i < private->data->mmsys_dev_num; i++)
587 put_device(private->all_drm_private[i]->mutex_dev);
588
589 return ret;
590 }
591
mtk_drm_kms_deinit(struct drm_device * drm)592 static void mtk_drm_kms_deinit(struct drm_device *drm)
593 {
594 drm_kms_helper_poll_fini(drm);
595 drm_atomic_helper_shutdown(drm);
596
597 component_unbind_all(drm->dev, drm);
598 }
599
600 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
601
602 /*
603 * We need to override this because the device used to import the memory is
604 * not dev->dev, as drm_gem_prime_import() expects.
605 */
mtk_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)606 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev,
607 struct dma_buf *dma_buf)
608 {
609 struct mtk_drm_private *private = dev->dev_private;
610
611 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
612 }
613
614 static const struct drm_driver mtk_drm_driver = {
615 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
616
617 .dumb_create = mtk_gem_dumb_create,
618 DRM_FBDEV_DMA_DRIVER_OPS,
619
620 .gem_prime_import = mtk_gem_prime_import,
621 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
622 .fops = &mtk_drm_fops,
623
624 .name = DRIVER_NAME,
625 .desc = DRIVER_DESC,
626 .major = DRIVER_MAJOR,
627 .minor = DRIVER_MINOR,
628 };
629
compare_dev(struct device * dev,void * data)630 static int compare_dev(struct device *dev, void *data)
631 {
632 return dev == (struct device *)data;
633 }
634
mtk_drm_bind(struct device * dev)635 static int mtk_drm_bind(struct device *dev)
636 {
637 struct mtk_drm_private *private = dev_get_drvdata(dev);
638 struct platform_device *pdev;
639 struct drm_device *drm;
640 int ret, i;
641
642 pdev = of_find_device_by_node(private->mutex_node);
643 if (!pdev) {
644 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
645 private->mutex_node);
646 of_node_put(private->mutex_node);
647 return -EPROBE_DEFER;
648 }
649
650 private->mutex_dev = &pdev->dev;
651 private->mtk_drm_bound = true;
652 private->dev = dev;
653
654 if (!mtk_drm_get_all_drm_priv(dev))
655 return 0;
656
657 drm = drm_dev_alloc(&mtk_drm_driver, dev);
658 if (IS_ERR(drm))
659 return PTR_ERR(drm);
660
661 private->drm_master = true;
662 drm->dev_private = private;
663 for (i = 0; i < private->data->mmsys_dev_num; i++)
664 private->all_drm_private[i]->drm = drm;
665
666 ret = mtk_drm_kms_init(drm);
667 if (ret < 0)
668 goto err_free;
669
670 ret = drm_dev_register(drm, 0);
671 if (ret < 0)
672 goto err_deinit;
673
674 drm_client_setup(drm, NULL);
675
676 return 0;
677
678 err_deinit:
679 mtk_drm_kms_deinit(drm);
680 err_free:
681 private->drm = NULL;
682 drm_dev_put(drm);
683 for (i = 0; i < private->data->mmsys_dev_num; i++)
684 private->all_drm_private[i]->drm = NULL;
685 return ret;
686 }
687
mtk_drm_unbind(struct device * dev)688 static void mtk_drm_unbind(struct device *dev)
689 {
690 struct mtk_drm_private *private = dev_get_drvdata(dev);
691
692 /* for multi mmsys dev, unregister drm dev in mmsys master */
693 if (private->drm_master) {
694 drm_dev_unregister(private->drm);
695 mtk_drm_kms_deinit(private->drm);
696 drm_dev_put(private->drm);
697 }
698 private->mtk_drm_bound = false;
699 private->drm_master = false;
700 private->drm = NULL;
701 }
702
703 static const struct component_master_ops mtk_drm_ops = {
704 .bind = mtk_drm_bind,
705 .unbind = mtk_drm_unbind,
706 };
707
708 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
709 { .compatible = "mediatek,mt8167-disp-aal",
710 .data = (void *)MTK_DISP_AAL},
711 { .compatible = "mediatek,mt8173-disp-aal",
712 .data = (void *)MTK_DISP_AAL},
713 { .compatible = "mediatek,mt8183-disp-aal",
714 .data = (void *)MTK_DISP_AAL},
715 { .compatible = "mediatek,mt8192-disp-aal",
716 .data = (void *)MTK_DISP_AAL},
717 { .compatible = "mediatek,mt8167-disp-ccorr",
718 .data = (void *)MTK_DISP_CCORR },
719 { .compatible = "mediatek,mt8183-disp-ccorr",
720 .data = (void *)MTK_DISP_CCORR },
721 { .compatible = "mediatek,mt8192-disp-ccorr",
722 .data = (void *)MTK_DISP_CCORR },
723 { .compatible = "mediatek,mt2701-disp-color",
724 .data = (void *)MTK_DISP_COLOR },
725 { .compatible = "mediatek,mt8167-disp-color",
726 .data = (void *)MTK_DISP_COLOR },
727 { .compatible = "mediatek,mt8173-disp-color",
728 .data = (void *)MTK_DISP_COLOR },
729 { .compatible = "mediatek,mt8167-disp-dither",
730 .data = (void *)MTK_DISP_DITHER },
731 { .compatible = "mediatek,mt8183-disp-dither",
732 .data = (void *)MTK_DISP_DITHER },
733 { .compatible = "mediatek,mt8195-disp-dsc",
734 .data = (void *)MTK_DISP_DSC },
735 { .compatible = "mediatek,mt8167-disp-gamma",
736 .data = (void *)MTK_DISP_GAMMA, },
737 { .compatible = "mediatek,mt8173-disp-gamma",
738 .data = (void *)MTK_DISP_GAMMA, },
739 { .compatible = "mediatek,mt8183-disp-gamma",
740 .data = (void *)MTK_DISP_GAMMA, },
741 { .compatible = "mediatek,mt8195-disp-gamma",
742 .data = (void *)MTK_DISP_GAMMA, },
743 { .compatible = "mediatek,mt8195-disp-merge",
744 .data = (void *)MTK_DISP_MERGE },
745 { .compatible = "mediatek,mt2701-disp-mutex",
746 .data = (void *)MTK_DISP_MUTEX },
747 { .compatible = "mediatek,mt2712-disp-mutex",
748 .data = (void *)MTK_DISP_MUTEX },
749 { .compatible = "mediatek,mt8167-disp-mutex",
750 .data = (void *)MTK_DISP_MUTEX },
751 { .compatible = "mediatek,mt8173-disp-mutex",
752 .data = (void *)MTK_DISP_MUTEX },
753 { .compatible = "mediatek,mt8183-disp-mutex",
754 .data = (void *)MTK_DISP_MUTEX },
755 { .compatible = "mediatek,mt8186-disp-mutex",
756 .data = (void *)MTK_DISP_MUTEX },
757 { .compatible = "mediatek,mt8188-disp-mutex",
758 .data = (void *)MTK_DISP_MUTEX },
759 { .compatible = "mediatek,mt8192-disp-mutex",
760 .data = (void *)MTK_DISP_MUTEX },
761 { .compatible = "mediatek,mt8195-disp-mutex",
762 .data = (void *)MTK_DISP_MUTEX },
763 { .compatible = "mediatek,mt8365-disp-mutex",
764 .data = (void *)MTK_DISP_MUTEX },
765 { .compatible = "mediatek,mt8173-disp-od",
766 .data = (void *)MTK_DISP_OD },
767 { .compatible = "mediatek,mt2701-disp-ovl",
768 .data = (void *)MTK_DISP_OVL },
769 { .compatible = "mediatek,mt8167-disp-ovl",
770 .data = (void *)MTK_DISP_OVL },
771 { .compatible = "mediatek,mt8173-disp-ovl",
772 .data = (void *)MTK_DISP_OVL },
773 { .compatible = "mediatek,mt8183-disp-ovl",
774 .data = (void *)MTK_DISP_OVL },
775 { .compatible = "mediatek,mt8192-disp-ovl",
776 .data = (void *)MTK_DISP_OVL },
777 { .compatible = "mediatek,mt8195-disp-ovl",
778 .data = (void *)MTK_DISP_OVL },
779 { .compatible = "mediatek,mt8183-disp-ovl-2l",
780 .data = (void *)MTK_DISP_OVL_2L },
781 { .compatible = "mediatek,mt8192-disp-ovl-2l",
782 .data = (void *)MTK_DISP_OVL_2L },
783 { .compatible = "mediatek,mt8192-disp-postmask",
784 .data = (void *)MTK_DISP_POSTMASK },
785 { .compatible = "mediatek,mt2701-disp-pwm",
786 .data = (void *)MTK_DISP_BLS },
787 { .compatible = "mediatek,mt8167-disp-pwm",
788 .data = (void *)MTK_DISP_PWM },
789 { .compatible = "mediatek,mt8173-disp-pwm",
790 .data = (void *)MTK_DISP_PWM },
791 { .compatible = "mediatek,mt2701-disp-rdma",
792 .data = (void *)MTK_DISP_RDMA },
793 { .compatible = "mediatek,mt8167-disp-rdma",
794 .data = (void *)MTK_DISP_RDMA },
795 { .compatible = "mediatek,mt8173-disp-rdma",
796 .data = (void *)MTK_DISP_RDMA },
797 { .compatible = "mediatek,mt8183-disp-rdma",
798 .data = (void *)MTK_DISP_RDMA },
799 { .compatible = "mediatek,mt8195-disp-rdma",
800 .data = (void *)MTK_DISP_RDMA },
801 { .compatible = "mediatek,mt8173-disp-ufoe",
802 .data = (void *)MTK_DISP_UFOE },
803 { .compatible = "mediatek,mt8173-disp-wdma",
804 .data = (void *)MTK_DISP_WDMA },
805 { .compatible = "mediatek,mt2701-dpi",
806 .data = (void *)MTK_DPI },
807 { .compatible = "mediatek,mt8167-dsi",
808 .data = (void *)MTK_DSI },
809 { .compatible = "mediatek,mt8173-dpi",
810 .data = (void *)MTK_DPI },
811 { .compatible = "mediatek,mt8183-dpi",
812 .data = (void *)MTK_DPI },
813 { .compatible = "mediatek,mt8186-dpi",
814 .data = (void *)MTK_DPI },
815 { .compatible = "mediatek,mt8188-dp-intf",
816 .data = (void *)MTK_DP_INTF },
817 { .compatible = "mediatek,mt8192-dpi",
818 .data = (void *)MTK_DPI },
819 { .compatible = "mediatek,mt8195-dp-intf",
820 .data = (void *)MTK_DP_INTF },
821 { .compatible = "mediatek,mt8195-dpi",
822 .data = (void *)MTK_DPI },
823 { .compatible = "mediatek,mt2701-dsi",
824 .data = (void *)MTK_DSI },
825 { .compatible = "mediatek,mt8173-dsi",
826 .data = (void *)MTK_DSI },
827 { .compatible = "mediatek,mt8183-dsi",
828 .data = (void *)MTK_DSI },
829 { .compatible = "mediatek,mt8186-dsi",
830 .data = (void *)MTK_DSI },
831 { .compatible = "mediatek,mt8188-dsi",
832 .data = (void *)MTK_DSI },
833 { }
834 };
835
mtk_drm_of_get_ddp_comp_type(struct device_node * node,enum mtk_ddp_comp_type * ctype)836 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype)
837 {
838 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
839
840 if (!of_id)
841 return -EINVAL;
842
843 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data);
844
845 return 0;
846 }
847
mtk_drm_of_get_ddp_ep_cid(struct device_node * node,int output_port,enum mtk_crtc_path crtc_path,struct device_node ** next,unsigned int * cid)848 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
849 int output_port, enum mtk_crtc_path crtc_path,
850 struct device_node **next, unsigned int *cid)
851 {
852 struct device_node *ep_dev_node, *ep_out;
853 enum mtk_ddp_comp_type comp_type;
854 int ret;
855
856 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path);
857 if (!ep_out)
858 return -ENOENT;
859
860 ep_dev_node = of_graph_get_remote_port_parent(ep_out);
861 of_node_put(ep_out);
862 if (!ep_dev_node)
863 return -EINVAL;
864
865 /*
866 * Pass the next node pointer regardless of failures in the later code
867 * so that if this function is called in a loop it will walk through all
868 * of the subsequent endpoints anyway.
869 */
870 *next = ep_dev_node;
871
872 if (!of_device_is_available(ep_dev_node))
873 return -ENODEV;
874
875 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type);
876 if (ret) {
877 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) {
878 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR;
879 return 0;
880 }
881 return ret;
882 }
883
884 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type);
885 if (ret < 0)
886 return ret;
887
888 /* All ok! Pass the Component ID to the caller. */
889 *cid = (unsigned int)ret;
890
891 return 0;
892 }
893
894 /**
895 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path
896 * @dev: The mediatek-drm device
897 * @cpath: CRTC Path relative to a VDO or MMSYS
898 * @out_path: Pointer to an array that will contain the new pipeline
899 * @out_path_len: Number of entries in the pipeline array
900 *
901 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending
902 * on the board-specific desired display configuration; this function walks
903 * through all of the output endpoints starting from a VDO or MMSYS hardware
904 * instance and builds the right pipeline as specified in device trees.
905 *
906 * Return:
907 * * %0 - Display HW Pipeline successfully built and validated
908 * * %-ENOENT - Display pipeline was not specified in device tree
909 * * %-EINVAL - Display pipeline built but validation failed
910 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller
911 */
mtk_drm_of_ddp_path_build_one(struct device * dev,enum mtk_crtc_path cpath,const unsigned int ** out_path,unsigned int * out_path_len)912 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath,
913 const unsigned int **out_path,
914 unsigned int *out_path_len)
915 {
916 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node;
917 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 };
918 unsigned int *final_ddp_path;
919 unsigned short int idx = 0;
920 bool ovl_adaptor_comp_added = false;
921 int ret;
922
923 /* Get the first entry for the temp_path array */
924 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]);
925 if (ret) {
926 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
927 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next);
928 ovl_adaptor_comp_added = true;
929 } else {
930 if (next)
931 dev_err(dev, "Invalid component %pOF\n", next);
932 else
933 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath);
934
935 return ret;
936 }
937 }
938 idx++;
939
940 /*
941 * Walk through port outputs until we reach the last valid mediatek-drm component.
942 * To be valid, this must end with an "invalid" component that is a display node.
943 */
944 do {
945 prev = next;
946 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]);
947 of_node_put(prev);
948 if (ret) {
949 of_node_put(next);
950 break;
951 }
952
953 /*
954 * If this is an OVL adaptor exclusive component and one of those
955 * was already added, don't add another instance of the generic
956 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether
957 * to probe that component master driver of which only one instance
958 * is needed and possible.
959 */
960 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
961 if (!ovl_adaptor_comp_added)
962 ovl_adaptor_comp_added = true;
963 else
964 idx--;
965 }
966 } while (++idx < DDP_COMPONENT_DRM_ID_MAX);
967
968 /*
969 * The device component might not be enabled: in that case, don't
970 * check the last entry and just report that the device is missing.
971 */
972 if (ret == -ENODEV)
973 return ret;
974
975 /* If the last entry is not a final display output, the configuration is wrong */
976 switch (temp_path[idx - 1]) {
977 case DDP_COMPONENT_DP_INTF0:
978 case DDP_COMPONENT_DP_INTF1:
979 case DDP_COMPONENT_DPI0:
980 case DDP_COMPONENT_DPI1:
981 case DDP_COMPONENT_DSI0:
982 case DDP_COMPONENT_DSI1:
983 case DDP_COMPONENT_DSI2:
984 case DDP_COMPONENT_DSI3:
985 break;
986 default:
987 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n",
988 temp_path[idx - 1], ret);
989 return -EINVAL;
990 }
991
992 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL);
993 if (!final_ddp_path)
994 return -ENOMEM;
995
996 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx);
997
998 /* Pipeline built! */
999 *out_path = final_ddp_path;
1000 *out_path_len = idx;
1001
1002 return 0;
1003 }
1004
mtk_drm_of_ddp_path_build(struct device * dev,struct device_node * node,struct mtk_mmsys_driver_data * data)1005 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node,
1006 struct mtk_mmsys_driver_data *data)
1007 {
1008 struct device_node *ep_node;
1009 struct of_endpoint of_ep;
1010 bool output_present[MAX_CRTC] = { false };
1011 int ret;
1012
1013 for_each_endpoint_of_node(node, ep_node) {
1014 ret = of_graph_parse_endpoint(ep_node, &of_ep);
1015 if (ret) {
1016 dev_err_probe(dev, ret, "Cannot parse endpoint\n");
1017 break;
1018 }
1019
1020 if (of_ep.id >= MAX_CRTC) {
1021 ret = dev_err_probe(dev, -EINVAL,
1022 "Invalid endpoint%u number\n", of_ep.port);
1023 break;
1024 }
1025
1026 output_present[of_ep.id] = true;
1027 }
1028
1029 if (ret) {
1030 of_node_put(ep_node);
1031 return ret;
1032 }
1033
1034 if (output_present[CRTC_MAIN]) {
1035 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN,
1036 &data->main_path, &data->main_len);
1037 if (ret && ret != -ENODEV)
1038 return ret;
1039 }
1040
1041 if (output_present[CRTC_EXT]) {
1042 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT,
1043 &data->ext_path, &data->ext_len);
1044 if (ret && ret != -ENODEV)
1045 return ret;
1046 }
1047
1048 if (output_present[CRTC_THIRD]) {
1049 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD,
1050 &data->third_path, &data->third_len);
1051 if (ret && ret != -ENODEV)
1052 return ret;
1053 }
1054
1055 return 0;
1056 }
1057
mtk_drm_probe(struct platform_device * pdev)1058 static int mtk_drm_probe(struct platform_device *pdev)
1059 {
1060 struct device *dev = &pdev->dev;
1061 struct device_node *phandle = dev->parent->of_node;
1062 const struct of_device_id *of_id;
1063 struct mtk_drm_private *private;
1064 struct mtk_mmsys_driver_data *mtk_drm_data;
1065 struct device_node *node;
1066 struct component_match *match = NULL;
1067 struct platform_device *ovl_adaptor;
1068 int ret;
1069 int i;
1070
1071 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
1072 if (!private)
1073 return -ENOMEM;
1074
1075 private->mmsys_dev = dev->parent;
1076 if (!private->mmsys_dev) {
1077 dev_err(dev, "Failed to get MMSYS device\n");
1078 return -ENODEV;
1079 }
1080
1081 of_id = of_match_node(mtk_drm_of_ids, phandle);
1082 if (!of_id)
1083 return -ENODEV;
1084
1085 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data;
1086 if (!mtk_drm_data)
1087 return -EINVAL;
1088
1089 /* Try to build the display pipeline from devicetree graphs */
1090 if (of_graph_is_present(phandle)) {
1091 dev_dbg(dev, "Building display pipeline for MMSYS %u\n",
1092 mtk_drm_data->mmsys_id);
1093 private->data = devm_kmemdup(dev, mtk_drm_data,
1094 sizeof(*mtk_drm_data), GFP_KERNEL);
1095 if (!private->data)
1096 return -ENOMEM;
1097
1098 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data);
1099 if (ret)
1100 return ret;
1101 } else {
1102 /* No devicetree graphs support: go with hardcoded paths if present */
1103 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id);
1104 private->data = mtk_drm_data;
1105 }
1106
1107 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
1108 sizeof(*private->all_drm_private),
1109 GFP_KERNEL);
1110 if (!private->all_drm_private)
1111 return -ENOMEM;
1112
1113 /* Bringup ovl_adaptor */
1114 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
1115 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
1116 PLATFORM_DEVID_AUTO,
1117 (void *)private->mmsys_dev,
1118 sizeof(*private->mmsys_dev));
1119 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
1120 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
1121 DDP_COMPONENT_DRM_OVL_ADAPTOR);
1122 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
1123 }
1124
1125 /* Iterate over sibling DISP function blocks */
1126 for_each_child_of_node(phandle->parent, node) {
1127 enum mtk_ddp_comp_type comp_type;
1128 int comp_id;
1129
1130 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type);
1131 if (ret)
1132 continue;
1133
1134 if (!of_device_is_available(node)) {
1135 dev_dbg(dev, "Skipping disabled component %pOF\n",
1136 node);
1137 continue;
1138 }
1139
1140 if (comp_type == MTK_DISP_MUTEX) {
1141 int id;
1142
1143 id = of_alias_get_id(node, "mutex");
1144 if (id < 0 || id == private->data->mmsys_id) {
1145 private->mutex_node = of_node_get(node);
1146 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
1147 }
1148 continue;
1149 }
1150
1151 comp_id = mtk_ddp_comp_get_id(node, comp_type);
1152 if (comp_id < 0) {
1153 dev_warn(dev, "Skipping unknown component %pOF\n",
1154 node);
1155 continue;
1156 }
1157
1158 if (!mtk_drm_find_mmsys_comp(private, comp_id))
1159 continue;
1160
1161 private->comp_node[comp_id] = of_node_get(node);
1162
1163 /*
1164 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
1165 * blocks have separate component platform drivers and initialize their own
1166 * DDP component structure. The others are initialized here.
1167 */
1168 if (comp_type == MTK_DISP_AAL ||
1169 comp_type == MTK_DISP_CCORR ||
1170 comp_type == MTK_DISP_COLOR ||
1171 comp_type == MTK_DISP_GAMMA ||
1172 comp_type == MTK_DISP_MERGE ||
1173 comp_type == MTK_DISP_OVL ||
1174 comp_type == MTK_DISP_OVL_2L ||
1175 comp_type == MTK_DISP_OVL_ADAPTOR ||
1176 comp_type == MTK_DISP_RDMA ||
1177 comp_type == MTK_DP_INTF ||
1178 comp_type == MTK_DPI ||
1179 comp_type == MTK_DSI) {
1180 dev_info(dev, "Adding component match for %pOF\n",
1181 node);
1182 drm_of_component_match_add(dev, &match, component_compare_of,
1183 node);
1184 }
1185
1186 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
1187 if (ret) {
1188 of_node_put(node);
1189 goto err_node;
1190 }
1191 }
1192
1193 if (!private->mutex_node) {
1194 dev_err(dev, "Failed to find disp-mutex node\n");
1195 ret = -ENODEV;
1196 goto err_node;
1197 }
1198
1199 pm_runtime_enable(dev);
1200
1201 platform_set_drvdata(pdev, private);
1202
1203 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
1204 if (ret)
1205 goto err_pm;
1206
1207 return 0;
1208
1209 err_pm:
1210 pm_runtime_disable(dev);
1211 err_node:
1212 of_node_put(private->mutex_node);
1213 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1214 of_node_put(private->comp_node[i]);
1215 return ret;
1216 }
1217
mtk_drm_remove(struct platform_device * pdev)1218 static void mtk_drm_remove(struct platform_device *pdev)
1219 {
1220 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1221 int i;
1222
1223 component_master_del(&pdev->dev, &mtk_drm_ops);
1224 pm_runtime_disable(&pdev->dev);
1225 of_node_put(private->mutex_node);
1226 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1227 of_node_put(private->comp_node[i]);
1228 }
1229
mtk_drm_shutdown(struct platform_device * pdev)1230 static void mtk_drm_shutdown(struct platform_device *pdev)
1231 {
1232 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1233
1234 drm_atomic_helper_shutdown(private->drm);
1235 }
1236
mtk_drm_sys_prepare(struct device * dev)1237 static int mtk_drm_sys_prepare(struct device *dev)
1238 {
1239 struct mtk_drm_private *private = dev_get_drvdata(dev);
1240 struct drm_device *drm = private->drm;
1241
1242 if (private->drm_master)
1243 return drm_mode_config_helper_suspend(drm);
1244 else
1245 return 0;
1246 }
1247
mtk_drm_sys_complete(struct device * dev)1248 static void mtk_drm_sys_complete(struct device *dev)
1249 {
1250 struct mtk_drm_private *private = dev_get_drvdata(dev);
1251 struct drm_device *drm = private->drm;
1252 int ret = 0;
1253
1254 if (private->drm_master)
1255 ret = drm_mode_config_helper_resume(drm);
1256 if (ret)
1257 dev_err(dev, "Failed to resume\n");
1258 }
1259
1260 static const struct dev_pm_ops mtk_drm_pm_ops = {
1261 .prepare = mtk_drm_sys_prepare,
1262 .complete = mtk_drm_sys_complete,
1263 };
1264
1265 static struct platform_driver mtk_drm_platform_driver = {
1266 .probe = mtk_drm_probe,
1267 .remove = mtk_drm_remove,
1268 .shutdown = mtk_drm_shutdown,
1269 .driver = {
1270 .name = "mediatek-drm",
1271 .pm = &mtk_drm_pm_ops,
1272 },
1273 };
1274
1275 static struct platform_driver * const mtk_drm_drivers[] = {
1276 &mtk_disp_aal_driver,
1277 &mtk_disp_ccorr_driver,
1278 &mtk_disp_color_driver,
1279 &mtk_disp_gamma_driver,
1280 &mtk_disp_merge_driver,
1281 &mtk_disp_ovl_adaptor_driver,
1282 &mtk_disp_ovl_driver,
1283 &mtk_disp_rdma_driver,
1284 &mtk_dpi_driver,
1285 &mtk_drm_platform_driver,
1286 &mtk_dsi_driver,
1287 &mtk_ethdr_driver,
1288 &mtk_mdp_rdma_driver,
1289 &mtk_padding_driver,
1290 };
1291
mtk_drm_init(void)1292 static int __init mtk_drm_init(void)
1293 {
1294 return platform_register_drivers(mtk_drm_drivers,
1295 ARRAY_SIZE(mtk_drm_drivers));
1296 }
1297
mtk_drm_exit(void)1298 static void __exit mtk_drm_exit(void)
1299 {
1300 platform_unregister_drivers(mtk_drm_drivers,
1301 ARRAY_SIZE(mtk_drm_drivers));
1302 }
1303
1304 module_init(mtk_drm_init);
1305 module_exit(mtk_drm_exit);
1306
1307 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1308 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1309 MODULE_LICENSE("GPL v2");
1310