1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2019 Intel Corporation. 4 */ 5 6 #ifndef __INTEL_PCH__ 7 #define __INTEL_PCH__ 8 9 struct drm_i915_private; 10 11 /* 12 * Sorted by south display engine compatibility. 13 * If the new PCH comes with a south display engine that is not 14 * inherited from the latest item, please do not add it to the 15 * end. Instead, add it right after its "parent" PCH. 16 */ 17 enum intel_pch { 18 PCH_NOP = -1, /* PCH without south display */ 19 PCH_NONE = 0, /* No PCH present */ 20 PCH_IBX, /* Ibexpeak PCH */ 21 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ 22 PCH_LPT_H, /* Lynxpoint/Wildcatpoint H PCH */ 23 PCH_LPT_LP, /* Lynxpoint/Wildcatpoint LP PCH */ 24 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ 25 PCH_CNP, /* Cannon/Comet Lake PCH */ 26 PCH_ICP, /* Ice Lake/Jasper Lake PCH */ 27 PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ 28 PCH_ADP, /* Alder Lake PCH */ 29 30 /* Fake PCHs, functionality handled on the same PCI dev */ 31 PCH_DG1 = 1024, 32 PCH_DG2, 33 PCH_MTL, 34 PCH_LNL, 35 }; 36 37 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) 38 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) 39 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) 40 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) 41 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) 42 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) 43 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) 44 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) 45 #define HAS_PCH_LPT_H(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_H) 46 #define HAS_PCH_LPT_LP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_LP) 47 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_H || \ 48 INTEL_PCH_TYPE(dev_priv) == PCH_LPT_LP) 49 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) 50 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) 51 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) 52 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) 53 54 void intel_detect_pch(struct drm_i915_private *dev_priv); 55 56 #endif /* __INTEL_PCH__ */ 57