1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/aperture.h>
31 #include <linux/acpi.h>
32 #include <linux/device.h>
33 #include <linux/module.h>
34 #include <linux/oom.h>
35 #include <linux/pci.h>
36 #include <linux/pm.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/slab.h>
39 #include <linux/string_helpers.h>
40 #include <linux/vga_switcheroo.h>
41 #include <linux/vt.h>
42
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_client.h>
45 #include <drm/drm_client_event.h>
46 #include <drm/drm_ioctl.h>
47 #include <drm/drm_managed.h>
48 #include <drm/drm_probe_helper.h>
49
50 #include "display/i9xx_display_sr.h"
51 #include "display/intel_bw.h"
52 #include "display/intel_cdclk.h"
53 #include "display/intel_crtc.h"
54 #include "display/intel_display_driver.h"
55 #include "display/intel_dmc.h"
56 #include "display/intel_dp.h"
57 #include "display/intel_dpt.h"
58 #include "display/intel_encoder.h"
59 #include "display/intel_fbdev.h"
60 #include "display/intel_hotplug.h"
61 #include "display/intel_overlay.h"
62 #include "display/intel_pch_refclk.h"
63 #include "display/intel_pps.h"
64 #include "display/intel_sprite_uapi.h"
65 #include "display/intel_vga.h"
66 #include "display/skl_watermark.h"
67
68 #include "gem/i915_gem_context.h"
69 #include "gem/i915_gem_create.h"
70 #include "gem/i915_gem_dmabuf.h"
71 #include "gem/i915_gem_ioctls.h"
72 #include "gem/i915_gem_mman.h"
73 #include "gem/i915_gem_pm.h"
74 #include "gt/intel_gt.h"
75 #include "gt/intel_gt_pm.h"
76 #include "gt/intel_gt_print.h"
77 #include "gt/intel_rc6.h"
78
79 #include "pxp/intel_pxp.h"
80 #include "pxp/intel_pxp_debugfs.h"
81 #include "pxp/intel_pxp_pm.h"
82
83 #include "soc/intel_dram.h"
84 #include "soc/intel_gmch.h"
85
86 #include "i915_debugfs.h"
87 #include "i915_driver.h"
88 #include "i915_drm_client.h"
89 #include "i915_drv.h"
90 #include "i915_file_private.h"
91 #include "i915_getparam.h"
92 #include "i915_hwmon.h"
93 #include "i915_ioc32.h"
94 #include "i915_ioctl.h"
95 #include "i915_irq.h"
96 #include "i915_memcpy.h"
97 #include "i915_perf.h"
98 #include "i915_query.h"
99 #include "i915_reg.h"
100 #include "i915_switcheroo.h"
101 #include "i915_sysfs.h"
102 #include "i915_utils.h"
103 #include "i915_vgpu.h"
104 #include "intel_clock_gating.h"
105 #include "intel_cpu_info.h"
106 #include "intel_gvt.h"
107 #include "intel_memory_region.h"
108 #include "intel_pci_config.h"
109 #include "intel_pcode.h"
110 #include "intel_region_ttm.h"
111 #include "intel_sbi.h"
112 #include "vlv_sideband.h"
113 #include "vlv_suspend.h"
114
115 static const struct drm_driver i915_drm_driver;
116
i915_workqueues_init(struct drm_i915_private * dev_priv)117 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
118 {
119 /*
120 * The i915 workqueue is primarily used for batched retirement of
121 * requests (and thus managing bo) once the task has been completed
122 * by the GPU. i915_retire_requests() is called directly when we
123 * need high-priority retirement, such as waiting for an explicit
124 * bo.
125 *
126 * It is also used for periodic low-priority events, such as
127 * idle-timers and recording error state.
128 *
129 * All tasks on the workqueue are expected to acquire the dev mutex
130 * so there is no point in running more than one instance of the
131 * workqueue at any time. Use an ordered one.
132 */
133 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
134 if (dev_priv->wq == NULL)
135 goto out_err;
136
137 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
138 if (dev_priv->display.hotplug.dp_wq == NULL)
139 goto out_free_wq;
140
141 /*
142 * The unordered i915 workqueue should be used for all work
143 * scheduling that do not require running in order, which used
144 * to be scheduled on the system_wq before moving to a driver
145 * instance due deprecation of flush_scheduled_work().
146 */
147 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0);
148 if (dev_priv->unordered_wq == NULL)
149 goto out_free_dp_wq;
150
151 return 0;
152
153 out_free_dp_wq:
154 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
155 out_free_wq:
156 destroy_workqueue(dev_priv->wq);
157 out_err:
158 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
159
160 return -ENOMEM;
161 }
162
i915_workqueues_cleanup(struct drm_i915_private * dev_priv)163 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
164 {
165 destroy_workqueue(dev_priv->unordered_wq);
166 destroy_workqueue(dev_priv->display.hotplug.dp_wq);
167 destroy_workqueue(dev_priv->wq);
168 }
169
170 /*
171 * We don't keep the workarounds for pre-production hardware, so we expect our
172 * driver to fail on these machines in one way or another. A little warning on
173 * dmesg may help both the user and the bug triagers.
174 *
175 * Our policy for removing pre-production workarounds is to keep the
176 * current gen workarounds as a guide to the bring-up of the next gen
177 * (workarounds have a habit of persisting!). Anything older than that
178 * should be removed along with the complications they introduce.
179 */
intel_detect_preproduction_hw(struct drm_i915_private * dev_priv)180 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
181 {
182 bool pre = false;
183
184 pre |= IS_HASWELL_EARLY_SDV(dev_priv);
185 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
186 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
187 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
188 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
189 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
190 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
191 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
192 pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
193 pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
194 pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
195
196 if (pre) {
197 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
198 "It may not be fully functional.\n");
199 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
200 }
201 }
202
sanitize_gpu(struct drm_i915_private * i915)203 static void sanitize_gpu(struct drm_i915_private *i915)
204 {
205 if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) {
206 struct intel_gt *gt;
207 unsigned int i;
208
209 for_each_gt(gt, i915, i)
210 intel_gt_reset_all_engines(gt);
211 }
212 }
213
214 /**
215 * i915_driver_early_probe - setup state not requiring device access
216 * @dev_priv: device private
217 *
218 * Initialize everything that is a "SW-only" state, that is state not
219 * requiring accessing the device or exposing the driver via kernel internal
220 * or userspace interfaces. Example steps belonging here: lock initialization,
221 * system memory allocation, setting up device specific attributes and
222 * function hooks not requiring accessing the device.
223 */
i915_driver_early_probe(struct drm_i915_private * dev_priv)224 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
225 {
226 struct intel_display *display = &dev_priv->display;
227 int ret = 0;
228
229 if (i915_inject_probe_failure(dev_priv))
230 return -ENODEV;
231
232 intel_device_info_runtime_init_early(dev_priv);
233
234 intel_step_init(dev_priv);
235
236 intel_uncore_mmio_debug_init_early(dev_priv);
237
238 spin_lock_init(&dev_priv->irq_lock);
239 spin_lock_init(&dev_priv->gpu_error.lock);
240
241 intel_sbi_init(dev_priv);
242 vlv_iosf_sb_init(dev_priv);
243 mutex_init(&dev_priv->sb_lock);
244
245 i915_memcpy_init_early(dev_priv);
246 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
247
248 ret = i915_workqueues_init(dev_priv);
249 if (ret < 0)
250 return ret;
251
252 ret = vlv_suspend_init(dev_priv);
253 if (ret < 0)
254 goto err_workqueues;
255
256 ret = intel_region_ttm_device_init(dev_priv);
257 if (ret)
258 goto err_ttm;
259
260 ret = intel_root_gt_init_early(dev_priv);
261 if (ret < 0)
262 goto err_rootgt;
263
264 i915_gem_init_early(dev_priv);
265
266 /* This must be called before any calls to HAS_PCH_* */
267 intel_detect_pch(dev_priv);
268
269 intel_irq_init(dev_priv);
270 intel_display_driver_early_probe(display);
271 intel_clock_gating_hooks_init(dev_priv);
272
273 intel_detect_preproduction_hw(dev_priv);
274
275 return 0;
276
277 err_rootgt:
278 intel_region_ttm_device_fini(dev_priv);
279 err_ttm:
280 vlv_suspend_cleanup(dev_priv);
281 err_workqueues:
282 i915_workqueues_cleanup(dev_priv);
283 return ret;
284 }
285
286 /**
287 * i915_driver_late_release - cleanup the setup done in
288 * i915_driver_early_probe()
289 * @dev_priv: device private
290 */
i915_driver_late_release(struct drm_i915_private * dev_priv)291 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
292 {
293 struct intel_display *display = &dev_priv->display;
294
295 intel_irq_fini(dev_priv);
296 intel_power_domains_cleanup(display);
297 i915_gem_cleanup_early(dev_priv);
298 intel_gt_driver_late_release_all(dev_priv);
299 intel_region_ttm_device_fini(dev_priv);
300 vlv_suspend_cleanup(dev_priv);
301 i915_workqueues_cleanup(dev_priv);
302
303 mutex_destroy(&dev_priv->sb_lock);
304 vlv_iosf_sb_fini(dev_priv);
305 intel_sbi_fini(dev_priv);
306
307 i915_params_free(&dev_priv->params);
308 }
309
310 /**
311 * i915_driver_mmio_probe - setup device MMIO
312 * @dev_priv: device private
313 *
314 * Setup minimal device state necessary for MMIO accesses later in the
315 * initialization sequence. The setup here should avoid any other device-wide
316 * side effects or exposing the driver via kernel internal or user space
317 * interfaces.
318 */
i915_driver_mmio_probe(struct drm_i915_private * dev_priv)319 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
320 {
321 struct intel_display *display = &dev_priv->display;
322 struct intel_gt *gt;
323 int ret, i;
324
325 if (i915_inject_probe_failure(dev_priv))
326 return -ENODEV;
327
328 ret = intel_gmch_bridge_setup(dev_priv);
329 if (ret < 0)
330 return ret;
331
332 for_each_gt(gt, dev_priv, i) {
333 ret = intel_uncore_init_mmio(gt->uncore);
334 if (ret)
335 return ret;
336
337 ret = drmm_add_action_or_reset(&dev_priv->drm,
338 intel_uncore_fini_mmio,
339 gt->uncore);
340 if (ret)
341 return ret;
342 }
343
344 /* Try to make sure MCHBAR is enabled before poking at it */
345 intel_gmch_bar_setup(dev_priv);
346 intel_device_info_runtime_init(dev_priv);
347 intel_display_device_info_runtime_init(display);
348
349 for_each_gt(gt, dev_priv, i) {
350 ret = intel_gt_init_mmio(gt);
351 if (ret)
352 goto err_uncore;
353 }
354
355 /* As early as possible, scrub existing GPU state before clobbering */
356 sanitize_gpu(dev_priv);
357
358 return 0;
359
360 err_uncore:
361 intel_gmch_bar_teardown(dev_priv);
362
363 return ret;
364 }
365
366 /**
367 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
368 * @dev_priv: device private
369 */
i915_driver_mmio_release(struct drm_i915_private * dev_priv)370 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
371 {
372 intel_gmch_bar_teardown(dev_priv);
373 }
374
375 /**
376 * i915_set_dma_info - set all relevant PCI dma info as configured for the
377 * platform
378 * @i915: valid i915 instance
379 *
380 * Set the dma max segment size, device and coherent masks. The dma mask set
381 * needs to occur before i915_ggtt_probe_hw.
382 *
383 * A couple of platforms have special needs. Address them as well.
384 *
385 */
i915_set_dma_info(struct drm_i915_private * i915)386 static int i915_set_dma_info(struct drm_i915_private *i915)
387 {
388 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
389 int ret;
390
391 GEM_BUG_ON(!mask_size);
392
393 /*
394 * We don't have a max segment size, so set it to the max so sg's
395 * debugging layer doesn't complain
396 */
397 dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
398
399 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
400 if (ret)
401 goto mask_err;
402
403 /* overlay on gen2 is broken and can't address above 1G */
404 if (GRAPHICS_VER(i915) == 2)
405 mask_size = 30;
406
407 /*
408 * 965GM sometimes incorrectly writes to hardware status page (HWS)
409 * using 32bit addressing, overwriting memory if HWS is located
410 * above 4GB.
411 *
412 * The documentation also mentions an issue with undefined
413 * behaviour if any general state is accessed within a page above 4GB,
414 * which also needs to be handled carefully.
415 */
416 if (IS_I965G(i915) || IS_I965GM(i915))
417 mask_size = 32;
418
419 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
420 if (ret)
421 goto mask_err;
422
423 return 0;
424
425 mask_err:
426 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
427 return ret;
428 }
429
430 /* Wa_14022698537:dg2 */
i915_enable_g8(struct drm_i915_private * i915)431 static void i915_enable_g8(struct drm_i915_private *i915)
432 {
433 if (IS_DG2(i915)) {
434 if (IS_DG2_D(i915) && !intel_match_g8_cpu())
435 return;
436
437 snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP,
438 POWER_SETUP_SUBCOMMAND_G8_ENABLE, 0, 0);
439 }
440 }
441
i915_pcode_init(struct drm_i915_private * i915)442 static int i915_pcode_init(struct drm_i915_private *i915)
443 {
444 struct intel_gt *gt;
445 int id, ret;
446
447 for_each_gt(gt, i915, id) {
448 ret = intel_pcode_init(gt->uncore);
449 if (ret) {
450 gt_err(gt, "intel_pcode_init failed %d\n", ret);
451 return ret;
452 }
453 }
454
455 i915_enable_g8(i915);
456 return 0;
457 }
458
459 /**
460 * i915_driver_hw_probe - setup state requiring device access
461 * @dev_priv: device private
462 *
463 * Setup state that requires accessing the device, but doesn't require
464 * exposing the driver via kernel internal or userspace interfaces.
465 */
i915_driver_hw_probe(struct drm_i915_private * dev_priv)466 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
467 {
468 struct intel_display *display = &dev_priv->display;
469 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
470 int ret;
471
472 if (i915_inject_probe_failure(dev_priv))
473 return -ENODEV;
474
475 if (HAS_PPGTT(dev_priv)) {
476 if (intel_vgpu_active(dev_priv) &&
477 !intel_vgpu_has_full_ppgtt(dev_priv)) {
478 drm_err(&dev_priv->drm,
479 "incompatible vGPU found, support for isolated ppGTT required\n");
480 return -ENXIO;
481 }
482 }
483
484 if (HAS_EXECLISTS(dev_priv)) {
485 /*
486 * Older GVT emulation depends upon intercepting CSB mmio,
487 * which we no longer use, preferring to use the HWSP cache
488 * instead.
489 */
490 if (intel_vgpu_active(dev_priv) &&
491 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
492 drm_err(&dev_priv->drm,
493 "old vGPU host found, support for HWSP emulation required\n");
494 return -ENXIO;
495 }
496 }
497
498 /* needs to be done before ggtt probe */
499 intel_dram_edram_detect(dev_priv);
500
501 ret = i915_set_dma_info(dev_priv);
502 if (ret)
503 return ret;
504
505 ret = i915_perf_init(dev_priv);
506 if (ret)
507 return ret;
508
509 ret = i915_ggtt_probe_hw(dev_priv);
510 if (ret)
511 goto err_perf;
512
513 ret = aperture_remove_conflicting_pci_devices(pdev, dev_priv->drm.driver->name);
514 if (ret)
515 goto err_ggtt;
516
517 ret = i915_ggtt_init_hw(dev_priv);
518 if (ret)
519 goto err_ggtt;
520
521 /*
522 * Make sure we probe lmem before we probe stolen-lmem. The BAR size
523 * might be different due to bar resizing.
524 */
525 ret = intel_gt_tiles_init(dev_priv);
526 if (ret)
527 goto err_ggtt;
528
529 ret = intel_memory_regions_hw_probe(dev_priv);
530 if (ret)
531 goto err_ggtt;
532
533 ret = i915_ggtt_enable_hw(dev_priv);
534 if (ret) {
535 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
536 goto err_mem_regions;
537 }
538
539 pci_set_master(pdev);
540
541 /* On the 945G/GM, the chipset reports the MSI capability on the
542 * integrated graphics even though the support isn't actually there
543 * according to the published specs. It doesn't appear to function
544 * correctly in testing on 945G.
545 * This may be a side effect of MSI having been made available for PEG
546 * and the registers being closely associated.
547 *
548 * According to chipset errata, on the 965GM, MSI interrupts may
549 * be lost or delayed, and was defeatured. MSI interrupts seem to
550 * get lost on g4x as well, and interrupt delivery seems to stay
551 * properly dead afterwards. So we'll just disable them for all
552 * pre-gen5 chipsets.
553 *
554 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
555 * interrupts even when in MSI mode. This results in spurious
556 * interrupt warnings if the legacy irq no. is shared with another
557 * device. The kernel then disables that interrupt source and so
558 * prevents the other device from working properly.
559 */
560 if (GRAPHICS_VER(dev_priv) >= 5) {
561 if (pci_enable_msi(pdev) < 0)
562 drm_dbg(&dev_priv->drm, "can't enable MSI");
563 }
564
565 ret = intel_gvt_init(dev_priv);
566 if (ret)
567 goto err_msi;
568
569 intel_opregion_setup(display);
570
571 ret = i915_pcode_init(dev_priv);
572 if (ret)
573 goto err_opregion;
574
575 /*
576 * Fill the dram structure to get the system dram info. This will be
577 * used for memory latency calculation.
578 */
579 intel_dram_detect(dev_priv);
580
581 intel_bw_init_hw(dev_priv);
582
583 return 0;
584
585 err_opregion:
586 intel_opregion_cleanup(display);
587 err_msi:
588 if (pdev->msi_enabled)
589 pci_disable_msi(pdev);
590 err_mem_regions:
591 intel_memory_regions_driver_release(dev_priv);
592 err_ggtt:
593 i915_ggtt_driver_release(dev_priv);
594 i915_gem_drain_freed_objects(dev_priv);
595 i915_ggtt_driver_late_release(dev_priv);
596 err_perf:
597 i915_perf_fini(dev_priv);
598 return ret;
599 }
600
601 /**
602 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
603 * @dev_priv: device private
604 */
i915_driver_hw_remove(struct drm_i915_private * dev_priv)605 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
606 {
607 struct intel_display *display = &dev_priv->display;
608 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
609
610 i915_perf_fini(dev_priv);
611
612 intel_opregion_cleanup(display);
613
614 if (pdev->msi_enabled)
615 pci_disable_msi(pdev);
616 }
617
618 /**
619 * i915_driver_register - register the driver with the rest of the system
620 * @dev_priv: device private
621 *
622 * Perform any steps necessary to make the driver available via kernel
623 * internal or userspace interfaces.
624 */
i915_driver_register(struct drm_i915_private * dev_priv)625 static void i915_driver_register(struct drm_i915_private *dev_priv)
626 {
627 struct intel_display *display = &dev_priv->display;
628 struct intel_gt *gt;
629 unsigned int i;
630
631 i915_gem_driver_register(dev_priv);
632 i915_pmu_register(dev_priv);
633
634 intel_vgpu_register(dev_priv);
635
636 /* Reveal our presence to userspace */
637 if (drm_dev_register(&dev_priv->drm, 0)) {
638 drm_err(&dev_priv->drm,
639 "Failed to register driver for userspace access!\n");
640 return;
641 }
642
643 i915_debugfs_register(dev_priv);
644 i915_setup_sysfs(dev_priv);
645
646 /* Depends on sysfs having been initialized */
647 i915_perf_register(dev_priv);
648
649 for_each_gt(gt, dev_priv, i)
650 intel_gt_driver_register(gt);
651
652 intel_pxp_debugfs_register(dev_priv->pxp);
653
654 i915_hwmon_register(dev_priv);
655
656 intel_display_driver_register(display);
657
658 intel_power_domains_enable(display);
659 intel_runtime_pm_enable(&dev_priv->runtime_pm);
660
661 if (i915_switcheroo_register(dev_priv))
662 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
663 }
664
665 /**
666 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
667 * @dev_priv: device private
668 */
i915_driver_unregister(struct drm_i915_private * dev_priv)669 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
670 {
671 struct intel_display *display = &dev_priv->display;
672 struct intel_gt *gt;
673 unsigned int i;
674
675 i915_switcheroo_unregister(dev_priv);
676
677 intel_runtime_pm_disable(&dev_priv->runtime_pm);
678 intel_power_domains_disable(display);
679
680 intel_display_driver_unregister(display);
681
682 intel_pxp_fini(dev_priv);
683
684 for_each_gt(gt, dev_priv, i)
685 intel_gt_driver_unregister(gt);
686
687 i915_hwmon_unregister(dev_priv);
688
689 i915_perf_unregister(dev_priv);
690 i915_pmu_unregister(dev_priv);
691
692 i915_teardown_sysfs(dev_priv);
693 drm_dev_unplug(&dev_priv->drm);
694
695 i915_gem_driver_unregister(dev_priv);
696 }
697
698 void
i915_print_iommu_status(struct drm_i915_private * i915,struct drm_printer * p)699 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
700 {
701 drm_printf(p, "iommu: %s\n",
702 str_enabled_disabled(i915_vtd_active(i915)));
703 }
704
i915_welcome_messages(struct drm_i915_private * dev_priv)705 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
706 {
707 if (drm_debug_enabled(DRM_UT_DRIVER)) {
708 struct drm_printer p = drm_dbg_printer(&dev_priv->drm, DRM_UT_DRIVER,
709 "device info:");
710 struct intel_gt *gt;
711 unsigned int i;
712
713 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
714 INTEL_DEVID(dev_priv),
715 INTEL_REVID(dev_priv),
716 intel_platform_name(INTEL_INFO(dev_priv)->platform),
717 intel_subplatform(RUNTIME_INFO(dev_priv),
718 INTEL_INFO(dev_priv)->platform),
719 GRAPHICS_VER(dev_priv));
720
721 intel_device_info_print(INTEL_INFO(dev_priv),
722 RUNTIME_INFO(dev_priv), &p);
723 i915_print_iommu_status(dev_priv, &p);
724 for_each_gt(gt, dev_priv, i)
725 intel_gt_info_print(>->info, &p);
726 }
727
728 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
729 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
730 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
731 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
732 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
733 drm_info(&dev_priv->drm,
734 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
735 }
736
737 static struct drm_i915_private *
i915_driver_create(struct pci_dev * pdev,const struct pci_device_id * ent)738 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
739 {
740 const struct intel_device_info *match_info =
741 (struct intel_device_info *)ent->driver_data;
742 struct drm_i915_private *i915;
743
744 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
745 struct drm_i915_private, drm);
746 if (IS_ERR(i915))
747 return i915;
748
749 pci_set_drvdata(pdev, &i915->drm);
750
751 /* Device parameters start as a copy of module parameters. */
752 i915_params_copy(&i915->params, &i915_modparams);
753
754 /* Set up device info and initial runtime info. */
755 intel_device_info_driver_create(i915, pdev->device, match_info);
756
757 intel_display_device_probe(pdev);
758
759 return i915;
760 }
761
762 /**
763 * i915_driver_probe - setup chip and create an initial config
764 * @pdev: PCI device
765 * @ent: matching PCI ID entry
766 *
767 * The driver probe routine has to do several things:
768 * - drive output discovery via intel_display_driver_probe()
769 * - initialize the memory manager
770 * - allocate initial config memory
771 * - setup the DRM framebuffer with the allocated memory
772 */
i915_driver_probe(struct pci_dev * pdev,const struct pci_device_id * ent)773 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
774 {
775 struct drm_i915_private *i915;
776 struct intel_display *display;
777 int ret;
778
779 ret = pci_enable_device(pdev);
780 if (ret) {
781 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
782 return ret;
783 }
784
785 i915 = i915_driver_create(pdev, ent);
786 if (IS_ERR(i915)) {
787 pci_disable_device(pdev);
788 return PTR_ERR(i915);
789 }
790
791 display = &i915->display;
792
793 ret = i915_driver_early_probe(i915);
794 if (ret < 0)
795 goto out_pci_disable;
796
797 disable_rpm_wakeref_asserts(&i915->runtime_pm);
798
799 intel_vgpu_detect(i915);
800
801 ret = intel_gt_probe_all(i915);
802 if (ret < 0)
803 goto out_runtime_pm_put;
804
805 ret = i915_driver_mmio_probe(i915);
806 if (ret < 0)
807 goto out_runtime_pm_put;
808
809 ret = i915_driver_hw_probe(i915);
810 if (ret < 0)
811 goto out_cleanup_mmio;
812
813 ret = intel_display_driver_probe_noirq(display);
814 if (ret < 0)
815 goto out_cleanup_hw;
816
817 ret = intel_irq_install(i915);
818 if (ret)
819 goto out_cleanup_modeset;
820
821 ret = intel_display_driver_probe_nogem(display);
822 if (ret)
823 goto out_cleanup_irq;
824
825 ret = i915_gem_init(i915);
826 if (ret)
827 goto out_cleanup_modeset2;
828
829 ret = intel_pxp_init(i915);
830 if (ret && ret != -ENODEV)
831 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret);
832
833 ret = intel_display_driver_probe(display);
834 if (ret)
835 goto out_cleanup_gem;
836
837 i915_driver_register(i915);
838
839 enable_rpm_wakeref_asserts(&i915->runtime_pm);
840
841 i915_welcome_messages(i915);
842
843 i915->do_release = true;
844
845 return 0;
846
847 out_cleanup_gem:
848 i915_gem_suspend(i915);
849 i915_gem_driver_remove(i915);
850 i915_gem_driver_release(i915);
851 out_cleanup_modeset2:
852 /* FIXME clean up the error path */
853 intel_display_driver_remove(display);
854 intel_irq_uninstall(i915);
855 intel_display_driver_remove_noirq(display);
856 goto out_cleanup_modeset;
857 out_cleanup_irq:
858 intel_irq_uninstall(i915);
859 out_cleanup_modeset:
860 intel_display_driver_remove_nogem(display);
861 out_cleanup_hw:
862 i915_driver_hw_remove(i915);
863 intel_memory_regions_driver_release(i915);
864 i915_ggtt_driver_release(i915);
865 i915_gem_drain_freed_objects(i915);
866 i915_ggtt_driver_late_release(i915);
867 out_cleanup_mmio:
868 i915_driver_mmio_release(i915);
869 out_runtime_pm_put:
870 enable_rpm_wakeref_asserts(&i915->runtime_pm);
871 i915_driver_late_release(i915);
872 out_pci_disable:
873 pci_disable_device(pdev);
874 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
875 return ret;
876 }
877
i915_driver_remove(struct drm_i915_private * i915)878 void i915_driver_remove(struct drm_i915_private *i915)
879 {
880 struct intel_display *display = &i915->display;
881 intel_wakeref_t wakeref;
882
883 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
884
885 i915_driver_unregister(i915);
886
887 /* Flush any external code that still may be under the RCU lock */
888 synchronize_rcu();
889
890 i915_gem_suspend(i915);
891
892 intel_gvt_driver_remove(i915);
893
894 intel_display_driver_remove(display);
895
896 intel_irq_uninstall(i915);
897
898 intel_display_driver_remove_noirq(display);
899
900 i915_reset_error_state(i915);
901 i915_gem_driver_remove(i915);
902
903 intel_display_driver_remove_nogem(display);
904
905 i915_driver_hw_remove(i915);
906
907 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
908 }
909
i915_driver_release(struct drm_device * dev)910 static void i915_driver_release(struct drm_device *dev)
911 {
912 struct drm_i915_private *dev_priv = to_i915(dev);
913 struct intel_display *display = &dev_priv->display;
914 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
915 intel_wakeref_t wakeref;
916
917 if (!dev_priv->do_release)
918 return;
919
920 wakeref = intel_runtime_pm_get(rpm);
921
922 i915_gem_driver_release(dev_priv);
923
924 intel_memory_regions_driver_release(dev_priv);
925 i915_ggtt_driver_release(dev_priv);
926 i915_gem_drain_freed_objects(dev_priv);
927 i915_ggtt_driver_late_release(dev_priv);
928
929 i915_driver_mmio_release(dev_priv);
930
931 intel_runtime_pm_put(rpm, wakeref);
932
933 intel_runtime_pm_driver_release(rpm);
934
935 i915_driver_late_release(dev_priv);
936
937 intel_display_device_remove(display);
938 }
939
i915_driver_open(struct drm_device * dev,struct drm_file * file)940 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
941 {
942 struct drm_i915_private *i915 = to_i915(dev);
943 int ret;
944
945 ret = i915_gem_open(i915, file);
946 if (ret)
947 return ret;
948
949 return 0;
950 }
951
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)952 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
953 {
954 struct drm_i915_file_private *file_priv = file->driver_priv;
955
956 i915_gem_context_close(file);
957 i915_drm_client_put(file_priv->client);
958
959 kfree_rcu(file_priv, rcu);
960
961 /* Catch up with all the deferred frees from "this" client */
962 i915_gem_flush_free_objects(to_i915(dev));
963 }
964
i915_driver_shutdown(struct drm_i915_private * i915)965 void i915_driver_shutdown(struct drm_i915_private *i915)
966 {
967 struct intel_display *display = &i915->display;
968
969 disable_rpm_wakeref_asserts(&i915->runtime_pm);
970 intel_runtime_pm_disable(&i915->runtime_pm);
971 intel_power_domains_disable(display);
972
973 drm_client_dev_suspend(&i915->drm, false);
974 if (HAS_DISPLAY(i915)) {
975 drm_kms_helper_poll_disable(&i915->drm);
976 intel_display_driver_disable_user_access(display);
977
978 drm_atomic_helper_shutdown(&i915->drm);
979 }
980
981 intel_dp_mst_suspend(display);
982
983 intel_irq_suspend(i915);
984 intel_hpd_cancel_work(i915);
985
986 if (HAS_DISPLAY(i915))
987 intel_display_driver_suspend_access(display);
988
989 intel_encoder_suspend_all(&i915->display);
990 intel_encoder_shutdown_all(&i915->display);
991
992 intel_dmc_suspend(&i915->display);
993
994 i915_gem_suspend(i915);
995
996 /*
997 * The only requirement is to reboot with display DC states disabled,
998 * for now leaving all display power wells in the INIT power domain
999 * enabled.
1000 *
1001 * TODO:
1002 * - unify the pci_driver::shutdown sequence here with the
1003 * pci_driver.driver.pm.poweroff,poweroff_late sequence.
1004 * - unify the driver remove and system/runtime suspend sequences with
1005 * the above unified shutdown/poweroff sequence.
1006 */
1007 intel_power_domains_driver_remove(display);
1008 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1009
1010 intel_runtime_pm_driver_last_release(&i915->runtime_pm);
1011 }
1012
suspend_to_idle(struct drm_i915_private * dev_priv)1013 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1014 {
1015 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1016 if (acpi_target_system_state() < ACPI_STATE_S3)
1017 return true;
1018 #endif
1019 return false;
1020 }
1021
i915_drm_complete(struct drm_device * dev)1022 static void i915_drm_complete(struct drm_device *dev)
1023 {
1024 struct drm_i915_private *i915 = to_i915(dev);
1025
1026 intel_pxp_resume_complete(i915->pxp);
1027 }
1028
i915_drm_prepare(struct drm_device * dev)1029 static int i915_drm_prepare(struct drm_device *dev)
1030 {
1031 struct drm_i915_private *i915 = to_i915(dev);
1032
1033 intel_pxp_suspend_prepare(i915->pxp);
1034
1035 /*
1036 * NB intel_display_driver_suspend() may issue new requests after we've
1037 * ostensibly marked the GPU as ready-to-sleep here. We need to
1038 * split out that work and pull it forward so that after point,
1039 * the GPU is not woken again.
1040 */
1041 return i915_gem_backup_suspend(i915);
1042 }
1043
i915_drm_suspend(struct drm_device * dev)1044 static int i915_drm_suspend(struct drm_device *dev)
1045 {
1046 struct drm_i915_private *dev_priv = to_i915(dev);
1047 struct intel_display *display = &dev_priv->display;
1048 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1049 pci_power_t opregion_target_state;
1050
1051 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1052
1053 /* We do a lot of poking in a lot of registers, make sure they work
1054 * properly. */
1055 intel_power_domains_disable(display);
1056 drm_client_dev_suspend(dev, false);
1057 if (HAS_DISPLAY(dev_priv)) {
1058 drm_kms_helper_poll_disable(dev);
1059 intel_display_driver_disable_user_access(display);
1060 }
1061
1062 pci_save_state(pdev);
1063
1064 intel_display_driver_suspend(display);
1065
1066 intel_irq_suspend(dev_priv);
1067 intel_hpd_cancel_work(dev_priv);
1068
1069 if (HAS_DISPLAY(dev_priv))
1070 intel_display_driver_suspend_access(display);
1071
1072 intel_encoder_suspend_all(&dev_priv->display);
1073
1074 /* Must be called before GGTT is suspended. */
1075 intel_dpt_suspend(display);
1076 i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1077
1078 i9xx_display_sr_save(display);
1079
1080 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1081 intel_opregion_suspend(display, opregion_target_state);
1082
1083 dev_priv->suspend_count++;
1084
1085 intel_dmc_suspend(display);
1086
1087 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1088
1089 i915_gem_drain_freed_objects(dev_priv);
1090
1091 return 0;
1092 }
1093
i915_drm_suspend_late(struct drm_device * dev,bool hibernation)1094 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1095 {
1096 struct drm_i915_private *dev_priv = to_i915(dev);
1097 struct intel_display *display = &dev_priv->display;
1098 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1099 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1100 struct intel_gt *gt;
1101 int ret, i;
1102 bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1103
1104 disable_rpm_wakeref_asserts(rpm);
1105
1106 intel_pxp_suspend(dev_priv->pxp);
1107
1108 i915_gem_suspend_late(dev_priv);
1109
1110 for_each_gt(gt, dev_priv, i)
1111 intel_uncore_suspend(gt->uncore);
1112
1113 intel_display_power_suspend_late(display, s2idle);
1114
1115 ret = vlv_suspend_complete(dev_priv);
1116 if (ret) {
1117 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1118 intel_display_power_resume_early(display);
1119
1120 goto out;
1121 }
1122
1123 pci_disable_device(pdev);
1124 /*
1125 * During hibernation on some platforms the BIOS may try to access
1126 * the device even though it's already in D3 and hang the machine. So
1127 * leave the device in D0 on those platforms and hope the BIOS will
1128 * power down the device properly. The issue was seen on multiple old
1129 * GENs with different BIOS vendors, so having an explicit blacklist
1130 * is impractical; apply the workaround on everything pre GEN6. The
1131 * platforms where the issue was seen:
1132 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1133 * Fujitsu FSC S7110
1134 * Acer Aspire 1830T
1135 */
1136 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1137 pci_set_power_state(pdev, PCI_D3hot);
1138
1139 out:
1140 enable_rpm_wakeref_asserts(rpm);
1141 if (!dev_priv->uncore.user_forcewake_count)
1142 intel_runtime_pm_driver_release(rpm);
1143
1144 return ret;
1145 }
1146
i915_driver_suspend_switcheroo(struct drm_i915_private * i915,pm_message_t state)1147 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1148 pm_message_t state)
1149 {
1150 int error;
1151
1152 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1153 state.event != PM_EVENT_FREEZE))
1154 return -EINVAL;
1155
1156 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1157 return 0;
1158
1159 error = i915_drm_suspend(&i915->drm);
1160 if (error)
1161 return error;
1162
1163 return i915_drm_suspend_late(&i915->drm, false);
1164 }
1165
i915_drm_resume(struct drm_device * dev)1166 static int i915_drm_resume(struct drm_device *dev)
1167 {
1168 struct drm_i915_private *dev_priv = to_i915(dev);
1169 struct intel_display *display = &dev_priv->display;
1170 struct intel_gt *gt;
1171 int ret, i;
1172
1173 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1174
1175 ret = i915_pcode_init(dev_priv);
1176 if (ret)
1177 return ret;
1178
1179 sanitize_gpu(dev_priv);
1180
1181 ret = i915_ggtt_enable_hw(dev_priv);
1182 if (ret)
1183 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1184
1185 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1186
1187 for_each_gt(gt, dev_priv, i)
1188 if (GRAPHICS_VER(gt->i915) >= 8)
1189 setup_private_pat(gt);
1190
1191 /* Must be called after GGTT is resumed. */
1192 intel_dpt_resume(display);
1193
1194 intel_dmc_resume(display);
1195
1196 i9xx_display_sr_restore(display);
1197
1198 intel_vga_redisable(display);
1199
1200 intel_gmbus_reset(display);
1201
1202 intel_pps_unlock_regs_wa(display);
1203
1204 intel_init_pch_refclk(dev_priv);
1205
1206 /*
1207 * Interrupts have to be enabled before any batches are run. If not the
1208 * GPU will hang. i915_gem_init_hw() will initiate batches to
1209 * update/restore the context.
1210 *
1211 * drm_mode_config_reset() needs AUX interrupts.
1212 *
1213 * Modeset enabling in intel_display_driver_init_hw() also needs working
1214 * interrupts.
1215 */
1216 intel_irq_resume(dev_priv);
1217
1218 if (HAS_DISPLAY(dev_priv))
1219 drm_mode_config_reset(dev);
1220
1221 i915_gem_resume(dev_priv);
1222
1223 intel_display_driver_init_hw(display);
1224
1225 intel_clock_gating_init(dev_priv);
1226
1227 if (HAS_DISPLAY(dev_priv))
1228 intel_display_driver_resume_access(display);
1229
1230 intel_hpd_init(dev_priv);
1231
1232 intel_display_driver_resume(display);
1233
1234 if (HAS_DISPLAY(dev_priv)) {
1235 intel_display_driver_enable_user_access(display);
1236 drm_kms_helper_poll_enable(dev);
1237 }
1238 intel_hpd_poll_disable(dev_priv);
1239
1240 intel_opregion_resume(display);
1241
1242 drm_client_dev_resume(dev, false);
1243
1244 intel_power_domains_enable(display);
1245
1246 intel_gvt_resume(dev_priv);
1247
1248 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1249
1250 return 0;
1251 }
1252
i915_drm_resume_early(struct drm_device * dev)1253 static int i915_drm_resume_early(struct drm_device *dev)
1254 {
1255 struct drm_i915_private *dev_priv = to_i915(dev);
1256 struct intel_display *display = &dev_priv->display;
1257 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1258 struct intel_gt *gt;
1259 int ret, i;
1260
1261 /*
1262 * We have a resume ordering issue with the snd-hda driver also
1263 * requiring our device to be power up. Due to the lack of a
1264 * parent/child relationship we currently solve this with an early
1265 * resume hook.
1266 *
1267 * FIXME: This should be solved with a special hdmi sink device or
1268 * similar so that power domains can be employed.
1269 */
1270
1271 /*
1272 * Note that we need to set the power state explicitly, since we
1273 * powered off the device during freeze and the PCI core won't power
1274 * it back up for us during thaw. Powering off the device during
1275 * freeze is not a hard requirement though, and during the
1276 * suspend/resume phases the PCI core makes sure we get here with the
1277 * device powered on. So in case we change our freeze logic and keep
1278 * the device powered we can also remove the following set power state
1279 * call.
1280 */
1281 ret = pci_set_power_state(pdev, PCI_D0);
1282 if (ret) {
1283 drm_err(&dev_priv->drm,
1284 "failed to set PCI D0 power state (%d)\n", ret);
1285 return ret;
1286 }
1287
1288 /*
1289 * Note that pci_enable_device() first enables any parent bridge
1290 * device and only then sets the power state for this device. The
1291 * bridge enabling is a nop though, since bridge devices are resumed
1292 * first. The order of enabling power and enabling the device is
1293 * imposed by the PCI core as described above, so here we preserve the
1294 * same order for the freeze/thaw phases.
1295 *
1296 * TODO: eventually we should remove pci_disable_device() /
1297 * pci_enable_enable_device() from suspend/resume. Due to how they
1298 * depend on the device enable refcount we can't anyway depend on them
1299 * disabling/enabling the device.
1300 */
1301 if (pci_enable_device(pdev))
1302 return -EIO;
1303
1304 pci_set_master(pdev);
1305
1306 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1307
1308 ret = vlv_resume_prepare(dev_priv, false);
1309 if (ret)
1310 drm_err(&dev_priv->drm,
1311 "Resume prepare failed: %d, continuing anyway\n", ret);
1312
1313 for_each_gt(gt, dev_priv, i)
1314 intel_gt_resume_early(gt);
1315
1316 intel_display_power_resume_early(display);
1317
1318 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1319
1320 return ret;
1321 }
1322
i915_driver_resume_switcheroo(struct drm_i915_private * i915)1323 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1324 {
1325 int ret;
1326
1327 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1328 return 0;
1329
1330 ret = i915_drm_resume_early(&i915->drm);
1331 if (ret)
1332 return ret;
1333
1334 return i915_drm_resume(&i915->drm);
1335 }
1336
i915_pm_prepare(struct device * kdev)1337 static int i915_pm_prepare(struct device *kdev)
1338 {
1339 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1340
1341 if (!i915) {
1342 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1343 return -ENODEV;
1344 }
1345
1346 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1347 return 0;
1348
1349 return i915_drm_prepare(&i915->drm);
1350 }
1351
i915_pm_suspend(struct device * kdev)1352 static int i915_pm_suspend(struct device *kdev)
1353 {
1354 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1355
1356 if (!i915) {
1357 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1358 return -ENODEV;
1359 }
1360
1361 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1362 return 0;
1363
1364 return i915_drm_suspend(&i915->drm);
1365 }
1366
i915_pm_suspend_late(struct device * kdev)1367 static int i915_pm_suspend_late(struct device *kdev)
1368 {
1369 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1370
1371 /*
1372 * We have a suspend ordering issue with the snd-hda driver also
1373 * requiring our device to be power up. Due to the lack of a
1374 * parent/child relationship we currently solve this with an late
1375 * suspend hook.
1376 *
1377 * FIXME: This should be solved with a special hdmi sink device or
1378 * similar so that power domains can be employed.
1379 */
1380 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1381 return 0;
1382
1383 return i915_drm_suspend_late(&i915->drm, false);
1384 }
1385
i915_pm_poweroff_late(struct device * kdev)1386 static int i915_pm_poweroff_late(struct device *kdev)
1387 {
1388 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1389
1390 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1391 return 0;
1392
1393 return i915_drm_suspend_late(&i915->drm, true);
1394 }
1395
i915_pm_resume_early(struct device * kdev)1396 static int i915_pm_resume_early(struct device *kdev)
1397 {
1398 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1399
1400 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1401 return 0;
1402
1403 return i915_drm_resume_early(&i915->drm);
1404 }
1405
i915_pm_resume(struct device * kdev)1406 static int i915_pm_resume(struct device *kdev)
1407 {
1408 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1409
1410 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1411 return 0;
1412
1413 return i915_drm_resume(&i915->drm);
1414 }
1415
i915_pm_complete(struct device * kdev)1416 static void i915_pm_complete(struct device *kdev)
1417 {
1418 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1419
1420 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1421 return;
1422
1423 i915_drm_complete(&i915->drm);
1424 }
1425
1426 /* freeze: before creating the hibernation_image */
i915_pm_freeze(struct device * kdev)1427 static int i915_pm_freeze(struct device *kdev)
1428 {
1429 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1430 int ret;
1431
1432 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1433 ret = i915_drm_suspend(&i915->drm);
1434 if (ret)
1435 return ret;
1436 }
1437
1438 ret = i915_gem_freeze(i915);
1439 if (ret)
1440 return ret;
1441
1442 return 0;
1443 }
1444
i915_pm_freeze_late(struct device * kdev)1445 static int i915_pm_freeze_late(struct device *kdev)
1446 {
1447 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1448 int ret;
1449
1450 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1451 ret = i915_drm_suspend_late(&i915->drm, true);
1452 if (ret)
1453 return ret;
1454 }
1455
1456 ret = i915_gem_freeze_late(i915);
1457 if (ret)
1458 return ret;
1459
1460 return 0;
1461 }
1462
1463 /* thaw: called after creating the hibernation image, but before turning off. */
i915_pm_thaw_early(struct device * kdev)1464 static int i915_pm_thaw_early(struct device *kdev)
1465 {
1466 return i915_pm_resume_early(kdev);
1467 }
1468
i915_pm_thaw(struct device * kdev)1469 static int i915_pm_thaw(struct device *kdev)
1470 {
1471 return i915_pm_resume(kdev);
1472 }
1473
1474 /* restore: called after loading the hibernation image. */
i915_pm_restore_early(struct device * kdev)1475 static int i915_pm_restore_early(struct device *kdev)
1476 {
1477 return i915_pm_resume_early(kdev);
1478 }
1479
i915_pm_restore(struct device * kdev)1480 static int i915_pm_restore(struct device *kdev)
1481 {
1482 return i915_pm_resume(kdev);
1483 }
1484
intel_runtime_suspend(struct device * kdev)1485 static int intel_runtime_suspend(struct device *kdev)
1486 {
1487 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1488 struct intel_display *display = &dev_priv->display;
1489 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1490 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1491 struct pci_dev *root_pdev;
1492 struct intel_gt *gt;
1493 int ret, i;
1494
1495 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1496 return -ENODEV;
1497
1498 drm_dbg(&dev_priv->drm, "Suspending device\n");
1499
1500 disable_rpm_wakeref_asserts(rpm);
1501
1502 /*
1503 * We are safe here against re-faults, since the fault handler takes
1504 * an RPM reference.
1505 */
1506 i915_gem_runtime_suspend(dev_priv);
1507
1508 intel_pxp_runtime_suspend(dev_priv->pxp);
1509
1510 for_each_gt(gt, dev_priv, i)
1511 intel_gt_runtime_suspend(gt);
1512
1513 intel_irq_suspend(dev_priv);
1514
1515 for_each_gt(gt, dev_priv, i)
1516 intel_uncore_suspend(gt->uncore);
1517
1518 intel_display_power_suspend(display);
1519
1520 ret = vlv_suspend_complete(dev_priv);
1521 if (ret) {
1522 drm_err(&dev_priv->drm,
1523 "Runtime suspend failed, disabling it (%d)\n", ret);
1524 intel_uncore_runtime_resume(&dev_priv->uncore);
1525
1526 intel_irq_resume(dev_priv);
1527
1528 for_each_gt(gt, dev_priv, i)
1529 intel_gt_runtime_resume(gt);
1530
1531 enable_rpm_wakeref_asserts(rpm);
1532
1533 return ret;
1534 }
1535
1536 enable_rpm_wakeref_asserts(rpm);
1537 intel_runtime_pm_driver_release(rpm);
1538
1539 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1540 drm_err(&dev_priv->drm,
1541 "Unclaimed access detected prior to suspending\n");
1542
1543 /*
1544 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1545 * This should be totally removed when we handle the pci states properly
1546 * on runtime PM.
1547 */
1548 root_pdev = pcie_find_root_port(pdev);
1549 if (root_pdev)
1550 pci_d3cold_disable(root_pdev);
1551
1552 /*
1553 * FIXME: We really should find a document that references the arguments
1554 * used below!
1555 */
1556 if (IS_BROADWELL(dev_priv)) {
1557 /*
1558 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1559 * being detected, and the call we do at intel_runtime_resume()
1560 * won't be able to restore them. Since PCI_D3hot matches the
1561 * actual specification and appears to be working, use it.
1562 */
1563 intel_opregion_notify_adapter(display, PCI_D3hot);
1564 } else {
1565 /*
1566 * current versions of firmware which depend on this opregion
1567 * notification have repurposed the D1 definition to mean
1568 * "runtime suspended" vs. what you would normally expect (D3)
1569 * to distinguish it from notifications that might be sent via
1570 * the suspend path.
1571 */
1572 intel_opregion_notify_adapter(display, PCI_D1);
1573 }
1574
1575 assert_forcewakes_inactive(&dev_priv->uncore);
1576
1577 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1578 intel_hpd_poll_enable(dev_priv);
1579
1580 drm_dbg(&dev_priv->drm, "Device suspended\n");
1581 return 0;
1582 }
1583
intel_runtime_resume(struct device * kdev)1584 static int intel_runtime_resume(struct device *kdev)
1585 {
1586 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1587 struct intel_display *display = &dev_priv->display;
1588 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1589 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1590 struct pci_dev *root_pdev;
1591 struct intel_gt *gt;
1592 int ret, i;
1593
1594 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1595 return -ENODEV;
1596
1597 drm_dbg(&dev_priv->drm, "Resuming device\n");
1598
1599 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1600 disable_rpm_wakeref_asserts(rpm);
1601
1602 intel_opregion_notify_adapter(display, PCI_D0);
1603
1604 root_pdev = pcie_find_root_port(pdev);
1605 if (root_pdev)
1606 pci_d3cold_enable(root_pdev);
1607
1608 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1609 drm_dbg(&dev_priv->drm,
1610 "Unclaimed access during suspend, bios?\n");
1611
1612 intel_display_power_resume(display);
1613
1614 ret = vlv_resume_prepare(dev_priv, true);
1615
1616 for_each_gt(gt, dev_priv, i)
1617 intel_uncore_runtime_resume(gt->uncore);
1618
1619 intel_irq_resume(dev_priv);
1620
1621 /*
1622 * No point of rolling back things in case of an error, as the best
1623 * we can do is to hope that things will still work (and disable RPM).
1624 */
1625 for_each_gt(gt, dev_priv, i)
1626 intel_gt_runtime_resume(gt);
1627
1628 intel_pxp_runtime_resume(dev_priv->pxp);
1629
1630 /*
1631 * On VLV/CHV display interrupts are part of the display
1632 * power well, so hpd is reinitialized from there. For
1633 * everyone else do it here.
1634 */
1635 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1636 intel_hpd_init(dev_priv);
1637 intel_hpd_poll_disable(dev_priv);
1638 }
1639
1640 skl_watermark_ipc_update(dev_priv);
1641
1642 enable_rpm_wakeref_asserts(rpm);
1643
1644 if (ret)
1645 drm_err(&dev_priv->drm,
1646 "Runtime resume failed, disabling it (%d)\n", ret);
1647 else
1648 drm_dbg(&dev_priv->drm, "Device resumed\n");
1649
1650 return ret;
1651 }
1652
1653 const struct dev_pm_ops i915_pm_ops = {
1654 /*
1655 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1656 * PMSG_RESUME]
1657 */
1658 .prepare = i915_pm_prepare,
1659 .suspend = i915_pm_suspend,
1660 .suspend_late = i915_pm_suspend_late,
1661 .resume_early = i915_pm_resume_early,
1662 .resume = i915_pm_resume,
1663 .complete = i915_pm_complete,
1664
1665 /*
1666 * S4 event handlers
1667 * @freeze, @freeze_late : called (1) before creating the
1668 * hibernation image [PMSG_FREEZE] and
1669 * (2) after rebooting, before restoring
1670 * the image [PMSG_QUIESCE]
1671 * @thaw, @thaw_early : called (1) after creating the hibernation
1672 * image, before writing it [PMSG_THAW]
1673 * and (2) after failing to create or
1674 * restore the image [PMSG_RECOVER]
1675 * @poweroff, @poweroff_late: called after writing the hibernation
1676 * image, before rebooting [PMSG_HIBERNATE]
1677 * @restore, @restore_early : called after rebooting and restoring the
1678 * hibernation image [PMSG_RESTORE]
1679 */
1680 .freeze = i915_pm_freeze,
1681 .freeze_late = i915_pm_freeze_late,
1682 .thaw_early = i915_pm_thaw_early,
1683 .thaw = i915_pm_thaw,
1684 .poweroff = i915_pm_suspend,
1685 .poweroff_late = i915_pm_poweroff_late,
1686 .restore_early = i915_pm_restore_early,
1687 .restore = i915_pm_restore,
1688
1689 /* S0ix (via runtime suspend) event handlers */
1690 .runtime_suspend = intel_runtime_suspend,
1691 .runtime_resume = intel_runtime_resume,
1692 };
1693
1694 static const struct file_operations i915_driver_fops = {
1695 .owner = THIS_MODULE,
1696 .open = drm_open,
1697 .release = drm_release_noglobal,
1698 .unlocked_ioctl = drm_ioctl,
1699 .mmap = i915_gem_mmap,
1700 .poll = drm_poll,
1701 .read = drm_read,
1702 .compat_ioctl = i915_ioc32_compat_ioctl,
1703 .llseek = noop_llseek,
1704 #ifdef CONFIG_PROC_FS
1705 .show_fdinfo = drm_show_fdinfo,
1706 #endif
1707 .fop_flags = FOP_UNSIGNED_OFFSET,
1708 };
1709
1710 static int
i915_gem_reject_pin_ioctl(struct drm_device * dev,void * data,struct drm_file * file)1711 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1712 struct drm_file *file)
1713 {
1714 return -ENODEV;
1715 }
1716
1717 static const struct drm_ioctl_desc i915_ioctls[] = {
1718 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1719 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1720 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1721 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1722 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1723 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1724 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1725 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1726 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1727 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1728 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1730 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1731 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1732 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1733 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1734 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1735 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1736 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1737 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1738 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1739 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1740 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1741 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1742 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1743 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1744 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1745 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1746 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1747 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1748 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1749 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1750 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1751 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1752 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1753 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1754 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1755 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1756 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1757 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_crtc_get_pipe_from_crtc_id_ioctl, 0),
1758 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1759 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1760 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1761 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1762 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1763 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1764 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1765 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1766 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1767 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1768 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1769 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1770 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1771 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1772 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1773 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1774 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1775 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1776 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1777 };
1778
1779 /*
1780 * Interface history:
1781 *
1782 * 1.1: Original.
1783 * 1.2: Add Power Management
1784 * 1.3: Add vblank support
1785 * 1.4: Fix cmdbuffer path, add heap destroy
1786 * 1.5: Add vblank pipe configuration
1787 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1788 * - Support vertical blank on secondary display pipe
1789 */
1790 #define DRIVER_MAJOR 1
1791 #define DRIVER_MINOR 6
1792 #define DRIVER_PATCHLEVEL 0
1793
1794 static const struct drm_driver i915_drm_driver = {
1795 /* Don't use MTRRs here; the Xserver or userspace app should
1796 * deal with them for Intel hardware.
1797 */
1798 .driver_features =
1799 DRIVER_GEM |
1800 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1801 DRIVER_SYNCOBJ_TIMELINE,
1802 .release = i915_driver_release,
1803 .open = i915_driver_open,
1804 .postclose = i915_driver_postclose,
1805 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo),
1806
1807 .gem_prime_import = i915_gem_prime_import,
1808
1809 .dumb_create = i915_gem_dumb_create,
1810 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1811
1812 INTEL_FBDEV_DRIVER_OPS,
1813
1814 .ioctls = i915_ioctls,
1815 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1816 .fops = &i915_driver_fops,
1817 .name = DRIVER_NAME,
1818 .desc = DRIVER_DESC,
1819 .major = DRIVER_MAJOR,
1820 .minor = DRIVER_MINOR,
1821 .patchlevel = DRIVER_PATCHLEVEL,
1822 };
1823