1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2014-2018 Intel Corporation
4  */
5 
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_context.h"
9 #include "intel_engine_pm.h"
10 #include "intel_engine_regs.h"
11 #include "intel_gpu_commands.h"
12 #include "intel_gt.h"
13 #include "intel_gt_ccs_mode.h"
14 #include "intel_gt_mcr.h"
15 #include "intel_gt_print.h"
16 #include "intel_gt_regs.h"
17 #include "intel_ring.h"
18 #include "intel_workarounds.h"
19 
20 #include "display/intel_fbc_regs.h"
21 
22 /**
23  * DOC: Hardware workarounds
24  *
25  * Hardware workarounds are register programming documented to be executed in
26  * the driver that fall outside of the normal programming sequences for a
27  * platform. There are some basic categories of workarounds, depending on
28  * how/when they are applied:
29  *
30  * - Context workarounds: workarounds that touch registers that are
31  *   saved/restored to/from the HW context image. The list is emitted (via Load
32  *   Register Immediate commands) once when initializing the device and saved in
33  *   the default context. That default context is then used on every context
34  *   creation to have a "primed golden context", i.e. a context image that
35  *   already contains the changes needed to all the registers.
36  *
37  *   Context workarounds should be implemented in the \*_ctx_workarounds_init()
38  *   variants respective to the targeted platforms.
39  *
40  * - Engine workarounds: the list of these WAs is applied whenever the specific
41  *   engine is reset. It's also possible that a set of engine classes share a
42  *   common power domain and they are reset together. This happens on some
43  *   platforms with render and compute engines. In this case (at least) one of
44  *   them need to keeep the workaround programming: the approach taken in the
45  *   driver is to tie those workarounds to the first compute/render engine that
46  *   is registered.  When executing with GuC submission, engine resets are
47  *   outside of kernel driver control, hence the list of registers involved in
48  *   written once, on engine initialization, and then passed to GuC, that
49  *   saves/restores their values before/after the reset takes place. See
50  *   ``drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c`` for reference.
51  *
52  *   Workarounds for registers specific to RCS and CCS should be implemented in
53  *   rcs_engine_wa_init() and ccs_engine_wa_init(), respectively; those for
54  *   registers belonging to BCS, VCS or VECS should be implemented in
55  *   xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
56  *   engine's MMIO range but that are part of of the common RCS/CCS reset domain
57  *   should be implemented in general_render_compute_wa_init(). The settings
58  *   about the CCS load balancing should be added in ccs_engine_wa_mode().
59  *
60  * - GT workarounds: the list of these WAs is applied whenever these registers
61  *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
62  *
63  *   GT workarounds should be implemented in the \*_gt_workarounds_init()
64  *   variants respective to the targeted platforms.
65  *
66  * - Register whitelist: some workarounds need to be implemented in userspace,
67  *   but need to touch privileged registers. The whitelist in the kernel
68  *   instructs the hardware to allow the access to happen. From the kernel side,
69  *   this is just a special case of a MMIO workaround (as we write the list of
70  *   these to/be-whitelisted registers to some special HW registers).
71  *
72  *   Register whitelisting should be done in the \*_whitelist_build() variants
73  *   respective to the targeted platforms.
74  *
75  * - Workaround batchbuffers: buffers that get executed automatically by the
76  *   hardware on every HW context restore. These buffers are created and
77  *   programmed in the default context so the hardware always go through those
78  *   programming sequences when switching contexts. The support for workaround
79  *   batchbuffers is enabled these hardware mechanisms:
80  *
81  *   #. INDIRECT_CTX: A batchbuffer and an offset are provided in the default
82  *      context, pointing the hardware to jump to that location when that offset
83  *      is reached in the context restore. Workaround batchbuffer in the driver
84  *      currently uses this mechanism for all platforms.
85  *
86  *   #. BB_PER_CTX_PTR: A batchbuffer is provided in the default context,
87  *      pointing the hardware to a buffer to continue executing after the
88  *      engine registers are restored in a context restore sequence. This is
89  *      currently not used in the driver.
90  *
91  * - Other:  There are WAs that, due to their nature, cannot be applied from a
92  *   central place. Those are peppered around the rest of the code, as needed.
93  *   Workarounds related to the display IP are the main example.
94  *
95  * .. [1] Technically, some registers are powercontext saved & restored, so they
96  *    survive a suspend/resume. In practice, writing them again is not too
97  *    costly and simplifies things, so it's the approach taken in the driver.
98  */
99 
wa_init_start(struct i915_wa_list * wal,struct intel_gt * gt,const char * name,const char * engine_name)100 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt,
101 			  const char *name, const char *engine_name)
102 {
103 	wal->gt = gt;
104 	wal->name = name;
105 	wal->engine_name = engine_name;
106 }
107 
108 #define WA_LIST_CHUNK (1 << 4)
109 
wa_init_finish(struct i915_wa_list * wal)110 static void wa_init_finish(struct i915_wa_list *wal)
111 {
112 	/* Trim unused entries. */
113 	if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) {
114 		struct i915_wa *list = kmemdup_array(wal->list, wal->count,
115 						     sizeof(*list), GFP_KERNEL);
116 
117 		if (list) {
118 			kfree(wal->list);
119 			wal->list = list;
120 		}
121 	}
122 
123 	if (!wal->count)
124 		return;
125 
126 	gt_dbg(wal->gt, "Initialized %u %s workarounds on %s\n",
127 	       wal->wa_count, wal->name, wal->engine_name);
128 }
129 
130 static enum forcewake_domains
wal_get_fw_for_rmw(struct intel_uncore * uncore,const struct i915_wa_list * wal)131 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
132 {
133 	enum forcewake_domains fw = 0;
134 	struct i915_wa *wa;
135 	unsigned int i;
136 
137 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
138 		fw |= intel_uncore_forcewake_for_reg(uncore,
139 						     wa->reg,
140 						     FW_REG_READ |
141 						     FW_REG_WRITE);
142 
143 	return fw;
144 }
145 
_wa_add(struct i915_wa_list * wal,const struct i915_wa * wa)146 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
147 {
148 	unsigned int addr = i915_mmio_reg_offset(wa->reg);
149 	struct drm_i915_private *i915 = wal->gt->i915;
150 	unsigned int start = 0, end = wal->count;
151 	const unsigned int grow = WA_LIST_CHUNK;
152 	struct i915_wa *wa_;
153 
154 	GEM_BUG_ON(!is_power_of_2(grow));
155 
156 	if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */
157 		struct i915_wa *list;
158 
159 		list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa),
160 				     GFP_KERNEL);
161 		if (!list) {
162 			drm_err(&i915->drm, "No space for workaround init!\n");
163 			return;
164 		}
165 
166 		if (wal->list) {
167 			memcpy(list, wal->list, sizeof(*wa) * wal->count);
168 			kfree(wal->list);
169 		}
170 
171 		wal->list = list;
172 	}
173 
174 	while (start < end) {
175 		unsigned int mid = start + (end - start) / 2;
176 
177 		if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) {
178 			start = mid + 1;
179 		} else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) {
180 			end = mid;
181 		} else {
182 			wa_ = &wal->list[mid];
183 
184 			if ((wa->clr | wa_->clr) && !(wa->clr & ~wa_->clr)) {
185 				drm_err(&i915->drm,
186 					"Discarding overwritten w/a for reg %04x (clear: %08x, set: %08x)\n",
187 					i915_mmio_reg_offset(wa_->reg),
188 					wa_->clr, wa_->set);
189 
190 				wa_->set &= ~wa->clr;
191 			}
192 
193 			wal->wa_count++;
194 			wa_->set |= wa->set;
195 			wa_->clr |= wa->clr;
196 			wa_->read |= wa->read;
197 			return;
198 		}
199 	}
200 
201 	wal->wa_count++;
202 	wa_ = &wal->list[wal->count++];
203 	*wa_ = *wa;
204 
205 	while (wa_-- > wal->list) {
206 		GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) ==
207 			   i915_mmio_reg_offset(wa_[1].reg));
208 		if (i915_mmio_reg_offset(wa_[1].reg) >
209 		    i915_mmio_reg_offset(wa_[0].reg))
210 			break;
211 
212 		swap(wa_[1], wa_[0]);
213 	}
214 }
215 
wa_add(struct i915_wa_list * wal,i915_reg_t reg,u32 clear,u32 set,u32 read_mask,bool masked_reg)216 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
217 		   u32 clear, u32 set, u32 read_mask, bool masked_reg)
218 {
219 	struct i915_wa wa = {
220 		.reg  = reg,
221 		.clr  = clear,
222 		.set  = set,
223 		.read = read_mask,
224 		.masked_reg = masked_reg,
225 	};
226 
227 	_wa_add(wal, &wa);
228 }
229 
wa_mcr_add(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 clear,u32 set,u32 read_mask,bool masked_reg)230 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
231 		       u32 clear, u32 set, u32 read_mask, bool masked_reg)
232 {
233 	struct i915_wa wa = {
234 		.mcr_reg = reg,
235 		.clr  = clear,
236 		.set  = set,
237 		.read = read_mask,
238 		.masked_reg = masked_reg,
239 		.is_mcr = 1,
240 	};
241 
242 	_wa_add(wal, &wa);
243 }
244 
245 static void
wa_write_clr_set(struct i915_wa_list * wal,i915_reg_t reg,u32 clear,u32 set)246 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
247 {
248 	wa_add(wal, reg, clear, set, clear | set, false);
249 }
250 
251 static void
wa_mcr_write_clr_set(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 clear,u32 set)252 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
253 {
254 	wa_mcr_add(wal, reg, clear, set, clear | set, false);
255 }
256 
257 static void
wa_write(struct i915_wa_list * wal,i915_reg_t reg,u32 set)258 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
259 {
260 	wa_write_clr_set(wal, reg, ~0, set);
261 }
262 
263 static void
wa_write_or(struct i915_wa_list * wal,i915_reg_t reg,u32 set)264 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
265 {
266 	wa_write_clr_set(wal, reg, set, set);
267 }
268 
269 static void
wa_mcr_write_or(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 set)270 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
271 {
272 	wa_mcr_write_clr_set(wal, reg, set, set);
273 }
274 
275 static void
wa_write_clr(struct i915_wa_list * wal,i915_reg_t reg,u32 clr)276 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
277 {
278 	wa_write_clr_set(wal, reg, clr, 0);
279 }
280 
281 static void
wa_mcr_write_clr(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 clr)282 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
283 {
284 	wa_mcr_write_clr_set(wal, reg, clr, 0);
285 }
286 
287 /*
288  * WA operations on "masked register". A masked register has the upper 16 bits
289  * documented as "masked" in b-spec. Its purpose is to allow writing to just a
290  * portion of the register without a rmw: you simply write in the upper 16 bits
291  * the mask of bits you are going to modify.
292  *
293  * The wa_masked_* family of functions already does the necessary operations to
294  * calculate the mask based on the parameters passed, so user only has to
295  * provide the lower 16 bits of that register.
296  */
297 
298 static void
wa_masked_en(struct i915_wa_list * wal,i915_reg_t reg,u32 val)299 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
300 {
301 	wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
302 }
303 
304 static void
wa_mcr_masked_en(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 val)305 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
306 {
307 	wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
308 }
309 
310 static void
wa_masked_dis(struct i915_wa_list * wal,i915_reg_t reg,u32 val)311 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
312 {
313 	wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
314 }
315 
316 static void
wa_mcr_masked_dis(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 val)317 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
318 {
319 	wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
320 }
321 
322 static void
wa_masked_field_set(struct i915_wa_list * wal,i915_reg_t reg,u32 mask,u32 val)323 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
324 		    u32 mask, u32 val)
325 {
326 	wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
327 }
328 
329 static void
wa_mcr_masked_field_set(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 mask,u32 val)330 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
331 			u32 mask, u32 val)
332 {
333 	wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
334 }
335 
gen6_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)336 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
337 				      struct i915_wa_list *wal)
338 {
339 	wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
340 }
341 
gen7_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)342 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine,
343 				      struct i915_wa_list *wal)
344 {
345 	wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
346 }
347 
gen8_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)348 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
349 				      struct i915_wa_list *wal)
350 {
351 	wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
352 
353 	/* WaDisableAsyncFlipPerfMode:bdw,chv */
354 	wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
355 
356 	/* WaDisablePartialInstShootdown:bdw,chv */
357 	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
358 			 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
359 
360 	/* Use Force Non-Coherent whenever executing a 3D context. This is a
361 	 * workaround for a possible hang in the unlikely event a TLB
362 	 * invalidation occurs during a PSD flush.
363 	 */
364 	/* WaForceEnableNonCoherent:bdw,chv */
365 	/* WaHdcDisableFetchWhenMasked:bdw,chv */
366 	wa_masked_en(wal, HDC_CHICKEN0,
367 		     HDC_DONOT_FETCH_MEM_WHEN_MASKED |
368 		     HDC_FORCE_NON_COHERENT);
369 
370 	/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
371 	 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
372 	 *  polygons in the same 8x4 pixel/sample area to be processed without
373 	 *  stalling waiting for the earlier ones to write to Hierarchical Z
374 	 *  buffer."
375 	 *
376 	 * This optimization is off by default for BDW and CHV; turn it on.
377 	 */
378 	wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
379 
380 	/* Wa4x4STCOptimizationDisable:bdw,chv */
381 	wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
382 
383 	/*
384 	 * BSpec recommends 8x4 when MSAA is used,
385 	 * however in practice 16x4 seems fastest.
386 	 *
387 	 * Note that PS/WM thread counts depend on the WIZ hashing
388 	 * disable bit, which we don't touch here, but it's good
389 	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
390 	 */
391 	wa_masked_field_set(wal, GEN7_GT_MODE,
392 			    GEN6_WIZ_HASHING_MASK,
393 			    GEN6_WIZ_HASHING_16x4);
394 }
395 
bdw_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)396 static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
397 				     struct i915_wa_list *wal)
398 {
399 	struct drm_i915_private *i915 = engine->i915;
400 
401 	gen8_ctx_workarounds_init(engine, wal);
402 
403 	/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
404 	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
405 
406 	/* WaDisableDopClockGating:bdw
407 	 *
408 	 * Also see the related UCGTCL1 write in bdw_init_clock_gating()
409 	 * to disable EUTC clock gating.
410 	 */
411 	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
412 			 DOP_CLOCK_GATING_DISABLE);
413 
414 	wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
415 			 GEN8_SAMPLER_POWER_BYPASS_DIS);
416 
417 	wa_masked_en(wal, HDC_CHICKEN0,
418 		     /* WaForceContextSaveRestoreNonCoherent:bdw */
419 		     HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
420 		     /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
421 		     (INTEL_INFO(i915)->gt == 3 ? HDC_FENCE_DEST_SLM_DISABLE : 0));
422 }
423 
chv_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)424 static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
425 				     struct i915_wa_list *wal)
426 {
427 	gen8_ctx_workarounds_init(engine, wal);
428 
429 	/* WaDisableThreadStallDopClockGating:chv */
430 	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
431 
432 	/* Improve HiZ throughput on CHV. */
433 	wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
434 }
435 
gen9_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)436 static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
437 				      struct i915_wa_list *wal)
438 {
439 	struct drm_i915_private *i915 = engine->i915;
440 
441 	if (HAS_LLC(i915)) {
442 		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
443 		 *
444 		 * Must match Display Engine. See
445 		 * WaCompressedResourceDisplayNewHashMode.
446 		 */
447 		wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
448 			     GEN9_PBE_COMPRESSED_HASH_SELECTION);
449 		wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
450 				 GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
451 	}
452 
453 	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
454 	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
455 	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
456 			 FLOW_CONTROL_ENABLE |
457 			 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
458 
459 	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
460 	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
461 	wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
462 			 GEN9_ENABLE_YV12_BUGFIX |
463 			 GEN9_ENABLE_GPGPU_PREEMPTION);
464 
465 	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
466 	/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
467 	wa_masked_en(wal, CACHE_MODE_1,
468 		     GEN8_4x4_STC_OPTIMIZATION_DISABLE |
469 		     GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
470 
471 	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
472 	wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
473 			  GEN9_CCS_TLB_PREFETCH_ENABLE);
474 
475 	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
476 	wa_masked_en(wal, HDC_CHICKEN0,
477 		     HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
478 		     HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
479 
480 	/* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
481 	 * both tied to WaForceContextSaveRestoreNonCoherent
482 	 * in some hsds for skl. We keep the tie for all gen9. The
483 	 * documentation is a bit hazy and so we want to get common behaviour,
484 	 * even though there is no clear evidence we would need both on kbl/bxt.
485 	 * This area has been source of system hangs so we play it safe
486 	 * and mimic the skl regardless of what bspec says.
487 	 *
488 	 * Use Force Non-Coherent whenever executing a 3D context. This
489 	 * is a workaround for a possible hang in the unlikely event
490 	 * a TLB invalidation occurs during a PSD flush.
491 	 */
492 
493 	/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
494 	wa_masked_en(wal, HDC_CHICKEN0,
495 		     HDC_FORCE_NON_COHERENT);
496 
497 	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
498 	if (IS_SKYLAKE(i915) ||
499 	    IS_KABYLAKE(i915) ||
500 	    IS_COFFEELAKE(i915) ||
501 	    IS_COMETLAKE(i915))
502 		wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
503 				 GEN8_SAMPLER_POWER_BYPASS_DIS);
504 
505 	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
506 	wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
507 
508 	/*
509 	 * Supporting preemption with fine-granularity requires changes in the
510 	 * batch buffer programming. Since we can't break old userspace, we
511 	 * need to set our default preemption level to safe value. Userspace is
512 	 * still able to use more fine-grained preemption levels, since in
513 	 * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
514 	 * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
515 	 * not real HW workarounds, but merely a way to start using preemption
516 	 * while maintaining old contract with userspace.
517 	 */
518 
519 	/* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
520 	wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
521 
522 	/* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
523 	wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
524 			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
525 			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
526 
527 	/* WaClearHIZ_WM_CHICKEN3:bxt,glk */
528 	if (IS_GEN9_LP(i915))
529 		wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
530 }
531 
skl_tune_iz_hashing(struct intel_engine_cs * engine,struct i915_wa_list * wal)532 static void skl_tune_iz_hashing(struct intel_engine_cs *engine,
533 				struct i915_wa_list *wal)
534 {
535 	struct intel_gt *gt = engine->gt;
536 	u8 vals[3] = { 0, 0, 0 };
537 	unsigned int i;
538 
539 	for (i = 0; i < 3; i++) {
540 		u8 ss;
541 
542 		/*
543 		 * Only consider slices where one, and only one, subslice has 7
544 		 * EUs
545 		 */
546 		if (!is_power_of_2(gt->info.sseu.subslice_7eu[i]))
547 			continue;
548 
549 		/*
550 		 * subslice_7eu[i] != 0 (because of the check above) and
551 		 * ss_max == 4 (maximum number of subslices possible per slice)
552 		 *
553 		 * ->    0 <= ss <= 3;
554 		 */
555 		ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1;
556 		vals[i] = 3 - ss;
557 	}
558 
559 	if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
560 		return;
561 
562 	/* Tune IZ hashing. See intel_device_info_runtime_init() */
563 	wa_masked_field_set(wal, GEN7_GT_MODE,
564 			    GEN9_IZ_HASHING_MASK(2) |
565 			    GEN9_IZ_HASHING_MASK(1) |
566 			    GEN9_IZ_HASHING_MASK(0),
567 			    GEN9_IZ_HASHING(2, vals[2]) |
568 			    GEN9_IZ_HASHING(1, vals[1]) |
569 			    GEN9_IZ_HASHING(0, vals[0]));
570 }
571 
skl_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)572 static void skl_ctx_workarounds_init(struct intel_engine_cs *engine,
573 				     struct i915_wa_list *wal)
574 {
575 	gen9_ctx_workarounds_init(engine, wal);
576 	skl_tune_iz_hashing(engine, wal);
577 }
578 
bxt_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)579 static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
580 				     struct i915_wa_list *wal)
581 {
582 	gen9_ctx_workarounds_init(engine, wal);
583 
584 	/* WaDisableThreadStallDopClockGating:bxt */
585 	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
586 			 STALL_DOP_GATING_DISABLE);
587 
588 	/* WaToEnableHwFixForPushConstHWBug:bxt */
589 	wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
590 		     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
591 }
592 
kbl_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)593 static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
594 				     struct i915_wa_list *wal)
595 {
596 	struct drm_i915_private *i915 = engine->i915;
597 
598 	gen9_ctx_workarounds_init(engine, wal);
599 
600 	/* WaToEnableHwFixForPushConstHWBug:kbl */
601 	if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER))
602 		wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
603 			     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
604 
605 	/* WaDisableSbeCacheDispatchPortSharing:kbl */
606 	wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
607 			 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
608 }
609 
glk_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)610 static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
611 				     struct i915_wa_list *wal)
612 {
613 	gen9_ctx_workarounds_init(engine, wal);
614 
615 	/* WaToEnableHwFixForPushConstHWBug:glk */
616 	wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
617 		     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
618 }
619 
cfl_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)620 static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
621 				     struct i915_wa_list *wal)
622 {
623 	gen9_ctx_workarounds_init(engine, wal);
624 
625 	/* WaToEnableHwFixForPushConstHWBug:cfl */
626 	wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
627 		     GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
628 
629 	/* WaDisableSbeCacheDispatchPortSharing:cfl */
630 	wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
631 			 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
632 }
633 
icl_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)634 static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
635 				     struct i915_wa_list *wal)
636 {
637 	/* Wa_1406697149 (WaDisableBankHangMode:icl) */
638 	wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
639 
640 	/* WaForceEnableNonCoherent:icl
641 	 * This is not the same workaround as in early Gen9 platforms, where
642 	 * lacking this could cause system hangs, but coherency performance
643 	 * overhead is high and only a few compute workloads really need it
644 	 * (the register is whitelisted in hardware now, so UMDs can opt in
645 	 * for coherency if they have a good reason).
646 	 */
647 	wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
648 
649 	/* WaEnableFloatBlendOptimization:icl */
650 	wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
651 		   _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
652 		   0 /* write-only, so skip validation */,
653 		   true);
654 
655 	/* WaDisableGPGPUMidThreadPreemption:icl */
656 	wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
657 			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
658 			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
659 
660 	/* allow headerless messages for preemptible GPGPU context */
661 	wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
662 			 GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
663 
664 	/* Wa_1604278689:icl,ehl */
665 	wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
666 	wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER,
667 			 0,
668 			 0xFFFFFFFF);
669 
670 	/* Wa_1406306137:icl,ehl */
671 	wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
672 }
673 
674 /*
675  * These settings aren't actually workarounds, but general tuning settings that
676  * need to be programmed on dg2 platform.
677  */
dg2_ctx_gt_tuning_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)678 static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
679 				   struct i915_wa_list *wal)
680 {
681 	wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
682 	wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
683 			     REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
684 	wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK,
685 			     FF_MODE2_TDS_TIMER_128);
686 }
687 
gen12_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)688 static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
689 				       struct i915_wa_list *wal)
690 {
691 	struct drm_i915_private *i915 = engine->i915;
692 
693 	/*
694 	 * Wa_1409142259:tgl,dg1,adl-p,adl-n
695 	 * Wa_1409347922:tgl,dg1,adl-p
696 	 * Wa_1409252684:tgl,dg1,adl-p
697 	 * Wa_1409217633:tgl,dg1,adl-p
698 	 * Wa_1409207793:tgl,dg1,adl-p
699 	 * Wa_1409178076:tgl,dg1,adl-p,adl-n
700 	 * Wa_1408979724:tgl,dg1,adl-p,adl-n
701 	 * Wa_14010443199:tgl,rkl,dg1,adl-p,adl-n
702 	 * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p,adl-n
703 	 * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p,adl-n
704 	 * Wa_22010465259:tgl,rkl,dg1,adl-s,adl-p,adl-n
705 	 */
706 	wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
707 		     GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
708 
709 	/* WaDisableGPGPUMidThreadPreemption:gen12 */
710 	wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
711 			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
712 			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
713 
714 	/*
715 	 * Wa_16011163337 - GS_TIMER
716 	 *
717 	 * TDS_TIMER: Although some platforms refer to it as Wa_1604555607, we
718 	 * need to program it even on those that don't explicitly list that
719 	 * workaround.
720 	 *
721 	 * Note that the programming of GEN12_FF_MODE2 is further modified
722 	 * according to the FF_MODE2 guidance given by Wa_1608008084.
723 	 * Wa_1608008084 tells us the FF_MODE2 register will return the wrong
724 	 * value when read from the CPU.
725 	 *
726 	 * The default value for this register is zero for all fields.
727 	 * So instead of doing a RMW we should just write the desired values
728 	 * for TDS and GS timers. Note that since the readback can't be trusted,
729 	 * the clear mask is just set to ~0 to make sure other bits are not
730 	 * inadvertently set. For the same reason read verification is ignored.
731 	 */
732 	wa_add(wal,
733 	       GEN12_FF_MODE2,
734 	       ~0,
735 	       FF_MODE2_TDS_TIMER_128 | FF_MODE2_GS_TIMER_224,
736 	       0, false);
737 
738 	if (!IS_DG1(i915)) {
739 		/* Wa_1806527549 */
740 		wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);
741 
742 		/* Wa_1606376872 */
743 		wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);
744 	}
745 
746 	/*
747 	 * This bit must be set to enable performance optimization for fast
748 	 * clears.
749 	 */
750 	wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, WAIT_ON_DEPTH_STALL_DONE_DISABLE);
751 }
752 
dg1_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)753 static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
754 				     struct i915_wa_list *wal)
755 {
756 	gen12_ctx_workarounds_init(engine, wal);
757 
758 	/* Wa_1409044764 */
759 	wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3,
760 		      DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
761 
762 	/* Wa_22010493298 */
763 	wa_masked_en(wal, HIZ_CHICKEN,
764 		     DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
765 }
766 
dg2_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)767 static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
768 				     struct i915_wa_list *wal)
769 {
770 	dg2_ctx_gt_tuning_init(engine, wal);
771 
772 	/* Wa_16013271637:dg2 */
773 	wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
774 			 MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
775 
776 	/* Wa_14014947963:dg2 */
777 	wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
778 
779 	/* Wa_18018764978:dg2 */
780 	wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
781 
782 	/* Wa_18019271663:dg2 */
783 	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
784 
785 	/* Wa_14019877138:dg2 */
786 	wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
787 }
788 
xelpg_ctx_gt_tuning_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)789 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
790 				     struct i915_wa_list *wal)
791 {
792 	struct intel_gt *gt = engine->gt;
793 
794 	dg2_ctx_gt_tuning_init(engine, wal);
795 
796 	/*
797 	 * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in
798 	 * gen12_emit_indirect_ctx_rcs() rather than here on some early
799 	 * steppings.
800 	 */
801 	if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
802 	      IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))
803 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
804 }
805 
xelpg_ctx_workarounds_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)806 static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
807 				       struct i915_wa_list *wal)
808 {
809 	struct intel_gt *gt = engine->gt;
810 
811 	xelpg_ctx_gt_tuning_init(engine, wal);
812 
813 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
814 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
815 		/* Wa_14014947963 */
816 		wa_masked_field_set(wal, VF_PREEMPTION,
817 				    PREEMPTION_VERTEX_COUNT, 0x4000);
818 
819 		/* Wa_16013271637 */
820 		wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
821 				 MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
822 
823 		/* Wa_18019627453 */
824 		wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
825 
826 		/* Wa_18018764978 */
827 		wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
828 	}
829 
830 	/* Wa_18019271663 */
831 	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
832 
833 	/* Wa_14019877138 */
834 	wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
835 }
836 
fakewa_disable_nestedbb_mode(struct intel_engine_cs * engine,struct i915_wa_list * wal)837 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
838 					 struct i915_wa_list *wal)
839 {
840 	/*
841 	 * This is a "fake" workaround defined by software to ensure we
842 	 * maintain reliable, backward-compatible behavior for userspace with
843 	 * regards to how nested MI_BATCH_BUFFER_START commands are handled.
844 	 *
845 	 * The per-context setting of MI_MODE[12] determines whether the bits
846 	 * of a nested MI_BATCH_BUFFER_START instruction should be interpreted
847 	 * in the traditional manner or whether they should instead use a new
848 	 * tgl+ meaning that breaks backward compatibility, but allows nesting
849 	 * into 3rd-level batchbuffers.  When this new capability was first
850 	 * added in TGL, it remained off by default unless a context
851 	 * intentionally opted in to the new behavior.  However Xe_HPG now
852 	 * flips this on by default and requires that we explicitly opt out if
853 	 * we don't want the new behavior.
854 	 *
855 	 * From a SW perspective, we want to maintain the backward-compatible
856 	 * behavior for userspace, so we'll apply a fake workaround to set it
857 	 * back to the legacy behavior on platforms where the hardware default
858 	 * is to break compatibility.  At the moment there is no Linux
859 	 * userspace that utilizes third-level batchbuffers, so this will avoid
860 	 * userspace from needing to make any changes.  using the legacy
861 	 * meaning is the correct thing to do.  If/when we have userspace
862 	 * consumers that want to utilize third-level batch nesting, we can
863 	 * provide a context parameter to allow them to opt-in.
864 	 */
865 	wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN);
866 }
867 
gen12_ctx_gt_mocs_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)868 static void gen12_ctx_gt_mocs_init(struct intel_engine_cs *engine,
869 				   struct i915_wa_list *wal)
870 {
871 	u8 mocs;
872 
873 	/*
874 	 * Some blitter commands do not have a field for MOCS, those
875 	 * commands will use MOCS index pointed by BLIT_CCTL.
876 	 * BLIT_CCTL registers are needed to be programmed to un-cached.
877 	 */
878 	if (engine->class == COPY_ENGINE_CLASS) {
879 		mocs = engine->gt->mocs.uc_index;
880 		wa_write_clr_set(wal,
881 				 BLIT_CCTL(engine->mmio_base),
882 				 BLIT_CCTL_MASK,
883 				 BLIT_CCTL_MOCS(mocs, mocs));
884 	}
885 }
886 
887 /*
888  * gen12_ctx_gt_fake_wa_init() aren't programmingan official workaround
889  * defined by the hardware team, but it programming general context registers.
890  * Adding those context register programming in context workaround
891  * allow us to use the wa framework for proper application and validation.
892  */
893 static void
gen12_ctx_gt_fake_wa_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)894 gen12_ctx_gt_fake_wa_init(struct intel_engine_cs *engine,
895 			  struct i915_wa_list *wal)
896 {
897 	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
898 		fakewa_disable_nestedbb_mode(engine, wal);
899 
900 	gen12_ctx_gt_mocs_init(engine, wal);
901 }
902 
903 static void
__intel_engine_init_ctx_wa(struct intel_engine_cs * engine,struct i915_wa_list * wal,const char * name)904 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
905 			   struct i915_wa_list *wal,
906 			   const char *name)
907 {
908 	struct drm_i915_private *i915 = engine->i915;
909 
910 	wa_init_start(wal, engine->gt, name, engine->name);
911 
912 	/* Applies to all engines */
913 	/*
914 	 * Fake workarounds are not the actual workaround but
915 	 * programming of context registers using workaround framework.
916 	 */
917 	if (GRAPHICS_VER(i915) >= 12)
918 		gen12_ctx_gt_fake_wa_init(engine, wal);
919 
920 	if (engine->class != RENDER_CLASS)
921 		goto done;
922 
923 	if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
924 		xelpg_ctx_workarounds_init(engine, wal);
925 	else if (IS_DG2(i915))
926 		dg2_ctx_workarounds_init(engine, wal);
927 	else if (IS_DG1(i915))
928 		dg1_ctx_workarounds_init(engine, wal);
929 	else if (GRAPHICS_VER(i915) == 12)
930 		gen12_ctx_workarounds_init(engine, wal);
931 	else if (GRAPHICS_VER(i915) == 11)
932 		icl_ctx_workarounds_init(engine, wal);
933 	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
934 		cfl_ctx_workarounds_init(engine, wal);
935 	else if (IS_GEMINILAKE(i915))
936 		glk_ctx_workarounds_init(engine, wal);
937 	else if (IS_KABYLAKE(i915))
938 		kbl_ctx_workarounds_init(engine, wal);
939 	else if (IS_BROXTON(i915))
940 		bxt_ctx_workarounds_init(engine, wal);
941 	else if (IS_SKYLAKE(i915))
942 		skl_ctx_workarounds_init(engine, wal);
943 	else if (IS_CHERRYVIEW(i915))
944 		chv_ctx_workarounds_init(engine, wal);
945 	else if (IS_BROADWELL(i915))
946 		bdw_ctx_workarounds_init(engine, wal);
947 	else if (GRAPHICS_VER(i915) == 7)
948 		gen7_ctx_workarounds_init(engine, wal);
949 	else if (GRAPHICS_VER(i915) == 6)
950 		gen6_ctx_workarounds_init(engine, wal);
951 	else if (GRAPHICS_VER(i915) < 8)
952 		;
953 	else
954 		MISSING_CASE(GRAPHICS_VER(i915));
955 
956 done:
957 	wa_init_finish(wal);
958 }
959 
intel_engine_init_ctx_wa(struct intel_engine_cs * engine)960 void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
961 {
962 	__intel_engine_init_ctx_wa(engine, &engine->ctx_wa_list, "context");
963 }
964 
intel_engine_emit_ctx_wa(struct i915_request * rq)965 int intel_engine_emit_ctx_wa(struct i915_request *rq)
966 {
967 	struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
968 	struct intel_uncore *uncore = rq->engine->uncore;
969 	enum forcewake_domains fw;
970 	unsigned long flags;
971 	struct i915_wa *wa;
972 	unsigned int i;
973 	u32 *cs;
974 	int ret;
975 
976 	if (wal->count == 0)
977 		return 0;
978 
979 	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
980 	if (ret)
981 		return ret;
982 
983 	if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
984 	     IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS)
985 		cs = intel_ring_begin(rq, (wal->count * 2 + 6));
986 	else
987 		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
988 
989 	if (IS_ERR(cs))
990 		return PTR_ERR(cs);
991 
992 	fw = wal_get_fw_for_rmw(uncore, wal);
993 
994 	intel_gt_mcr_lock(wal->gt, &flags);
995 	spin_lock(&uncore->lock);
996 	intel_uncore_forcewake_get__locked(uncore, fw);
997 
998 	*cs++ = MI_LOAD_REGISTER_IMM(wal->count);
999 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1000 		u32 val;
1001 
1002 		/* Skip reading the register if it's not really needed */
1003 		if (wa->masked_reg || (wa->clr | wa->set) == U32_MAX) {
1004 			val = wa->set;
1005 		} else {
1006 			val = wa->is_mcr ?
1007 				intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) :
1008 				intel_uncore_read_fw(uncore, wa->reg);
1009 			val &= ~wa->clr;
1010 			val |= wa->set;
1011 		}
1012 
1013 		*cs++ = i915_mmio_reg_offset(wa->reg);
1014 		*cs++ = val;
1015 	}
1016 	*cs++ = MI_NOOP;
1017 
1018 	/* Wa_14019789679 */
1019 	if ((IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
1020 	     IS_DG2(rq->i915)) && rq->engine->class == RENDER_CLASS) {
1021 		*cs++ = CMD_3DSTATE_MESH_CONTROL;
1022 		*cs++ = 0;
1023 		*cs++ = 0;
1024 		*cs++ = MI_NOOP;
1025 	}
1026 
1027 	intel_uncore_forcewake_put__locked(uncore, fw);
1028 	spin_unlock(&uncore->lock);
1029 	intel_gt_mcr_unlock(wal->gt, flags);
1030 
1031 	intel_ring_advance(rq, cs);
1032 
1033 	ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
1034 	if (ret)
1035 		return ret;
1036 
1037 	return 0;
1038 }
1039 
1040 static void
gen4_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1041 gen4_gt_workarounds_init(struct intel_gt *gt,
1042 			 struct i915_wa_list *wal)
1043 {
1044 	/* WaDisable_RenderCache_OperationalFlush:gen4,ilk */
1045 	wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
1046 }
1047 
1048 static void
g4x_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1049 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1050 {
1051 	gen4_gt_workarounds_init(gt, wal);
1052 
1053 	/* WaDisableRenderCachePipelinedFlush:g4x,ilk */
1054 	wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
1055 }
1056 
1057 static void
ilk_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1058 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1059 {
1060 	g4x_gt_workarounds_init(gt, wal);
1061 
1062 	wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
1063 }
1064 
1065 static void
snb_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1066 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1067 {
1068 }
1069 
1070 static void
ivb_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1071 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1072 {
1073 	/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
1074 	wa_masked_dis(wal,
1075 		      GEN7_COMMON_SLICE_CHICKEN1,
1076 		      GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
1077 
1078 	/* WaApplyL3ControlAndL3ChickenMode:ivb */
1079 	wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
1080 	wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
1081 
1082 	/* WaForceL3Serialization:ivb */
1083 	wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1084 }
1085 
1086 static void
vlv_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1087 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1088 {
1089 	/* WaForceL3Serialization:vlv */
1090 	wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE);
1091 
1092 	/*
1093 	 * WaIncreaseL3CreditsForVLVB0:vlv
1094 	 * This is the hardware default actually.
1095 	 */
1096 	wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
1097 }
1098 
1099 static void
hsw_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1100 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1101 {
1102 	/* L3 caching of data atomics doesn't work -- disable it. */
1103 	wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
1104 
1105 	wa_add(wal,
1106 	       HSW_ROW_CHICKEN3, 0,
1107 	       _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
1108 	       0 /* XXX does this reg exist? */, true);
1109 
1110 	/* WaVSRefCountFullforceMissDisable:hsw */
1111 	wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME);
1112 }
1113 
1114 static void
gen9_wa_init_mcr(struct drm_i915_private * i915,struct i915_wa_list * wal)1115 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
1116 {
1117 	const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
1118 	unsigned int slice, subslice;
1119 	u32 mcr, mcr_mask;
1120 
1121 	GEM_BUG_ON(GRAPHICS_VER(i915) != 9);
1122 
1123 	/*
1124 	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,glk,kbl,cml
1125 	 * Before any MMIO read into slice/subslice specific registers, MCR
1126 	 * packet control register needs to be programmed to point to any
1127 	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
1128 	 * This means each subsequent MMIO read will be forwarded to an
1129 	 * specific s/ss combination, but this is OK since these registers
1130 	 * are consistent across s/ss in almost all cases. In the rare
1131 	 * occasions, such as INSTDONE, where this value is dependent
1132 	 * on s/ss combo, the read should be done with read_subslice_reg.
1133 	 */
1134 	slice = ffs(sseu->slice_mask) - 1;
1135 	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw));
1136 	subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice));
1137 	GEM_BUG_ON(!subslice);
1138 	subslice--;
1139 
1140 	/*
1141 	 * We use GEN8_MCR..() macros to calculate the |mcr| value for
1142 	 * Gen9 to address WaProgramMgsrForCorrectSliceSpecificMmioReads
1143 	 */
1144 	mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1145 	mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1146 
1147 	drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr);
1148 
1149 	wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
1150 }
1151 
1152 static void
gen9_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1153 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1154 {
1155 	struct drm_i915_private *i915 = gt->i915;
1156 
1157 	/* WaProgramMgsrForCorrectSliceSpecificMmioReads:glk,kbl,cml,gen9 */
1158 	gen9_wa_init_mcr(i915, wal);
1159 
1160 	/* WaDisableKillLogic:bxt,skl,kbl */
1161 	if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
1162 		wa_write_or(wal,
1163 			    GAM_ECOCHK,
1164 			    ECOCHK_DIS_TLB);
1165 
1166 	if (HAS_LLC(i915)) {
1167 		/* WaCompressedResourceSamplerPbeMediaNewHashMode:skl,kbl
1168 		 *
1169 		 * Must match Display Engine. See
1170 		 * WaCompressedResourceDisplayNewHashMode.
1171 		 */
1172 		wa_write_or(wal,
1173 			    MMCD_MISC_CTRL,
1174 			    MMCD_PCLA | MMCD_HOTSPOT_EN);
1175 	}
1176 
1177 	/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
1178 	wa_write_or(wal,
1179 		    GAM_ECOCHK,
1180 		    BDW_DISABLE_HDC_INVALIDATION);
1181 }
1182 
1183 static void
skl_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1184 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1185 {
1186 	gen9_gt_workarounds_init(gt, wal);
1187 
1188 	/* WaDisableGafsUnitClkGating:skl */
1189 	wa_write_or(wal,
1190 		    GEN7_UCGCTL4,
1191 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1192 
1193 	/* WaInPlaceDecompressionHang:skl */
1194 	if (IS_SKYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, STEP_A0, STEP_H0))
1195 		wa_write_or(wal,
1196 			    GEN9_GAMT_ECO_REG_RW_IA,
1197 			    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1198 }
1199 
1200 static void
kbl_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1201 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1202 {
1203 	gen9_gt_workarounds_init(gt, wal);
1204 
1205 	/* WaDisableDynamicCreditSharing:kbl */
1206 	if (IS_KABYLAKE(gt->i915) && IS_GRAPHICS_STEP(gt->i915, 0, STEP_C0))
1207 		wa_write_or(wal,
1208 			    GAMT_CHKN_BIT_REG,
1209 			    GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1210 
1211 	/* WaDisableGafsUnitClkGating:kbl */
1212 	wa_write_or(wal,
1213 		    GEN7_UCGCTL4,
1214 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1215 
1216 	/* WaInPlaceDecompressionHang:kbl */
1217 	wa_write_or(wal,
1218 		    GEN9_GAMT_ECO_REG_RW_IA,
1219 		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1220 }
1221 
1222 static void
glk_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1223 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1224 {
1225 	gen9_gt_workarounds_init(gt, wal);
1226 }
1227 
1228 static void
cfl_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1229 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1230 {
1231 	gen9_gt_workarounds_init(gt, wal);
1232 
1233 	/* WaDisableGafsUnitClkGating:cfl */
1234 	wa_write_or(wal,
1235 		    GEN7_UCGCTL4,
1236 		    GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1237 
1238 	/* WaInPlaceDecompressionHang:cfl */
1239 	wa_write_or(wal,
1240 		    GEN9_GAMT_ECO_REG_RW_IA,
1241 		    GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1242 }
1243 
__set_mcr_steering(struct i915_wa_list * wal,i915_reg_t steering_reg,unsigned int slice,unsigned int subslice)1244 static void __set_mcr_steering(struct i915_wa_list *wal,
1245 			       i915_reg_t steering_reg,
1246 			       unsigned int slice, unsigned int subslice)
1247 {
1248 	u32 mcr, mcr_mask;
1249 
1250 	mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1251 	mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1252 
1253 	wa_write_clr_set(wal, steering_reg, mcr_mask, mcr);
1254 }
1255 
debug_dump_steering(struct intel_gt * gt)1256 static void debug_dump_steering(struct intel_gt *gt)
1257 {
1258 	struct drm_printer p = drm_dbg_printer(&gt->i915->drm, DRM_UT_DRIVER,
1259 					       "MCR Steering:");
1260 
1261 	if (drm_debug_enabled(DRM_UT_DRIVER))
1262 		intel_gt_mcr_report_steering(&p, gt, false);
1263 }
1264 
__add_mcr_wa(struct intel_gt * gt,struct i915_wa_list * wal,unsigned int slice,unsigned int subslice)1265 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal,
1266 			 unsigned int slice, unsigned int subslice)
1267 {
1268 	__set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice);
1269 
1270 	gt->default_steering.groupid = slice;
1271 	gt->default_steering.instanceid = subslice;
1272 
1273 	debug_dump_steering(gt);
1274 }
1275 
1276 static void
icl_wa_init_mcr(struct intel_gt * gt,struct i915_wa_list * wal)1277 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1278 {
1279 	const struct sseu_dev_info *sseu = &gt->info.sseu;
1280 	unsigned int subslice;
1281 
1282 	GEM_BUG_ON(GRAPHICS_VER(gt->i915) < 11);
1283 	GEM_BUG_ON(hweight8(sseu->slice_mask) > 1);
1284 
1285 	/*
1286 	 * Although a platform may have subslices, we need to always steer
1287 	 * reads to the lowest instance that isn't fused off.  When Render
1288 	 * Power Gating is enabled, grabbing forcewake will only power up a
1289 	 * single subslice (the "minconfig") if there isn't a real workload
1290 	 * that needs to be run; this means that if we steer register reads to
1291 	 * one of the higher subslices, we run the risk of reading back 0's or
1292 	 * random garbage.
1293 	 */
1294 	subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0));
1295 
1296 	/*
1297 	 * If the subslice we picked above also steers us to a valid L3 bank,
1298 	 * then we can just rely on the default steering and won't need to
1299 	 * worry about explicitly re-steering L3BANK reads later.
1300 	 */
1301 	if (gt->info.l3bank_mask & BIT(subslice))
1302 		gt->steering_table[L3BANK] = NULL;
1303 
1304 	__add_mcr_wa(gt, wal, 0, subslice);
1305 }
1306 
1307 static void
xehp_init_mcr(struct intel_gt * gt,struct i915_wa_list * wal)1308 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal)
1309 {
1310 	const struct sseu_dev_info *sseu = &gt->info.sseu;
1311 	unsigned long slice, subslice = 0, slice_mask = 0;
1312 	u32 lncf_mask = 0;
1313 	int i;
1314 
1315 	/*
1316 	 * On Xe_HP the steering increases in complexity. There are now several
1317 	 * more units that require steering and we're not guaranteed to be able
1318 	 * to find a common setting for all of them. These are:
1319 	 * - GSLICE (fusable)
1320 	 * - DSS (sub-unit within gslice; fusable)
1321 	 * - L3 Bank (fusable)
1322 	 * - MSLICE (fusable)
1323 	 * - LNCF (sub-unit within mslice; always present if mslice is present)
1324 	 *
1325 	 * We'll do our default/implicit steering based on GSLICE (in the
1326 	 * sliceid field) and DSS (in the subsliceid field).  If we can
1327 	 * find overlap between the valid MSLICE and/or LNCF values with
1328 	 * a suitable GSLICE, then we can just reuse the default value and
1329 	 * skip and explicit steering at runtime.
1330 	 *
1331 	 * We only need to look for overlap between GSLICE/MSLICE/LNCF to find
1332 	 * a valid sliceid value.  DSS steering is the only type of steering
1333 	 * that utilizes the 'subsliceid' bits.
1334 	 *
1335 	 * Also note that, even though the steering domain is called "GSlice"
1336 	 * and it is encoded in the register using the gslice format, the spec
1337 	 * says that the combined (geometry | compute) fuse should be used to
1338 	 * select the steering.
1339 	 */
1340 
1341 	/* Find the potential gslice candidates */
1342 	slice_mask = intel_slicemask_from_xehp_dssmask(sseu->subslice_mask,
1343 						       GEN_DSS_PER_GSLICE);
1344 
1345 	/*
1346 	 * Find the potential LNCF candidates.  Either LNCF within a valid
1347 	 * mslice is fine.
1348 	 */
1349 	for_each_set_bit(i, &gt->info.mslice_mask, GEN12_MAX_MSLICES)
1350 		lncf_mask |= (0x3 << (i * 2));
1351 
1352 	/*
1353 	 * Are there any sliceid values that work for both GSLICE and LNCF
1354 	 * steering?
1355 	 */
1356 	if (slice_mask & lncf_mask) {
1357 		slice_mask &= lncf_mask;
1358 		gt->steering_table[LNCF] = NULL;
1359 	}
1360 
1361 	/* How about sliceid values that also work for MSLICE steering? */
1362 	if (slice_mask & gt->info.mslice_mask) {
1363 		slice_mask &= gt->info.mslice_mask;
1364 		gt->steering_table[MSLICE] = NULL;
1365 	}
1366 
1367 	slice = __ffs(slice_mask);
1368 	subslice = intel_sseu_find_first_xehp_dss(sseu, GEN_DSS_PER_GSLICE, slice) %
1369 		GEN_DSS_PER_GSLICE;
1370 
1371 	__add_mcr_wa(gt, wal, slice, subslice);
1372 
1373 	/*
1374 	 * SQIDI ranges are special because they use different steering
1375 	 * registers than everything else we work with.  On XeHP SDV and
1376 	 * DG2-G10, any value in the steering registers will work fine since
1377 	 * all instances are present, but DG2-G11 only has SQIDI instances at
1378 	 * ID's 2 and 3, so we need to steer to one of those.  For simplicity
1379 	 * we'll just steer to a hardcoded "2" since that value will work
1380 	 * everywhere.
1381 	 */
1382 	__set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2);
1383 	__set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2);
1384 
1385 	/*
1386 	 * On DG2, GAM registers have a dedicated steering control register
1387 	 * and must always be programmed to a hardcoded groupid of "1."
1388 	 */
1389 	if (IS_DG2(gt->i915))
1390 		__set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0);
1391 }
1392 
1393 static void
icl_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1394 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1395 {
1396 	struct drm_i915_private *i915 = gt->i915;
1397 
1398 	icl_wa_init_mcr(gt, wal);
1399 
1400 	/* WaModifyGamTlbPartitioning:icl */
1401 	wa_write_clr_set(wal,
1402 			 GEN11_GACB_PERF_CTRL,
1403 			 GEN11_HASH_CTRL_MASK,
1404 			 GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4);
1405 
1406 	/* Wa_1405766107:icl
1407 	 * Formerly known as WaCL2SFHalfMaxAlloc
1408 	 */
1409 	wa_write_or(wal,
1410 		    GEN11_LSN_UNSLCVC,
1411 		    GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
1412 		    GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC);
1413 
1414 	/* Wa_220166154:icl
1415 	 * Formerly known as WaDisCtxReload
1416 	 */
1417 	wa_write_or(wal,
1418 		    GEN8_GAMW_ECO_DEV_RW_IA,
1419 		    GAMW_ECO_DEV_CTX_RELOAD_DISABLE);
1420 
1421 	/* Wa_1406463099:icl
1422 	 * Formerly known as WaGamTlbPendError
1423 	 */
1424 	wa_write_or(wal,
1425 		    GAMT_CHKN_BIT_REG,
1426 		    GAMT_CHKN_DISABLE_L3_COH_PIPE);
1427 
1428 	/*
1429 	 * Wa_1408615072:icl,ehl  (vsunit)
1430 	 * Wa_1407596294:icl,ehl  (hsunit)
1431 	 */
1432 	wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1433 		    VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
1434 
1435 	/* Wa_1407352427:icl,ehl */
1436 	wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
1437 		    PSDUNIT_CLKGATE_DIS);
1438 
1439 	/* Wa_1406680159:icl,ehl */
1440 	wa_mcr_write_or(wal,
1441 			GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1442 			GWUNIT_CLKGATE_DIS);
1443 
1444 	/* Wa_1607087056:icl,ehl,jsl */
1445 	if (IS_ICELAKE(i915) ||
1446 		((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
1447 		IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)))
1448 		wa_write_or(wal,
1449 			    GEN11_SLICE_UNIT_LEVEL_CLKGATE,
1450 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
1451 
1452 	/*
1453 	 * This is not a documented workaround, but rather an optimization
1454 	 * to reduce sampler power.
1455 	 */
1456 	wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1457 }
1458 
1459 /*
1460  * Though there are per-engine instances of these registers,
1461  * they retain their value through engine resets and should
1462  * only be provided on the GT workaround list rather than
1463  * the engine-specific workaround list.
1464  */
1465 static void
wa_14011060649(struct intel_gt * gt,struct i915_wa_list * wal)1466 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal)
1467 {
1468 	struct intel_engine_cs *engine;
1469 	int id;
1470 
1471 	for_each_engine(engine, gt, id) {
1472 		if (engine->class != VIDEO_DECODE_CLASS ||
1473 		    (engine->instance % 2))
1474 			continue;
1475 
1476 		wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base),
1477 			    IECPUNIT_CLKGATE_DIS);
1478 	}
1479 }
1480 
1481 static void
gen12_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1482 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1483 {
1484 	icl_wa_init_mcr(gt, wal);
1485 
1486 	/* Wa_14011060649:tgl,rkl,dg1,adl-s,adl-p */
1487 	wa_14011060649(gt, wal);
1488 
1489 	/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
1490 	wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
1491 
1492 	/*
1493 	 * Wa_14015795083
1494 	 *
1495 	 * Firmware on some gen12 platforms locks the MISCCPCTL register,
1496 	 * preventing i915 from modifying it for this workaround.  Skip the
1497 	 * readback verification for this workaround on debug builds; if the
1498 	 * workaround doesn't stick due to firmware behavior, it's not an error
1499 	 * that we want CI to flag.
1500 	 */
1501 	wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
1502 	       0, 0, false);
1503 }
1504 
1505 static void
dg1_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1506 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1507 {
1508 	gen12_gt_workarounds_init(gt, wal);
1509 
1510 	/* Wa_1409420604:dg1 */
1511 	wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2,
1512 			CPSSUNIT_CLKGATE_DIS);
1513 
1514 	/* Wa_1408615072:dg1 */
1515 	/* Empirical testing shows this register is unaffected by engine reset. */
1516 	wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL);
1517 }
1518 
1519 static void
dg2_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1520 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1521 {
1522 	xehp_init_mcr(gt, wal);
1523 
1524 	/* Wa_14011060649:dg2 */
1525 	wa_14011060649(gt, wal);
1526 
1527 	if (IS_DG2_G10(gt->i915)) {
1528 		/* Wa_22010523718:dg2 */
1529 		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
1530 			    CG3DDISCFEG_CLKGATE_DIS);
1531 
1532 		/* Wa_14011006942:dg2 */
1533 		wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
1534 				DSS_ROUTER_CLKGATE_DIS);
1535 	}
1536 
1537 	/* Wa_14014830051:dg2 */
1538 	wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1539 
1540 	/*
1541 	 * Wa_14015795083
1542 	 * Skip verification for possibly locked register.
1543 	 */
1544 	wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
1545 	       0, 0, false);
1546 
1547 	/* Wa_18018781329 */
1548 	wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1549 	wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1550 	wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1551 	wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB);
1552 
1553 	/* Wa_1509235366:dg2 */
1554 	wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL,
1555 			INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE);
1556 
1557 	/* Wa_14010648519:dg2 */
1558 	wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
1559 }
1560 
1561 static void
xelpg_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1562 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1563 {
1564 	/* Wa_14018575942 / Wa_18018781329 */
1565 	wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
1566 	wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
1567 
1568 	/* Wa_22016670082 */
1569 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
1570 
1571 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
1572 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
1573 		/* Wa_14014830051 */
1574 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
1575 
1576 		/* Wa_14015795083 */
1577 		wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
1578 	}
1579 
1580 	/*
1581 	 * Unlike older platforms, we no longer setup implicit steering here;
1582 	 * all MCR accesses are explicitly steered.
1583 	 */
1584 	debug_dump_steering(gt);
1585 }
1586 
1587 static void
wa_16021867713(struct intel_gt * gt,struct i915_wa_list * wal)1588 wa_16021867713(struct intel_gt *gt, struct i915_wa_list *wal)
1589 {
1590 	struct intel_engine_cs *engine;
1591 	int id;
1592 
1593 	for_each_engine(engine, gt, id)
1594 		if (engine->class == VIDEO_DECODE_CLASS)
1595 			wa_write_or(wal, VDBOX_CGCTL3F1C(engine->mmio_base),
1596 				    MFXPIPE_CLKGATE_DIS);
1597 }
1598 
1599 static void
xelpmp_gt_workarounds_init(struct intel_gt * gt,struct i915_wa_list * wal)1600 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
1601 {
1602 	wa_16021867713(gt, wal);
1603 
1604 	/*
1605 	 * Wa_14018778641
1606 	 * Wa_18018781329
1607 	 *
1608 	 * Note that although these registers are MCR on the primary
1609 	 * GT, the media GT's versions are regular singleton registers.
1610 	 */
1611 	wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB);
1612 
1613 	/*
1614 	 * Wa_14018575942
1615 	 *
1616 	 * Issue is seen on media KPI test running on VDBOX engine
1617 	 * especially VP9 encoding WLs
1618 	 */
1619 	wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB);
1620 
1621 	/* Wa_22016670082 */
1622 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
1623 
1624 	debug_dump_steering(gt);
1625 }
1626 
1627 /*
1628  * The bspec performance guide has recommended MMIO tuning settings.  These
1629  * aren't truly "workarounds" but we want to program them through the
1630  * workaround infrastructure to make sure they're (re)applied at the proper
1631  * times.
1632  *
1633  * The programming in this function is for settings that persist through
1634  * engine resets and also are not part of any engine's register state context.
1635  * I.e., settings that only need to be re-applied in the event of a full GT
1636  * reset.
1637  */
gt_tuning_settings(struct intel_gt * gt,struct i915_wa_list * wal)1638 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
1639 {
1640 	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
1641 		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1642 		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1643 	}
1644 
1645 	if (IS_DG2(gt->i915)) {
1646 		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
1647 		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
1648 	}
1649 }
1650 
1651 static void
gt_init_workarounds(struct intel_gt * gt,struct i915_wa_list * wal)1652 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
1653 {
1654 	struct drm_i915_private *i915 = gt->i915;
1655 
1656 	gt_tuning_settings(gt, wal);
1657 
1658 	if (gt->type == GT_MEDIA) {
1659 		if (MEDIA_VER_FULL(i915) == IP_VER(13, 0))
1660 			xelpmp_gt_workarounds_init(gt, wal);
1661 		else
1662 			MISSING_CASE(MEDIA_VER_FULL(i915));
1663 
1664 		return;
1665 	}
1666 
1667 	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
1668 		xelpg_gt_workarounds_init(gt, wal);
1669 	else if (IS_DG2(i915))
1670 		dg2_gt_workarounds_init(gt, wal);
1671 	else if (IS_DG1(i915))
1672 		dg1_gt_workarounds_init(gt, wal);
1673 	else if (GRAPHICS_VER(i915) == 12)
1674 		gen12_gt_workarounds_init(gt, wal);
1675 	else if (GRAPHICS_VER(i915) == 11)
1676 		icl_gt_workarounds_init(gt, wal);
1677 	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
1678 		cfl_gt_workarounds_init(gt, wal);
1679 	else if (IS_GEMINILAKE(i915))
1680 		glk_gt_workarounds_init(gt, wal);
1681 	else if (IS_KABYLAKE(i915))
1682 		kbl_gt_workarounds_init(gt, wal);
1683 	else if (IS_BROXTON(i915))
1684 		gen9_gt_workarounds_init(gt, wal);
1685 	else if (IS_SKYLAKE(i915))
1686 		skl_gt_workarounds_init(gt, wal);
1687 	else if (IS_HASWELL(i915))
1688 		hsw_gt_workarounds_init(gt, wal);
1689 	else if (IS_VALLEYVIEW(i915))
1690 		vlv_gt_workarounds_init(gt, wal);
1691 	else if (IS_IVYBRIDGE(i915))
1692 		ivb_gt_workarounds_init(gt, wal);
1693 	else if (GRAPHICS_VER(i915) == 6)
1694 		snb_gt_workarounds_init(gt, wal);
1695 	else if (GRAPHICS_VER(i915) == 5)
1696 		ilk_gt_workarounds_init(gt, wal);
1697 	else if (IS_G4X(i915))
1698 		g4x_gt_workarounds_init(gt, wal);
1699 	else if (GRAPHICS_VER(i915) == 4)
1700 		gen4_gt_workarounds_init(gt, wal);
1701 	else if (GRAPHICS_VER(i915) <= 8)
1702 		;
1703 	else
1704 		MISSING_CASE(GRAPHICS_VER(i915));
1705 }
1706 
intel_gt_init_workarounds(struct intel_gt * gt)1707 void intel_gt_init_workarounds(struct intel_gt *gt)
1708 {
1709 	struct i915_wa_list *wal = &gt->wa_list;
1710 
1711 	wa_init_start(wal, gt, "GT", "global");
1712 	gt_init_workarounds(gt, wal);
1713 	wa_init_finish(wal);
1714 }
1715 
1716 static bool
wa_verify(struct intel_gt * gt,const struct i915_wa * wa,u32 cur,const char * name,const char * from)1717 wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,
1718 	  const char *name, const char *from)
1719 {
1720 	if ((cur ^ wa->set) & wa->read) {
1721 		gt_err(gt,
1722 		       "%s workaround lost on %s! (reg[%x]=0x%x, relevant bits were 0x%x vs expected 0x%x)\n",
1723 		       name, from, i915_mmio_reg_offset(wa->reg),
1724 		       cur, cur & wa->read, wa->set & wa->read);
1725 
1726 		return false;
1727 	}
1728 
1729 	return true;
1730 }
1731 
wa_list_apply(const struct i915_wa_list * wal)1732 static void wa_list_apply(const struct i915_wa_list *wal)
1733 {
1734 	struct intel_gt *gt = wal->gt;
1735 	struct intel_uncore *uncore = gt->uncore;
1736 	enum forcewake_domains fw;
1737 	unsigned long flags;
1738 	struct i915_wa *wa;
1739 	unsigned int i;
1740 
1741 	if (!wal->count)
1742 		return;
1743 
1744 	fw = wal_get_fw_for_rmw(uncore, wal);
1745 
1746 	intel_gt_mcr_lock(gt, &flags);
1747 	spin_lock(&uncore->lock);
1748 	intel_uncore_forcewake_get__locked(uncore, fw);
1749 
1750 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
1751 		u32 val, old = 0;
1752 
1753 		/* open-coded rmw due to steering */
1754 		if (wa->clr)
1755 			old = wa->is_mcr ?
1756 				intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1757 				intel_uncore_read_fw(uncore, wa->reg);
1758 		val = (old & ~wa->clr) | wa->set;
1759 		if (val != old || !wa->clr) {
1760 			if (wa->is_mcr)
1761 				intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val);
1762 			else
1763 				intel_uncore_write_fw(uncore, wa->reg, val);
1764 		}
1765 
1766 		if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
1767 			u32 val = wa->is_mcr ?
1768 				intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1769 				intel_uncore_read_fw(uncore, wa->reg);
1770 
1771 			wa_verify(gt, wa, val, wal->name, "application");
1772 		}
1773 	}
1774 
1775 	intel_uncore_forcewake_put__locked(uncore, fw);
1776 	spin_unlock(&uncore->lock);
1777 	intel_gt_mcr_unlock(gt, flags);
1778 }
1779 
intel_gt_apply_workarounds(struct intel_gt * gt)1780 void intel_gt_apply_workarounds(struct intel_gt *gt)
1781 {
1782 	wa_list_apply(&gt->wa_list);
1783 }
1784 
wa_list_verify(struct intel_gt * gt,const struct i915_wa_list * wal,const char * from)1785 static bool wa_list_verify(struct intel_gt *gt,
1786 			   const struct i915_wa_list *wal,
1787 			   const char *from)
1788 {
1789 	struct intel_uncore *uncore = gt->uncore;
1790 	struct i915_wa *wa;
1791 	enum forcewake_domains fw;
1792 	unsigned long flags;
1793 	unsigned int i;
1794 	bool ok = true;
1795 
1796 	fw = wal_get_fw_for_rmw(uncore, wal);
1797 
1798 	intel_gt_mcr_lock(gt, &flags);
1799 	spin_lock(&uncore->lock);
1800 	intel_uncore_forcewake_get__locked(uncore, fw);
1801 
1802 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
1803 		ok &= wa_verify(wal->gt, wa, wa->is_mcr ?
1804 				intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
1805 				intel_uncore_read_fw(uncore, wa->reg),
1806 				wal->name, from);
1807 
1808 	intel_uncore_forcewake_put__locked(uncore, fw);
1809 	spin_unlock(&uncore->lock);
1810 	intel_gt_mcr_unlock(gt, flags);
1811 
1812 	return ok;
1813 }
1814 
intel_gt_verify_workarounds(struct intel_gt * gt,const char * from)1815 bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
1816 {
1817 	return wa_list_verify(gt, &gt->wa_list, from);
1818 }
1819 
1820 __maybe_unused
is_nonpriv_flags_valid(u32 flags)1821 static bool is_nonpriv_flags_valid(u32 flags)
1822 {
1823 	/* Check only valid flag bits are set */
1824 	if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
1825 		return false;
1826 
1827 	/* NB: Only 3 out of 4 enum values are valid for access field */
1828 	if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
1829 	    RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
1830 		return false;
1831 
1832 	return true;
1833 }
1834 
1835 static void
whitelist_reg_ext(struct i915_wa_list * wal,i915_reg_t reg,u32 flags)1836 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
1837 {
1838 	struct i915_wa wa = {
1839 		.reg = reg
1840 	};
1841 
1842 	if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1843 		return;
1844 
1845 	if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1846 		return;
1847 
1848 	wa.reg.reg |= flags;
1849 	_wa_add(wal, &wa);
1850 }
1851 
1852 static void
whitelist_mcr_reg_ext(struct i915_wa_list * wal,i915_mcr_reg_t reg,u32 flags)1853 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
1854 {
1855 	struct i915_wa wa = {
1856 		.mcr_reg = reg,
1857 		.is_mcr = 1,
1858 	};
1859 
1860 	if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1861 		return;
1862 
1863 	if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
1864 		return;
1865 
1866 	wa.mcr_reg.reg |= flags;
1867 	_wa_add(wal, &wa);
1868 }
1869 
1870 static void
whitelist_reg(struct i915_wa_list * wal,i915_reg_t reg)1871 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1872 {
1873 	whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1874 }
1875 
1876 static void
whitelist_mcr_reg(struct i915_wa_list * wal,i915_mcr_reg_t reg)1877 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
1878 {
1879 	whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1880 }
1881 
gen9_whitelist_build(struct i915_wa_list * w)1882 static void gen9_whitelist_build(struct i915_wa_list *w)
1883 {
1884 	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
1885 	whitelist_reg(w, GEN9_CTX_PREEMPT_REG);
1886 
1887 	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl,[cnl] */
1888 	whitelist_reg(w, GEN8_CS_CHICKEN1);
1889 
1890 	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
1891 	whitelist_reg(w, GEN8_HDC_CHICKEN1);
1892 
1893 	/* WaSendPushConstantsFromMMIO:skl,bxt */
1894 	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
1895 }
1896 
skl_whitelist_build(struct intel_engine_cs * engine)1897 static void skl_whitelist_build(struct intel_engine_cs *engine)
1898 {
1899 	struct i915_wa_list *w = &engine->whitelist;
1900 
1901 	if (engine->class != RENDER_CLASS)
1902 		return;
1903 
1904 	gen9_whitelist_build(w);
1905 
1906 	/* WaDisableLSQCROPERFforOCL:skl */
1907 	whitelist_mcr_reg(w, GEN8_L3SQCREG4);
1908 }
1909 
bxt_whitelist_build(struct intel_engine_cs * engine)1910 static void bxt_whitelist_build(struct intel_engine_cs *engine)
1911 {
1912 	if (engine->class != RENDER_CLASS)
1913 		return;
1914 
1915 	gen9_whitelist_build(&engine->whitelist);
1916 }
1917 
kbl_whitelist_build(struct intel_engine_cs * engine)1918 static void kbl_whitelist_build(struct intel_engine_cs *engine)
1919 {
1920 	struct i915_wa_list *w = &engine->whitelist;
1921 
1922 	if (engine->class != RENDER_CLASS)
1923 		return;
1924 
1925 	gen9_whitelist_build(w);
1926 
1927 	/* WaDisableLSQCROPERFforOCL:kbl */
1928 	whitelist_mcr_reg(w, GEN8_L3SQCREG4);
1929 }
1930 
glk_whitelist_build(struct intel_engine_cs * engine)1931 static void glk_whitelist_build(struct intel_engine_cs *engine)
1932 {
1933 	struct i915_wa_list *w = &engine->whitelist;
1934 
1935 	if (engine->class != RENDER_CLASS)
1936 		return;
1937 
1938 	gen9_whitelist_build(w);
1939 
1940 	/* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
1941 	whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1942 }
1943 
cfl_whitelist_build(struct intel_engine_cs * engine)1944 static void cfl_whitelist_build(struct intel_engine_cs *engine)
1945 {
1946 	struct i915_wa_list *w = &engine->whitelist;
1947 
1948 	if (engine->class != RENDER_CLASS)
1949 		return;
1950 
1951 	gen9_whitelist_build(w);
1952 
1953 	/*
1954 	 * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1955 	 *
1956 	 * This covers 4 register which are next to one another :
1957 	 *   - PS_INVOCATION_COUNT
1958 	 *   - PS_INVOCATION_COUNT_UDW
1959 	 *   - PS_DEPTH_COUNT
1960 	 *   - PS_DEPTH_COUNT_UDW
1961 	 */
1962 	whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1963 			  RING_FORCE_TO_NONPRIV_ACCESS_RD |
1964 			  RING_FORCE_TO_NONPRIV_RANGE_4);
1965 }
1966 
allow_read_ctx_timestamp(struct intel_engine_cs * engine)1967 static void allow_read_ctx_timestamp(struct intel_engine_cs *engine)
1968 {
1969 	struct i915_wa_list *w = &engine->whitelist;
1970 
1971 	if (engine->class != RENDER_CLASS)
1972 		whitelist_reg_ext(w,
1973 				  RING_CTX_TIMESTAMP(engine->mmio_base),
1974 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
1975 }
1976 
cml_whitelist_build(struct intel_engine_cs * engine)1977 static void cml_whitelist_build(struct intel_engine_cs *engine)
1978 {
1979 	allow_read_ctx_timestamp(engine);
1980 
1981 	cfl_whitelist_build(engine);
1982 }
1983 
icl_whitelist_build(struct intel_engine_cs * engine)1984 static void icl_whitelist_build(struct intel_engine_cs *engine)
1985 {
1986 	struct i915_wa_list *w = &engine->whitelist;
1987 
1988 	allow_read_ctx_timestamp(engine);
1989 
1990 	switch (engine->class) {
1991 	case RENDER_CLASS:
1992 		/* WaAllowUMDToModifyHalfSliceChicken7:icl */
1993 		whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7);
1994 
1995 		/* WaAllowUMDToModifySamplerMode:icl */
1996 		whitelist_mcr_reg(w, GEN10_SAMPLER_MODE);
1997 
1998 		/* WaEnableStateCacheRedirectToCS:icl */
1999 		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
2000 
2001 		/*
2002 		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
2003 		 *
2004 		 * This covers 4 register which are next to one another :
2005 		 *   - PS_INVOCATION_COUNT
2006 		 *   - PS_INVOCATION_COUNT_UDW
2007 		 *   - PS_DEPTH_COUNT
2008 		 *   - PS_DEPTH_COUNT_UDW
2009 		 */
2010 		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2011 				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
2012 				  RING_FORCE_TO_NONPRIV_RANGE_4);
2013 		break;
2014 
2015 	case VIDEO_DECODE_CLASS:
2016 		/* hucStatusRegOffset */
2017 		whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
2018 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
2019 		/* hucUKernelHdrInfoRegOffset */
2020 		whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
2021 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
2022 		/* hucStatus2RegOffset */
2023 		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
2024 				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
2025 		break;
2026 
2027 	default:
2028 		break;
2029 	}
2030 }
2031 
tgl_whitelist_build(struct intel_engine_cs * engine)2032 static void tgl_whitelist_build(struct intel_engine_cs *engine)
2033 {
2034 	struct i915_wa_list *w = &engine->whitelist;
2035 
2036 	allow_read_ctx_timestamp(engine);
2037 
2038 	switch (engine->class) {
2039 	case RENDER_CLASS:
2040 		/*
2041 		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
2042 		 * Wa_1408556865:tgl
2043 		 *
2044 		 * This covers 4 registers which are next to one another :
2045 		 *   - PS_INVOCATION_COUNT
2046 		 *   - PS_INVOCATION_COUNT_UDW
2047 		 *   - PS_DEPTH_COUNT
2048 		 *   - PS_DEPTH_COUNT_UDW
2049 		 */
2050 		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
2051 				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
2052 				  RING_FORCE_TO_NONPRIV_RANGE_4);
2053 
2054 		/*
2055 		 * Wa_1808121037:tgl
2056 		 * Wa_14012131227:dg1
2057 		 * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p
2058 		 */
2059 		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
2060 
2061 		/* Wa_1806527549:tgl */
2062 		whitelist_reg(w, HIZ_CHICKEN);
2063 
2064 		/* Required by recommended tuning setting (not a workaround) */
2065 		whitelist_reg(w, GEN11_COMMON_SLICE_CHICKEN3);
2066 
2067 		break;
2068 	default:
2069 		break;
2070 	}
2071 }
2072 
dg2_whitelist_build(struct intel_engine_cs * engine)2073 static void dg2_whitelist_build(struct intel_engine_cs *engine)
2074 {
2075 	struct i915_wa_list *w = &engine->whitelist;
2076 
2077 	switch (engine->class) {
2078 	case RENDER_CLASS:
2079 		/* Required by recommended tuning setting (not a workaround) */
2080 		whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
2081 		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
2082 		break;
2083 	default:
2084 		break;
2085 	}
2086 }
2087 
xelpg_whitelist_build(struct intel_engine_cs * engine)2088 static void xelpg_whitelist_build(struct intel_engine_cs *engine)
2089 {
2090 	struct i915_wa_list *w = &engine->whitelist;
2091 
2092 	switch (engine->class) {
2093 	case RENDER_CLASS:
2094 		/* Required by recommended tuning setting (not a workaround) */
2095 		whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
2096 		whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
2097 		break;
2098 	default:
2099 		break;
2100 	}
2101 }
2102 
intel_engine_init_whitelist(struct intel_engine_cs * engine)2103 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
2104 {
2105 	struct drm_i915_private *i915 = engine->i915;
2106 	struct i915_wa_list *w = &engine->whitelist;
2107 
2108 	wa_init_start(w, engine->gt, "whitelist", engine->name);
2109 
2110 	if (engine->gt->type == GT_MEDIA)
2111 		; /* none yet */
2112 	else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
2113 		xelpg_whitelist_build(engine);
2114 	else if (IS_DG2(i915))
2115 		dg2_whitelist_build(engine);
2116 	else if (GRAPHICS_VER(i915) == 12)
2117 		tgl_whitelist_build(engine);
2118 	else if (GRAPHICS_VER(i915) == 11)
2119 		icl_whitelist_build(engine);
2120 	else if (IS_COMETLAKE(i915))
2121 		cml_whitelist_build(engine);
2122 	else if (IS_COFFEELAKE(i915))
2123 		cfl_whitelist_build(engine);
2124 	else if (IS_GEMINILAKE(i915))
2125 		glk_whitelist_build(engine);
2126 	else if (IS_KABYLAKE(i915))
2127 		kbl_whitelist_build(engine);
2128 	else if (IS_BROXTON(i915))
2129 		bxt_whitelist_build(engine);
2130 	else if (IS_SKYLAKE(i915))
2131 		skl_whitelist_build(engine);
2132 	else if (GRAPHICS_VER(i915) <= 8)
2133 		;
2134 	else
2135 		MISSING_CASE(GRAPHICS_VER(i915));
2136 
2137 	wa_init_finish(w);
2138 }
2139 
intel_engine_apply_whitelist(struct intel_engine_cs * engine)2140 void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
2141 {
2142 	const struct i915_wa_list *wal = &engine->whitelist;
2143 	struct intel_uncore *uncore = engine->uncore;
2144 	const u32 base = engine->mmio_base;
2145 	struct i915_wa *wa;
2146 	unsigned int i;
2147 
2148 	if (!wal->count)
2149 		return;
2150 
2151 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
2152 		intel_uncore_write(uncore,
2153 				   RING_FORCE_TO_NONPRIV(base, i),
2154 				   i915_mmio_reg_offset(wa->reg));
2155 
2156 	/* And clear the rest just in case of garbage */
2157 	for (; i < RING_MAX_NONPRIV_SLOTS; i++)
2158 		intel_uncore_write(uncore,
2159 				   RING_FORCE_TO_NONPRIV(base, i),
2160 				   i915_mmio_reg_offset(RING_NOPID(base)));
2161 }
2162 
2163 /*
2164  * engine_fake_wa_init(), a place holder to program the registers
2165  * which are not part of an official workaround defined by the
2166  * hardware team.
2167  * Adding programming of those register inside workaround will
2168  * allow utilizing wa framework to proper application and verification.
2169  */
2170 static void
engine_fake_wa_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)2171 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2172 {
2173 	u8 mocs_w, mocs_r;
2174 
2175 	/*
2176 	 * RING_CMD_CCTL specifies the default MOCS entry that will be used
2177 	 * by the command streamer when executing commands that don't have
2178 	 * a way to explicitly specify a MOCS setting.  The default should
2179 	 * usually reference whichever MOCS entry corresponds to uncached
2180 	 * behavior, although use of a WB cached entry is recommended by the
2181 	 * spec in certain circumstances on specific platforms.
2182 	 */
2183 	if (GRAPHICS_VER(engine->i915) >= 12) {
2184 		mocs_r = engine->gt->mocs.uc_index;
2185 		mocs_w = engine->gt->mocs.uc_index;
2186 
2187 		if (HAS_L3_CCS_READ(engine->i915) &&
2188 		    engine->class == COMPUTE_CLASS) {
2189 			mocs_r = engine->gt->mocs.wb_index;
2190 
2191 			/*
2192 			 * Even on the few platforms where MOCS 0 is a
2193 			 * legitimate table entry, it's never the correct
2194 			 * setting to use here; we can assume the MOCS init
2195 			 * just forgot to initialize wb_index.
2196 			 */
2197 			drm_WARN_ON(&engine->i915->drm, mocs_r == 0);
2198 		}
2199 
2200 		wa_masked_field_set(wal,
2201 				    RING_CMD_CCTL(engine->mmio_base),
2202 				    CMD_CCTL_MOCS_MASK,
2203 				    CMD_CCTL_MOCS_OVERRIDE(mocs_w, mocs_r));
2204 	}
2205 }
2206 
2207 static void
rcs_engine_wa_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)2208 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2209 {
2210 	struct drm_i915_private *i915 = engine->i915;
2211 	struct intel_gt *gt = engine->gt;
2212 
2213 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2214 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
2215 		/* Wa_22014600077 */
2216 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2217 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
2218 	}
2219 
2220 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2221 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
2222 	    IS_DG2(i915)) {
2223 		/* Wa_1509727124 */
2224 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2225 				 SC_DISABLE_POWER_OPTIMIZATION_EBB);
2226 	}
2227 
2228 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2229 	    IS_DG2(i915)) {
2230 		/* Wa_22012856258 */
2231 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2232 				 GEN12_DISABLE_READ_SUPPRESSION);
2233 	}
2234 
2235 	if (IS_DG2(i915)) {
2236 		/*
2237 		 * Wa_22010960976:dg2
2238 		 * Wa_14013347512:dg2
2239 		 */
2240 		wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
2241 				  LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
2242 	}
2243 
2244 	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
2245 	    IS_DG2(i915)) {
2246 		/* Wa_14015150844 */
2247 		wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
2248 			   _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
2249 			   0, true);
2250 	}
2251 
2252 	if (IS_DG2(i915) || IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
2253 	    IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2254 		/*
2255 		 * Wa_1606700617:tgl,dg1,adl-p
2256 		 * Wa_22010271021:tgl,rkl,dg1,adl-s,adl-p
2257 		 * Wa_14010826681:tgl,dg1,rkl,adl-p
2258 		 * Wa_18019627453:dg2
2259 		 */
2260 		wa_masked_en(wal,
2261 			     GEN9_CS_DEBUG_MODE1,
2262 			     FF_DOP_CLOCK_GATE_DISABLE);
2263 	}
2264 
2265 	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
2266 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2267 		/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
2268 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
2269 
2270 		/*
2271 		 * Wa_1407928979:tgl A*
2272 		 * Wa_18011464164:tgl[B0+],dg1[B0+]
2273 		 * Wa_22010931296:tgl[B0+],dg1[B0+]
2274 		 * Wa_14010919138:rkl,dg1,adl-s,adl-p
2275 		 */
2276 		wa_write_or(wal, GEN7_FF_THREAD_MODE,
2277 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
2278 
2279 		/* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
2280 		wa_mcr_masked_en(wal,
2281 				 GEN10_SAMPLER_MODE,
2282 				 ENABLE_SMALLPL);
2283 	}
2284 
2285 	if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
2286 	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
2287 		/* Wa_1409804808 */
2288 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
2289 				 GEN12_PUSH_CONST_DEREF_HOLD_DIS);
2290 
2291 		/* Wa_14010229206 */
2292 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
2293 	}
2294 
2295 	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
2296 		/*
2297 		 * Wa_1607297627
2298 		 *
2299 		 * On TGL and RKL there are multiple entries for this WA in the
2300 		 * BSpec; some indicate this is an A0-only WA, others indicate
2301 		 * it applies to all steppings so we trust the "all steppings."
2302 		 */
2303 		wa_masked_en(wal,
2304 			     RING_PSMI_CTL(RENDER_RING_BASE),
2305 			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
2306 			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
2307 	}
2308 
2309 	if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {
2310 		/*
2311 		 * "Disable Repacking for Compression (masked R/W access)
2312 		 *  before rendering compressed surfaces for display."
2313 		 */
2314 		wa_masked_en(wal, CACHE_MODE_0_GEN7,
2315 			     DISABLE_REPACKING_FOR_COMPRESSION);
2316 	}
2317 
2318 	if (GRAPHICS_VER(i915) == 11) {
2319 		/* This is not an Wa. Enable for better image quality */
2320 		wa_masked_en(wal,
2321 			     _3D_CHICKEN3,
2322 			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
2323 
2324 		/*
2325 		 * Wa_1405543622:icl
2326 		 * Formerly known as WaGAPZPriorityScheme
2327 		 */
2328 		wa_write_or(wal,
2329 			    GEN8_GARBCNTL,
2330 			    GEN11_ARBITRATION_PRIO_ORDER_MASK);
2331 
2332 		/*
2333 		 * Wa_1604223664:icl
2334 		 * Formerly known as WaL3BankAddressHashing
2335 		 */
2336 		wa_write_clr_set(wal,
2337 				 GEN8_GARBCNTL,
2338 				 GEN11_HASH_CTRL_EXCL_MASK,
2339 				 GEN11_HASH_CTRL_EXCL_BIT0);
2340 		wa_write_clr_set(wal,
2341 				 GEN11_GLBLINVL,
2342 				 GEN11_BANK_HASH_ADDR_EXCL_MASK,
2343 				 GEN11_BANK_HASH_ADDR_EXCL_BIT0);
2344 
2345 		/*
2346 		 * Wa_1405733216:icl
2347 		 * Formerly known as WaDisableCleanEvicts
2348 		 */
2349 		wa_mcr_write_or(wal,
2350 				GEN8_L3SQCREG4,
2351 				GEN11_LQSC_CLEAN_EVICT_DISABLE);
2352 
2353 		/* Wa_1606682166:icl */
2354 		wa_write_or(wal,
2355 			    GEN7_SARCHKMD,
2356 			    GEN7_DISABLE_SAMPLER_PREFETCH);
2357 
2358 		/* Wa_1409178092:icl */
2359 		wa_mcr_write_clr_set(wal,
2360 				     GEN11_SCRATCH2,
2361 				     GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
2362 				     0);
2363 
2364 		/* WaEnable32PlaneMode:icl */
2365 		wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
2366 			     GEN11_ENABLE_32_PLANE_MODE);
2367 
2368 		/*
2369 		 * Wa_1408767742:icl[a2..forever],ehl[all]
2370 		 * Wa_1605460711:icl[a0..c0]
2371 		 */
2372 		wa_write_or(wal,
2373 			    GEN7_FF_THREAD_MODE,
2374 			    GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
2375 
2376 		/* Wa_22010271021 */
2377 		wa_masked_en(wal,
2378 			     GEN9_CS_DEBUG_MODE1,
2379 			     FF_DOP_CLOCK_GATE_DISABLE);
2380 	}
2381 
2382 	/*
2383 	 * Intel platforms that support fine-grained preemption (i.e., gen9 and
2384 	 * beyond) allow the kernel-mode driver to choose between two different
2385 	 * options for controlling preemption granularity and behavior.
2386 	 *
2387 	 * Option 1 (hardware default):
2388 	 *   Preemption settings are controlled in a global manner via
2389 	 *   kernel-only register CS_DEBUG_MODE1 (0x20EC).  Any granularity
2390 	 *   and settings chosen by the kernel-mode driver will apply to all
2391 	 *   userspace clients.
2392 	 *
2393 	 * Option 2:
2394 	 *   Preemption settings are controlled on a per-context basis via
2395 	 *   register CS_CHICKEN1 (0x2580).  CS_CHICKEN1 is saved/restored on
2396 	 *   context switch and is writable by userspace (e.g., via
2397 	 *   MI_LOAD_REGISTER_IMMEDIATE instructions placed in a batch buffer)
2398 	 *   which allows different userspace drivers/clients to select
2399 	 *   different settings, or to change those settings on the fly in
2400 	 *   response to runtime needs.  This option was known by name
2401 	 *   "FtrPerCtxtPreemptionGranularityControl" at one time, although
2402 	 *   that name is somewhat misleading as other non-granularity
2403 	 *   preemption settings are also impacted by this decision.
2404 	 *
2405 	 * On Linux, our policy has always been to let userspace drivers
2406 	 * control preemption granularity/settings (Option 2).  This was
2407 	 * originally mandatory on gen9 to prevent ABI breakage (old gen9
2408 	 * userspace developed before object-level preemption was enabled would
2409 	 * not behave well if i915 were to go with Option 1 and enable that
2410 	 * preemption in a global manner).  On gen9 each context would have
2411 	 * object-level preemption disabled by default (see
2412 	 * WaDisable3DMidCmdPreemption in gen9_ctx_workarounds_init), but
2413 	 * userspace drivers could opt-in to object-level preemption as they
2414 	 * saw fit.  For post-gen9 platforms, we continue to utilize Option 2;
2415 	 * even though it is no longer necessary for ABI compatibility when
2416 	 * enabling a new platform, it does ensure that userspace will be able
2417 	 * to implement any workarounds that show up requiring temporary
2418 	 * adjustments to preemption behavior at runtime.
2419 	 *
2420 	 * Notes/Workarounds:
2421 	 *  - Wa_14015141709:  On DG2 and early steppings of MTL,
2422 	 *      CS_CHICKEN1[0] does not disable object-level preemption as
2423 	 *      it is supposed to (nor does CS_DEBUG_MODE1[0] if we had been
2424 	 *      using Option 1).  Effectively this means userspace is unable
2425 	 *      to disable object-level preemption on these platforms/steppings
2426 	 *      despite the setting here.
2427 	 *
2428 	 *  - Wa_16013994831:  May require that userspace program
2429 	 *      CS_CHICKEN1[10] when certain runtime conditions are true.
2430 	 *      Userspace requires Option 2 to be in effect for their update of
2431 	 *      CS_CHICKEN1[10] to be effective.
2432 	 *
2433 	 * Other workarounds may appear in the future that will also require
2434 	 * Option 2 behavior to allow proper userspace implementation.
2435 	 */
2436 	if (GRAPHICS_VER(i915) >= 9)
2437 		wa_masked_en(wal,
2438 			     GEN7_FF_SLICE_CS_CHICKEN1,
2439 			     GEN9_FFSC_PERCTX_PREEMPT_CTRL);
2440 
2441 	if (IS_SKYLAKE(i915) ||
2442 	    IS_KABYLAKE(i915) ||
2443 	    IS_COFFEELAKE(i915) ||
2444 	    IS_COMETLAKE(i915)) {
2445 		/* WaEnableGapsTsvCreditFix:skl,kbl,cfl */
2446 		wa_write_or(wal,
2447 			    GEN8_GARBCNTL,
2448 			    GEN9_GAPS_TSV_CREDIT_DISABLE);
2449 	}
2450 
2451 	if (IS_BROXTON(i915)) {
2452 		/* WaDisablePooledEuLoadBalancingFix:bxt */
2453 		wa_masked_en(wal,
2454 			     FF_SLICE_CS_CHICKEN2,
2455 			     GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
2456 	}
2457 
2458 	if (GRAPHICS_VER(i915) == 9) {
2459 		/* WaContextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
2460 		wa_masked_en(wal,
2461 			     GEN9_CSFE_CHICKEN1_RCS,
2462 			     GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
2463 
2464 		/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
2465 		wa_mcr_write_or(wal,
2466 				BDW_SCRATCH1,
2467 				GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
2468 
2469 		/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
2470 		if (IS_GEN9_LP(i915))
2471 			wa_mcr_write_clr_set(wal,
2472 					     GEN8_L3SQCREG1,
2473 					     L3_PRIO_CREDITS_MASK,
2474 					     L3_GENERAL_PRIO_CREDITS(62) |
2475 					     L3_HIGH_PRIO_CREDITS(2));
2476 
2477 		/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
2478 		wa_mcr_write_or(wal,
2479 				GEN8_L3SQCREG4,
2480 				GEN8_LQSC_FLUSH_COHERENT_LINES);
2481 
2482 		/* Disable atomics in L3 to prevent unrecoverable hangs */
2483 		wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
2484 				 GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
2485 		wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,
2486 				     GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
2487 		wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,
2488 				     EVICTION_PERF_FIX_ENABLE, 0);
2489 	}
2490 
2491 	if (IS_HASWELL(i915)) {
2492 		/* WaSampleCChickenBitEnable:hsw */
2493 		wa_masked_en(wal,
2494 			     HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
2495 
2496 		wa_masked_dis(wal,
2497 			      CACHE_MODE_0_GEN7,
2498 			      /* enable HiZ Raw Stall Optimization */
2499 			      HIZ_RAW_STALL_OPT_DISABLE);
2500 	}
2501 
2502 	if (IS_VALLEYVIEW(i915)) {
2503 		/* WaDisableEarlyCull:vlv */
2504 		wa_masked_en(wal,
2505 			     _3D_CHICKEN3,
2506 			     _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
2507 
2508 		/*
2509 		 * WaVSThreadDispatchOverride:ivb,vlv
2510 		 *
2511 		 * This actually overrides the dispatch
2512 		 * mode for all thread types.
2513 		 */
2514 		wa_write_clr_set(wal,
2515 				 GEN7_FF_THREAD_MODE,
2516 				 GEN7_FF_SCHED_MASK,
2517 				 GEN7_FF_TS_SCHED_HW |
2518 				 GEN7_FF_VS_SCHED_HW |
2519 				 GEN7_FF_DS_SCHED_HW);
2520 
2521 		/* WaPsdDispatchEnable:vlv */
2522 		/* WaDisablePSDDualDispatchEnable:vlv */
2523 		wa_masked_en(wal,
2524 			     GEN7_HALF_SLICE_CHICKEN1,
2525 			     GEN7_MAX_PS_THREAD_DEP |
2526 			     GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2527 	}
2528 
2529 	if (IS_IVYBRIDGE(i915)) {
2530 		/* WaDisableEarlyCull:ivb */
2531 		wa_masked_en(wal,
2532 			     _3D_CHICKEN3,
2533 			     _3D_CHICKEN_SF_DISABLE_OBJEND_CULL);
2534 
2535 		if (0) { /* causes HiZ corruption on ivb:gt1 */
2536 			/* enable HiZ Raw Stall Optimization */
2537 			wa_masked_dis(wal,
2538 				      CACHE_MODE_0_GEN7,
2539 				      HIZ_RAW_STALL_OPT_DISABLE);
2540 		}
2541 
2542 		/*
2543 		 * WaVSThreadDispatchOverride:ivb,vlv
2544 		 *
2545 		 * This actually overrides the dispatch
2546 		 * mode for all thread types.
2547 		 */
2548 		wa_write_clr_set(wal,
2549 				 GEN7_FF_THREAD_MODE,
2550 				 GEN7_FF_SCHED_MASK,
2551 				 GEN7_FF_TS_SCHED_HW |
2552 				 GEN7_FF_VS_SCHED_HW |
2553 				 GEN7_FF_DS_SCHED_HW);
2554 
2555 		/* WaDisablePSDDualDispatchEnable:ivb */
2556 		if (INTEL_INFO(i915)->gt == 1)
2557 			wa_masked_en(wal,
2558 				     GEN7_HALF_SLICE_CHICKEN1,
2559 				     GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
2560 	}
2561 
2562 	if (GRAPHICS_VER(i915) == 7) {
2563 		/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
2564 		wa_masked_en(wal,
2565 			     RING_MODE_GEN7(RENDER_RING_BASE),
2566 			     GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
2567 
2568 		/* WaDisable_RenderCache_OperationalFlush:ivb,vlv,hsw */
2569 		wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE);
2570 
2571 		/*
2572 		 * BSpec says this must be set, even though
2573 		 * WaDisable4x2SubspanOptimization:ivb,hsw
2574 		 * WaDisable4x2SubspanOptimization isn't listed for VLV.
2575 		 */
2576 		wa_masked_en(wal,
2577 			     CACHE_MODE_1,
2578 			     PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
2579 
2580 		/*
2581 		 * BSpec recommends 8x4 when MSAA is used,
2582 		 * however in practice 16x4 seems fastest.
2583 		 *
2584 		 * Note that PS/WM thread counts depend on the WIZ hashing
2585 		 * disable bit, which we don't touch here, but it's good
2586 		 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
2587 		 */
2588 		wa_masked_field_set(wal,
2589 				    GEN7_GT_MODE,
2590 				    GEN6_WIZ_HASHING_MASK,
2591 				    GEN6_WIZ_HASHING_16x4);
2592 	}
2593 
2594 	if (IS_GRAPHICS_VER(i915, 6, 7))
2595 		/*
2596 		 * We need to disable the AsyncFlip performance optimisations in
2597 		 * order to use MI_WAIT_FOR_EVENT within the CS. It should
2598 		 * already be programmed to '1' on all products.
2599 		 *
2600 		 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
2601 		 */
2602 		wa_masked_en(wal,
2603 			     RING_MI_MODE(RENDER_RING_BASE),
2604 			     ASYNC_FLIP_PERF_DISABLE);
2605 
2606 	if (GRAPHICS_VER(i915) == 6) {
2607 		/*
2608 		 * Required for the hardware to program scanline values for
2609 		 * waiting
2610 		 * WaEnableFlushTlbInvalidationMode:snb
2611 		 */
2612 		wa_masked_en(wal,
2613 			     GFX_MODE,
2614 			     GFX_TLB_INVALIDATE_EXPLICIT);
2615 
2616 		/* WaDisableHiZPlanesWhenMSAAEnabled:snb */
2617 		wa_masked_en(wal,
2618 			     _3D_CHICKEN,
2619 			     _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB);
2620 
2621 		wa_masked_en(wal,
2622 			     _3D_CHICKEN3,
2623 			     /* WaStripsFansDisableFastClipPerformanceFix:snb */
2624 			     _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL |
2625 			     /*
2626 			      * Bspec says:
2627 			      * "This bit must be set if 3DSTATE_CLIP clip mode is set
2628 			      * to normal and 3DSTATE_SF number of SF output attributes
2629 			      * is more than 16."
2630 			      */
2631 			     _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH);
2632 
2633 		/*
2634 		 * BSpec recommends 8x4 when MSAA is used,
2635 		 * however in practice 16x4 seems fastest.
2636 		 *
2637 		 * Note that PS/WM thread counts depend on the WIZ hashing
2638 		 * disable bit, which we don't touch here, but it's good
2639 		 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
2640 		 */
2641 		wa_masked_field_set(wal,
2642 				    GEN6_GT_MODE,
2643 				    GEN6_WIZ_HASHING_MASK,
2644 				    GEN6_WIZ_HASHING_16x4);
2645 
2646 		/* WaDisable_RenderCache_OperationalFlush:snb */
2647 		wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
2648 
2649 		/*
2650 		 * From the Sandybridge PRM, volume 1 part 3, page 24:
2651 		 * "If this bit is set, STCunit will have LRA as replacement
2652 		 *  policy. [...] This bit must be reset. LRA replacement
2653 		 *  policy is not supported."
2654 		 */
2655 		wa_masked_dis(wal,
2656 			      CACHE_MODE_0,
2657 			      CM0_STC_EVICT_DISABLE_LRA_SNB);
2658 	}
2659 
2660 	if (IS_GRAPHICS_VER(i915, 4, 6))
2661 		/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
2662 		wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
2663 		       0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
2664 		       /* XXX bit doesn't stick on Broadwater */
2665 		       IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);
2666 
2667 	if (GRAPHICS_VER(i915) == 4)
2668 		/*
2669 		 * Disable CONSTANT_BUFFER before it is loaded from the context
2670 		 * image. For as it is loaded, it is executed and the stored
2671 		 * address may no longer be valid, leading to a GPU hang.
2672 		 *
2673 		 * This imposes the requirement that userspace reload their
2674 		 * CONSTANT_BUFFER on every batch, fortunately a requirement
2675 		 * they are already accustomed to from before contexts were
2676 		 * enabled.
2677 		 */
2678 		wa_add(wal, ECOSKPD(RENDER_RING_BASE),
2679 		       0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE),
2680 		       0 /* XXX bit doesn't stick on Broadwater */,
2681 		       true);
2682 }
2683 
2684 static void
xcs_engine_wa_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)2685 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2686 {
2687 	struct drm_i915_private *i915 = engine->i915;
2688 
2689 	/* WaKBLVECSSemaphoreWaitPoll:kbl */
2690 	if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_F0)) {
2691 		wa_write(wal,
2692 			 RING_SEMA_WAIT_POLL(engine->mmio_base),
2693 			 1);
2694 	}
2695 	/* Wa_16018031267, Wa_16018063123 */
2696 	if (NEEDS_FASTCOLOR_BLT_WABB(engine))
2697 		wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
2698 				    XEHP_BLITTER_SCHEDULING_MODE_MASK,
2699 				    XEHP_BLITTER_ROUND_ROBIN_MODE);
2700 }
2701 
2702 static void
ccs_engine_wa_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)2703 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2704 {
2705 	/* boilerplate for any CCS engine workaround */
2706 }
2707 
2708 /*
2709  * The bspec performance guide has recommended MMIO tuning settings.  These
2710  * aren't truly "workarounds" but we want to program them with the same
2711  * workaround infrastructure to ensure that they're automatically added to
2712  * the GuC save/restore lists, re-applied at the right times, and checked for
2713  * any conflicting programming requested by real workarounds.
2714  *
2715  * Programming settings should be added here only if their registers are not
2716  * part of an engine's register state context.  If a register is part of a
2717  * context, then any tuning settings should be programmed in an appropriate
2718  * function invoked by __intel_engine_init_ctx_wa().
2719  */
2720 static void
add_render_compute_tuning_settings(struct intel_gt * gt,struct i915_wa_list * wal)2721 add_render_compute_tuning_settings(struct intel_gt *gt,
2722 				   struct i915_wa_list *wal)
2723 {
2724 	struct drm_i915_private *i915 = gt->i915;
2725 
2726 	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
2727 		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
2728 
2729 	/*
2730 	 * This tuning setting proves beneficial only on ATS-M designs; the
2731 	 * default "age based" setting is optimal on regular DG2 and other
2732 	 * platforms.
2733 	 */
2734 	if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
2735 		wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
2736 					THREAD_EX_ARB_MODE_RR_AFTER_DEP);
2737 
2738 	if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))
2739 		wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
2740 }
2741 
ccs_engine_wa_mode(struct intel_engine_cs * engine,struct i915_wa_list * wal)2742 static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2743 {
2744 	struct intel_gt *gt = engine->gt;
2745 	u32 mode;
2746 
2747 	if (!IS_DG2(gt->i915))
2748 		return;
2749 
2750 	/*
2751 	 * Wa_14019159160: This workaround, along with others, leads to
2752 	 * significant challenges in utilizing load balancing among the
2753 	 * CCS slices. Consequently, an architectural decision has been
2754 	 * made to completely disable automatic CCS load balancing.
2755 	 */
2756 	wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
2757 
2758 	/*
2759 	 * After having disabled automatic load balancing we need to
2760 	 * assign all slices to a single CCS. We will call it CCS mode 1
2761 	 */
2762 	mode = intel_gt_apply_ccs_mode(gt);
2763 	wa_masked_en(wal, XEHP_CCS_MODE, mode);
2764 }
2765 
2766 /*
2767  * The workarounds in this function apply to shared registers in
2768  * the general render reset domain that aren't tied to a
2769  * specific engine.  Since all render+compute engines get reset
2770  * together, and the contents of these registers are lost during
2771  * the shared render domain reset, we'll define such workarounds
2772  * here and then add them to just a single RCS or CCS engine's
2773  * workaround list (whichever engine has the XXXX flag).
2774  */
2775 static void
general_render_compute_wa_init(struct intel_engine_cs * engine,struct i915_wa_list * wal)2776 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2777 {
2778 	struct drm_i915_private *i915 = engine->i915;
2779 	struct intel_gt *gt = engine->gt;
2780 
2781 	add_render_compute_tuning_settings(gt, wal);
2782 
2783 	if (GRAPHICS_VER(i915) >= 11) {
2784 		/* This is not a Wa (although referred to as
2785 		 * WaSetInidrectStateOverride in places), this allows
2786 		 * applications that reference sampler states through
2787 		 * the BindlessSamplerStateBaseAddress to have their
2788 		 * border color relative to DynamicStateBaseAddress
2789 		 * rather than BindlessSamplerStateBaseAddress.
2790 		 *
2791 		 * Otherwise SAMPLER_STATE border colors have to be
2792 		 * copied in multiple heaps (DynamicStateBaseAddress &
2793 		 * BindlessSamplerStateBaseAddress)
2794 		 *
2795 		 * BSpec: 46052
2796 		 */
2797 		wa_mcr_masked_en(wal,
2798 				 GEN10_SAMPLER_MODE,
2799 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
2800 	}
2801 
2802 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
2803 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||
2804 	    IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74))) {
2805 		/* Wa_14017856879 */
2806 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
2807 
2808 		/* Wa_14020495402 */
2809 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING);
2810 	}
2811 
2812 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2813 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
2814 		/*
2815 		 * Wa_14017066071
2816 		 * Wa_14017654203
2817 		 */
2818 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
2819 				 MTL_DISABLE_SAMPLER_SC_OOO);
2820 
2821 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
2822 		/* Wa_22015279794 */
2823 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
2824 				 DISABLE_PREFETCH_INTO_IC);
2825 
2826 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2827 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
2828 	    IS_DG2(i915)) {
2829 		/* Wa_22013037850 */
2830 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
2831 				DISABLE_128B_EVICTION_COMMAND_UDW);
2832 
2833 		/* Wa_18017747507 */
2834 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
2835 	}
2836 
2837 	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
2838 	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
2839 	    IS_DG2(i915)) {
2840 		/* Wa_22014226127 */
2841 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
2842 	}
2843 
2844 	if (IS_DG2(i915)) {
2845 		/* Wa_14015227452:dg2,pvc */
2846 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
2847 
2848 		/*
2849 		 * Wa_16011620976:dg2_g11
2850 		 * Wa_22015475538:dg2
2851 		 */
2852 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
2853 
2854 		/* Wa_18028616096 */
2855 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3);
2856 	}
2857 
2858 	if (IS_DG2_G11(i915)) {
2859 		/*
2860 		 * Wa_22012826095:dg2
2861 		 * Wa_22013059131:dg2
2862 		 */
2863 		wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
2864 				     MAXREQS_PER_BANK,
2865 				     REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
2866 
2867 		/* Wa_22013059131:dg2 */
2868 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
2869 				FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
2870 
2871 		/*
2872 		 * Wa_22012654132
2873 		 *
2874 		 * Note that register 0xE420 is write-only and cannot be read
2875 		 * back for verification on DG2 (due to Wa_14012342262), so
2876 		 * we need to explicitly skip the readback.
2877 		 */
2878 		wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
2879 			   _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
2880 			   0 /* write-only, so skip validation */,
2881 			   true);
2882 	}
2883 }
2884 
2885 static void
engine_init_workarounds(struct intel_engine_cs * engine,struct i915_wa_list * wal)2886 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2887 {
2888 	if (GRAPHICS_VER(engine->i915) < 4)
2889 		return;
2890 
2891 	engine_fake_wa_init(engine, wal);
2892 
2893 	/*
2894 	 * These are common workarounds that just need to applied
2895 	 * to a single RCS/CCS engine's workaround list since
2896 	 * they're reset as part of the general render domain reset.
2897 	 */
2898 	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {
2899 		general_render_compute_wa_init(engine, wal);
2900 		ccs_engine_wa_mode(engine, wal);
2901 	}
2902 
2903 	if (engine->class == COMPUTE_CLASS)
2904 		ccs_engine_wa_init(engine, wal);
2905 	else if (engine->class == RENDER_CLASS)
2906 		rcs_engine_wa_init(engine, wal);
2907 	else
2908 		xcs_engine_wa_init(engine, wal);
2909 }
2910 
intel_engine_init_workarounds(struct intel_engine_cs * engine)2911 void intel_engine_init_workarounds(struct intel_engine_cs *engine)
2912 {
2913 	struct i915_wa_list *wal = &engine->wa_list;
2914 
2915 	wa_init_start(wal, engine->gt, "engine", engine->name);
2916 	engine_init_workarounds(engine, wal);
2917 	wa_init_finish(wal);
2918 }
2919 
intel_engine_apply_workarounds(struct intel_engine_cs * engine)2920 void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
2921 {
2922 	wa_list_apply(&engine->wa_list);
2923 }
2924 
2925 static const struct i915_range mcr_ranges_gen8[] = {
2926 	{ .start = 0x5500, .end = 0x55ff },
2927 	{ .start = 0x7000, .end = 0x7fff },
2928 	{ .start = 0x9400, .end = 0x97ff },
2929 	{ .start = 0xb000, .end = 0xb3ff },
2930 	{ .start = 0xe000, .end = 0xe7ff },
2931 	{},
2932 };
2933 
2934 static const struct i915_range mcr_ranges_gen12[] = {
2935 	{ .start =  0x8150, .end =  0x815f },
2936 	{ .start =  0x9520, .end =  0x955f },
2937 	{ .start =  0xb100, .end =  0xb3ff },
2938 	{ .start =  0xde80, .end =  0xe8ff },
2939 	{ .start = 0x24a00, .end = 0x24a7f },
2940 	{},
2941 };
2942 
2943 static const struct i915_range mcr_ranges_xehp[] = {
2944 	{ .start =  0x4000, .end =  0x4aff },
2945 	{ .start =  0x5200, .end =  0x52ff },
2946 	{ .start =  0x5400, .end =  0x7fff },
2947 	{ .start =  0x8140, .end =  0x815f },
2948 	{ .start =  0x8c80, .end =  0x8dff },
2949 	{ .start =  0x94d0, .end =  0x955f },
2950 	{ .start =  0x9680, .end =  0x96ff },
2951 	{ .start =  0xb000, .end =  0xb3ff },
2952 	{ .start =  0xc800, .end =  0xcfff },
2953 	{ .start =  0xd800, .end =  0xd8ff },
2954 	{ .start =  0xdc00, .end =  0xffff },
2955 	{ .start = 0x17000, .end = 0x17fff },
2956 	{ .start = 0x24a00, .end = 0x24a7f },
2957 	{},
2958 };
2959 
mcr_range(struct drm_i915_private * i915,u32 offset)2960 static bool mcr_range(struct drm_i915_private *i915, u32 offset)
2961 {
2962 	const struct i915_range *mcr_ranges;
2963 	int i;
2964 
2965 	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
2966 		mcr_ranges = mcr_ranges_xehp;
2967 	else if (GRAPHICS_VER(i915) >= 12)
2968 		mcr_ranges = mcr_ranges_gen12;
2969 	else if (GRAPHICS_VER(i915) >= 8)
2970 		mcr_ranges = mcr_ranges_gen8;
2971 	else
2972 		return false;
2973 
2974 	/*
2975 	 * Registers in these ranges are affected by the MCR selector
2976 	 * which only controls CPU initiated MMIO. Routing does not
2977 	 * work for CS access so we cannot verify them on this path.
2978 	 */
2979 	for (i = 0; mcr_ranges[i].start; i++)
2980 		if (offset >= mcr_ranges[i].start &&
2981 		    offset <= mcr_ranges[i].end)
2982 			return true;
2983 
2984 	return false;
2985 }
2986 
2987 static int
wa_list_srm(struct i915_request * rq,const struct i915_wa_list * wal,struct i915_vma * vma)2988 wa_list_srm(struct i915_request *rq,
2989 	    const struct i915_wa_list *wal,
2990 	    struct i915_vma *vma)
2991 {
2992 	struct drm_i915_private *i915 = rq->i915;
2993 	unsigned int i, count = 0;
2994 	const struct i915_wa *wa;
2995 	u32 srm, *cs;
2996 
2997 	srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
2998 	if (GRAPHICS_VER(i915) >= 8)
2999 		srm++;
3000 
3001 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3002 		if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
3003 			count++;
3004 	}
3005 
3006 	cs = intel_ring_begin(rq, 4 * count);
3007 	if (IS_ERR(cs))
3008 		return PTR_ERR(cs);
3009 
3010 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3011 		u32 offset = i915_mmio_reg_offset(wa->reg);
3012 
3013 		if (mcr_range(i915, offset))
3014 			continue;
3015 
3016 		*cs++ = srm;
3017 		*cs++ = offset;
3018 		*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
3019 		*cs++ = 0;
3020 	}
3021 	intel_ring_advance(rq, cs);
3022 
3023 	return 0;
3024 }
3025 
engine_wa_list_verify(struct intel_context * ce,const struct i915_wa_list * const wal,const char * from)3026 static int engine_wa_list_verify(struct intel_context *ce,
3027 				 const struct i915_wa_list * const wal,
3028 				 const char *from)
3029 {
3030 	const struct i915_wa *wa;
3031 	struct i915_request *rq;
3032 	struct i915_vma *vma;
3033 	struct i915_gem_ww_ctx ww;
3034 	unsigned int i;
3035 	u32 *results;
3036 	int err;
3037 
3038 	if (!wal->count)
3039 		return 0;
3040 
3041 	vma = __vm_create_scratch_for_read(&ce->engine->gt->ggtt->vm,
3042 					   wal->count * sizeof(u32));
3043 	if (IS_ERR(vma))
3044 		return PTR_ERR(vma);
3045 
3046 	intel_engine_pm_get(ce->engine);
3047 	i915_gem_ww_ctx_init(&ww, false);
3048 retry:
3049 	err = i915_gem_object_lock(vma->obj, &ww);
3050 	if (err == 0)
3051 		err = intel_context_pin_ww(ce, &ww);
3052 	if (err)
3053 		goto err_pm;
3054 
3055 	err = i915_vma_pin_ww(vma, &ww, 0, 0,
3056 			   i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER);
3057 	if (err)
3058 		goto err_unpin;
3059 
3060 	rq = i915_request_create(ce);
3061 	if (IS_ERR(rq)) {
3062 		err = PTR_ERR(rq);
3063 		goto err_vma;
3064 	}
3065 
3066 	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
3067 	if (err == 0)
3068 		err = wa_list_srm(rq, wal, vma);
3069 
3070 	i915_request_get(rq);
3071 	if (err)
3072 		i915_request_set_error_once(rq, err);
3073 	i915_request_add(rq);
3074 
3075 	if (err)
3076 		goto err_rq;
3077 
3078 	if (i915_request_wait(rq, 0, HZ / 5) < 0) {
3079 		err = -ETIME;
3080 		goto err_rq;
3081 	}
3082 
3083 	results = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
3084 	if (IS_ERR(results)) {
3085 		err = PTR_ERR(results);
3086 		goto err_rq;
3087 	}
3088 
3089 	err = 0;
3090 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
3091 		if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
3092 			continue;
3093 
3094 		if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
3095 			err = -ENXIO;
3096 	}
3097 
3098 	i915_gem_object_unpin_map(vma->obj);
3099 
3100 err_rq:
3101 	i915_request_put(rq);
3102 err_vma:
3103 	i915_vma_unpin(vma);
3104 err_unpin:
3105 	intel_context_unpin(ce);
3106 err_pm:
3107 	if (err == -EDEADLK) {
3108 		err = i915_gem_ww_ctx_backoff(&ww);
3109 		if (!err)
3110 			goto retry;
3111 	}
3112 	i915_gem_ww_ctx_fini(&ww);
3113 	intel_engine_pm_put(ce->engine);
3114 	i915_vma_put(vma);
3115 	return err;
3116 }
3117 
intel_engine_verify_workarounds(struct intel_engine_cs * engine,const char * from)3118 int intel_engine_verify_workarounds(struct intel_engine_cs *engine,
3119 				    const char *from)
3120 {
3121 	return engine_wa_list_verify(engine->kernel_context,
3122 				     &engine->wa_list,
3123 				     from);
3124 }
3125 
3126 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3127 #include "selftest_workarounds.c"
3128 #endif
3129