1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include "i915_drv.h"
7 #include "i915_reg.h"
8 #include "intel_atomic.h"
9 #include "intel_cx0_phy_regs.h"
10 #include "intel_ddi.h"
11 #include "intel_de.h"
12 #include "intel_display.h"
13 #include "intel_display_driver.h"
14 #include "intel_display_power_map.h"
15 #include "intel_display_types.h"
16 #include "intel_dkl_phy_regs.h"
17 #include "intel_dp.h"
18 #include "intel_dp_mst.h"
19 #include "intel_mg_phy_regs.h"
20 #include "intel_modeset_lock.h"
21 #include "intel_tc.h"
22
23 #define DP_PIN_ASSIGNMENT_C 0x3
24 #define DP_PIN_ASSIGNMENT_D 0x4
25 #define DP_PIN_ASSIGNMENT_E 0x5
26
27 enum tc_port_mode {
28 TC_PORT_DISCONNECTED,
29 TC_PORT_TBT_ALT,
30 TC_PORT_DP_ALT,
31 TC_PORT_LEGACY,
32 };
33
34 struct intel_tc_port;
35
36 struct intel_tc_phy_ops {
37 enum intel_display_power_domain (*cold_off_domain)(struct intel_tc_port *tc);
38 u32 (*hpd_live_status)(struct intel_tc_port *tc);
39 bool (*is_ready)(struct intel_tc_port *tc);
40 bool (*is_owned)(struct intel_tc_port *tc);
41 void (*get_hw_state)(struct intel_tc_port *tc);
42 bool (*connect)(struct intel_tc_port *tc, int required_lanes);
43 void (*disconnect)(struct intel_tc_port *tc);
44 void (*init)(struct intel_tc_port *tc);
45 };
46
47 struct intel_tc_port {
48 struct intel_digital_port *dig_port;
49
50 const struct intel_tc_phy_ops *phy_ops;
51
52 struct mutex lock; /* protects the TypeC port mode */
53 intel_wakeref_t lock_wakeref;
54 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
55 enum intel_display_power_domain lock_power_domain;
56 #endif
57 struct delayed_work disconnect_phy_work;
58 struct delayed_work link_reset_work;
59 int link_refcount;
60 bool legacy_port:1;
61 const char *port_name;
62 enum tc_port_mode mode;
63 enum tc_port_mode init_mode;
64 enum phy_fia phy_fia;
65 u8 phy_fia_idx;
66 };
67
68 static enum intel_display_power_domain
69 tc_phy_cold_off_domain(struct intel_tc_port *);
70 static u32 tc_phy_hpd_live_status(struct intel_tc_port *tc);
71 static bool tc_phy_is_ready(struct intel_tc_port *tc);
72 static bool tc_phy_wait_for_ready(struct intel_tc_port *tc);
73 static enum tc_port_mode tc_phy_get_current_mode(struct intel_tc_port *tc);
74
tc_port_mode_name(enum tc_port_mode mode)75 static const char *tc_port_mode_name(enum tc_port_mode mode)
76 {
77 static const char * const names[] = {
78 [TC_PORT_DISCONNECTED] = "disconnected",
79 [TC_PORT_TBT_ALT] = "tbt-alt",
80 [TC_PORT_DP_ALT] = "dp-alt",
81 [TC_PORT_LEGACY] = "legacy",
82 };
83
84 if (WARN_ON(mode >= ARRAY_SIZE(names)))
85 mode = TC_PORT_DISCONNECTED;
86
87 return names[mode];
88 }
89
to_tc_port(struct intel_digital_port * dig_port)90 static struct intel_tc_port *to_tc_port(struct intel_digital_port *dig_port)
91 {
92 return dig_port->tc;
93 }
94
tc_to_i915(struct intel_tc_port * tc)95 static struct drm_i915_private *tc_to_i915(struct intel_tc_port *tc)
96 {
97 return to_i915(tc->dig_port->base.base.dev);
98 }
99
intel_tc_port_in_mode(struct intel_digital_port * dig_port,enum tc_port_mode mode)100 static bool intel_tc_port_in_mode(struct intel_digital_port *dig_port,
101 enum tc_port_mode mode)
102 {
103 struct intel_tc_port *tc = to_tc_port(dig_port);
104
105 return intel_encoder_is_tc(&dig_port->base) && tc->mode == mode;
106 }
107
intel_tc_port_in_tbt_alt_mode(struct intel_digital_port * dig_port)108 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port)
109 {
110 return intel_tc_port_in_mode(dig_port, TC_PORT_TBT_ALT);
111 }
112
intel_tc_port_in_dp_alt_mode(struct intel_digital_port * dig_port)113 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port)
114 {
115 return intel_tc_port_in_mode(dig_port, TC_PORT_DP_ALT);
116 }
117
intel_tc_port_in_legacy_mode(struct intel_digital_port * dig_port)118 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
119 {
120 return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY);
121 }
122
intel_tc_port_handles_hpd_glitches(struct intel_digital_port * dig_port)123 bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port)
124 {
125 struct intel_tc_port *tc = to_tc_port(dig_port);
126
127 return intel_encoder_is_tc(&dig_port->base) && !tc->legacy_port;
128 }
129
130 /*
131 * The display power domains used for TC ports depending on the
132 * platform and TC mode (legacy, DP-alt, TBT):
133 *
134 * POWER_DOMAIN_DISPLAY_CORE:
135 * --------------------------
136 * ADLP/all modes:
137 * - TCSS/IOM access for PHY ready state.
138 * ADLP+/all modes:
139 * - DE/north-,south-HPD ISR access for HPD live state.
140 *
141 * POWER_DOMAIN_PORT_DDI_LANES_<port>:
142 * -----------------------------------
143 * ICL+/all modes:
144 * - DE/DDI_BUF access for port enabled state.
145 * ADLP/all modes:
146 * - DE/DDI_BUF access for PHY owned state.
147 *
148 * POWER_DOMAIN_AUX_USBC<TC port index>:
149 * -------------------------------------
150 * ICL/legacy mode:
151 * - TCSS/IOM,FIA access for PHY ready, owned and HPD live state
152 * - TCSS/PHY: block TC-cold power state for using the PHY AUX and
153 * main lanes.
154 * ADLP/legacy, DP-alt modes:
155 * - TCSS/PHY: block TC-cold power state for using the PHY AUX and
156 * main lanes.
157 *
158 * POWER_DOMAIN_TC_COLD_OFF:
159 * -------------------------
160 * ICL/DP-alt, TBT mode:
161 * - TCSS/TBT: block TC-cold power state for using the (direct or
162 * TBT DP-IN) AUX and main lanes.
163 *
164 * TGL/all modes:
165 * - TCSS/IOM,FIA access for PHY ready, owned and HPD live state
166 * - TCSS/PHY: block TC-cold power state for using the (direct or
167 * TBT DP-IN) AUX and main lanes.
168 *
169 * ADLP/TBT mode:
170 * - TCSS/TBT: block TC-cold power state for using the (TBT DP-IN)
171 * AUX and main lanes.
172 *
173 * XELPDP+/all modes:
174 * - TCSS/IOM,FIA access for PHY ready, owned state
175 * - TCSS/PHY: block TC-cold power state for using the (direct or
176 * TBT DP-IN) AUX and main lanes.
177 */
intel_tc_cold_requires_aux_pw(struct intel_digital_port * dig_port)178 bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
179 {
180 struct intel_display *display = to_intel_display(dig_port);
181 struct intel_tc_port *tc = to_tc_port(dig_port);
182
183 return tc_phy_cold_off_domain(tc) ==
184 intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
185 }
186
187 static intel_wakeref_t
__tc_cold_block(struct intel_tc_port * tc,enum intel_display_power_domain * domain)188 __tc_cold_block(struct intel_tc_port *tc, enum intel_display_power_domain *domain)
189 {
190 struct intel_display *display = to_intel_display(tc->dig_port);
191
192 *domain = tc_phy_cold_off_domain(tc);
193
194 return intel_display_power_get(display, *domain);
195 }
196
197 static intel_wakeref_t
tc_cold_block(struct intel_tc_port * tc)198 tc_cold_block(struct intel_tc_port *tc)
199 {
200 enum intel_display_power_domain domain;
201 intel_wakeref_t wakeref;
202
203 wakeref = __tc_cold_block(tc, &domain);
204 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
205 tc->lock_power_domain = domain;
206 #endif
207 return wakeref;
208 }
209
210 static void
__tc_cold_unblock(struct intel_tc_port * tc,enum intel_display_power_domain domain,intel_wakeref_t wakeref)211 __tc_cold_unblock(struct intel_tc_port *tc, enum intel_display_power_domain domain,
212 intel_wakeref_t wakeref)
213 {
214 struct intel_display *display = to_intel_display(tc->dig_port);
215
216 intel_display_power_put(display, domain, wakeref);
217 }
218
219 static void
tc_cold_unblock(struct intel_tc_port * tc,intel_wakeref_t wakeref)220 tc_cold_unblock(struct intel_tc_port *tc, intel_wakeref_t wakeref)
221 {
222 enum intel_display_power_domain domain = tc_phy_cold_off_domain(tc);
223
224 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
225 drm_WARN_ON(&tc_to_i915(tc)->drm, tc->lock_power_domain != domain);
226 #endif
227 __tc_cold_unblock(tc, domain, wakeref);
228 }
229
230 static void
assert_display_core_power_enabled(struct intel_tc_port * tc)231 assert_display_core_power_enabled(struct intel_tc_port *tc)
232 {
233 struct intel_display *display = to_intel_display(tc->dig_port);
234
235 drm_WARN_ON(display->drm,
236 !intel_display_power_is_enabled(display, POWER_DOMAIN_DISPLAY_CORE));
237 }
238
239 static void
assert_tc_cold_blocked(struct intel_tc_port * tc)240 assert_tc_cold_blocked(struct intel_tc_port *tc)
241 {
242 struct intel_display *display = to_intel_display(tc->dig_port);
243 bool enabled;
244
245 enabled = intel_display_power_is_enabled(display,
246 tc_phy_cold_off_domain(tc));
247 drm_WARN_ON(display->drm, !enabled);
248 }
249
250 static enum intel_display_power_domain
tc_port_power_domain(struct intel_tc_port * tc)251 tc_port_power_domain(struct intel_tc_port *tc)
252 {
253 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
254
255 return POWER_DOMAIN_PORT_DDI_LANES_TC1 + tc_port - TC_PORT_1;
256 }
257
258 static void
assert_tc_port_power_enabled(struct intel_tc_port * tc)259 assert_tc_port_power_enabled(struct intel_tc_port *tc)
260 {
261 struct intel_display *display = to_intel_display(tc->dig_port);
262
263 drm_WARN_ON(display->drm,
264 !intel_display_power_is_enabled(display, tc_port_power_domain(tc)));
265 }
266
intel_tc_port_get_lane_mask(struct intel_digital_port * dig_port)267 static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
268 {
269 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
270 struct intel_tc_port *tc = to_tc_port(dig_port);
271 u32 lane_mask;
272
273 lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia));
274
275 drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
276 assert_tc_cold_blocked(tc);
277
278 lane_mask &= DP_LANE_ASSIGNMENT_MASK(tc->phy_fia_idx);
279 return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
280 }
281
intel_tc_port_get_pin_assignment_mask(struct intel_digital_port * dig_port)282 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
283 {
284 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
285 struct intel_tc_port *tc = to_tc_port(dig_port);
286 u32 pin_mask;
287
288 pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(tc->phy_fia));
289
290 drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
291 assert_tc_cold_blocked(tc);
292
293 return (pin_mask & DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx)) >>
294 DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
295 }
296
lnl_tc_port_get_max_lane_count(struct intel_digital_port * dig_port)297 static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
298 {
299 struct intel_display *display = to_intel_display(dig_port);
300 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
301 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
302 intel_wakeref_t wakeref;
303 u32 val, pin_assignment;
304
305 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
306 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
307
308 pin_assignment =
309 REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
310
311 switch (pin_assignment) {
312 default:
313 MISSING_CASE(pin_assignment);
314 fallthrough;
315 case DP_PIN_ASSIGNMENT_D:
316 return 2;
317 case DP_PIN_ASSIGNMENT_C:
318 case DP_PIN_ASSIGNMENT_E:
319 return 4;
320 }
321 }
322
mtl_tc_port_get_max_lane_count(struct intel_digital_port * dig_port)323 static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
324 {
325 struct intel_display *display = to_intel_display(dig_port);
326 intel_wakeref_t wakeref;
327 u32 pin_mask;
328
329 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
330 pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
331
332 switch (pin_mask) {
333 default:
334 MISSING_CASE(pin_mask);
335 fallthrough;
336 case DP_PIN_ASSIGNMENT_D:
337 return 2;
338 case DP_PIN_ASSIGNMENT_C:
339 case DP_PIN_ASSIGNMENT_E:
340 return 4;
341 }
342 }
343
intel_tc_port_get_max_lane_count(struct intel_digital_port * dig_port)344 static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
345 {
346 struct intel_display *display = to_intel_display(dig_port);
347 intel_wakeref_t wakeref;
348 u32 lane_mask = 0;
349
350 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
351 lane_mask = intel_tc_port_get_lane_mask(dig_port);
352
353 switch (lane_mask) {
354 default:
355 MISSING_CASE(lane_mask);
356 fallthrough;
357 case 0x1:
358 case 0x2:
359 case 0x4:
360 case 0x8:
361 return 1;
362 case 0x3:
363 case 0xc:
364 return 2;
365 case 0xf:
366 return 4;
367 }
368 }
369
intel_tc_port_max_lane_count(struct intel_digital_port * dig_port)370 int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
371 {
372 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
373 struct intel_tc_port *tc = to_tc_port(dig_port);
374
375 if (!intel_encoder_is_tc(&dig_port->base) || tc->mode != TC_PORT_DP_ALT)
376 return 4;
377
378 assert_tc_cold_blocked(tc);
379
380 if (DISPLAY_VER(i915) >= 20)
381 return lnl_tc_port_get_max_lane_count(dig_port);
382
383 if (DISPLAY_VER(i915) >= 14)
384 return mtl_tc_port_get_max_lane_count(dig_port);
385
386 return intel_tc_port_get_max_lane_count(dig_port);
387 }
388
intel_tc_port_set_fia_lane_count(struct intel_digital_port * dig_port,int required_lanes)389 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
390 int required_lanes)
391 {
392 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
393 struct intel_tc_port *tc = to_tc_port(dig_port);
394 bool lane_reversal = dig_port->lane_reversal;
395 u32 val;
396
397 if (DISPLAY_VER(i915) >= 14)
398 return;
399
400 drm_WARN_ON(&i915->drm,
401 lane_reversal && tc->mode != TC_PORT_LEGACY);
402
403 assert_tc_cold_blocked(tc);
404
405 val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(tc->phy_fia));
406 val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc->phy_fia_idx);
407
408 switch (required_lanes) {
409 case 1:
410 val |= lane_reversal ?
411 DFLEXDPMLE1_DPMLETC_ML3(tc->phy_fia_idx) :
412 DFLEXDPMLE1_DPMLETC_ML0(tc->phy_fia_idx);
413 break;
414 case 2:
415 val |= lane_reversal ?
416 DFLEXDPMLE1_DPMLETC_ML3_2(tc->phy_fia_idx) :
417 DFLEXDPMLE1_DPMLETC_ML1_0(tc->phy_fia_idx);
418 break;
419 case 4:
420 val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc->phy_fia_idx);
421 break;
422 default:
423 MISSING_CASE(required_lanes);
424 }
425
426 intel_de_write(i915, PORT_TX_DFLEXDPMLE1(tc->phy_fia), val);
427 }
428
tc_port_fixup_legacy_flag(struct intel_tc_port * tc,u32 live_status_mask)429 static void tc_port_fixup_legacy_flag(struct intel_tc_port *tc,
430 u32 live_status_mask)
431 {
432 struct drm_i915_private *i915 = tc_to_i915(tc);
433 u32 valid_hpd_mask;
434
435 drm_WARN_ON(&i915->drm, tc->mode != TC_PORT_DISCONNECTED);
436
437 if (hweight32(live_status_mask) != 1)
438 return;
439
440 if (tc->legacy_port)
441 valid_hpd_mask = BIT(TC_PORT_LEGACY);
442 else
443 valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
444 BIT(TC_PORT_TBT_ALT);
445
446 if (!(live_status_mask & ~valid_hpd_mask))
447 return;
448
449 /* If live status mismatches the VBT flag, trust the live status. */
450 drm_dbg_kms(&i915->drm,
451 "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n",
452 tc->port_name, live_status_mask, valid_hpd_mask);
453
454 tc->legacy_port = !tc->legacy_port;
455 }
456
tc_phy_load_fia_params(struct intel_tc_port * tc,bool modular_fia)457 static void tc_phy_load_fia_params(struct intel_tc_port *tc, bool modular_fia)
458 {
459 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
460
461 /*
462 * Each Modular FIA instance houses 2 TC ports. In SOC that has more
463 * than two TC ports, there are multiple instances of Modular FIA.
464 */
465 if (modular_fia) {
466 tc->phy_fia = tc_port / 2;
467 tc->phy_fia_idx = tc_port % 2;
468 } else {
469 tc->phy_fia = FIA1;
470 tc->phy_fia_idx = tc_port;
471 }
472 }
473
474 /*
475 * ICL TC PHY handlers
476 * -------------------
477 */
478 static enum intel_display_power_domain
icl_tc_phy_cold_off_domain(struct intel_tc_port * tc)479 icl_tc_phy_cold_off_domain(struct intel_tc_port *tc)
480 {
481 struct intel_display *display = to_intel_display(tc->dig_port);
482 struct intel_digital_port *dig_port = tc->dig_port;
483
484 if (tc->legacy_port)
485 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
486
487 return POWER_DOMAIN_TC_COLD_OFF;
488 }
489
icl_tc_phy_hpd_live_status(struct intel_tc_port * tc)490 static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc)
491 {
492 struct intel_display *display = to_intel_display(tc->dig_port);
493 struct drm_i915_private *i915 = tc_to_i915(tc);
494 struct intel_digital_port *dig_port = tc->dig_port;
495 u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
496 intel_wakeref_t wakeref;
497 u32 fia_isr;
498 u32 pch_isr;
499 u32 mask = 0;
500
501 with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) {
502 fia_isr = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia));
503 pch_isr = intel_de_read(i915, SDEISR);
504 }
505
506 if (fia_isr == 0xffffffff) {
507 drm_dbg_kms(&i915->drm,
508 "Port %s: PHY in TCCOLD, nothing connected\n",
509 tc->port_name);
510 return mask;
511 }
512
513 if (fia_isr & TC_LIVE_STATE_TBT(tc->phy_fia_idx))
514 mask |= BIT(TC_PORT_TBT_ALT);
515 if (fia_isr & TC_LIVE_STATE_TC(tc->phy_fia_idx))
516 mask |= BIT(TC_PORT_DP_ALT);
517
518 if (pch_isr & isr_bit)
519 mask |= BIT(TC_PORT_LEGACY);
520
521 return mask;
522 }
523
524 /*
525 * Return the PHY status complete flag indicating that display can acquire the
526 * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink
527 * is connected and it's ready to switch the ownership to display. The flag
528 * will be left cleared when a TBT-alt sink is connected, where the PHY is
529 * owned by the TBT subsystem and so switching the ownership to display is not
530 * required.
531 */
icl_tc_phy_is_ready(struct intel_tc_port * tc)532 static bool icl_tc_phy_is_ready(struct intel_tc_port *tc)
533 {
534 struct drm_i915_private *i915 = tc_to_i915(tc);
535 u32 val;
536
537 assert_tc_cold_blocked(tc);
538
539 val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(tc->phy_fia));
540 if (val == 0xffffffff) {
541 drm_dbg_kms(&i915->drm,
542 "Port %s: PHY in TCCOLD, assuming not ready\n",
543 tc->port_name);
544 return false;
545 }
546
547 return val & DP_PHY_MODE_STATUS_COMPLETED(tc->phy_fia_idx);
548 }
549
icl_tc_phy_take_ownership(struct intel_tc_port * tc,bool take)550 static bool icl_tc_phy_take_ownership(struct intel_tc_port *tc,
551 bool take)
552 {
553 struct drm_i915_private *i915 = tc_to_i915(tc);
554 u32 val;
555
556 assert_tc_cold_blocked(tc);
557
558 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
559 if (val == 0xffffffff) {
560 drm_dbg_kms(&i915->drm,
561 "Port %s: PHY in TCCOLD, can't %s ownership\n",
562 tc->port_name, take ? "take" : "release");
563
564 return false;
565 }
566
567 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);
568 if (take)
569 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);
570
571 intel_de_write(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia), val);
572
573 return true;
574 }
575
icl_tc_phy_is_owned(struct intel_tc_port * tc)576 static bool icl_tc_phy_is_owned(struct intel_tc_port *tc)
577 {
578 struct drm_i915_private *i915 = tc_to_i915(tc);
579 u32 val;
580
581 assert_tc_cold_blocked(tc);
582
583 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia));
584 if (val == 0xffffffff) {
585 drm_dbg_kms(&i915->drm,
586 "Port %s: PHY in TCCOLD, assume not owned\n",
587 tc->port_name);
588 return false;
589 }
590
591 return val & DP_PHY_MODE_STATUS_NOT_SAFE(tc->phy_fia_idx);
592 }
593
icl_tc_phy_get_hw_state(struct intel_tc_port * tc)594 static void icl_tc_phy_get_hw_state(struct intel_tc_port *tc)
595 {
596 enum intel_display_power_domain domain;
597 intel_wakeref_t tc_cold_wref;
598
599 tc_cold_wref = __tc_cold_block(tc, &domain);
600
601 tc->mode = tc_phy_get_current_mode(tc);
602 if (tc->mode != TC_PORT_DISCONNECTED)
603 tc->lock_wakeref = tc_cold_block(tc);
604
605 __tc_cold_unblock(tc, domain, tc_cold_wref);
606 }
607
608 /*
609 * This function implements the first part of the Connect Flow described by our
610 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
611 * lanes, EDID, etc) is done as needed in the typical places.
612 *
613 * Unlike the other ports, type-C ports are not available to use as soon as we
614 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
615 * display, USB, etc. As a result, handshaking through FIA is required around
616 * connect and disconnect to cleanly transfer ownership with the controller and
617 * set the type-C power state.
618 */
tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port * tc,int required_lanes)619 static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port *tc,
620 int required_lanes)
621 {
622 struct drm_i915_private *i915 = tc_to_i915(tc);
623 struct intel_digital_port *dig_port = tc->dig_port;
624 int max_lanes;
625
626 max_lanes = intel_tc_port_max_lane_count(dig_port);
627 if (tc->mode == TC_PORT_LEGACY) {
628 drm_WARN_ON(&i915->drm, max_lanes != 4);
629 return true;
630 }
631
632 drm_WARN_ON(&i915->drm, tc->mode != TC_PORT_DP_ALT);
633
634 /*
635 * Now we have to re-check the live state, in case the port recently
636 * became disconnected. Not necessary for legacy mode.
637 */
638 if (!(tc_phy_hpd_live_status(tc) & BIT(TC_PORT_DP_ALT))) {
639 drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
640 tc->port_name);
641 return false;
642 }
643
644 if (max_lanes < required_lanes) {
645 drm_dbg_kms(&i915->drm,
646 "Port %s: PHY max lanes %d < required lanes %d\n",
647 tc->port_name,
648 max_lanes, required_lanes);
649 return false;
650 }
651
652 return true;
653 }
654
icl_tc_phy_connect(struct intel_tc_port * tc,int required_lanes)655 static bool icl_tc_phy_connect(struct intel_tc_port *tc,
656 int required_lanes)
657 {
658 struct drm_i915_private *i915 = tc_to_i915(tc);
659
660 tc->lock_wakeref = tc_cold_block(tc);
661
662 if (tc->mode == TC_PORT_TBT_ALT)
663 return true;
664
665 if ((!tc_phy_is_ready(tc) ||
666 !icl_tc_phy_take_ownership(tc, true)) &&
667 !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
668 drm_dbg_kms(&i915->drm, "Port %s: can't take PHY ownership (ready %s)\n",
669 tc->port_name,
670 str_yes_no(tc_phy_is_ready(tc)));
671 goto out_unblock_tc_cold;
672 }
673
674
675 if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
676 goto out_release_phy;
677
678 return true;
679
680 out_release_phy:
681 icl_tc_phy_take_ownership(tc, false);
682 out_unblock_tc_cold:
683 tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
684
685 return false;
686 }
687
688 /*
689 * See the comment at the connect function. This implements the Disconnect
690 * Flow.
691 */
icl_tc_phy_disconnect(struct intel_tc_port * tc)692 static void icl_tc_phy_disconnect(struct intel_tc_port *tc)
693 {
694 switch (tc->mode) {
695 case TC_PORT_LEGACY:
696 case TC_PORT_DP_ALT:
697 icl_tc_phy_take_ownership(tc, false);
698 fallthrough;
699 case TC_PORT_TBT_ALT:
700 tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
701 break;
702 default:
703 MISSING_CASE(tc->mode);
704 }
705 }
706
icl_tc_phy_init(struct intel_tc_port * tc)707 static void icl_tc_phy_init(struct intel_tc_port *tc)
708 {
709 tc_phy_load_fia_params(tc, false);
710 }
711
712 static const struct intel_tc_phy_ops icl_tc_phy_ops = {
713 .cold_off_domain = icl_tc_phy_cold_off_domain,
714 .hpd_live_status = icl_tc_phy_hpd_live_status,
715 .is_ready = icl_tc_phy_is_ready,
716 .is_owned = icl_tc_phy_is_owned,
717 .get_hw_state = icl_tc_phy_get_hw_state,
718 .connect = icl_tc_phy_connect,
719 .disconnect = icl_tc_phy_disconnect,
720 .init = icl_tc_phy_init,
721 };
722
723 /*
724 * TGL TC PHY handlers
725 * -------------------
726 */
727 static enum intel_display_power_domain
tgl_tc_phy_cold_off_domain(struct intel_tc_port * tc)728 tgl_tc_phy_cold_off_domain(struct intel_tc_port *tc)
729 {
730 return POWER_DOMAIN_TC_COLD_OFF;
731 }
732
tgl_tc_phy_init(struct intel_tc_port * tc)733 static void tgl_tc_phy_init(struct intel_tc_port *tc)
734 {
735 struct intel_display *display = to_intel_display(tc->dig_port);
736 struct drm_i915_private *i915 = tc_to_i915(tc);
737 intel_wakeref_t wakeref;
738 u32 val;
739
740 with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref)
741 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1));
742
743 drm_WARN_ON(&i915->drm, val == 0xffffffff);
744
745 tc_phy_load_fia_params(tc, val & MODULAR_FIA_MASK);
746 }
747
748 static const struct intel_tc_phy_ops tgl_tc_phy_ops = {
749 .cold_off_domain = tgl_tc_phy_cold_off_domain,
750 .hpd_live_status = icl_tc_phy_hpd_live_status,
751 .is_ready = icl_tc_phy_is_ready,
752 .is_owned = icl_tc_phy_is_owned,
753 .get_hw_state = icl_tc_phy_get_hw_state,
754 .connect = icl_tc_phy_connect,
755 .disconnect = icl_tc_phy_disconnect,
756 .init = tgl_tc_phy_init,
757 };
758
759 /*
760 * ADLP TC PHY handlers
761 * --------------------
762 */
763 static enum intel_display_power_domain
adlp_tc_phy_cold_off_domain(struct intel_tc_port * tc)764 adlp_tc_phy_cold_off_domain(struct intel_tc_port *tc)
765 {
766 struct intel_display *display = to_intel_display(tc->dig_port);
767 struct intel_digital_port *dig_port = tc->dig_port;
768
769 if (tc->mode != TC_PORT_TBT_ALT)
770 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch);
771
772 return POWER_DOMAIN_TC_COLD_OFF;
773 }
774
adlp_tc_phy_hpd_live_status(struct intel_tc_port * tc)775 static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc)
776 {
777 struct intel_display *display = to_intel_display(tc->dig_port);
778 struct drm_i915_private *i915 = tc_to_i915(tc);
779 struct intel_digital_port *dig_port = tc->dig_port;
780 enum hpd_pin hpd_pin = dig_port->base.hpd_pin;
781 u32 cpu_isr_bits = i915->display.hotplug.hpd[hpd_pin];
782 u32 pch_isr_bit = i915->display.hotplug.pch_hpd[hpd_pin];
783 intel_wakeref_t wakeref;
784 u32 cpu_isr;
785 u32 pch_isr;
786 u32 mask = 0;
787
788 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
789 cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR);
790 pch_isr = intel_de_read(i915, SDEISR);
791 }
792
793 if (cpu_isr & (cpu_isr_bits & GEN11_DE_TC_HOTPLUG_MASK))
794 mask |= BIT(TC_PORT_DP_ALT);
795 if (cpu_isr & (cpu_isr_bits & GEN11_DE_TBT_HOTPLUG_MASK))
796 mask |= BIT(TC_PORT_TBT_ALT);
797
798 if (pch_isr & pch_isr_bit)
799 mask |= BIT(TC_PORT_LEGACY);
800
801 return mask;
802 }
803
804 /*
805 * Return the PHY status complete flag indicating that display can acquire the
806 * PHY ownership. The IOM firmware sets this flag when it's ready to switch
807 * the ownership to display, regardless of what sink is connected (TBT-alt,
808 * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT
809 * subsystem and so switching the ownership to display is not required.
810 */
adlp_tc_phy_is_ready(struct intel_tc_port * tc)811 static bool adlp_tc_phy_is_ready(struct intel_tc_port *tc)
812 {
813 struct drm_i915_private *i915 = tc_to_i915(tc);
814 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base);
815 u32 val;
816
817 assert_display_core_power_enabled(tc);
818
819 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
820 if (val == 0xffffffff) {
821 drm_dbg_kms(&i915->drm,
822 "Port %s: PHY in TCCOLD, assuming not ready\n",
823 tc->port_name);
824 return false;
825 }
826
827 return val & TCSS_DDI_STATUS_READY;
828 }
829
adlp_tc_phy_take_ownership(struct intel_tc_port * tc,bool take)830 static bool adlp_tc_phy_take_ownership(struct intel_tc_port *tc,
831 bool take)
832 {
833 struct drm_i915_private *i915 = tc_to_i915(tc);
834 enum port port = tc->dig_port->base.port;
835
836 assert_tc_port_power_enabled(tc);
837
838 intel_de_rmw(i915, DDI_BUF_CTL(port), DDI_BUF_CTL_TC_PHY_OWNERSHIP,
839 take ? DDI_BUF_CTL_TC_PHY_OWNERSHIP : 0);
840
841 return true;
842 }
843
adlp_tc_phy_is_owned(struct intel_tc_port * tc)844 static bool adlp_tc_phy_is_owned(struct intel_tc_port *tc)
845 {
846 struct drm_i915_private *i915 = tc_to_i915(tc);
847 enum port port = tc->dig_port->base.port;
848 u32 val;
849
850 assert_tc_port_power_enabled(tc);
851
852 val = intel_de_read(i915, DDI_BUF_CTL(port));
853 return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
854 }
855
adlp_tc_phy_get_hw_state(struct intel_tc_port * tc)856 static void adlp_tc_phy_get_hw_state(struct intel_tc_port *tc)
857 {
858 struct intel_display *display = to_intel_display(tc->dig_port);
859 enum intel_display_power_domain port_power_domain =
860 tc_port_power_domain(tc);
861 intel_wakeref_t port_wakeref;
862
863 port_wakeref = intel_display_power_get(display, port_power_domain);
864
865 tc->mode = tc_phy_get_current_mode(tc);
866 if (tc->mode != TC_PORT_DISCONNECTED)
867 tc->lock_wakeref = tc_cold_block(tc);
868
869 intel_display_power_put(display, port_power_domain, port_wakeref);
870 }
871
adlp_tc_phy_connect(struct intel_tc_port * tc,int required_lanes)872 static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
873 {
874 struct intel_display *display = to_intel_display(tc->dig_port);
875 struct drm_i915_private *i915 = tc_to_i915(tc);
876 enum intel_display_power_domain port_power_domain =
877 tc_port_power_domain(tc);
878 intel_wakeref_t port_wakeref;
879
880 if (tc->mode == TC_PORT_TBT_ALT) {
881 tc->lock_wakeref = tc_cold_block(tc);
882 return true;
883 }
884
885 port_wakeref = intel_display_power_get(display, port_power_domain);
886
887 if (!adlp_tc_phy_take_ownership(tc, true) &&
888 !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
889 drm_dbg_kms(&i915->drm, "Port %s: can't take PHY ownership\n",
890 tc->port_name);
891 goto out_put_port_power;
892 }
893
894 if (!tc_phy_is_ready(tc) &&
895 !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
896 drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
897 tc->port_name);
898 goto out_release_phy;
899 }
900
901 tc->lock_wakeref = tc_cold_block(tc);
902
903 if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
904 goto out_unblock_tc_cold;
905
906 intel_display_power_put(display, port_power_domain, port_wakeref);
907
908 return true;
909
910 out_unblock_tc_cold:
911 tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
912 out_release_phy:
913 adlp_tc_phy_take_ownership(tc, false);
914 out_put_port_power:
915 intel_display_power_put(display, port_power_domain, port_wakeref);
916
917 return false;
918 }
919
adlp_tc_phy_disconnect(struct intel_tc_port * tc)920 static void adlp_tc_phy_disconnect(struct intel_tc_port *tc)
921 {
922 struct intel_display *display = to_intel_display(tc->dig_port);
923 enum intel_display_power_domain port_power_domain =
924 tc_port_power_domain(tc);
925 intel_wakeref_t port_wakeref;
926
927 port_wakeref = intel_display_power_get(display, port_power_domain);
928
929 tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
930
931 switch (tc->mode) {
932 case TC_PORT_LEGACY:
933 case TC_PORT_DP_ALT:
934 adlp_tc_phy_take_ownership(tc, false);
935 fallthrough;
936 case TC_PORT_TBT_ALT:
937 break;
938 default:
939 MISSING_CASE(tc->mode);
940 }
941
942 intel_display_power_put(display, port_power_domain, port_wakeref);
943 }
944
adlp_tc_phy_init(struct intel_tc_port * tc)945 static void adlp_tc_phy_init(struct intel_tc_port *tc)
946 {
947 tc_phy_load_fia_params(tc, true);
948 }
949
950 static const struct intel_tc_phy_ops adlp_tc_phy_ops = {
951 .cold_off_domain = adlp_tc_phy_cold_off_domain,
952 .hpd_live_status = adlp_tc_phy_hpd_live_status,
953 .is_ready = adlp_tc_phy_is_ready,
954 .is_owned = adlp_tc_phy_is_owned,
955 .get_hw_state = adlp_tc_phy_get_hw_state,
956 .connect = adlp_tc_phy_connect,
957 .disconnect = adlp_tc_phy_disconnect,
958 .init = adlp_tc_phy_init,
959 };
960
961 /*
962 * XELPDP TC PHY handlers
963 * ----------------------
964 */
xelpdp_tc_phy_hpd_live_status(struct intel_tc_port * tc)965 static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc)
966 {
967 struct intel_display *display = to_intel_display(tc->dig_port);
968 struct drm_i915_private *i915 = tc_to_i915(tc);
969 struct intel_digital_port *dig_port = tc->dig_port;
970 enum hpd_pin hpd_pin = dig_port->base.hpd_pin;
971 u32 pica_isr_bits = i915->display.hotplug.hpd[hpd_pin];
972 u32 pch_isr_bit = i915->display.hotplug.pch_hpd[hpd_pin];
973 intel_wakeref_t wakeref;
974 u32 pica_isr;
975 u32 pch_isr;
976 u32 mask = 0;
977
978 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
979 pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR);
980 pch_isr = intel_de_read(i915, SDEISR);
981 }
982
983 if (pica_isr & (pica_isr_bits & XELPDP_DP_ALT_HOTPLUG_MASK))
984 mask |= BIT(TC_PORT_DP_ALT);
985 if (pica_isr & (pica_isr_bits & XELPDP_TBT_HOTPLUG_MASK))
986 mask |= BIT(TC_PORT_TBT_ALT);
987
988 if (tc->legacy_port && (pch_isr & pch_isr_bit))
989 mask |= BIT(TC_PORT_LEGACY);
990
991 return mask;
992 }
993
994 static bool
xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port * tc)995 xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
996 {
997 struct drm_i915_private *i915 = tc_to_i915(tc);
998 enum port port = tc->dig_port->base.port;
999 i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
1000
1001 assert_tc_cold_blocked(tc);
1002
1003 return intel_de_read(i915, reg) & XELPDP_TCSS_POWER_STATE;
1004 }
1005
1006 static bool
xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port * tc,bool enabled)1007 xelpdp_tc_phy_wait_for_tcss_power(struct intel_tc_port *tc, bool enabled)
1008 {
1009 struct drm_i915_private *i915 = tc_to_i915(tc);
1010
1011 if (wait_for(xelpdp_tc_phy_tcss_power_is_enabled(tc) == enabled, 5)) {
1012 drm_dbg_kms(&i915->drm,
1013 "Port %s: timeout waiting for TCSS power to get %s\n",
1014 str_enabled_disabled(enabled),
1015 tc->port_name);
1016 return false;
1017 }
1018
1019 return true;
1020 }
1021
1022 /*
1023 * Gfx driver WA 14020908590 for PTL tcss_rxdetect_clkswb_req/ack
1024 * handshake violation when pwwreq= 0->1 during TC7/10 entry
1025 */
xelpdp_tc_power_request_wa(struct intel_display * display,bool enable)1026 static void xelpdp_tc_power_request_wa(struct intel_display *display, bool enable)
1027 {
1028 /* check if mailbox is running busy */
1029 if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
1030 TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
1031 drm_dbg_kms(display->drm,
1032 "Timeout waiting for TCSS mailbox run/busy bit to clear\n");
1033 return;
1034 }
1035
1036 intel_de_write(display, TCSS_DISP_MAILBOX_IN_DATA, enable ? 1 : 0);
1037 intel_de_write(display, TCSS_DISP_MAILBOX_IN_CMD,
1038 TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY |
1039 TCSS_DISP_MAILBOX_IN_CMD_DATA(0x1));
1040
1041 /* wait to clear mailbox running busy bit before continuing */
1042 if (intel_de_wait_for_clear(display, TCSS_DISP_MAILBOX_IN_CMD,
1043 TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY, 10)) {
1044 drm_dbg_kms(display->drm,
1045 "Timeout after writing data to mailbox. Mailbox run/busy bit did not clear\n");
1046 return;
1047 }
1048 }
1049
__xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port * tc,bool enable)1050 static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
1051 {
1052 struct intel_display *display = to_intel_display(tc->dig_port);
1053 enum port port = tc->dig_port->base.port;
1054 i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port);
1055 u32 val;
1056
1057 assert_tc_cold_blocked(tc);
1058
1059 if (DISPLAY_VER(display) == 30)
1060 xelpdp_tc_power_request_wa(display, enable);
1061
1062 val = intel_de_read(display, reg);
1063 if (enable)
1064 val |= XELPDP_TCSS_POWER_REQUEST;
1065 else
1066 val &= ~XELPDP_TCSS_POWER_REQUEST;
1067 intel_de_write(display, reg, val);
1068 }
1069
xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port * tc,bool enable)1070 static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
1071 {
1072 struct drm_i915_private *i915 = tc_to_i915(tc);
1073
1074 __xelpdp_tc_phy_enable_tcss_power(tc, enable);
1075
1076 if (enable && !tc_phy_wait_for_ready(tc))
1077 goto out_disable;
1078
1079 if (!xelpdp_tc_phy_wait_for_tcss_power(tc, enable))
1080 goto out_disable;
1081
1082 return true;
1083
1084 out_disable:
1085 if (drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY))
1086 return false;
1087
1088 if (!enable)
1089 return false;
1090
1091 __xelpdp_tc_phy_enable_tcss_power(tc, false);
1092 xelpdp_tc_phy_wait_for_tcss_power(tc, false);
1093
1094 return false;
1095 }
1096
xelpdp_tc_phy_take_ownership(struct intel_tc_port * tc,bool take)1097 static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
1098 {
1099 struct drm_i915_private *i915 = tc_to_i915(tc);
1100 enum port port = tc->dig_port->base.port;
1101 i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
1102 u32 val;
1103
1104 assert_tc_cold_blocked(tc);
1105
1106 val = intel_de_read(i915, reg);
1107 if (take)
1108 val |= XELPDP_TC_PHY_OWNERSHIP;
1109 else
1110 val &= ~XELPDP_TC_PHY_OWNERSHIP;
1111 intel_de_write(i915, reg, val);
1112 }
1113
xelpdp_tc_phy_is_owned(struct intel_tc_port * tc)1114 static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
1115 {
1116 struct drm_i915_private *i915 = tc_to_i915(tc);
1117 enum port port = tc->dig_port->base.port;
1118 i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
1119
1120 assert_tc_cold_blocked(tc);
1121
1122 return intel_de_read(i915, reg) & XELPDP_TC_PHY_OWNERSHIP;
1123 }
1124
xelpdp_tc_phy_get_hw_state(struct intel_tc_port * tc)1125 static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
1126 {
1127 struct drm_i915_private *i915 = tc_to_i915(tc);
1128 intel_wakeref_t tc_cold_wref;
1129 enum intel_display_power_domain domain;
1130
1131 tc_cold_wref = __tc_cold_block(tc, &domain);
1132
1133 tc->mode = tc_phy_get_current_mode(tc);
1134 if (tc->mode != TC_PORT_DISCONNECTED)
1135 tc->lock_wakeref = tc_cold_block(tc);
1136
1137 drm_WARN_ON(&i915->drm,
1138 (tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) &&
1139 !xelpdp_tc_phy_tcss_power_is_enabled(tc));
1140
1141 __tc_cold_unblock(tc, domain, tc_cold_wref);
1142 }
1143
xelpdp_tc_phy_connect(struct intel_tc_port * tc,int required_lanes)1144 static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
1145 {
1146 tc->lock_wakeref = tc_cold_block(tc);
1147
1148 if (tc->mode == TC_PORT_TBT_ALT)
1149 return true;
1150
1151 if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
1152 goto out_unblock_tccold;
1153
1154 xelpdp_tc_phy_take_ownership(tc, true);
1155
1156 if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
1157 goto out_release_phy;
1158
1159 return true;
1160
1161 out_release_phy:
1162 xelpdp_tc_phy_take_ownership(tc, false);
1163 xelpdp_tc_phy_wait_for_tcss_power(tc, false);
1164
1165 out_unblock_tccold:
1166 tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
1167
1168 return false;
1169 }
1170
xelpdp_tc_phy_disconnect(struct intel_tc_port * tc)1171 static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
1172 {
1173 switch (tc->mode) {
1174 case TC_PORT_LEGACY:
1175 case TC_PORT_DP_ALT:
1176 xelpdp_tc_phy_take_ownership(tc, false);
1177 xelpdp_tc_phy_enable_tcss_power(tc, false);
1178 fallthrough;
1179 case TC_PORT_TBT_ALT:
1180 tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
1181 break;
1182 default:
1183 MISSING_CASE(tc->mode);
1184 }
1185 }
1186
1187 static const struct intel_tc_phy_ops xelpdp_tc_phy_ops = {
1188 .cold_off_domain = tgl_tc_phy_cold_off_domain,
1189 .hpd_live_status = xelpdp_tc_phy_hpd_live_status,
1190 .is_ready = adlp_tc_phy_is_ready,
1191 .is_owned = xelpdp_tc_phy_is_owned,
1192 .get_hw_state = xelpdp_tc_phy_get_hw_state,
1193 .connect = xelpdp_tc_phy_connect,
1194 .disconnect = xelpdp_tc_phy_disconnect,
1195 .init = adlp_tc_phy_init,
1196 };
1197
1198 /*
1199 * Generic TC PHY handlers
1200 * -----------------------
1201 */
1202 static enum intel_display_power_domain
tc_phy_cold_off_domain(struct intel_tc_port * tc)1203 tc_phy_cold_off_domain(struct intel_tc_port *tc)
1204 {
1205 return tc->phy_ops->cold_off_domain(tc);
1206 }
1207
tc_phy_hpd_live_status(struct intel_tc_port * tc)1208 static u32 tc_phy_hpd_live_status(struct intel_tc_port *tc)
1209 {
1210 struct drm_i915_private *i915 = tc_to_i915(tc);
1211 u32 mask;
1212
1213 mask = tc->phy_ops->hpd_live_status(tc);
1214
1215 /* The sink can be connected only in a single mode. */
1216 drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1);
1217
1218 return mask;
1219 }
1220
tc_phy_is_ready(struct intel_tc_port * tc)1221 static bool tc_phy_is_ready(struct intel_tc_port *tc)
1222 {
1223 return tc->phy_ops->is_ready(tc);
1224 }
1225
tc_phy_is_owned(struct intel_tc_port * tc)1226 static bool tc_phy_is_owned(struct intel_tc_port *tc)
1227 {
1228 return tc->phy_ops->is_owned(tc);
1229 }
1230
tc_phy_get_hw_state(struct intel_tc_port * tc)1231 static void tc_phy_get_hw_state(struct intel_tc_port *tc)
1232 {
1233 tc->phy_ops->get_hw_state(tc);
1234 }
1235
tc_phy_is_ready_and_owned(struct intel_tc_port * tc,bool phy_is_ready,bool phy_is_owned)1236 static bool tc_phy_is_ready_and_owned(struct intel_tc_port *tc,
1237 bool phy_is_ready, bool phy_is_owned)
1238 {
1239 struct drm_i915_private *i915 = tc_to_i915(tc);
1240
1241 drm_WARN_ON(&i915->drm, phy_is_owned && !phy_is_ready);
1242
1243 return phy_is_ready && phy_is_owned;
1244 }
1245
tc_phy_is_connected(struct intel_tc_port * tc,enum icl_port_dpll_id port_pll_type)1246 static bool tc_phy_is_connected(struct intel_tc_port *tc,
1247 enum icl_port_dpll_id port_pll_type)
1248 {
1249 struct intel_encoder *encoder = &tc->dig_port->base;
1250 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1251 bool phy_is_ready = tc_phy_is_ready(tc);
1252 bool phy_is_owned = tc_phy_is_owned(tc);
1253 bool is_connected;
1254
1255 if (tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned))
1256 is_connected = port_pll_type == ICL_PORT_DPLL_MG_PHY;
1257 else
1258 is_connected = port_pll_type == ICL_PORT_DPLL_DEFAULT;
1259
1260 drm_dbg_kms(&i915->drm,
1261 "Port %s: PHY connected: %s (ready: %s, owned: %s, pll_type: %s)\n",
1262 tc->port_name,
1263 str_yes_no(is_connected),
1264 str_yes_no(phy_is_ready),
1265 str_yes_no(phy_is_owned),
1266 port_pll_type == ICL_PORT_DPLL_DEFAULT ? "tbt" : "non-tbt");
1267
1268 return is_connected;
1269 }
1270
tc_phy_wait_for_ready(struct intel_tc_port * tc)1271 static bool tc_phy_wait_for_ready(struct intel_tc_port *tc)
1272 {
1273 struct drm_i915_private *i915 = tc_to_i915(tc);
1274
1275 if (wait_for(tc_phy_is_ready(tc), 500)) {
1276 drm_err(&i915->drm, "Port %s: timeout waiting for PHY ready\n",
1277 tc->port_name);
1278
1279 return false;
1280 }
1281
1282 return true;
1283 }
1284
1285 static enum tc_port_mode
hpd_mask_to_tc_mode(u32 live_status_mask)1286 hpd_mask_to_tc_mode(u32 live_status_mask)
1287 {
1288 if (live_status_mask)
1289 return fls(live_status_mask) - 1;
1290
1291 return TC_PORT_DISCONNECTED;
1292 }
1293
1294 static enum tc_port_mode
tc_phy_hpd_live_mode(struct intel_tc_port * tc)1295 tc_phy_hpd_live_mode(struct intel_tc_port *tc)
1296 {
1297 u32 live_status_mask = tc_phy_hpd_live_status(tc);
1298
1299 return hpd_mask_to_tc_mode(live_status_mask);
1300 }
1301
1302 static enum tc_port_mode
get_tc_mode_in_phy_owned_state(struct intel_tc_port * tc,enum tc_port_mode live_mode)1303 get_tc_mode_in_phy_owned_state(struct intel_tc_port *tc,
1304 enum tc_port_mode live_mode)
1305 {
1306 switch (live_mode) {
1307 case TC_PORT_LEGACY:
1308 case TC_PORT_DP_ALT:
1309 return live_mode;
1310 default:
1311 MISSING_CASE(live_mode);
1312 fallthrough;
1313 case TC_PORT_TBT_ALT:
1314 case TC_PORT_DISCONNECTED:
1315 if (tc->legacy_port)
1316 return TC_PORT_LEGACY;
1317 else
1318 return TC_PORT_DP_ALT;
1319 }
1320 }
1321
1322 static enum tc_port_mode
get_tc_mode_in_phy_not_owned_state(struct intel_tc_port * tc,enum tc_port_mode live_mode)1323 get_tc_mode_in_phy_not_owned_state(struct intel_tc_port *tc,
1324 enum tc_port_mode live_mode)
1325 {
1326 switch (live_mode) {
1327 case TC_PORT_LEGACY:
1328 return TC_PORT_DISCONNECTED;
1329 case TC_PORT_DP_ALT:
1330 case TC_PORT_TBT_ALT:
1331 return TC_PORT_TBT_ALT;
1332 default:
1333 MISSING_CASE(live_mode);
1334 fallthrough;
1335 case TC_PORT_DISCONNECTED:
1336 if (tc->legacy_port)
1337 return TC_PORT_DISCONNECTED;
1338 else
1339 return TC_PORT_TBT_ALT;
1340 }
1341 }
1342
1343 static enum tc_port_mode
tc_phy_get_current_mode(struct intel_tc_port * tc)1344 tc_phy_get_current_mode(struct intel_tc_port *tc)
1345 {
1346 struct drm_i915_private *i915 = tc_to_i915(tc);
1347 enum tc_port_mode live_mode = tc_phy_hpd_live_mode(tc);
1348 bool phy_is_ready;
1349 bool phy_is_owned;
1350 enum tc_port_mode mode;
1351
1352 /*
1353 * For legacy ports the IOM firmware initializes the PHY during boot-up
1354 * and system resume whether or not a sink is connected. Wait here for
1355 * the initialization to get ready.
1356 */
1357 if (tc->legacy_port)
1358 tc_phy_wait_for_ready(tc);
1359
1360 phy_is_ready = tc_phy_is_ready(tc);
1361 phy_is_owned = tc_phy_is_owned(tc);
1362
1363 if (!tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned)) {
1364 mode = get_tc_mode_in_phy_not_owned_state(tc, live_mode);
1365 } else {
1366 drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT);
1367 mode = get_tc_mode_in_phy_owned_state(tc, live_mode);
1368 }
1369
1370 drm_dbg_kms(&i915->drm,
1371 "Port %s: PHY mode: %s (ready: %s, owned: %s, HPD: %s)\n",
1372 tc->port_name,
1373 tc_port_mode_name(mode),
1374 str_yes_no(phy_is_ready),
1375 str_yes_no(phy_is_owned),
1376 tc_port_mode_name(live_mode));
1377
1378 return mode;
1379 }
1380
default_tc_mode(struct intel_tc_port * tc)1381 static enum tc_port_mode default_tc_mode(struct intel_tc_port *tc)
1382 {
1383 if (tc->legacy_port)
1384 return TC_PORT_LEGACY;
1385
1386 return TC_PORT_TBT_ALT;
1387 }
1388
1389 static enum tc_port_mode
hpd_mask_to_target_mode(struct intel_tc_port * tc,u32 live_status_mask)1390 hpd_mask_to_target_mode(struct intel_tc_port *tc, u32 live_status_mask)
1391 {
1392 enum tc_port_mode mode = hpd_mask_to_tc_mode(live_status_mask);
1393
1394 if (mode != TC_PORT_DISCONNECTED)
1395 return mode;
1396
1397 return default_tc_mode(tc);
1398 }
1399
1400 static enum tc_port_mode
tc_phy_get_target_mode(struct intel_tc_port * tc)1401 tc_phy_get_target_mode(struct intel_tc_port *tc)
1402 {
1403 u32 live_status_mask = tc_phy_hpd_live_status(tc);
1404
1405 return hpd_mask_to_target_mode(tc, live_status_mask);
1406 }
1407
tc_phy_connect(struct intel_tc_port * tc,int required_lanes)1408 static void tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
1409 {
1410 struct drm_i915_private *i915 = tc_to_i915(tc);
1411 u32 live_status_mask = tc_phy_hpd_live_status(tc);
1412 bool connected;
1413
1414 tc_port_fixup_legacy_flag(tc, live_status_mask);
1415
1416 tc->mode = hpd_mask_to_target_mode(tc, live_status_mask);
1417
1418 connected = tc->phy_ops->connect(tc, required_lanes);
1419 if (!connected && tc->mode != default_tc_mode(tc)) {
1420 tc->mode = default_tc_mode(tc);
1421 connected = tc->phy_ops->connect(tc, required_lanes);
1422 }
1423
1424 drm_WARN_ON(&i915->drm, !connected);
1425 }
1426
tc_phy_disconnect(struct intel_tc_port * tc)1427 static void tc_phy_disconnect(struct intel_tc_port *tc)
1428 {
1429 if (tc->mode != TC_PORT_DISCONNECTED) {
1430 tc->phy_ops->disconnect(tc);
1431 tc->mode = TC_PORT_DISCONNECTED;
1432 }
1433 }
1434
tc_phy_init(struct intel_tc_port * tc)1435 static void tc_phy_init(struct intel_tc_port *tc)
1436 {
1437 mutex_lock(&tc->lock);
1438 tc->phy_ops->init(tc);
1439 mutex_unlock(&tc->lock);
1440 }
1441
intel_tc_port_reset_mode(struct intel_tc_port * tc,int required_lanes,bool force_disconnect)1442 static void intel_tc_port_reset_mode(struct intel_tc_port *tc,
1443 int required_lanes, bool force_disconnect)
1444 {
1445 struct intel_display *display = to_intel_display(tc->dig_port);
1446 struct intel_digital_port *dig_port = tc->dig_port;
1447 enum tc_port_mode old_tc_mode = tc->mode;
1448
1449 intel_display_power_flush_work(display);
1450 if (!intel_tc_cold_requires_aux_pw(dig_port)) {
1451 enum intel_display_power_domain aux_domain;
1452 bool aux_powered;
1453
1454 aux_domain = intel_aux_power_domain(dig_port);
1455 aux_powered = intel_display_power_is_enabled(display, aux_domain);
1456 drm_WARN_ON(display->drm, aux_powered);
1457 }
1458
1459 tc_phy_disconnect(tc);
1460 if (!force_disconnect)
1461 tc_phy_connect(tc, required_lanes);
1462
1463 drm_dbg_kms(display->drm, "Port %s: TC port mode reset (%s -> %s)\n",
1464 tc->port_name,
1465 tc_port_mode_name(old_tc_mode),
1466 tc_port_mode_name(tc->mode));
1467 }
1468
intel_tc_port_needs_reset(struct intel_tc_port * tc)1469 static bool intel_tc_port_needs_reset(struct intel_tc_port *tc)
1470 {
1471 return tc_phy_get_target_mode(tc) != tc->mode;
1472 }
1473
intel_tc_port_update_mode(struct intel_tc_port * tc,int required_lanes,bool force_disconnect)1474 static void intel_tc_port_update_mode(struct intel_tc_port *tc,
1475 int required_lanes, bool force_disconnect)
1476 {
1477 if (force_disconnect ||
1478 intel_tc_port_needs_reset(tc))
1479 intel_tc_port_reset_mode(tc, required_lanes, force_disconnect);
1480 }
1481
__intel_tc_port_get_link(struct intel_tc_port * tc)1482 static void __intel_tc_port_get_link(struct intel_tc_port *tc)
1483 {
1484 tc->link_refcount++;
1485 }
1486
__intel_tc_port_put_link(struct intel_tc_port * tc)1487 static void __intel_tc_port_put_link(struct intel_tc_port *tc)
1488 {
1489 tc->link_refcount--;
1490 }
1491
tc_port_is_enabled(struct intel_tc_port * tc)1492 static bool tc_port_is_enabled(struct intel_tc_port *tc)
1493 {
1494 struct drm_i915_private *i915 = tc_to_i915(tc);
1495 struct intel_digital_port *dig_port = tc->dig_port;
1496
1497 assert_tc_port_power_enabled(tc);
1498
1499 return intel_de_read(i915, DDI_BUF_CTL(dig_port->base.port)) &
1500 DDI_BUF_CTL_ENABLE;
1501 }
1502
1503 /**
1504 * intel_tc_port_init_mode: Read out HW state and init the given port's TypeC mode
1505 * @dig_port: digital port
1506 *
1507 * Read out the HW state and initialize the TypeC mode of @dig_port. The mode
1508 * will be locked until intel_tc_port_sanitize_mode() is called.
1509 */
intel_tc_port_init_mode(struct intel_digital_port * dig_port)1510 void intel_tc_port_init_mode(struct intel_digital_port *dig_port)
1511 {
1512 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1513 struct intel_tc_port *tc = to_tc_port(dig_port);
1514 bool update_mode = false;
1515
1516 mutex_lock(&tc->lock);
1517
1518 drm_WARN_ON(&i915->drm, tc->mode != TC_PORT_DISCONNECTED);
1519 drm_WARN_ON(&i915->drm, tc->lock_wakeref);
1520 drm_WARN_ON(&i915->drm, tc->link_refcount);
1521
1522 tc_phy_get_hw_state(tc);
1523 /*
1524 * Save the initial mode for the state check in
1525 * intel_tc_port_sanitize_mode().
1526 */
1527 tc->init_mode = tc->mode;
1528
1529 /*
1530 * The PHY needs to be connected for AUX to work during HW readout and
1531 * MST topology resume, but the PHY mode can only be changed if the
1532 * port is disabled.
1533 *
1534 * An exception is the case where BIOS leaves the PHY incorrectly
1535 * disconnected on an enabled legacy port. Work around that by
1536 * connecting the PHY even though the port is enabled. This doesn't
1537 * cause a problem as the PHY ownership state is ignored by the
1538 * IOM/TCSS firmware (only display can own the PHY in that case).
1539 */
1540 if (!tc_port_is_enabled(tc)) {
1541 update_mode = true;
1542 } else if (tc->mode == TC_PORT_DISCONNECTED) {
1543 drm_WARN_ON(&i915->drm, !tc->legacy_port);
1544 drm_err(&i915->drm,
1545 "Port %s: PHY disconnected on enabled port, connecting it\n",
1546 tc->port_name);
1547 update_mode = true;
1548 }
1549
1550 if (update_mode)
1551 intel_tc_port_update_mode(tc, 1, false);
1552
1553 /* Prevent changing tc->mode until intel_tc_port_sanitize_mode() is called. */
1554 __intel_tc_port_get_link(tc);
1555
1556 mutex_unlock(&tc->lock);
1557 }
1558
tc_port_has_active_links(struct intel_tc_port * tc,const struct intel_crtc_state * crtc_state)1559 static bool tc_port_has_active_links(struct intel_tc_port *tc,
1560 const struct intel_crtc_state *crtc_state)
1561 {
1562 struct drm_i915_private *i915 = tc_to_i915(tc);
1563 struct intel_digital_port *dig_port = tc->dig_port;
1564 enum icl_port_dpll_id pll_type = ICL_PORT_DPLL_DEFAULT;
1565 int active_links = 0;
1566
1567 if (dig_port->dp.is_mst) {
1568 /* TODO: get the PLL type for MST, once HW readout is done for it. */
1569 active_links = intel_dp_mst_encoder_active_links(dig_port);
1570 } else if (crtc_state && crtc_state->hw.active) {
1571 pll_type = intel_ddi_port_pll_type(&dig_port->base, crtc_state);
1572 active_links = 1;
1573 }
1574
1575 if (active_links && !tc_phy_is_connected(tc, pll_type))
1576 drm_err(&i915->drm,
1577 "Port %s: PHY disconnected with %d active link(s)\n",
1578 tc->port_name, active_links);
1579
1580 return active_links;
1581 }
1582
1583 /**
1584 * intel_tc_port_sanitize_mode: Sanitize the given port's TypeC mode
1585 * @dig_port: digital port
1586 * @crtc_state: atomic state of CRTC connected to @dig_port
1587 *
1588 * Sanitize @dig_port's TypeC mode wrt. the encoder's state right after driver
1589 * loading and system resume:
1590 * If the encoder is enabled keep the TypeC mode/PHY connected state locked until
1591 * the encoder is disabled.
1592 * If the encoder is disabled make sure the PHY is disconnected.
1593 * @crtc_state is valid if @dig_port is enabled, NULL otherwise.
1594 */
intel_tc_port_sanitize_mode(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)1595 void intel_tc_port_sanitize_mode(struct intel_digital_port *dig_port,
1596 const struct intel_crtc_state *crtc_state)
1597 {
1598 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1599 struct intel_tc_port *tc = to_tc_port(dig_port);
1600
1601 mutex_lock(&tc->lock);
1602
1603 drm_WARN_ON(&i915->drm, tc->link_refcount != 1);
1604 if (!tc_port_has_active_links(tc, crtc_state)) {
1605 /*
1606 * TBT-alt is the default mode in any case the PHY ownership is not
1607 * held (regardless of the sink's connected live state), so
1608 * we'll just switch to disconnected mode from it here without
1609 * a note.
1610 */
1611 if (tc->init_mode != TC_PORT_TBT_ALT &&
1612 tc->init_mode != TC_PORT_DISCONNECTED)
1613 drm_dbg_kms(&i915->drm,
1614 "Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
1615 tc->port_name,
1616 tc_port_mode_name(tc->init_mode));
1617 tc_phy_disconnect(tc);
1618 __intel_tc_port_put_link(tc);
1619 }
1620
1621 drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
1622 tc->port_name,
1623 tc_port_mode_name(tc->mode));
1624
1625 mutex_unlock(&tc->lock);
1626 }
1627
1628 /*
1629 * The type-C ports are different because even when they are connected, they may
1630 * not be available/usable by the graphics driver: see the comment on
1631 * icl_tc_phy_connect(). So in our driver instead of adding the additional
1632 * concept of "usable" and make everything check for "connected and usable" we
1633 * define a port as "connected" when it is not only connected, but also when it
1634 * is usable by the rest of the driver. That maintains the old assumption that
1635 * connected ports are usable, and avoids exposing to the users objects they
1636 * can't really use.
1637 */
intel_tc_port_connected(struct intel_encoder * encoder)1638 bool intel_tc_port_connected(struct intel_encoder *encoder)
1639 {
1640 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1641 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1642 struct intel_tc_port *tc = to_tc_port(dig_port);
1643 u32 mask = ~0;
1644
1645 drm_WARN_ON(&i915->drm, !intel_tc_port_ref_held(dig_port));
1646
1647 if (tc->mode != TC_PORT_DISCONNECTED)
1648 mask = BIT(tc->mode);
1649
1650 return tc_phy_hpd_live_status(tc) & mask;
1651 }
1652
__intel_tc_port_link_needs_reset(struct intel_tc_port * tc)1653 static bool __intel_tc_port_link_needs_reset(struct intel_tc_port *tc)
1654 {
1655 bool ret;
1656
1657 mutex_lock(&tc->lock);
1658
1659 ret = tc->link_refcount &&
1660 tc->mode == TC_PORT_DP_ALT &&
1661 intel_tc_port_needs_reset(tc);
1662
1663 mutex_unlock(&tc->lock);
1664
1665 return ret;
1666 }
1667
intel_tc_port_link_needs_reset(struct intel_digital_port * dig_port)1668 bool intel_tc_port_link_needs_reset(struct intel_digital_port *dig_port)
1669 {
1670 if (!intel_encoder_is_tc(&dig_port->base))
1671 return false;
1672
1673 return __intel_tc_port_link_needs_reset(to_tc_port(dig_port));
1674 }
1675
reset_link_commit(struct intel_tc_port * tc,struct intel_atomic_state * state,struct drm_modeset_acquire_ctx * ctx)1676 static int reset_link_commit(struct intel_tc_port *tc,
1677 struct intel_atomic_state *state,
1678 struct drm_modeset_acquire_ctx *ctx)
1679 {
1680 struct drm_i915_private *i915 = tc_to_i915(tc);
1681 struct intel_digital_port *dig_port = tc->dig_port;
1682 struct intel_dp *intel_dp = enc_to_intel_dp(&dig_port->base);
1683 struct intel_crtc *crtc;
1684 u8 pipe_mask;
1685 int ret;
1686
1687 ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex, ctx);
1688 if (ret)
1689 return ret;
1690
1691 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
1692 if (ret)
1693 return ret;
1694
1695 if (!pipe_mask)
1696 return 0;
1697
1698 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
1699 struct intel_crtc_state *crtc_state;
1700
1701 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
1702 if (IS_ERR(crtc_state))
1703 return PTR_ERR(crtc_state);
1704
1705 crtc_state->uapi.connectors_changed = true;
1706 }
1707
1708 if (!__intel_tc_port_link_needs_reset(tc))
1709 return 0;
1710
1711 return drm_atomic_commit(&state->base);
1712 }
1713
reset_link(struct intel_tc_port * tc)1714 static int reset_link(struct intel_tc_port *tc)
1715 {
1716 struct drm_i915_private *i915 = tc_to_i915(tc);
1717 struct drm_modeset_acquire_ctx ctx;
1718 struct drm_atomic_state *_state;
1719 struct intel_atomic_state *state;
1720 int ret;
1721
1722 _state = drm_atomic_state_alloc(&i915->drm);
1723 if (!_state)
1724 return -ENOMEM;
1725
1726 state = to_intel_atomic_state(_state);
1727 state->internal = true;
1728
1729 intel_modeset_lock_ctx_retry(&ctx, state, 0, ret)
1730 ret = reset_link_commit(tc, state, &ctx);
1731
1732 drm_atomic_state_put(&state->base);
1733
1734 return ret;
1735 }
1736
intel_tc_port_link_reset_work(struct work_struct * work)1737 static void intel_tc_port_link_reset_work(struct work_struct *work)
1738 {
1739 struct intel_tc_port *tc =
1740 container_of(work, struct intel_tc_port, link_reset_work.work);
1741 struct drm_i915_private *i915 = tc_to_i915(tc);
1742 int ret;
1743
1744 if (!__intel_tc_port_link_needs_reset(tc))
1745 return;
1746
1747 mutex_lock(&i915->drm.mode_config.mutex);
1748
1749 drm_dbg_kms(&i915->drm,
1750 "Port %s: TypeC DP-alt sink disconnected, resetting link\n",
1751 tc->port_name);
1752 ret = reset_link(tc);
1753 drm_WARN_ON(&i915->drm, ret);
1754
1755 mutex_unlock(&i915->drm.mode_config.mutex);
1756 }
1757
intel_tc_port_link_reset(struct intel_digital_port * dig_port)1758 bool intel_tc_port_link_reset(struct intel_digital_port *dig_port)
1759 {
1760 if (!intel_tc_port_link_needs_reset(dig_port))
1761 return false;
1762
1763 queue_delayed_work(system_unbound_wq,
1764 &to_tc_port(dig_port)->link_reset_work,
1765 msecs_to_jiffies(2000));
1766
1767 return true;
1768 }
1769
intel_tc_port_link_cancel_reset_work(struct intel_digital_port * dig_port)1770 void intel_tc_port_link_cancel_reset_work(struct intel_digital_port *dig_port)
1771 {
1772 struct intel_tc_port *tc = to_tc_port(dig_port);
1773
1774 if (!intel_encoder_is_tc(&dig_port->base))
1775 return;
1776
1777 cancel_delayed_work(&tc->link_reset_work);
1778 }
1779
__intel_tc_port_lock(struct intel_tc_port * tc,int required_lanes)1780 static void __intel_tc_port_lock(struct intel_tc_port *tc,
1781 int required_lanes)
1782 {
1783 struct drm_i915_private *i915 = tc_to_i915(tc);
1784
1785 mutex_lock(&tc->lock);
1786
1787 cancel_delayed_work(&tc->disconnect_phy_work);
1788
1789 if (!tc->link_refcount)
1790 intel_tc_port_update_mode(tc, required_lanes,
1791 false);
1792
1793 drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_DISCONNECTED);
1794 drm_WARN_ON(&i915->drm, tc->mode != TC_PORT_TBT_ALT &&
1795 !tc_phy_is_owned(tc));
1796 }
1797
intel_tc_port_lock(struct intel_digital_port * dig_port)1798 void intel_tc_port_lock(struct intel_digital_port *dig_port)
1799 {
1800 __intel_tc_port_lock(to_tc_port(dig_port), 1);
1801 }
1802
1803 /*
1804 * Disconnect the given digital port from its TypeC PHY (handing back the
1805 * control of the PHY to the TypeC subsystem). This will happen in a delayed
1806 * manner after each aux transactions and modeset disables.
1807 */
intel_tc_port_disconnect_phy_work(struct work_struct * work)1808 static void intel_tc_port_disconnect_phy_work(struct work_struct *work)
1809 {
1810 struct intel_tc_port *tc =
1811 container_of(work, struct intel_tc_port, disconnect_phy_work.work);
1812
1813 mutex_lock(&tc->lock);
1814
1815 if (!tc->link_refcount)
1816 intel_tc_port_update_mode(tc, 1, true);
1817
1818 mutex_unlock(&tc->lock);
1819 }
1820
1821 /**
1822 * intel_tc_port_flush_work: flush the work disconnecting the PHY
1823 * @dig_port: digital port
1824 *
1825 * Flush the delayed work disconnecting an idle PHY.
1826 */
intel_tc_port_flush_work(struct intel_digital_port * dig_port)1827 static void intel_tc_port_flush_work(struct intel_digital_port *dig_port)
1828 {
1829 flush_delayed_work(&to_tc_port(dig_port)->disconnect_phy_work);
1830 }
1831
intel_tc_port_suspend(struct intel_digital_port * dig_port)1832 void intel_tc_port_suspend(struct intel_digital_port *dig_port)
1833 {
1834 struct intel_tc_port *tc = to_tc_port(dig_port);
1835
1836 cancel_delayed_work_sync(&tc->link_reset_work);
1837 intel_tc_port_flush_work(dig_port);
1838 }
1839
intel_tc_port_unlock(struct intel_digital_port * dig_port)1840 void intel_tc_port_unlock(struct intel_digital_port *dig_port)
1841 {
1842 struct intel_tc_port *tc = to_tc_port(dig_port);
1843
1844 if (!tc->link_refcount && tc->mode != TC_PORT_DISCONNECTED)
1845 queue_delayed_work(system_unbound_wq, &tc->disconnect_phy_work,
1846 msecs_to_jiffies(1000));
1847
1848 mutex_unlock(&tc->lock);
1849 }
1850
intel_tc_port_ref_held(struct intel_digital_port * dig_port)1851 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
1852 {
1853 struct intel_tc_port *tc = to_tc_port(dig_port);
1854
1855 return mutex_is_locked(&tc->lock) ||
1856 tc->link_refcount;
1857 }
1858
intel_tc_port_get_link(struct intel_digital_port * dig_port,int required_lanes)1859 void intel_tc_port_get_link(struct intel_digital_port *dig_port,
1860 int required_lanes)
1861 {
1862 struct intel_tc_port *tc = to_tc_port(dig_port);
1863
1864 __intel_tc_port_lock(tc, required_lanes);
1865 __intel_tc_port_get_link(tc);
1866 intel_tc_port_unlock(dig_port);
1867 }
1868
intel_tc_port_put_link(struct intel_digital_port * dig_port)1869 void intel_tc_port_put_link(struct intel_digital_port *dig_port)
1870 {
1871 struct intel_tc_port *tc = to_tc_port(dig_port);
1872
1873 intel_tc_port_lock(dig_port);
1874 __intel_tc_port_put_link(tc);
1875 intel_tc_port_unlock(dig_port);
1876
1877 /*
1878 * The firmware will not update the HPD status of other TypeC ports
1879 * that are active in DP-alt mode with their sink disconnected, until
1880 * this port is disabled and its PHY gets disconnected. Make sure this
1881 * happens in a timely manner by disconnecting the PHY synchronously.
1882 */
1883 intel_tc_port_flush_work(dig_port);
1884 }
1885
intel_tc_port_init(struct intel_digital_port * dig_port,bool is_legacy)1886 int intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
1887 {
1888 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1889 struct intel_tc_port *tc;
1890 enum port port = dig_port->base.port;
1891 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
1892
1893 if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
1894 return -EINVAL;
1895
1896 tc = kzalloc(sizeof(*tc), GFP_KERNEL);
1897 if (!tc)
1898 return -ENOMEM;
1899
1900 dig_port->tc = tc;
1901 tc->dig_port = dig_port;
1902
1903 if (DISPLAY_VER(i915) >= 14)
1904 tc->phy_ops = &xelpdp_tc_phy_ops;
1905 else if (DISPLAY_VER(i915) >= 13)
1906 tc->phy_ops = &adlp_tc_phy_ops;
1907 else if (DISPLAY_VER(i915) >= 12)
1908 tc->phy_ops = &tgl_tc_phy_ops;
1909 else
1910 tc->phy_ops = &icl_tc_phy_ops;
1911
1912 tc->port_name = kasprintf(GFP_KERNEL, "%c/TC#%d", port_name(port),
1913 tc_port + 1);
1914 if (!tc->port_name) {
1915 kfree(tc);
1916 return -ENOMEM;
1917 }
1918
1919 mutex_init(&tc->lock);
1920 /* TODO: Combine the two works */
1921 INIT_DELAYED_WORK(&tc->disconnect_phy_work, intel_tc_port_disconnect_phy_work);
1922 INIT_DELAYED_WORK(&tc->link_reset_work, intel_tc_port_link_reset_work);
1923 tc->legacy_port = is_legacy;
1924 tc->mode = TC_PORT_DISCONNECTED;
1925 tc->link_refcount = 0;
1926
1927 tc_phy_init(tc);
1928
1929 intel_tc_port_init_mode(dig_port);
1930
1931 return 0;
1932 }
1933
intel_tc_port_cleanup(struct intel_digital_port * dig_port)1934 void intel_tc_port_cleanup(struct intel_digital_port *dig_port)
1935 {
1936 intel_tc_port_suspend(dig_port);
1937
1938 kfree(dig_port->tc->port_name);
1939 kfree(dig_port->tc);
1940 dig_port->tc = NULL;
1941 }
1942