1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 *
5 * Read out the current hardware modeset state, and sanitize it to the current
6 * state.
7 */
8
9 #include <drm/drm_atomic_uapi.h>
10 #include <drm/drm_atomic_state_helper.h>
11 #include <drm/drm_vblank.h>
12
13 #include "i915_drv.h"
14 #include "i915_reg.h"
15 #include "i9xx_wm.h"
16 #include "intel_atomic.h"
17 #include "intel_bw.h"
18 #include "intel_cmtg.h"
19 #include "intel_color.h"
20 #include "intel_crtc.h"
21 #include "intel_crtc_state_dump.h"
22 #include "intel_ddi.h"
23 #include "intel_de.h"
24 #include "intel_display.h"
25 #include "intel_display_power.h"
26 #include "intel_display_types.h"
27 #include "intel_dmc.h"
28 #include "intel_fifo_underrun.h"
29 #include "intel_modeset_setup.h"
30 #include "intel_pch_display.h"
31 #include "intel_pmdemand.h"
32 #include "intel_tc.h"
33 #include "intel_vblank.h"
34 #include "intel_wm.h"
35 #include "skl_watermark.h"
36
intel_crtc_disable_noatomic_begin(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)37 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
38 struct drm_modeset_acquire_ctx *ctx)
39 {
40 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
41 struct intel_crtc_state *crtc_state =
42 to_intel_crtc_state(crtc->base.state);
43 struct intel_plane *plane;
44 struct drm_atomic_state *state;
45 struct intel_crtc *temp_crtc;
46 enum pipe pipe = crtc->pipe;
47
48 if (!crtc_state->hw.active)
49 return;
50
51 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
52 const struct intel_plane_state *plane_state =
53 to_intel_plane_state(plane->base.state);
54
55 if (plane_state->uapi.visible)
56 intel_plane_disable_noatomic(crtc, plane);
57 }
58
59 state = drm_atomic_state_alloc(&i915->drm);
60 if (!state) {
61 drm_dbg_kms(&i915->drm,
62 "failed to disable [CRTC:%d:%s], out of memory",
63 crtc->base.base.id, crtc->base.name);
64 return;
65 }
66
67 state->acquire_ctx = ctx;
68 to_intel_atomic_state(state)->internal = true;
69
70 /* Everything's already locked, -EDEADLK can't happen. */
71 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
72 BIT(pipe) |
73 intel_crtc_joiner_secondary_pipes(crtc_state)) {
74 struct intel_crtc_state *temp_crtc_state =
75 intel_atomic_get_crtc_state(state, temp_crtc);
76 int ret;
77
78 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base);
79
80 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
81 }
82
83 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
84
85 drm_atomic_state_put(state);
86
87 drm_dbg_kms(&i915->drm,
88 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
89 crtc->base.base.id, crtc->base.name);
90
91 crtc->active = false;
92 crtc->base.enabled = false;
93
94 if (crtc_state->shared_dpll)
95 intel_unreference_shared_dpll_crtc(crtc,
96 crtc_state->shared_dpll,
97 &crtc_state->shared_dpll->state);
98 }
99
set_encoder_for_connector(struct intel_connector * connector,struct intel_encoder * encoder)100 static void set_encoder_for_connector(struct intel_connector *connector,
101 struct intel_encoder *encoder)
102 {
103 struct drm_connector_state *conn_state = connector->base.state;
104
105 if (conn_state->crtc)
106 drm_connector_put(&connector->base);
107
108 if (encoder) {
109 conn_state->best_encoder = &encoder->base;
110 conn_state->crtc = encoder->base.crtc;
111 drm_connector_get(&connector->base);
112 } else {
113 conn_state->best_encoder = NULL;
114 conn_state->crtc = NULL;
115 }
116 }
117
reset_encoder_connector_state(struct intel_encoder * encoder)118 static void reset_encoder_connector_state(struct intel_encoder *encoder)
119 {
120 struct intel_display *display = to_intel_display(encoder);
121 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
122 struct intel_pmdemand_state *pmdemand_state =
123 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
124 struct intel_connector *connector;
125 struct drm_connector_list_iter conn_iter;
126
127 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
128 for_each_intel_connector_iter(connector, &conn_iter) {
129 if (connector->base.encoder != &encoder->base)
130 continue;
131
132 /* Clear the corresponding bit in pmdemand active phys mask */
133 intel_pmdemand_update_phys_mask(display, encoder,
134 pmdemand_state, false);
135
136 set_encoder_for_connector(connector, NULL);
137
138 connector->base.dpms = DRM_MODE_DPMS_OFF;
139 connector->base.encoder = NULL;
140 }
141 drm_connector_list_iter_end(&conn_iter);
142 }
143
reset_crtc_encoder_state(struct intel_crtc * crtc)144 static void reset_crtc_encoder_state(struct intel_crtc *crtc)
145 {
146 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
147 struct intel_encoder *encoder;
148
149 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) {
150 reset_encoder_connector_state(encoder);
151 encoder->base.crtc = NULL;
152 }
153 }
154
intel_crtc_disable_noatomic_complete(struct intel_crtc * crtc)155 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
156 {
157 struct intel_display *display = to_intel_display(crtc);
158 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
159 struct intel_pmdemand_state *pmdemand_state =
160 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
161 struct intel_crtc_state *crtc_state =
162 to_intel_crtc_state(crtc->base.state);
163 enum pipe pipe = crtc->pipe;
164
165 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
166 intel_crtc_free_hw_state(crtc_state);
167 intel_crtc_state_reset(crtc_state, crtc);
168
169 reset_crtc_encoder_state(crtc);
170
171 intel_fbc_disable(crtc);
172 intel_update_watermarks(i915);
173
174 intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains);
175
176 intel_cdclk_crtc_disable_noatomic(crtc);
177 skl_wm_crtc_disable_noatomic(crtc);
178 intel_bw_crtc_disable_noatomic(crtc);
179
180 intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);
181 }
182
183 /*
184 * Return all the pipes using a transcoder in @transcoder_mask.
185 * For joiner configs return only the joiner primary.
186 */
get_transcoder_pipes(struct drm_i915_private * i915,u8 transcoder_mask)187 static u8 get_transcoder_pipes(struct drm_i915_private *i915,
188 u8 transcoder_mask)
189 {
190 struct intel_crtc *temp_crtc;
191 u8 pipes = 0;
192
193 for_each_intel_crtc(&i915->drm, temp_crtc) {
194 struct intel_crtc_state *temp_crtc_state =
195 to_intel_crtc_state(temp_crtc->base.state);
196
197 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
198 continue;
199
200 if (intel_crtc_is_joiner_secondary(temp_crtc_state))
201 continue;
202
203 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
204 pipes |= BIT(temp_crtc->pipe);
205 }
206
207 return pipes;
208 }
209
210 /*
211 * Return the port sync master and slave pipes linked to @crtc.
212 * For joiner configs return only the joiner primary pipes.
213 */
get_portsync_pipes(struct intel_crtc * crtc,u8 * master_pipe_mask,u8 * slave_pipes_mask)214 static void get_portsync_pipes(struct intel_crtc *crtc,
215 u8 *master_pipe_mask, u8 *slave_pipes_mask)
216 {
217 struct intel_display *display = to_intel_display(crtc);
218 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
219 struct intel_crtc_state *crtc_state =
220 to_intel_crtc_state(crtc->base.state);
221 struct intel_crtc *master_crtc;
222 struct intel_crtc_state *master_crtc_state;
223 enum transcoder master_transcoder;
224
225 if (!is_trans_port_sync_mode(crtc_state)) {
226 *master_pipe_mask = BIT(crtc->pipe);
227 *slave_pipes_mask = 0;
228
229 return;
230 }
231
232 if (is_trans_port_sync_master(crtc_state))
233 master_transcoder = crtc_state->cpu_transcoder;
234 else
235 master_transcoder = crtc_state->master_transcoder;
236
237 *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder));
238 drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask));
239
240 master_crtc = intel_crtc_for_pipe(display, ffs(*master_pipe_mask) - 1);
241 master_crtc_state = to_intel_crtc_state(master_crtc->base.state);
242 *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask);
243 }
244
get_joiner_secondary_pipes(struct drm_i915_private * i915,u8 primary_pipes_mask)245 static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask)
246 {
247 struct intel_crtc *primary_crtc;
248 u8 pipes = 0;
249
250 for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) {
251 struct intel_crtc_state *primary_crtc_state =
252 to_intel_crtc_state(primary_crtc->base.state);
253
254 pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state);
255 }
256
257 return pipes;
258 }
259
intel_crtc_disable_noatomic(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)260 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
261 struct drm_modeset_acquire_ctx *ctx)
262 {
263 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
264 u8 portsync_master_mask;
265 u8 portsync_slaves_mask;
266 u8 joiner_secondaries_mask;
267 struct intel_crtc *temp_crtc;
268
269 /* TODO: Add support for MST */
270 get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask);
271 joiner_secondaries_mask = get_joiner_secondary_pipes(i915,
272 portsync_master_mask |
273 portsync_slaves_mask);
274
275 drm_WARN_ON(&i915->drm,
276 portsync_master_mask & portsync_slaves_mask ||
277 portsync_master_mask & joiner_secondaries_mask ||
278 portsync_slaves_mask & joiner_secondaries_mask);
279
280 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask)
281 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
282
283 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask)
284 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
285
286 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask)
287 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
288
289 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
290 joiner_secondaries_mask |
291 portsync_slaves_mask |
292 portsync_master_mask)
293 intel_crtc_disable_noatomic_complete(temp_crtc);
294 }
295
intel_modeset_update_connector_atomic_state(struct drm_i915_private * i915)296 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
297 {
298 struct intel_connector *connector;
299 struct drm_connector_list_iter conn_iter;
300
301 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
302 for_each_intel_connector_iter(connector, &conn_iter) {
303 struct drm_connector_state *conn_state = connector->base.state;
304 struct intel_encoder *encoder =
305 to_intel_encoder(connector->base.encoder);
306
307 set_encoder_for_connector(connector, encoder);
308
309 if (encoder) {
310 struct intel_crtc *crtc =
311 to_intel_crtc(encoder->base.crtc);
312 const struct intel_crtc_state *crtc_state =
313 to_intel_crtc_state(crtc->base.state);
314
315 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
316 }
317 }
318 drm_connector_list_iter_end(&conn_iter);
319 }
320
intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state * crtc_state)321 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
322 {
323 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
324
325 if (intel_crtc_is_joiner_secondary(crtc_state))
326 return;
327
328 crtc_state->uapi.enable = crtc_state->hw.enable;
329 crtc_state->uapi.active = crtc_state->hw.active;
330 drm_WARN_ON(crtc_state->uapi.crtc->dev,
331 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
332
333 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
334 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
335
336 if (DISPLAY_INFO(i915)->color.degamma_lut_size) {
337 /* assume 1:1 mapping */
338 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
339 crtc_state->pre_csc_lut);
340 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
341 crtc_state->post_csc_lut);
342 } else {
343 /*
344 * ilk/snb hw may be configured for either pre_csc_lut
345 * or post_csc_lut, but we don't advertise degamma_lut as
346 * being available in the uapi since there is only one
347 * hardware LUT. Always assign the result of the readout
348 * to gamma_lut as that is the only valid source of LUTs
349 * in the uapi.
350 */
351 drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut &&
352 crtc_state->pre_csc_lut);
353
354 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
355 NULL);
356 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
357 crtc_state->post_csc_lut ?:
358 crtc_state->pre_csc_lut);
359 }
360
361 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
362 crtc_state->hw.degamma_lut);
363 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
364 crtc_state->hw.gamma_lut);
365 drm_property_replace_blob(&crtc_state->uapi.ctm,
366 crtc_state->hw.ctm);
367 }
368
369 static void
intel_sanitize_plane_mapping(struct drm_i915_private * i915)370 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
371 {
372 struct intel_display *display = &i915->display;
373 struct intel_crtc *crtc;
374
375 if (DISPLAY_VER(i915) >= 4)
376 return;
377
378 for_each_intel_crtc(&i915->drm, crtc) {
379 struct intel_plane *plane =
380 to_intel_plane(crtc->base.primary);
381 struct intel_crtc *plane_crtc;
382 enum pipe pipe;
383
384 if (!plane->get_hw_state(plane, &pipe))
385 continue;
386
387 if (pipe == crtc->pipe)
388 continue;
389
390 drm_dbg_kms(&i915->drm,
391 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
392 plane->base.base.id, plane->base.name);
393
394 plane_crtc = intel_crtc_for_pipe(display, pipe);
395 intel_plane_disable_noatomic(plane_crtc, plane);
396 }
397 }
398
intel_crtc_has_encoders(struct intel_crtc * crtc)399 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
400 {
401 struct drm_device *dev = crtc->base.dev;
402 struct intel_encoder *encoder;
403
404 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
405 return true;
406
407 return false;
408 }
409
intel_crtc_needs_link_reset(struct intel_crtc * crtc)410 static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
411 {
412 struct drm_device *dev = crtc->base.dev;
413 struct intel_encoder *encoder;
414
415 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
416 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
417
418 if (dig_port && intel_tc_port_link_needs_reset(dig_port))
419 return true;
420 }
421
422 return false;
423 }
424
intel_encoder_find_connector(struct intel_encoder * encoder)425 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
426 {
427 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
428 struct drm_connector_list_iter conn_iter;
429 struct intel_connector *connector;
430 struct intel_connector *found_connector = NULL;
431
432 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
433 for_each_intel_connector_iter(connector, &conn_iter) {
434 if (&encoder->base == connector->base.encoder) {
435 found_connector = connector;
436 break;
437 }
438 }
439 drm_connector_list_iter_end(&conn_iter);
440
441 return found_connector;
442 }
443
intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state * crtc_state)444 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
445 {
446 struct intel_display *display = to_intel_display(crtc_state);
447 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
448
449 /*
450 * We start out with underrun reporting disabled on active
451 * pipes to avoid races.
452 *
453 * Also on gmch platforms we dont have any hardware bits to
454 * disable the underrun reporting. Which means we need to start
455 * out with underrun reporting disabled also on inactive pipes,
456 * since otherwise we'll complain about the garbage we read when
457 * e.g. coming up after runtime pm.
458 *
459 * No protection against concurrent access is required - at
460 * worst a fifo underrun happens which also sets this to false.
461 */
462 intel_init_fifo_underrun_reporting(display, crtc,
463 !crtc_state->hw.active &&
464 !HAS_GMCH(display));
465 }
466
intel_sanitize_crtc(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)467 static bool intel_sanitize_crtc(struct intel_crtc *crtc,
468 struct drm_modeset_acquire_ctx *ctx)
469 {
470 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
471 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
472 bool needs_link_reset;
473
474 if (crtc_state->hw.active) {
475 struct intel_plane *plane;
476
477 /* Disable everything but the primary plane */
478 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
479 const struct intel_plane_state *plane_state =
480 to_intel_plane_state(plane->base.state);
481
482 if (plane_state->uapi.visible &&
483 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
484 intel_plane_disable_noatomic(crtc, plane);
485 }
486
487 /* Disable any background color/etc. set by the BIOS */
488 intel_color_commit_noarm(NULL, crtc_state);
489 intel_color_commit_arm(NULL, crtc_state);
490 }
491
492 if (!crtc_state->hw.active ||
493 intel_crtc_is_joiner_secondary(crtc_state))
494 return false;
495
496 needs_link_reset = intel_crtc_needs_link_reset(crtc);
497
498 /*
499 * Adjust the state of the output pipe according to whether we have
500 * active connectors/encoders.
501 */
502 if (!needs_link_reset && intel_crtc_has_encoders(crtc))
503 return false;
504
505 intel_crtc_disable_noatomic(crtc, ctx);
506
507 /*
508 * The HPD state on other active/disconnected TC ports may be stuck in
509 * the connected state until this port is disabled and a ~10ms delay has
510 * passed, wait here for that so that sanitizing other CRTCs will see the
511 * up-to-date HPD state.
512 */
513 if (needs_link_reset)
514 msleep(20);
515
516 return true;
517 }
518
intel_sanitize_all_crtcs(struct drm_i915_private * i915,struct drm_modeset_acquire_ctx * ctx)519 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915,
520 struct drm_modeset_acquire_ctx *ctx)
521 {
522 struct intel_crtc *crtc;
523 u32 crtcs_forced_off = 0;
524
525 /*
526 * An active and disconnected TypeC port prevents the HPD live state
527 * to get updated on other active/disconnected TypeC ports, so after
528 * a port gets disabled the CRTCs using other TypeC ports must be
529 * rechecked wrt. their link status.
530 */
531 for (;;) {
532 u32 old_mask = crtcs_forced_off;
533
534 for_each_intel_crtc(&i915->drm, crtc) {
535 u32 crtc_mask = drm_crtc_mask(&crtc->base);
536
537 if (crtcs_forced_off & crtc_mask)
538 continue;
539
540 if (intel_sanitize_crtc(crtc, ctx))
541 crtcs_forced_off |= crtc_mask;
542 }
543 if (crtcs_forced_off == old_mask)
544 break;
545 }
546
547 for_each_intel_crtc(&i915->drm, crtc) {
548 struct intel_crtc_state *crtc_state =
549 to_intel_crtc_state(crtc->base.state);
550
551 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
552 }
553 }
554
has_bogus_dpll_config(const struct intel_crtc_state * crtc_state)555 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
556 {
557 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
558
559 /*
560 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
561 * the hardware when a high res displays plugged in. DPLL P
562 * divider is zero, and the pipe timings are bonkers. We'll
563 * try to disable everything in that case.
564 *
565 * FIXME would be nice to be able to sanitize this state
566 * without several WARNs, but for now let's take the easy
567 * road.
568 */
569 return IS_SANDYBRIDGE(i915) &&
570 crtc_state->hw.active &&
571 crtc_state->shared_dpll &&
572 crtc_state->port_clock == 0;
573 }
574
intel_sanitize_encoder(struct intel_encoder * encoder)575 static void intel_sanitize_encoder(struct intel_encoder *encoder)
576 {
577 struct intel_display *display = to_intel_display(encoder);
578 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
579 struct intel_connector *connector;
580 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
581 struct intel_crtc_state *crtc_state = crtc ?
582 to_intel_crtc_state(crtc->base.state) : NULL;
583 struct intel_pmdemand_state *pmdemand_state =
584 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
585
586 /*
587 * We need to check both for a crtc link (meaning that the encoder is
588 * active and trying to read from a pipe) and the pipe itself being
589 * active.
590 */
591 bool has_active_crtc = crtc_state &&
592 crtc_state->hw.active;
593
594 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
595 drm_dbg_kms(&i915->drm,
596 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
597 pipe_name(crtc->pipe));
598 has_active_crtc = false;
599 }
600
601 connector = intel_encoder_find_connector(encoder);
602 if (connector && !has_active_crtc) {
603 drm_dbg_kms(&i915->drm,
604 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
605 encoder->base.base.id,
606 encoder->base.name);
607
608 /* Clear the corresponding bit in pmdemand active phys mask */
609 intel_pmdemand_update_phys_mask(display, encoder,
610 pmdemand_state, false);
611
612 /*
613 * Connector is active, but has no active pipe. This is fallout
614 * from our resume register restoring. Disable the encoder
615 * manually again.
616 */
617 if (crtc_state) {
618 struct drm_encoder *best_encoder;
619
620 drm_dbg_kms(&i915->drm,
621 "[ENCODER:%d:%s] manually disabled\n",
622 encoder->base.base.id,
623 encoder->base.name);
624
625 /* avoid oopsing in case the hooks consult best_encoder */
626 best_encoder = connector->base.state->best_encoder;
627 connector->base.state->best_encoder = &encoder->base;
628
629 /* FIXME NULL atomic state passed! */
630 if (encoder->disable)
631 encoder->disable(NULL, encoder, crtc_state,
632 connector->base.state);
633 if (encoder->post_disable)
634 encoder->post_disable(NULL, encoder, crtc_state,
635 connector->base.state);
636
637 connector->base.state->best_encoder = best_encoder;
638 }
639 encoder->base.crtc = NULL;
640
641 /*
642 * Inconsistent output/port/pipe state happens presumably due to
643 * a bug in one of the get_hw_state functions. Or someplace else
644 * in our code, like the register restore mess on resume. Clamp
645 * things to off as a safer default.
646 */
647 connector->base.dpms = DRM_MODE_DPMS_OFF;
648 connector->base.encoder = NULL;
649 }
650
651 /* notify opregion of the sanitized encoder state */
652 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
653
654 if (HAS_DDI(i915))
655 intel_ddi_sanitize_encoder_pll_mapping(encoder);
656 }
657
658 /* FIXME read out full plane state for all planes */
readout_plane_state(struct drm_i915_private * i915)659 static void readout_plane_state(struct drm_i915_private *i915)
660 {
661 struct intel_display *display = &i915->display;
662 struct intel_plane *plane;
663 struct intel_crtc *crtc;
664
665 for_each_intel_plane(&i915->drm, plane) {
666 struct intel_plane_state *plane_state =
667 to_intel_plane_state(plane->base.state);
668 struct intel_crtc_state *crtc_state;
669 enum pipe pipe = PIPE_A;
670 bool visible;
671
672 visible = plane->get_hw_state(plane, &pipe);
673
674 crtc = intel_crtc_for_pipe(display, pipe);
675 crtc_state = to_intel_crtc_state(crtc->base.state);
676
677 intel_set_plane_visible(crtc_state, plane_state, visible);
678
679 drm_dbg_kms(&i915->drm,
680 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
681 plane->base.base.id, plane->base.name,
682 str_enabled_disabled(visible), pipe_name(pipe));
683 }
684
685 for_each_intel_crtc(&i915->drm, crtc) {
686 struct intel_crtc_state *crtc_state =
687 to_intel_crtc_state(crtc->base.state);
688
689 intel_plane_fixup_bitmasks(crtc_state);
690 }
691 }
692
intel_modeset_readout_hw_state(struct drm_i915_private * i915)693 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
694 {
695 struct intel_display *display = &i915->display;
696 struct intel_pmdemand_state *pmdemand_state =
697 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
698 enum pipe pipe;
699 struct intel_crtc *crtc;
700 struct intel_encoder *encoder;
701 struct intel_connector *connector;
702 struct drm_connector_list_iter conn_iter;
703
704 for_each_intel_crtc(&i915->drm, crtc) {
705 struct intel_crtc_state *crtc_state =
706 to_intel_crtc_state(crtc->base.state);
707
708 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
709 intel_crtc_free_hw_state(crtc_state);
710 intel_crtc_state_reset(crtc_state, crtc);
711
712 intel_crtc_get_pipe_config(crtc_state);
713
714 crtc_state->hw.enable = crtc_state->hw.active;
715
716 crtc->base.enabled = crtc_state->hw.enable;
717 crtc->active = crtc_state->hw.active;
718
719 drm_dbg_kms(&i915->drm,
720 "[CRTC:%d:%s] hw state readout: %s\n",
721 crtc->base.base.id, crtc->base.name,
722 str_enabled_disabled(crtc_state->hw.active));
723 }
724
725 readout_plane_state(i915);
726
727 for_each_intel_encoder(&i915->drm, encoder) {
728 struct intel_crtc_state *crtc_state = NULL;
729
730 pipe = 0;
731
732 if (encoder->get_hw_state(encoder, &pipe)) {
733 crtc = intel_crtc_for_pipe(display, pipe);
734 crtc_state = to_intel_crtc_state(crtc->base.state);
735
736 encoder->base.crtc = &crtc->base;
737 intel_encoder_get_config(encoder, crtc_state);
738
739 /* read out to secondary crtc as well for joiner */
740 if (crtc_state->joiner_pipes) {
741 struct intel_crtc *secondary_crtc;
742
743 /* encoder should read be linked to joiner primary */
744 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
745
746 for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,
747 intel_crtc_joiner_secondary_pipes(crtc_state)) {
748 struct intel_crtc_state *secondary_crtc_state;
749
750 secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state);
751 intel_encoder_get_config(encoder, secondary_crtc_state);
752 }
753 }
754
755 intel_pmdemand_update_phys_mask(display, encoder,
756 pmdemand_state,
757 true);
758 } else {
759 intel_pmdemand_update_phys_mask(display, encoder,
760 pmdemand_state,
761 false);
762
763 encoder->base.crtc = NULL;
764 }
765
766 if (encoder->sync_state)
767 encoder->sync_state(encoder, crtc_state);
768
769 drm_dbg_kms(&i915->drm,
770 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
771 encoder->base.base.id, encoder->base.name,
772 str_enabled_disabled(encoder->base.crtc),
773 pipe_name(pipe));
774 }
775
776 intel_dpll_readout_hw_state(display);
777
778 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
779 for_each_intel_connector_iter(connector, &conn_iter) {
780 struct intel_crtc_state *crtc_state = NULL;
781
782 if (connector->get_hw_state(connector)) {
783 struct intel_crtc *crtc;
784
785 connector->base.dpms = DRM_MODE_DPMS_ON;
786
787 encoder = intel_attached_encoder(connector);
788 connector->base.encoder = &encoder->base;
789
790 crtc = to_intel_crtc(encoder->base.crtc);
791 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
792
793 if (crtc_state && crtc_state->hw.active) {
794 /*
795 * This has to be done during hardware readout
796 * because anything calling .crtc_disable may
797 * rely on the connector_mask being accurate.
798 */
799 crtc_state->uapi.connector_mask |=
800 drm_connector_mask(&connector->base);
801 crtc_state->uapi.encoder_mask |=
802 drm_encoder_mask(&encoder->base);
803 }
804 } else {
805 connector->base.dpms = DRM_MODE_DPMS_OFF;
806 connector->base.encoder = NULL;
807 }
808
809 if (connector->sync_state)
810 connector->sync_state(connector, crtc_state);
811
812 drm_dbg_kms(&i915->drm,
813 "[CONNECTOR:%d:%s] hw state readout: %s\n",
814 connector->base.base.id, connector->base.name,
815 str_enabled_disabled(connector->base.encoder));
816 }
817 drm_connector_list_iter_end(&conn_iter);
818
819 for_each_intel_crtc(&i915->drm, crtc) {
820 struct intel_crtc_state *crtc_state =
821 to_intel_crtc_state(crtc->base.state);
822 struct intel_plane *plane;
823
824 if (crtc_state->hw.active) {
825 /*
826 * The initial mode needs to be set in order to keep
827 * the atomic core happy. It wants a valid mode if the
828 * crtc's enabled, so we do the above call.
829 *
830 * But we don't set all the derived state fully, hence
831 * set a flag to indicate that a full recalculation is
832 * needed on the next commit.
833 */
834 crtc_state->inherited = true;
835
836 intel_crtc_update_active_timings(crtc_state,
837 crtc_state->vrr.enable);
838
839 intel_crtc_copy_hw_to_uapi_state(crtc_state);
840 }
841
842 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
843 const struct intel_plane_state *plane_state =
844 to_intel_plane_state(plane->base.state);
845
846 /*
847 * FIXME don't have the fb yet, so can't
848 * use intel_plane_data_rate() :(
849 */
850 if (plane_state->uapi.visible)
851 crtc_state->data_rate[plane->id] =
852 4 * crtc_state->pixel_rate;
853 /*
854 * FIXME don't have the fb yet, so can't
855 * use plane->min_cdclk() :(
856 */
857 if (plane_state->uapi.visible && plane->min_cdclk) {
858 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
859 crtc_state->min_cdclk[plane->id] =
860 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
861 else
862 crtc_state->min_cdclk[plane->id] =
863 crtc_state->pixel_rate;
864 }
865 drm_dbg_kms(&i915->drm,
866 "[PLANE:%d:%s] min_cdclk %d kHz\n",
867 plane->base.base.id, plane->base.name,
868 crtc_state->min_cdclk[plane->id]);
869 }
870
871 intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
872 crtc_state->port_clock);
873 }
874
875 /* TODO move here (or even earlier?) on all platforms */
876 if (DISPLAY_VER(display) >= 9)
877 intel_wm_get_hw_state(i915);
878
879 intel_bw_update_hw_state(display);
880 intel_cdclk_update_hw_state(display);
881
882 intel_pmdemand_init_pmdemand_params(display, pmdemand_state);
883 }
884
885 static void
get_encoder_power_domains(struct drm_i915_private * i915)886 get_encoder_power_domains(struct drm_i915_private *i915)
887 {
888 struct intel_encoder *encoder;
889
890 for_each_intel_encoder(&i915->drm, encoder) {
891 struct intel_crtc_state *crtc_state;
892
893 if (!encoder->get_power_domains)
894 continue;
895
896 /*
897 * MST-primary and inactive encoders don't have a crtc state
898 * and neither of these require any power domain references.
899 */
900 if (!encoder->base.crtc)
901 continue;
902
903 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
904 encoder->get_power_domains(encoder, crtc_state);
905 }
906 }
907
intel_early_display_was(struct drm_i915_private * i915)908 static void intel_early_display_was(struct drm_i915_private *i915)
909 {
910 /*
911 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
912 * Also known as Wa_14010480278.
913 */
914 if (IS_DISPLAY_VER(i915, 10, 12))
915 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
916
917 /*
918 * WaRsPkgCStateDisplayPMReq:hsw
919 * System hang if this isn't done before disabling all planes!
920 */
921 if (IS_HASWELL(i915))
922 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
923
924 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
925 /* Display WA #1142:kbl,cfl,cml */
926 intel_de_rmw(i915, CHICKEN_PAR1_1,
927 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
928 intel_de_rmw(i915, CHICKEN_MISC_2,
929 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
930 KBL_ARB_FILL_SPARE_14);
931 }
932 }
933
intel_modeset_setup_hw_state(struct drm_i915_private * i915,struct drm_modeset_acquire_ctx * ctx)934 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
935 struct drm_modeset_acquire_ctx *ctx)
936 {
937 struct intel_display *display = &i915->display;
938 struct intel_encoder *encoder;
939 struct intel_crtc *crtc;
940 intel_wakeref_t wakeref;
941
942 wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
943
944 intel_early_display_was(i915);
945 intel_modeset_readout_hw_state(i915);
946
947 /* HW state is read out, now we need to sanitize this mess. */
948 get_encoder_power_domains(i915);
949
950 intel_pch_sanitize(i915);
951
952 intel_cmtg_sanitize(display);
953
954 /*
955 * intel_sanitize_plane_mapping() may need to do vblank
956 * waits, so we need vblank interrupts restored beforehand.
957 */
958 for_each_intel_crtc(&i915->drm, crtc) {
959 struct intel_crtc_state *crtc_state =
960 to_intel_crtc_state(crtc->base.state);
961
962 intel_sanitize_fifo_underrun_reporting(crtc_state);
963
964 drm_crtc_vblank_reset(&crtc->base);
965
966 if (crtc_state->hw.active) {
967 intel_dmc_enable_pipe(display, crtc->pipe);
968 intel_crtc_vblank_on(crtc_state);
969 }
970 }
971
972 intel_fbc_sanitize(&i915->display);
973
974 intel_sanitize_plane_mapping(i915);
975
976 for_each_intel_encoder(&i915->drm, encoder)
977 intel_sanitize_encoder(encoder);
978
979 /*
980 * Sanitizing CRTCs needs their connector atomic state to be
981 * up-to-date, so ensure that already here.
982 */
983 intel_modeset_update_connector_atomic_state(i915);
984
985 intel_sanitize_all_crtcs(i915, ctx);
986
987 intel_dpll_sanitize_state(display);
988
989 /* TODO move earlier on all platforms */
990 if (DISPLAY_VER(display) < 9)
991 intel_wm_get_hw_state(i915);
992 intel_wm_sanitize(i915);
993
994 for_each_intel_crtc(&i915->drm, crtc) {
995 struct intel_crtc_state *crtc_state =
996 to_intel_crtc_state(crtc->base.state);
997 struct intel_power_domain_mask put_domains;
998
999 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
1000 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
1001 intel_modeset_put_crtc_power_domains(crtc, &put_domains);
1002 }
1003
1004 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
1005
1006 intel_power_domains_sanitize_state(display);
1007 }
1008