1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_CDCLK_H__
7 #define __INTEL_CDCLK_H__
8 
9 #include <linux/types.h>
10 
11 #include "intel_display_limits.h"
12 #include "intel_global_state.h"
13 
14 struct intel_atomic_state;
15 struct intel_crtc;
16 struct intel_crtc_state;
17 struct intel_display;
18 
19 struct intel_cdclk_config {
20 	unsigned int cdclk, vco, ref, bypass;
21 	u8 voltage_level;
22 	/* This field is only valid for Xe2LPD and above. */
23 	bool joined_mbus;
24 };
25 
26 struct intel_cdclk_state {
27 	struct intel_global_state base;
28 
29 	/*
30 	 * Logical configuration of cdclk (used for all scaling,
31 	 * watermark, etc. calculations and checks). This is
32 	 * computed as if all enabled crtcs were active.
33 	 */
34 	struct intel_cdclk_config logical;
35 
36 	/*
37 	 * Actual configuration of cdclk, can be different from the
38 	 * logical configuration only when all crtc's are DPMS off.
39 	 */
40 	struct intel_cdclk_config actual;
41 
42 	/* minimum acceptable cdclk to satisfy bandwidth requirements */
43 	int bw_min_cdclk;
44 	/* minimum acceptable cdclk for each pipe */
45 	int min_cdclk[I915_MAX_PIPES];
46 	/* minimum acceptable voltage level for each pipe */
47 	u8 min_voltage_level[I915_MAX_PIPES];
48 
49 	/* pipe to which cd2x update is synchronized */
50 	enum pipe pipe;
51 
52 	/* forced minimum cdclk for glk+ audio w/a */
53 	int force_min_cdclk;
54 
55 	/* bitmask of active pipes */
56 	u8 active_pipes;
57 
58 	/* update cdclk with pipes disabled */
59 	bool disable_pipes;
60 };
61 
62 void intel_cdclk_init_hw(struct intel_display *display);
63 void intel_cdclk_uninit_hw(struct intel_display *display);
64 void intel_init_cdclk_hooks(struct intel_display *display);
65 void intel_update_max_cdclk(struct intel_display *display);
66 void intel_update_cdclk(struct intel_display *display);
67 u32 intel_read_rawclk(struct intel_display *display);
68 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
69 			       const struct intel_cdclk_config *b);
70 int intel_mdclk_cdclk_ratio(struct intel_display *display,
71 			    const struct intel_cdclk_config *cdclk_config);
72 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state);
73 void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
74 void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
75 void intel_cdclk_dump_config(struct intel_display *display,
76 			     const struct intel_cdclk_config *cdclk_config,
77 			     const char *context);
78 int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
79 void intel_cdclk_get_cdclk(struct intel_display *display,
80 			   struct intel_cdclk_config *cdclk_config);
81 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
82 			     bool *need_cdclk_calc);
83 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus);
84 struct intel_cdclk_state *
85 intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
86 void intel_cdclk_update_hw_state(struct intel_display *display);
87 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc);
88 
89 #define to_intel_cdclk_state(global_state) \
90 	container_of_const((global_state), struct intel_cdclk_state, base)
91 
92 #define intel_atomic_get_old_cdclk_state(state) \
93 	to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->cdclk.obj))
94 #define intel_atomic_get_new_cdclk_state(state) \
95 	to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.obj))
96 
97 int intel_cdclk_init(struct intel_display *display);
98 void intel_cdclk_debugfs_register(struct intel_display *display);
99 
100 #endif /* __INTEL_CDCLK_H__ */
101