1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_BW_H__ 7 #define __INTEL_BW_H__ 8 9 #include <drm/drm_atomic.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_display_power.h" 13 #include "intel_global_state.h" 14 15 struct drm_i915_private; 16 struct intel_atomic_state; 17 struct intel_crtc; 18 struct intel_crtc_state; 19 struct intel_display; 20 21 struct intel_dbuf_bw { 22 unsigned int max_bw[I915_MAX_DBUF_SLICES]; 23 u8 active_planes[I915_MAX_DBUF_SLICES]; 24 }; 25 26 struct intel_bw_state { 27 struct intel_global_state base; 28 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES]; 29 30 /* 31 * Contains a bit mask, used to determine, whether correspondent 32 * pipe allows SAGV or not. 33 */ 34 u8 pipe_sagv_reject; 35 36 /* bitmask of active pipes */ 37 u8 active_pipes; 38 39 /* 40 * From MTL onwards, to lock a QGV point, punit expects the peak BW of 41 * the selected QGV point as the parameter in multiples of 100MB/s 42 */ 43 u16 qgv_point_peakbw; 44 45 /* 46 * Current QGV points mask, which restricts 47 * some particular SAGV states, not to confuse 48 * with pipe_sagv_mask. 49 */ 50 u16 qgv_points_mask; 51 52 /* 53 * Flag to force the QGV comparison in atomic check right after the 54 * hw state readout 55 */ 56 bool force_check_qgv; 57 58 int min_cdclk[I915_MAX_PIPES]; 59 unsigned int data_rate[I915_MAX_PIPES]; 60 u8 num_active_planes[I915_MAX_PIPES]; 61 }; 62 63 #define to_intel_bw_state(global_state) \ 64 container_of_const((global_state), struct intel_bw_state, base) 65 66 struct intel_bw_state * 67 intel_atomic_get_old_bw_state(struct intel_atomic_state *state); 68 69 struct intel_bw_state * 70 intel_atomic_get_new_bw_state(struct intel_atomic_state *state); 71 72 struct intel_bw_state * 73 intel_atomic_get_bw_state(struct intel_atomic_state *state); 74 75 void intel_bw_init_hw(struct drm_i915_private *dev_priv); 76 int intel_bw_init(struct drm_i915_private *dev_priv); 77 int intel_bw_atomic_check(struct intel_atomic_state *state); 78 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, 79 u32 points_mask); 80 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, 81 bool *need_cdclk_calc); 82 int intel_bw_min_cdclk(struct drm_i915_private *i915, 83 const struct intel_bw_state *bw_state); 84 void intel_bw_update_hw_state(struct intel_display *display); 85 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc); 86 87 #endif /* __INTEL_BW_H__ */ 88