1 /*
2  * Copyright © 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 /**
25  * DOC: atomic plane helpers
26  *
27  * The functions here are used by the atomic plane helper functions to
28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
29  * drm_plane->disable_plane()).  This allows plane updates to use the
30  * atomic state infrastructure and perform plane updates as separate
31  * prepare/check/commit/cleanup steps.
32  */
33 
34 #include <linux/dma-fence-chain.h>
35 #include <linux/dma-resv.h>
36 
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_blend.h>
39 #include <drm/drm_damage_helper.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_gem.h>
42 #include <drm/drm_gem_atomic_helper.h>
43 
44 #include "gem/i915_gem_object.h"
45 #include "i915_config.h"
46 #include "i915_scheduler_types.h"
47 #include "i915_vma.h"
48 #include "i9xx_plane_regs.h"
49 #include "intel_atomic_plane.h"
50 #include "intel_cdclk.h"
51 #include "intel_cursor.h"
52 #include "intel_display_rps.h"
53 #include "intel_display_trace.h"
54 #include "intel_display_types.h"
55 #include "intel_fb.h"
56 #include "intel_fb_pin.h"
57 #include "skl_scaler.h"
58 #include "skl_universal_plane.h"
59 #include "skl_watermark.h"
60 
intel_plane_state_reset(struct intel_plane_state * plane_state,struct intel_plane * plane)61 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
62 				    struct intel_plane *plane)
63 {
64 	memset(plane_state, 0, sizeof(*plane_state));
65 
66 	__drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
67 
68 	plane_state->scaler_id = -1;
69 }
70 
intel_plane_alloc(void)71 struct intel_plane *intel_plane_alloc(void)
72 {
73 	struct intel_plane_state *plane_state;
74 	struct intel_plane *plane;
75 
76 	plane = kzalloc(sizeof(*plane), GFP_KERNEL);
77 	if (!plane)
78 		return ERR_PTR(-ENOMEM);
79 
80 	plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
81 	if (!plane_state) {
82 		kfree(plane);
83 		return ERR_PTR(-ENOMEM);
84 	}
85 
86 	intel_plane_state_reset(plane_state, plane);
87 
88 	plane->base.state = &plane_state->uapi;
89 
90 	return plane;
91 }
92 
intel_plane_free(struct intel_plane * plane)93 void intel_plane_free(struct intel_plane *plane)
94 {
95 	intel_plane_destroy_state(&plane->base, plane->base.state);
96 	kfree(plane);
97 }
98 
99 /**
100  * intel_plane_destroy - destroy a plane
101  * @plane: plane to destroy
102  *
103  * Common destruction function for all types of planes (primary, cursor,
104  * sprite).
105  */
intel_plane_destroy(struct drm_plane * plane)106 void intel_plane_destroy(struct drm_plane *plane)
107 {
108 	drm_plane_cleanup(plane);
109 	kfree(to_intel_plane(plane));
110 }
111 
112 /**
113  * intel_plane_duplicate_state - duplicate plane state
114  * @plane: drm plane
115  *
116  * Allocates and returns a copy of the plane state (both common and
117  * Intel-specific) for the specified plane.
118  *
119  * Returns: The newly allocated plane state, or NULL on failure.
120  */
121 struct drm_plane_state *
intel_plane_duplicate_state(struct drm_plane * plane)122 intel_plane_duplicate_state(struct drm_plane *plane)
123 {
124 	struct intel_plane_state *intel_state;
125 
126 	intel_state = to_intel_plane_state(plane->state);
127 	intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
128 
129 	if (!intel_state)
130 		return NULL;
131 
132 	__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
133 
134 	intel_state->ggtt_vma = NULL;
135 	intel_state->dpt_vma = NULL;
136 	intel_state->flags = 0;
137 	intel_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
138 
139 	/* add reference to fb */
140 	if (intel_state->hw.fb)
141 		drm_framebuffer_get(intel_state->hw.fb);
142 
143 	return &intel_state->uapi;
144 }
145 
146 /**
147  * intel_plane_destroy_state - destroy plane state
148  * @plane: drm plane
149  * @state: state object to destroy
150  *
151  * Destroys the plane state (both common and Intel-specific) for the
152  * specified plane.
153  */
154 void
intel_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)155 intel_plane_destroy_state(struct drm_plane *plane,
156 			  struct drm_plane_state *state)
157 {
158 	struct intel_plane_state *plane_state = to_intel_plane_state(state);
159 
160 	drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
161 	drm_WARN_ON(plane->dev, plane_state->dpt_vma);
162 
163 	__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
164 	if (plane_state->hw.fb)
165 		drm_framebuffer_put(plane_state->hw.fb);
166 	kfree(plane_state);
167 }
168 
intel_plane_needs_physical(struct intel_plane * plane)169 bool intel_plane_needs_physical(struct intel_plane *plane)
170 {
171 	struct intel_display *display = to_intel_display(plane);
172 
173 	return plane->id == PLANE_CURSOR &&
174 		DISPLAY_INFO(display)->cursor_needs_physical;
175 }
176 
intel_plane_can_async_flip(struct intel_plane * plane,u64 modifier)177 bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier)
178 {
179 	return plane->can_async_flip && plane->can_async_flip(modifier);
180 }
181 
intel_adjusted_rate(const struct drm_rect * src,const struct drm_rect * dst,unsigned int rate)182 unsigned int intel_adjusted_rate(const struct drm_rect *src,
183 				 const struct drm_rect *dst,
184 				 unsigned int rate)
185 {
186 	unsigned int src_w, src_h, dst_w, dst_h;
187 
188 	src_w = drm_rect_width(src) >> 16;
189 	src_h = drm_rect_height(src) >> 16;
190 	dst_w = drm_rect_width(dst);
191 	dst_h = drm_rect_height(dst);
192 
193 	/* Downscaling limits the maximum pixel rate */
194 	dst_w = min(src_w, dst_w);
195 	dst_h = min(src_h, dst_h);
196 
197 	return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
198 				dst_w * dst_h);
199 }
200 
intel_plane_pixel_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)201 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
202 				    const struct intel_plane_state *plane_state)
203 {
204 	/*
205 	 * Note we don't check for plane visibility here as
206 	 * we want to use this when calculating the cursor
207 	 * watermarks even if the cursor is fully offscreen.
208 	 * That depends on the src/dst rectangles being
209 	 * correctly populated whenever the watermark code
210 	 * considers the cursor to be visible, whether or not
211 	 * it is actually visible.
212 	 *
213 	 * See: intel_wm_plane_visible() and intel_check_cursor()
214 	 */
215 
216 	return intel_adjusted_rate(&plane_state->uapi.src,
217 				   &plane_state->uapi.dst,
218 				   crtc_state->pixel_rate);
219 }
220 
intel_plane_data_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)221 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
222 				   const struct intel_plane_state *plane_state,
223 				   int color_plane)
224 {
225 	const struct drm_framebuffer *fb = plane_state->hw.fb;
226 
227 	if (!plane_state->uapi.visible)
228 		return 0;
229 
230 	return intel_plane_pixel_rate(crtc_state, plane_state) *
231 		fb->format->cpp[color_plane];
232 }
233 
234 static unsigned int
intel_plane_relative_data_rate(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,int color_plane)235 intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
236 			       const struct intel_plane_state *plane_state,
237 			       int color_plane)
238 {
239 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
240 	const struct drm_framebuffer *fb = plane_state->hw.fb;
241 	unsigned int rel_data_rate;
242 	int width, height;
243 
244 	if (plane->id == PLANE_CURSOR)
245 		return 0;
246 
247 	if (!plane_state->uapi.visible)
248 		return 0;
249 
250 	/*
251 	 * Src coordinates are already rotated by 270 degrees for
252 	 * the 90/270 degree plane rotation cases (to match the
253 	 * GTT mapping), hence no need to account for rotation here.
254 	 */
255 	width = drm_rect_width(&plane_state->uapi.src) >> 16;
256 	height = drm_rect_height(&plane_state->uapi.src) >> 16;
257 
258 	/* UV plane does 1/2 pixel sub-sampling */
259 	if (color_plane == 1) {
260 		width /= 2;
261 		height /= 2;
262 	}
263 
264 	rel_data_rate =
265 		skl_plane_relative_data_rate(crtc_state, plane, width, height,
266 					     fb->format->cpp[color_plane]);
267 	if (!rel_data_rate)
268 		return 0;
269 
270 	return intel_adjusted_rate(&plane_state->uapi.src,
271 				   &plane_state->uapi.dst,
272 				   rel_data_rate);
273 }
274 
intel_plane_calc_min_cdclk(struct intel_atomic_state * state,struct intel_plane * plane,bool * need_cdclk_calc)275 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
276 			       struct intel_plane *plane,
277 			       bool *need_cdclk_calc)
278 {
279 	struct intel_display *display = to_intel_display(plane);
280 	const struct intel_plane_state *plane_state =
281 		intel_atomic_get_new_plane_state(state, plane);
282 	struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
283 	const struct intel_cdclk_state *cdclk_state;
284 	const struct intel_crtc_state *old_crtc_state;
285 	struct intel_crtc_state *new_crtc_state;
286 
287 	if (!plane_state->uapi.visible || !plane->min_cdclk)
288 		return 0;
289 
290 	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
291 	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
292 
293 	new_crtc_state->min_cdclk[plane->id] =
294 		plane->min_cdclk(new_crtc_state, plane_state);
295 
296 	/*
297 	 * No need to check against the cdclk state if
298 	 * the min cdclk for the plane doesn't increase.
299 	 *
300 	 * Ie. we only ever increase the cdclk due to plane
301 	 * requirements. This can reduce back and forth
302 	 * display blinking due to constant cdclk changes.
303 	 */
304 	if (new_crtc_state->min_cdclk[plane->id] <=
305 	    old_crtc_state->min_cdclk[plane->id])
306 		return 0;
307 
308 	cdclk_state = intel_atomic_get_cdclk_state(state);
309 	if (IS_ERR(cdclk_state))
310 		return PTR_ERR(cdclk_state);
311 
312 	/*
313 	 * No need to recalculate the cdclk state if
314 	 * the min cdclk for the pipe doesn't increase.
315 	 *
316 	 * Ie. we only ever increase the cdclk due to plane
317 	 * requirements. This can reduce back and forth
318 	 * display blinking due to constant cdclk changes.
319 	 */
320 	if (new_crtc_state->min_cdclk[plane->id] <=
321 	    cdclk_state->min_cdclk[crtc->pipe])
322 		return 0;
323 
324 	drm_dbg_kms(display->drm,
325 		    "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
326 		    plane->base.base.id, plane->base.name,
327 		    new_crtc_state->min_cdclk[plane->id],
328 		    crtc->base.base.id, crtc->base.name,
329 		    cdclk_state->min_cdclk[crtc->pipe]);
330 	*need_cdclk_calc = true;
331 
332 	return 0;
333 }
334 
intel_plane_clear_hw_state(struct intel_plane_state * plane_state)335 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
336 {
337 	if (plane_state->hw.fb)
338 		drm_framebuffer_put(plane_state->hw.fb);
339 
340 	memset(&plane_state->hw, 0, sizeof(plane_state->hw));
341 }
342 
343 static void
intel_plane_copy_uapi_plane_damage(struct intel_plane_state * new_plane_state,const struct intel_plane_state * old_uapi_plane_state,const struct intel_plane_state * new_uapi_plane_state)344 intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state,
345 				   const struct intel_plane_state *old_uapi_plane_state,
346 				   const struct intel_plane_state *new_uapi_plane_state)
347 {
348 	struct intel_display *display = to_intel_display(new_plane_state);
349 	struct drm_rect *damage = &new_plane_state->damage;
350 
351 	/* damage property tracking enabled from display version 12 onwards */
352 	if (DISPLAY_VER(display) < 12)
353 		return;
354 
355 	if (!drm_atomic_helper_damage_merged(&old_uapi_plane_state->uapi,
356 					     &new_uapi_plane_state->uapi,
357 					     damage))
358 		/* Incase helper fails, mark whole plane region as damage */
359 		*damage = drm_plane_state_src(&new_uapi_plane_state->uapi);
360 }
361 
intel_plane_copy_uapi_to_hw_state(struct intel_plane_state * plane_state,const struct intel_plane_state * from_plane_state,struct intel_crtc * crtc)362 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
363 				       const struct intel_plane_state *from_plane_state,
364 				       struct intel_crtc *crtc)
365 {
366 	intel_plane_clear_hw_state(plane_state);
367 
368 	/*
369 	 * For the joiner secondary uapi.crtc will point at
370 	 * the primary crtc. So we explicitly assign the right
371 	 * secondary crtc to hw.crtc. uapi.crtc!=NULL simply
372 	 * indicates the plane is logically enabled on the uapi level.
373 	 */
374 	plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
375 
376 	plane_state->hw.fb = from_plane_state->uapi.fb;
377 	if (plane_state->hw.fb)
378 		drm_framebuffer_get(plane_state->hw.fb);
379 
380 	plane_state->hw.alpha = from_plane_state->uapi.alpha;
381 	plane_state->hw.pixel_blend_mode =
382 		from_plane_state->uapi.pixel_blend_mode;
383 	plane_state->hw.rotation = from_plane_state->uapi.rotation;
384 	plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
385 	plane_state->hw.color_range = from_plane_state->uapi.color_range;
386 	plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
387 
388 	plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
389 	plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
390 }
391 
intel_plane_copy_hw_state(struct intel_plane_state * plane_state,const struct intel_plane_state * from_plane_state)392 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
393 			       const struct intel_plane_state *from_plane_state)
394 {
395 	intel_plane_clear_hw_state(plane_state);
396 
397 	memcpy(&plane_state->hw, &from_plane_state->hw,
398 	       sizeof(plane_state->hw));
399 
400 	if (plane_state->hw.fb)
401 		drm_framebuffer_get(plane_state->hw.fb);
402 }
403 
intel_plane_set_invisible(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)404 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
405 			       struct intel_plane_state *plane_state)
406 {
407 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
408 
409 	crtc_state->active_planes &= ~BIT(plane->id);
410 	crtc_state->scaled_planes &= ~BIT(plane->id);
411 	crtc_state->nv12_planes &= ~BIT(plane->id);
412 	crtc_state->c8_planes &= ~BIT(plane->id);
413 	crtc_state->async_flip_planes &= ~BIT(plane->id);
414 	crtc_state->data_rate[plane->id] = 0;
415 	crtc_state->data_rate_y[plane->id] = 0;
416 	crtc_state->rel_data_rate[plane->id] = 0;
417 	crtc_state->rel_data_rate_y[plane->id] = 0;
418 	crtc_state->min_cdclk[plane->id] = 0;
419 
420 	plane_state->uapi.visible = false;
421 }
422 
intel_plane_is_scaled(const struct intel_plane_state * plane_state)423 static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
424 {
425 	int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
426 	int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
427 	int dst_w = drm_rect_width(&plane_state->uapi.dst);
428 	int dst_h = drm_rect_height(&plane_state->uapi.dst);
429 
430 	return src_w != dst_w || src_h != dst_h;
431 }
432 
intel_plane_do_async_flip(struct intel_plane * plane,const struct intel_crtc_state * old_crtc_state,const struct intel_crtc_state * new_crtc_state)433 static bool intel_plane_do_async_flip(struct intel_plane *plane,
434 				      const struct intel_crtc_state *old_crtc_state,
435 				      const struct intel_crtc_state *new_crtc_state)
436 {
437 	struct intel_display *display = to_intel_display(plane);
438 
439 	if (!plane->async_flip)
440 		return false;
441 
442 	if (!new_crtc_state->uapi.async_flip)
443 		return false;
444 
445 	/*
446 	 * In platforms after DISPLAY13, we might need to override
447 	 * first async flip in order to change watermark levels
448 	 * as part of optimization.
449 	 *
450 	 * And let's do this for all skl+ so that we can eg. change the
451 	 * modifier as well.
452 	 *
453 	 * TODO: For older platforms there is less reason to do this as
454 	 * only X-tile is supported with async flips, though we could
455 	 * extend this so other scanout parameters (stride/etc) could
456 	 * be changed as well...
457 	 */
458 	return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip;
459 }
460 
i9xx_must_disable_cxsr(const struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,const struct intel_plane_state * new_plane_state)461 static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
462 				   const struct intel_plane_state *old_plane_state,
463 				   const struct intel_plane_state *new_plane_state)
464 {
465 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
466 	bool old_visible = old_plane_state->uapi.visible;
467 	bool new_visible = new_plane_state->uapi.visible;
468 	u32 old_ctl = old_plane_state->ctl;
469 	u32 new_ctl = new_plane_state->ctl;
470 	bool modeset, turn_on, turn_off;
471 
472 	if (plane->id == PLANE_CURSOR)
473 		return false;
474 
475 	modeset = intel_crtc_needs_modeset(new_crtc_state);
476 	turn_off = old_visible && (!new_visible || modeset);
477 	turn_on = new_visible && (!old_visible || modeset);
478 
479 	/* Must disable CxSR around plane enable/disable */
480 	if (turn_on || turn_off)
481 		return true;
482 
483 	if (!old_visible || !new_visible)
484 		return false;
485 
486 	/*
487 	 * Most plane control register updates are blocked while in CxSR.
488 	 *
489 	 * Tiling mode is one exception where the primary plane can
490 	 * apparently handle it, whereas the sprites can not (the
491 	 * sprite issue being only relevant on VLV/CHV where CxSR
492 	 * is actually possible with a sprite enabled).
493 	 */
494 	if (plane->id == PLANE_PRIMARY) {
495 		old_ctl &= ~DISP_TILED;
496 		new_ctl &= ~DISP_TILED;
497 	}
498 
499 	return old_ctl != new_ctl;
500 }
501 
ilk_must_disable_cxsr(const struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,const struct intel_plane_state * new_plane_state)502 static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
503 				  const struct intel_plane_state *old_plane_state,
504 				  const struct intel_plane_state *new_plane_state)
505 {
506 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
507 	bool old_visible = old_plane_state->uapi.visible;
508 	bool new_visible = new_plane_state->uapi.visible;
509 	bool modeset, turn_on;
510 
511 	if (plane->id == PLANE_CURSOR)
512 		return false;
513 
514 	modeset = intel_crtc_needs_modeset(new_crtc_state);
515 	turn_on = new_visible && (!old_visible || modeset);
516 
517 	/*
518 	 * ILK/SNB DVSACNTR/Sprite Enable
519 	 * IVB SPR_CTL/Sprite Enable
520 	 * "When in Self Refresh Big FIFO mode, a write to enable the
521 	 *  plane will be internally buffered and delayed while Big FIFO
522 	 *  mode is exiting."
523 	 *
524 	 * Which means that enabling the sprite can take an extra frame
525 	 * when we start in big FIFO mode (LP1+). Thus we need to drop
526 	 * down to LP0 and wait for vblank in order to make sure the
527 	 * sprite gets enabled on the next vblank after the register write.
528 	 * Doing otherwise would risk enabling the sprite one frame after
529 	 * we've already signalled flip completion. We can resume LP1+
530 	 * once the sprite has been enabled.
531 	 *
532 	 * With experimental results seems this is needed also for primary
533 	 * plane, not only sprite plane.
534 	 */
535 	if (turn_on)
536 		return true;
537 
538 	/*
539 	 * WaCxSRDisabledForSpriteScaling:ivb
540 	 * IVB SPR_SCALE/Scaling Enable
541 	 * "Low Power watermarks must be disabled for at least one
542 	 *  frame before enabling sprite scaling, and kept disabled
543 	 *  until sprite scaling is disabled."
544 	 *
545 	 * ILK/SNB DVSASCALE/Scaling Enable
546 	 * "When in Self Refresh Big FIFO mode, scaling enable will be
547 	 *  masked off while Big FIFO mode is exiting."
548 	 *
549 	 * Despite the w/a only being listed for IVB we assume that
550 	 * the ILK/SNB note has similar ramifications, hence we apply
551 	 * the w/a on all three platforms.
552 	 */
553 	return !intel_plane_is_scaled(old_plane_state) &&
554 		intel_plane_is_scaled(new_plane_state);
555 }
556 
intel_plane_atomic_calc_changes(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)557 static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
558 					   struct intel_crtc_state *new_crtc_state,
559 					   const struct intel_plane_state *old_plane_state,
560 					   struct intel_plane_state *new_plane_state)
561 {
562 	struct intel_display *display = to_intel_display(new_crtc_state);
563 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
564 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
565 	bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
566 	bool was_crtc_enabled = old_crtc_state->hw.active;
567 	bool is_crtc_enabled = new_crtc_state->hw.active;
568 	bool turn_off, turn_on, visible, was_visible;
569 	int ret;
570 
571 	if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) {
572 		ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
573 		if (ret)
574 			return ret;
575 	}
576 
577 	was_visible = old_plane_state->uapi.visible;
578 	visible = new_plane_state->uapi.visible;
579 
580 	if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible))
581 		was_visible = false;
582 
583 	/*
584 	 * Visibility is calculated as if the crtc was on, but
585 	 * after scaler setup everything depends on it being off
586 	 * when the crtc isn't active.
587 	 *
588 	 * FIXME this is wrong for watermarks. Watermarks should also
589 	 * be computed as if the pipe would be active. Perhaps move
590 	 * per-plane wm computation to the .check_plane() hook, and
591 	 * only combine the results from all planes in the current place?
592 	 */
593 	if (!is_crtc_enabled) {
594 		intel_plane_set_invisible(new_crtc_state, new_plane_state);
595 		visible = false;
596 	}
597 
598 	if (!was_visible && !visible)
599 		return 0;
600 
601 	turn_off = was_visible && (!visible || mode_changed);
602 	turn_on = visible && (!was_visible || mode_changed);
603 
604 	drm_dbg_atomic(display->drm,
605 		       "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
606 		       crtc->base.base.id, crtc->base.name,
607 		       plane->base.base.id, plane->base.name,
608 		       was_visible, visible,
609 		       turn_off, turn_on, mode_changed);
610 
611 	if (visible || was_visible)
612 		new_crtc_state->fb_bits |= plane->frontbuffer_bit;
613 
614 	if (HAS_GMCH(display) &&
615 	    i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
616 		new_crtc_state->disable_cxsr = true;
617 
618 	if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) &&
619 	    ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
620 		new_crtc_state->disable_cxsr = true;
621 
622 	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
623 		new_crtc_state->do_async_flip = true;
624 		new_crtc_state->async_flip_planes |= BIT(plane->id);
625 	} else if (plane->need_async_flip_toggle_wa &&
626 		   new_crtc_state->uapi.async_flip) {
627 		/*
628 		 * On platforms with double buffered async flip bit we
629 		 * set the bit already one frame early during the sync
630 		 * flip (see {i9xx,skl}_plane_update_arm()). The
631 		 * hardware will therefore be ready to perform a real
632 		 * async flip during the next commit, without having
633 		 * to wait yet another frame for the bit to latch.
634 		 */
635 		new_crtc_state->async_flip_planes |= BIT(plane->id);
636 	}
637 
638 	return 0;
639 }
640 
intel_plane_atomic_check_with_state(const struct intel_crtc_state * old_crtc_state,struct intel_crtc_state * new_crtc_state,const struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)641 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
642 					struct intel_crtc_state *new_crtc_state,
643 					const struct intel_plane_state *old_plane_state,
644 					struct intel_plane_state *new_plane_state)
645 {
646 	struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
647 	const struct drm_framebuffer *fb = new_plane_state->hw.fb;
648 	int ret;
649 
650 	intel_plane_set_invisible(new_crtc_state, new_plane_state);
651 	new_crtc_state->enabled_planes &= ~BIT(plane->id);
652 
653 	if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
654 		return 0;
655 
656 	ret = plane->check_plane(new_crtc_state, new_plane_state);
657 	if (ret)
658 		return ret;
659 
660 	if (fb)
661 		new_crtc_state->enabled_planes |= BIT(plane->id);
662 
663 	/* FIXME pre-g4x don't work like this */
664 	if (new_plane_state->uapi.visible)
665 		new_crtc_state->active_planes |= BIT(plane->id);
666 
667 	if (new_plane_state->uapi.visible &&
668 	    intel_plane_is_scaled(new_plane_state))
669 		new_crtc_state->scaled_planes |= BIT(plane->id);
670 
671 	if (new_plane_state->uapi.visible &&
672 	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
673 		new_crtc_state->nv12_planes |= BIT(plane->id);
674 
675 	if (new_plane_state->uapi.visible &&
676 	    fb->format->format == DRM_FORMAT_C8)
677 		new_crtc_state->c8_planes |= BIT(plane->id);
678 
679 	if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
680 		new_crtc_state->update_planes |= BIT(plane->id);
681 
682 	if (new_plane_state->uapi.visible &&
683 	    intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
684 		new_crtc_state->data_rate_y[plane->id] =
685 			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
686 		new_crtc_state->data_rate[plane->id] =
687 			intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
688 
689 		new_crtc_state->rel_data_rate_y[plane->id] =
690 			intel_plane_relative_data_rate(new_crtc_state,
691 						       new_plane_state, 0);
692 		new_crtc_state->rel_data_rate[plane->id] =
693 			intel_plane_relative_data_rate(new_crtc_state,
694 						       new_plane_state, 1);
695 	} else if (new_plane_state->uapi.visible) {
696 		new_crtc_state->data_rate[plane->id] =
697 			intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
698 
699 		new_crtc_state->rel_data_rate[plane->id] =
700 			intel_plane_relative_data_rate(new_crtc_state,
701 						       new_plane_state, 0);
702 	}
703 
704 	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
705 					       old_plane_state, new_plane_state);
706 }
707 
708 struct intel_plane *
intel_crtc_get_plane(struct intel_crtc * crtc,enum plane_id plane_id)709 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
710 {
711 	struct intel_display *display = to_intel_display(crtc);
712 	struct intel_plane *plane;
713 
714 	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
715 		if (plane->id == plane_id)
716 			return plane;
717 	}
718 
719 	return NULL;
720 }
721 
intel_plane_atomic_check(struct intel_atomic_state * state,struct intel_plane * plane)722 int intel_plane_atomic_check(struct intel_atomic_state *state,
723 			     struct intel_plane *plane)
724 {
725 	struct intel_display *display = to_intel_display(state);
726 	struct intel_plane_state *new_plane_state =
727 		intel_atomic_get_new_plane_state(state, plane);
728 	const struct intel_plane_state *old_plane_state =
729 		intel_atomic_get_old_plane_state(state, plane);
730 	const struct intel_plane_state *new_primary_crtc_plane_state;
731 	const struct intel_plane_state *old_primary_crtc_plane_state;
732 	struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe);
733 	const struct intel_crtc_state *old_crtc_state =
734 		intel_atomic_get_old_crtc_state(state, crtc);
735 	struct intel_crtc_state *new_crtc_state =
736 		intel_atomic_get_new_crtc_state(state, crtc);
737 
738 	if (new_crtc_state && intel_crtc_is_joiner_secondary(new_crtc_state)) {
739 		struct intel_crtc *primary_crtc =
740 			intel_primary_crtc(new_crtc_state);
741 		struct intel_plane *primary_crtc_plane =
742 			intel_crtc_get_plane(primary_crtc, plane->id);
743 
744 		new_primary_crtc_plane_state =
745 			intel_atomic_get_new_plane_state(state, primary_crtc_plane);
746 		old_primary_crtc_plane_state =
747 			intel_atomic_get_old_plane_state(state, primary_crtc_plane);
748 	} else {
749 		new_primary_crtc_plane_state = new_plane_state;
750 		old_primary_crtc_plane_state = old_plane_state;
751 	}
752 
753 	intel_plane_copy_uapi_plane_damage(new_plane_state,
754 					   old_primary_crtc_plane_state,
755 					   new_primary_crtc_plane_state);
756 
757 	intel_plane_copy_uapi_to_hw_state(new_plane_state,
758 					  new_primary_crtc_plane_state,
759 					  crtc);
760 
761 	new_plane_state->uapi.visible = false;
762 	if (!new_crtc_state)
763 		return 0;
764 
765 	return intel_plane_atomic_check_with_state(old_crtc_state,
766 						   new_crtc_state,
767 						   old_plane_state,
768 						   new_plane_state);
769 }
770 
771 static struct intel_plane *
skl_next_plane_to_commit(struct intel_atomic_state * state,struct intel_crtc * crtc,struct skl_ddb_entry ddb[I915_MAX_PLANES],struct skl_ddb_entry ddb_y[I915_MAX_PLANES],unsigned int * update_mask)772 skl_next_plane_to_commit(struct intel_atomic_state *state,
773 			 struct intel_crtc *crtc,
774 			 struct skl_ddb_entry ddb[I915_MAX_PLANES],
775 			 struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
776 			 unsigned int *update_mask)
777 {
778 	struct intel_crtc_state *crtc_state =
779 		intel_atomic_get_new_crtc_state(state, crtc);
780 	struct intel_plane_state __maybe_unused *plane_state;
781 	struct intel_plane *plane;
782 	int i;
783 
784 	if (*update_mask == 0)
785 		return NULL;
786 
787 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
788 		enum plane_id plane_id = plane->id;
789 
790 		if (crtc->pipe != plane->pipe ||
791 		    !(*update_mask & BIT(plane_id)))
792 			continue;
793 
794 		if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
795 						ddb, I915_MAX_PLANES, plane_id) ||
796 		    skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
797 						ddb_y, I915_MAX_PLANES, plane_id))
798 			continue;
799 
800 		*update_mask &= ~BIT(plane_id);
801 		ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
802 		ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
803 
804 		return plane;
805 	}
806 
807 	/* should never happen */
808 	drm_WARN_ON(state->base.dev, 1);
809 
810 	return NULL;
811 }
812 
intel_plane_update_noarm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)813 void intel_plane_update_noarm(struct intel_dsb *dsb,
814 			      struct intel_plane *plane,
815 			      const struct intel_crtc_state *crtc_state,
816 			      const struct intel_plane_state *plane_state)
817 {
818 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
819 
820 	trace_intel_plane_update_noarm(plane_state, crtc);
821 
822 	if (plane->fbc)
823 		intel_fbc_dirty_rect_update_noarm(dsb, plane);
824 
825 	if (plane->update_noarm)
826 		plane->update_noarm(dsb, plane, crtc_state, plane_state);
827 }
828 
intel_plane_async_flip(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,bool async_flip)829 void intel_plane_async_flip(struct intel_dsb *dsb,
830 			    struct intel_plane *plane,
831 			    const struct intel_crtc_state *crtc_state,
832 			    const struct intel_plane_state *plane_state,
833 			    bool async_flip)
834 {
835 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
836 
837 	trace_intel_plane_async_flip(plane, crtc, async_flip);
838 	plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip);
839 }
840 
intel_plane_update_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)841 void intel_plane_update_arm(struct intel_dsb *dsb,
842 			    struct intel_plane *plane,
843 			    const struct intel_crtc_state *crtc_state,
844 			    const struct intel_plane_state *plane_state)
845 {
846 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
847 
848 	if (crtc_state->do_async_flip && plane->async_flip) {
849 		intel_plane_async_flip(dsb, plane, crtc_state, plane_state, true);
850 		return;
851 	}
852 
853 	trace_intel_plane_update_arm(plane_state, crtc);
854 	plane->update_arm(dsb, plane, crtc_state, plane_state);
855 }
856 
intel_plane_disable_arm(struct intel_dsb * dsb,struct intel_plane * plane,const struct intel_crtc_state * crtc_state)857 void intel_plane_disable_arm(struct intel_dsb *dsb,
858 			     struct intel_plane *plane,
859 			     const struct intel_crtc_state *crtc_state)
860 {
861 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
862 
863 	trace_intel_plane_disable_arm(plane, crtc);
864 	plane->disable_arm(dsb, plane, crtc_state);
865 }
866 
intel_crtc_planes_update_noarm(struct intel_dsb * dsb,struct intel_atomic_state * state,struct intel_crtc * crtc)867 void intel_crtc_planes_update_noarm(struct intel_dsb *dsb,
868 				    struct intel_atomic_state *state,
869 				    struct intel_crtc *crtc)
870 {
871 	struct intel_crtc_state *new_crtc_state =
872 		intel_atomic_get_new_crtc_state(state, crtc);
873 	u32 update_mask = new_crtc_state->update_planes;
874 	struct intel_plane_state *new_plane_state;
875 	struct intel_plane *plane;
876 	int i;
877 
878 	if (new_crtc_state->do_async_flip)
879 		return;
880 
881 	/*
882 	 * Since we only write non-arming registers here,
883 	 * the order does not matter even for skl+.
884 	 */
885 	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
886 		if (crtc->pipe != plane->pipe ||
887 		    !(update_mask & BIT(plane->id)))
888 			continue;
889 
890 		/* TODO: for mailbox updates this should be skipped */
891 		if (new_plane_state->uapi.visible ||
892 		    new_plane_state->is_y_plane)
893 			intel_plane_update_noarm(dsb, plane,
894 						 new_crtc_state, new_plane_state);
895 	}
896 }
897 
skl_crtc_planes_update_arm(struct intel_dsb * dsb,struct intel_atomic_state * state,struct intel_crtc * crtc)898 static void skl_crtc_planes_update_arm(struct intel_dsb *dsb,
899 				       struct intel_atomic_state *state,
900 				       struct intel_crtc *crtc)
901 {
902 	struct intel_crtc_state *old_crtc_state =
903 		intel_atomic_get_old_crtc_state(state, crtc);
904 	struct intel_crtc_state *new_crtc_state =
905 		intel_atomic_get_new_crtc_state(state, crtc);
906 	struct skl_ddb_entry ddb[I915_MAX_PLANES];
907 	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
908 	u32 update_mask = new_crtc_state->update_planes;
909 	struct intel_plane *plane;
910 
911 	memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
912 	       sizeof(old_crtc_state->wm.skl.plane_ddb));
913 	memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
914 	       sizeof(old_crtc_state->wm.skl.plane_ddb_y));
915 
916 	while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
917 		struct intel_plane_state *new_plane_state =
918 			intel_atomic_get_new_plane_state(state, plane);
919 
920 		/*
921 		 * TODO: for mailbox updates intel_plane_update_noarm()
922 		 * would have to be called here as well.
923 		 */
924 		if (new_plane_state->uapi.visible ||
925 		    new_plane_state->is_y_plane)
926 			intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);
927 		else
928 			intel_plane_disable_arm(dsb, plane, new_crtc_state);
929 	}
930 }
931 
i9xx_crtc_planes_update_arm(struct intel_dsb * dsb,struct intel_atomic_state * state,struct intel_crtc * crtc)932 static void i9xx_crtc_planes_update_arm(struct intel_dsb *dsb,
933 					struct intel_atomic_state *state,
934 					struct intel_crtc *crtc)
935 {
936 	struct intel_crtc_state *new_crtc_state =
937 		intel_atomic_get_new_crtc_state(state, crtc);
938 	u32 update_mask = new_crtc_state->update_planes;
939 	struct intel_plane_state *new_plane_state;
940 	struct intel_plane *plane;
941 	int i;
942 
943 	for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
944 		if (crtc->pipe != plane->pipe ||
945 		    !(update_mask & BIT(plane->id)))
946 			continue;
947 
948 		/*
949 		 * TODO: for mailbox updates intel_plane_update_noarm()
950 		 * would have to be called here as well.
951 		 */
952 		if (new_plane_state->uapi.visible)
953 			intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state);
954 		else
955 			intel_plane_disable_arm(dsb, plane, new_crtc_state);
956 	}
957 }
958 
intel_crtc_planes_update_arm(struct intel_dsb * dsb,struct intel_atomic_state * state,struct intel_crtc * crtc)959 void intel_crtc_planes_update_arm(struct intel_dsb *dsb,
960 				  struct intel_atomic_state *state,
961 				  struct intel_crtc *crtc)
962 {
963 	struct intel_display *display = to_intel_display(state);
964 
965 	if (DISPLAY_VER(display) >= 9)
966 		skl_crtc_planes_update_arm(dsb, state, crtc);
967 	else
968 		i9xx_crtc_planes_update_arm(dsb, state, crtc);
969 }
970 
intel_atomic_plane_check_clipping(struct intel_plane_state * plane_state,struct intel_crtc_state * crtc_state,int min_scale,int max_scale,bool can_position)971 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
972 				      struct intel_crtc_state *crtc_state,
973 				      int min_scale, int max_scale,
974 				      bool can_position)
975 {
976 	struct intel_display *display = to_intel_display(plane_state);
977 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
978 	struct drm_framebuffer *fb = plane_state->hw.fb;
979 	struct drm_rect *src = &plane_state->uapi.src;
980 	struct drm_rect *dst = &plane_state->uapi.dst;
981 	const struct drm_rect *clip = &crtc_state->pipe_src;
982 	unsigned int rotation = plane_state->hw.rotation;
983 	int hscale, vscale;
984 
985 	if (!fb) {
986 		plane_state->uapi.visible = false;
987 		return 0;
988 	}
989 
990 	drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
991 
992 	/* Check scaling */
993 	hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
994 	vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
995 	if (hscale < 0 || vscale < 0) {
996 		drm_dbg_kms(display->drm,
997 			    "[PLANE:%d:%s] invalid scaling "DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n",
998 			    plane->base.base.id, plane->base.name,
999 			    DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst));
1000 		return -ERANGE;
1001 	}
1002 
1003 	/*
1004 	 * FIXME: This might need further adjustment for seamless scaling
1005 	 * with phase information, for the 2p2 and 2p1 scenarios.
1006 	 */
1007 	plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
1008 
1009 	drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
1010 
1011 	if (!can_position && plane_state->uapi.visible &&
1012 	    !drm_rect_equals(dst, clip)) {
1013 		drm_dbg_kms(display->drm,
1014 			    "[PLANE:%d:%s] plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n",
1015 			    plane->base.base.id, plane->base.name,
1016 			    DRM_RECT_ARG(dst), DRM_RECT_ARG(clip));
1017 		return -EINVAL;
1018 	}
1019 
1020 	/* final plane coordinates will be relative to the plane's pipe */
1021 	drm_rect_translate(dst, -clip->x1, -clip->y1);
1022 
1023 	return 0;
1024 }
1025 
intel_plane_check_src_coordinates(struct intel_plane_state * plane_state)1026 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
1027 {
1028 	struct intel_display *display = to_intel_display(plane_state);
1029 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1030 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1031 	struct drm_rect *src = &plane_state->uapi.src;
1032 	u32 src_x, src_y, src_w, src_h, hsub, vsub;
1033 	bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
1034 
1035 	/*
1036 	 * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
1037 	 * abuses hsub/vsub so we can't use them here. But as they
1038 	 * are limited to 32bpp RGB formats we don't actually need
1039 	 * to check anything.
1040 	 */
1041 	if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
1042 	    fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
1043 		return 0;
1044 
1045 	/*
1046 	 * Hardware doesn't handle subpixel coordinates.
1047 	 * Adjust to (macro)pixel boundary, but be careful not to
1048 	 * increase the source viewport size, because that could
1049 	 * push the downscaling factor out of bounds.
1050 	 */
1051 	src_x = src->x1 >> 16;
1052 	src_w = drm_rect_width(src) >> 16;
1053 	src_y = src->y1 >> 16;
1054 	src_h = drm_rect_height(src) >> 16;
1055 
1056 	drm_rect_init(src, src_x << 16, src_y << 16,
1057 		      src_w << 16, src_h << 16);
1058 
1059 	if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
1060 		hsub = 2;
1061 		vsub = 2;
1062 	} else if (DISPLAY_VER(display) >= 20 &&
1063 		   intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
1064 		/*
1065 		 * This allows NV12 and P0xx formats to have odd size and/or odd
1066 		 * source coordinates on DISPLAY_VER(display) >= 20
1067 		 */
1068 		hsub = 1;
1069 		vsub = 1;
1070 
1071 		/* Wa_16023981245 */
1072 		if ((DISPLAY_VERx100(display) == 2000 ||
1073 		     DISPLAY_VERx100(display) == 3000) &&
1074 		     src_x % 2 != 0)
1075 			hsub = 2;
1076 	} else {
1077 		hsub = fb->format->hsub;
1078 		vsub = fb->format->vsub;
1079 	}
1080 
1081 	if (rotated)
1082 		hsub = vsub = max(hsub, vsub);
1083 
1084 	if (src_x % hsub || src_w % hsub) {
1085 		drm_dbg_kms(display->drm,
1086 			    "[PLANE:%d:%s] src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
1087 			    plane->base.base.id, plane->base.name,
1088 			    src_x, src_w, hsub, str_yes_no(rotated));
1089 		return -EINVAL;
1090 	}
1091 
1092 	if (src_y % vsub || src_h % vsub) {
1093 		drm_dbg_kms(display->drm,
1094 			    "[PLANE:%d:%s] src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
1095 			    plane->base.base.id, plane->base.name,
1096 			    src_y, src_h, vsub, str_yes_no(rotated));
1097 		return -EINVAL;
1098 	}
1099 
1100 	return 0;
1101 }
1102 
add_dma_resv_fences(struct dma_resv * resv,struct drm_plane_state * new_plane_state)1103 static int add_dma_resv_fences(struct dma_resv *resv,
1104 			       struct drm_plane_state *new_plane_state)
1105 {
1106 	struct dma_fence *fence = dma_fence_get(new_plane_state->fence);
1107 	struct dma_fence *new;
1108 	int ret;
1109 
1110 	ret = dma_resv_get_singleton(resv, dma_resv_usage_rw(false), &new);
1111 	if (ret)
1112 		goto error;
1113 
1114 	if (new && fence) {
1115 		struct dma_fence_chain *chain = dma_fence_chain_alloc();
1116 
1117 		if (!chain) {
1118 			ret = -ENOMEM;
1119 			goto error;
1120 		}
1121 
1122 		dma_fence_chain_init(chain, fence, new, 1);
1123 		fence = &chain->base;
1124 
1125 	} else if (new) {
1126 		fence = new;
1127 	}
1128 
1129 	dma_fence_put(new_plane_state->fence);
1130 	new_plane_state->fence = fence;
1131 	return 0;
1132 
1133 error:
1134 	dma_fence_put(fence);
1135 	return ret;
1136 }
1137 
1138 /**
1139  * intel_prepare_plane_fb - Prepare fb for usage on plane
1140  * @_plane: drm plane to prepare for
1141  * @_new_plane_state: the plane state being prepared
1142  *
1143  * Prepares a framebuffer for usage on a display plane.  Generally this
1144  * involves pinning the underlying object and updating the frontbuffer tracking
1145  * bits.  Some older platforms need special physical address handling for
1146  * cursor planes.
1147  *
1148  * Returns 0 on success, negative error code on failure.
1149  */
1150 static int
intel_prepare_plane_fb(struct drm_plane * _plane,struct drm_plane_state * _new_plane_state)1151 intel_prepare_plane_fb(struct drm_plane *_plane,
1152 		       struct drm_plane_state *_new_plane_state)
1153 {
1154 	struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
1155 	struct intel_plane *plane = to_intel_plane(_plane);
1156 	struct intel_display *display = to_intel_display(plane);
1157 	struct intel_plane_state *new_plane_state =
1158 		to_intel_plane_state(_new_plane_state);
1159 	struct intel_atomic_state *state =
1160 		to_intel_atomic_state(new_plane_state->uapi.state);
1161 	struct intel_plane_state *old_plane_state =
1162 		intel_atomic_get_old_plane_state(state, plane);
1163 	struct drm_gem_object *obj = intel_fb_bo(new_plane_state->hw.fb);
1164 	struct drm_gem_object *old_obj = intel_fb_bo(old_plane_state->hw.fb);
1165 	int ret;
1166 
1167 	if (old_obj) {
1168 		const struct intel_crtc_state *new_crtc_state =
1169 			intel_atomic_get_new_crtc_state(state,
1170 							to_intel_crtc(old_plane_state->hw.crtc));
1171 
1172 		/* Big Hammer, we also need to ensure that any pending
1173 		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1174 		 * current scanout is retired before unpinning the old
1175 		 * framebuffer. Note that we rely on userspace rendering
1176 		 * into the buffer attached to the pipe they are waiting
1177 		 * on. If not, userspace generates a GPU hang with IPEHR
1178 		 * point to the MI_WAIT_FOR_EVENT.
1179 		 *
1180 		 * This should only fail upon a hung GPU, in which case we
1181 		 * can safely continue.
1182 		 */
1183 		if (intel_crtc_needs_modeset(new_crtc_state)) {
1184 			ret = add_dma_resv_fences(old_obj->resv,
1185 						  &new_plane_state->uapi);
1186 			if (ret < 0)
1187 				return ret;
1188 		}
1189 	}
1190 
1191 	if (!obj)
1192 		return 0;
1193 
1194 	ret = intel_plane_pin_fb(new_plane_state, old_plane_state);
1195 	if (ret)
1196 		return ret;
1197 
1198 	ret = drm_gem_plane_helper_prepare_fb(&plane->base, &new_plane_state->uapi);
1199 	if (ret < 0)
1200 		goto unpin_fb;
1201 
1202 	if (new_plane_state->uapi.fence) {
1203 		i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1204 					     &attr);
1205 
1206 		intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1207 						     new_plane_state->uapi.fence);
1208 	}
1209 
1210 	/*
1211 	 * We declare pageflips to be interactive and so merit a small bias
1212 	 * towards upclocking to deliver the frame on time. By only changing
1213 	 * the RPS thresholds to sample more regularly and aim for higher
1214 	 * clocks we can hopefully deliver low power workloads (like kodi)
1215 	 * that are not quite steady state without resorting to forcing
1216 	 * maximum clocks following a vblank miss (see do_rps_boost()).
1217 	 */
1218 	intel_display_rps_mark_interactive(display, state, true);
1219 
1220 	return 0;
1221 
1222 unpin_fb:
1223 	intel_plane_unpin_fb(new_plane_state);
1224 
1225 	return ret;
1226 }
1227 
1228 /**
1229  * intel_cleanup_plane_fb - Cleans up an fb after plane use
1230  * @plane: drm plane to clean up for
1231  * @_old_plane_state: the state from the previous modeset
1232  *
1233  * Cleans up a framebuffer that has just been removed from a plane.
1234  */
1235 static void
intel_cleanup_plane_fb(struct drm_plane * plane,struct drm_plane_state * _old_plane_state)1236 intel_cleanup_plane_fb(struct drm_plane *plane,
1237 		       struct drm_plane_state *_old_plane_state)
1238 {
1239 	struct intel_display *display = to_intel_display(plane->dev);
1240 	struct intel_plane_state *old_plane_state =
1241 		to_intel_plane_state(_old_plane_state);
1242 	struct intel_atomic_state *state =
1243 		to_intel_atomic_state(old_plane_state->uapi.state);
1244 	struct drm_gem_object *obj = intel_fb_bo(old_plane_state->hw.fb);
1245 
1246 	if (!obj)
1247 		return;
1248 
1249 	intel_display_rps_mark_interactive(display, state, false);
1250 
1251 	intel_plane_unpin_fb(old_plane_state);
1252 }
1253 
1254 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1255 	.prepare_fb = intel_prepare_plane_fb,
1256 	.cleanup_fb = intel_cleanup_plane_fb,
1257 };
1258 
intel_plane_helper_add(struct intel_plane * plane)1259 void intel_plane_helper_add(struct intel_plane *plane)
1260 {
1261 	drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1262 }
1263 
intel_plane_init_cursor_vblank_work(struct intel_plane_state * old_plane_state,struct intel_plane_state * new_plane_state)1264 void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state,
1265 					 struct intel_plane_state *new_plane_state)
1266 {
1267 	if (!old_plane_state->ggtt_vma ||
1268 	    old_plane_state->ggtt_vma == new_plane_state->ggtt_vma)
1269 		return;
1270 
1271 	drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc,
1272 			     intel_cursor_unpin_work);
1273 }
1274 
link_nv12_planes(struct intel_crtc_state * crtc_state,struct intel_plane_state * uv_plane_state,struct intel_plane_state * y_plane_state)1275 static void link_nv12_planes(struct intel_crtc_state *crtc_state,
1276 			     struct intel_plane_state *uv_plane_state,
1277 			     struct intel_plane_state *y_plane_state)
1278 {
1279 	struct intel_display *display = to_intel_display(uv_plane_state);
1280 	struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane);
1281 	struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane);
1282 
1283 	drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n",
1284 		    uv_plane->base.base.id, uv_plane->base.name,
1285 		    y_plane->base.base.id, y_plane->base.name);
1286 
1287 	uv_plane_state->planar_linked_plane = y_plane;
1288 
1289 	y_plane_state->is_y_plane = true;
1290 	y_plane_state->planar_linked_plane = uv_plane;
1291 
1292 	crtc_state->enabled_planes |= BIT(y_plane->id);
1293 	crtc_state->active_planes |= BIT(y_plane->id);
1294 	crtc_state->update_planes |= BIT(y_plane->id);
1295 
1296 	crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id];
1297 	crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id];
1298 
1299 	/* Copy parameters to Y plane */
1300 	intel_plane_copy_hw_state(y_plane_state, uv_plane_state);
1301 	y_plane_state->uapi.src = uv_plane_state->uapi.src;
1302 	y_plane_state->uapi.dst = uv_plane_state->uapi.dst;
1303 
1304 	y_plane_state->ctl = uv_plane_state->ctl;
1305 	y_plane_state->color_ctl = uv_plane_state->color_ctl;
1306 	y_plane_state->view = uv_plane_state->view;
1307 	y_plane_state->decrypt = uv_plane_state->decrypt;
1308 
1309 	icl_link_nv12_planes(uv_plane_state, y_plane_state);
1310 }
1311 
unlink_nv12_plane(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)1312 static void unlink_nv12_plane(struct intel_crtc_state *crtc_state,
1313 			      struct intel_plane_state *plane_state)
1314 {
1315 	struct intel_display *display = to_intel_display(plane_state);
1316 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1317 
1318 	plane_state->planar_linked_plane = NULL;
1319 
1320 	if (!plane_state->is_y_plane)
1321 		return;
1322 
1323 	drm_WARN_ON(display->drm, plane_state->uapi.visible);
1324 
1325 	plane_state->is_y_plane = false;
1326 
1327 	crtc_state->enabled_planes &= ~BIT(plane->id);
1328 	crtc_state->active_planes &= ~BIT(plane->id);
1329 	crtc_state->update_planes |= BIT(plane->id);
1330 	crtc_state->data_rate[plane->id] = 0;
1331 	crtc_state->rel_data_rate[plane->id] = 0;
1332 }
1333 
icl_check_nv12_planes(struct intel_atomic_state * state,struct intel_crtc * crtc)1334 static int icl_check_nv12_planes(struct intel_atomic_state *state,
1335 				 struct intel_crtc *crtc)
1336 {
1337 	struct intel_display *display = to_intel_display(state);
1338 	struct intel_crtc_state *crtc_state =
1339 		intel_atomic_get_new_crtc_state(state, crtc);
1340 	struct intel_plane_state *plane_state;
1341 	struct intel_plane *plane;
1342 	int i;
1343 
1344 	if (DISPLAY_VER(display) < 11)
1345 		return 0;
1346 
1347 	/*
1348 	 * Destroy all old plane links and make the Y plane invisible
1349 	 * in the crtc_state->active_planes mask.
1350 	 */
1351 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1352 		if (plane->pipe != crtc->pipe)
1353 			continue;
1354 
1355 		if (plane_state->planar_linked_plane)
1356 			unlink_nv12_plane(crtc_state, plane_state);
1357 	}
1358 
1359 	if (!crtc_state->nv12_planes)
1360 		return 0;
1361 
1362 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1363 		struct intel_plane_state *y_plane_state = NULL;
1364 		struct intel_plane *y_plane;
1365 
1366 		if (plane->pipe != crtc->pipe)
1367 			continue;
1368 
1369 		if ((crtc_state->nv12_planes & BIT(plane->id)) == 0)
1370 			continue;
1371 
1372 		for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) {
1373 			if (!icl_is_nv12_y_plane(display, y_plane->id))
1374 				continue;
1375 
1376 			if (crtc_state->active_planes & BIT(y_plane->id))
1377 				continue;
1378 
1379 			y_plane_state = intel_atomic_get_plane_state(state, y_plane);
1380 			if (IS_ERR(y_plane_state))
1381 				return PTR_ERR(y_plane_state);
1382 
1383 			break;
1384 		}
1385 
1386 		if (!y_plane_state) {
1387 			drm_dbg_kms(display->drm,
1388 				    "[CRTC:%d:%s] need %d free Y planes for planar YUV\n",
1389 				    crtc->base.base.id, crtc->base.name,
1390 				    hweight8(crtc_state->nv12_planes));
1391 			return -EINVAL;
1392 		}
1393 
1394 		link_nv12_planes(crtc_state, plane_state, y_plane_state);
1395 	}
1396 
1397 	return 0;
1398 }
1399 
intel_crtc_add_planes_to_state(struct intel_atomic_state * state,struct intel_crtc * crtc,u8 plane_ids_mask)1400 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
1401 					  struct intel_crtc *crtc,
1402 					  u8 plane_ids_mask)
1403 {
1404 	struct intel_display *display = to_intel_display(state);
1405 	struct intel_plane *plane;
1406 
1407 	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
1408 		struct intel_plane_state *plane_state;
1409 
1410 		if ((plane_ids_mask & BIT(plane->id)) == 0)
1411 			continue;
1412 
1413 		plane_state = intel_atomic_get_plane_state(state, plane);
1414 		if (IS_ERR(plane_state))
1415 			return PTR_ERR(plane_state);
1416 	}
1417 
1418 	return 0;
1419 }
1420 
intel_atomic_add_affected_planes(struct intel_atomic_state * state,struct intel_crtc * crtc)1421 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
1422 				     struct intel_crtc *crtc)
1423 {
1424 	const struct intel_crtc_state *old_crtc_state =
1425 		intel_atomic_get_old_crtc_state(state, crtc);
1426 	const struct intel_crtc_state *new_crtc_state =
1427 		intel_atomic_get_new_crtc_state(state, crtc);
1428 
1429 	return intel_crtc_add_planes_to_state(state, crtc,
1430 					      old_crtc_state->enabled_planes |
1431 					      new_crtc_state->enabled_planes);
1432 }
1433 
active_planes_affects_min_cdclk(struct intel_display * display)1434 static bool active_planes_affects_min_cdclk(struct intel_display *display)
1435 {
1436 	/* See {hsw,vlv,ivb}_plane_ratio() */
1437 	return display->platform.broadwell || display->platform.haswell ||
1438 		display->platform.cherryview || display->platform.valleyview ||
1439 		display->platform.ivybridge;
1440 }
1441 
intel_joiner_affected_planes(struct intel_atomic_state * state,u8 joined_pipes)1442 static u8 intel_joiner_affected_planes(struct intel_atomic_state *state,
1443 				       u8 joined_pipes)
1444 {
1445 	const struct intel_plane_state *plane_state;
1446 	struct intel_plane *plane;
1447 	u8 affected_planes = 0;
1448 	int i;
1449 
1450 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1451 		struct intel_plane *linked = plane_state->planar_linked_plane;
1452 
1453 		if ((joined_pipes & BIT(plane->pipe)) == 0)
1454 			continue;
1455 
1456 		affected_planes |= BIT(plane->id);
1457 		if (linked)
1458 			affected_planes |= BIT(linked->id);
1459 	}
1460 
1461 	return affected_planes;
1462 }
1463 
intel_joiner_add_affected_planes(struct intel_atomic_state * state,u8 joined_pipes)1464 static int intel_joiner_add_affected_planes(struct intel_atomic_state *state,
1465 					    u8 joined_pipes)
1466 {
1467 	u8 prev_affected_planes, affected_planes = 0;
1468 
1469 	/*
1470 	 * We want all the joined pipes to have the same
1471 	 * set of planes in the atomic state, to make sure
1472 	 * state copying always works correctly, and the
1473 	 * UV<->Y plane linkage is always up to date.
1474 	 * Keep pulling planes in until we've determined
1475 	 * the full set of affected planes. A bit complicated
1476 	 * on account of each pipe being capable of selecting
1477 	 * their own Y planes independently of the other pipes,
1478 	 * and the selection being done from the set of
1479 	 * inactive planes.
1480 	 */
1481 	do {
1482 		struct intel_crtc *crtc;
1483 
1484 		for_each_intel_crtc_in_pipe_mask(state->base.dev, crtc, joined_pipes) {
1485 			int ret;
1486 
1487 			ret = intel_crtc_add_planes_to_state(state, crtc, affected_planes);
1488 			if (ret)
1489 				return ret;
1490 		}
1491 
1492 		prev_affected_planes = affected_planes;
1493 		affected_planes = intel_joiner_affected_planes(state, joined_pipes);
1494 	} while (affected_planes != prev_affected_planes);
1495 
1496 	return 0;
1497 }
1498 
intel_add_affected_planes(struct intel_atomic_state * state)1499 static int intel_add_affected_planes(struct intel_atomic_state *state)
1500 {
1501 	const struct intel_crtc_state *crtc_state;
1502 	struct intel_crtc *crtc;
1503 	int i;
1504 
1505 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
1506 		int ret;
1507 
1508 		ret = intel_joiner_add_affected_planes(state, intel_crtc_joined_pipe_mask(crtc_state));
1509 		if (ret)
1510 			return ret;
1511 	}
1512 
1513 	return 0;
1514 }
1515 
intel_atomic_check_planes(struct intel_atomic_state * state)1516 int intel_atomic_check_planes(struct intel_atomic_state *state)
1517 {
1518 	struct intel_display *display = to_intel_display(state);
1519 	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
1520 	struct intel_plane_state __maybe_unused *plane_state;
1521 	struct intel_plane *plane;
1522 	struct intel_crtc *crtc;
1523 	int i, ret;
1524 
1525 	ret = intel_add_affected_planes(state);
1526 	if (ret)
1527 		return ret;
1528 
1529 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1530 		ret = intel_plane_atomic_check(state, plane);
1531 		if (ret) {
1532 			drm_dbg_atomic(display->drm,
1533 				       "[PLANE:%d:%s] atomic driver check failed\n",
1534 				       plane->base.base.id, plane->base.name);
1535 			return ret;
1536 		}
1537 	}
1538 
1539 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1540 					    new_crtc_state, i) {
1541 		u8 old_active_planes, new_active_planes;
1542 
1543 		ret = icl_check_nv12_planes(state, crtc);
1544 		if (ret)
1545 			return ret;
1546 
1547 		/*
1548 		 * On some platforms the number of active planes affects
1549 		 * the planes' minimum cdclk calculation. Add such planes
1550 		 * to the state before we compute the minimum cdclk.
1551 		 */
1552 		if (!active_planes_affects_min_cdclk(display))
1553 			continue;
1554 
1555 		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1556 		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1557 
1558 		if (hweight8(old_active_planes) == hweight8(new_active_planes))
1559 			continue;
1560 
1561 		ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
1562 		if (ret)
1563 			return ret;
1564 	}
1565 
1566 	return 0;
1567 }
1568 
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)1569 u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
1570 {
1571 	return i915_ggtt_offset(plane_state->ggtt_vma);
1572 }
1573