1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 *
5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
6 */
7
8 #include "g4x_hdmi.h"
9 #include "i915_drv.h"
10 #include "i915_reg.h"
11 #include "intel_atomic.h"
12 #include "intel_audio.h"
13 #include "intel_connector.h"
14 #include "intel_crtc.h"
15 #include "intel_de.h"
16 #include "intel_display_power.h"
17 #include "intel_display_types.h"
18 #include "intel_dp_aux.h"
19 #include "intel_dpio_phy.h"
20 #include "intel_fdi.h"
21 #include "intel_fifo_underrun.h"
22 #include "intel_hdmi.h"
23 #include "intel_hotplug.h"
24 #include "intel_sdvo.h"
25 #include "vlv_sideband.h"
26
intel_hdmi_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)27 static void intel_hdmi_prepare(struct intel_encoder *encoder,
28 const struct intel_crtc_state *crtc_state)
29 {
30 struct intel_display *display = to_intel_display(encoder);
31 struct drm_i915_private *dev_priv = to_i915(display->drm);
32 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
33 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
34 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
35 u32 hdmi_val;
36
37 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
38
39 hdmi_val = SDVO_ENCODING_HDMI;
40 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
41 hdmi_val |= HDMI_COLOR_RANGE_16_235;
42 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
43 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
44 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
45 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
46
47 if (crtc_state->pipe_bpp > 24)
48 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
49 else
50 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
51
52 if (crtc_state->has_hdmi_sink)
53 hdmi_val |= HDMI_MODE_SELECT_HDMI;
54
55 if (HAS_PCH_CPT(dev_priv))
56 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
57 else if (display->platform.cherryview)
58 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
59 else
60 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
61
62 intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val);
63 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
64 }
65
intel_hdmi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)66 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
67 enum pipe *pipe)
68 {
69 struct intel_display *display = to_intel_display(encoder);
70 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
71 intel_wakeref_t wakeref;
72 bool ret;
73
74 wakeref = intel_display_power_get_if_enabled(display,
75 encoder->power_domain);
76 if (!wakeref)
77 return false;
78
79 ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe);
80
81 intel_display_power_put(display, encoder->power_domain, wakeref);
82
83 return ret;
84 }
85
connector_is_hdmi(struct drm_connector * connector)86 static bool connector_is_hdmi(struct drm_connector *connector)
87 {
88 struct intel_encoder *encoder =
89 intel_attached_encoder(to_intel_connector(connector));
90
91 return encoder && encoder->type == INTEL_OUTPUT_HDMI;
92 }
93
g4x_compute_has_hdmi_sink(struct intel_atomic_state * state,struct intel_crtc * this_crtc)94 static bool g4x_compute_has_hdmi_sink(struct intel_atomic_state *state,
95 struct intel_crtc *this_crtc)
96 {
97 const struct drm_connector_state *conn_state;
98 struct drm_connector *connector;
99 int i;
100
101 /*
102 * On g4x only one HDMI port can transmit infoframes/audio at
103 * any given time. Select the first suitable port for this duty.
104 *
105 * See also g4x_hdmi_connector_atomic_check().
106 */
107 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
108 struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder);
109 const struct intel_crtc_state *crtc_state;
110 struct intel_crtc *crtc;
111
112 if (!connector_is_hdmi(connector))
113 continue;
114
115 crtc = to_intel_crtc(conn_state->crtc);
116 if (!crtc)
117 continue;
118
119 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
120
121 if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state))
122 continue;
123
124 return crtc == this_crtc;
125 }
126
127 return false;
128 }
129
g4x_hdmi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)130 static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
131 struct intel_crtc_state *crtc_state,
132 struct drm_connector_state *conn_state)
133 {
134 struct intel_display *display = to_intel_display(encoder);
135 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
136 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
137 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
138
139 if (HAS_PCH_SPLIT(i915)) {
140 crtc_state->has_pch_encoder = true;
141 if (!intel_fdi_compute_pipe_bpp(crtc_state))
142 return -EINVAL;
143 }
144
145 if (display->platform.g4x)
146 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
147 else
148 crtc_state->has_hdmi_sink =
149 intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state);
150
151 return intel_hdmi_compute_config(encoder, crtc_state, conn_state);
152 }
153
intel_hdmi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)154 static void intel_hdmi_get_config(struct intel_encoder *encoder,
155 struct intel_crtc_state *pipe_config)
156 {
157 struct intel_display *display = to_intel_display(encoder);
158 struct drm_i915_private *dev_priv = to_i915(display->drm);
159 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
160 u32 tmp, flags = 0;
161 int dotclock;
162
163 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
164
165 tmp = intel_de_read(display, intel_hdmi->hdmi_reg);
166
167 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
168 flags |= DRM_MODE_FLAG_PHSYNC;
169 else
170 flags |= DRM_MODE_FLAG_NHSYNC;
171
172 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
173 flags |= DRM_MODE_FLAG_PVSYNC;
174 else
175 flags |= DRM_MODE_FLAG_NVSYNC;
176
177 if (tmp & HDMI_MODE_SELECT_HDMI)
178 pipe_config->has_hdmi_sink = true;
179
180 pipe_config->infoframes.enable |=
181 intel_hdmi_infoframes_enabled(encoder, pipe_config);
182
183 if (pipe_config->infoframes.enable)
184 pipe_config->has_infoframe = true;
185
186 if (tmp & HDMI_AUDIO_ENABLE)
187 pipe_config->has_audio = true;
188
189 if (!HAS_PCH_SPLIT(dev_priv) &&
190 tmp & HDMI_COLOR_RANGE_16_235)
191 pipe_config->limited_color_range = true;
192
193 pipe_config->hw.adjusted_mode.flags |= flags;
194
195 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
196 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3);
197 else
198 dotclock = pipe_config->port_clock;
199
200 if (pipe_config->pixel_multiplier)
201 dotclock /= pipe_config->pixel_multiplier;
202
203 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
204
205 pipe_config->lane_count = 4;
206
207 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
208
209 intel_read_infoframe(encoder, pipe_config,
210 HDMI_INFOFRAME_TYPE_AVI,
211 &pipe_config->infoframes.avi);
212 intel_read_infoframe(encoder, pipe_config,
213 HDMI_INFOFRAME_TYPE_SPD,
214 &pipe_config->infoframes.spd);
215 intel_read_infoframe(encoder, pipe_config,
216 HDMI_INFOFRAME_TYPE_VENDOR,
217 &pipe_config->infoframes.hdmi);
218
219 intel_audio_codec_get_config(encoder, pipe_config);
220 }
221
g4x_hdmi_enable_port(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)222 static void g4x_hdmi_enable_port(struct intel_encoder *encoder,
223 const struct intel_crtc_state *pipe_config)
224 {
225 struct intel_display *display = to_intel_display(encoder);
226 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
227 u32 temp;
228
229 temp = intel_de_read(display, intel_hdmi->hdmi_reg);
230
231 temp |= SDVO_ENABLE;
232
233 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
234 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
235 }
236
g4x_hdmi_audio_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)237 static void g4x_hdmi_audio_enable(struct intel_encoder *encoder,
238 const struct intel_crtc_state *crtc_state,
239 const struct drm_connector_state *conn_state)
240 {
241 struct intel_display *display = to_intel_display(encoder);
242 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
243
244 if (!crtc_state->has_audio)
245 return;
246
247 drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink);
248
249 /* Enable audio presence detect */
250 intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE);
251
252 intel_audio_codec_enable(encoder, crtc_state, conn_state);
253 }
254
g4x_hdmi_audio_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)255 static void g4x_hdmi_audio_disable(struct intel_encoder *encoder,
256 const struct intel_crtc_state *old_crtc_state,
257 const struct drm_connector_state *old_conn_state)
258 {
259 struct intel_display *display = to_intel_display(encoder);
260 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
261
262 if (!old_crtc_state->has_audio)
263 return;
264
265 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
266
267 /* Disable audio presence detect */
268 intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0);
269 }
270
g4x_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)271 static void g4x_enable_hdmi(struct intel_atomic_state *state,
272 struct intel_encoder *encoder,
273 const struct intel_crtc_state *pipe_config,
274 const struct drm_connector_state *conn_state)
275 {
276 g4x_hdmi_enable_port(encoder, pipe_config);
277 }
278
ibx_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)279 static void ibx_enable_hdmi(struct intel_atomic_state *state,
280 struct intel_encoder *encoder,
281 const struct intel_crtc_state *pipe_config,
282 const struct drm_connector_state *conn_state)
283 {
284 struct intel_display *display = to_intel_display(encoder);
285 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
286 u32 temp;
287
288 temp = intel_de_read(display, intel_hdmi->hdmi_reg);
289
290 temp |= SDVO_ENABLE;
291
292 /*
293 * HW workaround, need to write this twice for issue
294 * that may result in first write getting masked.
295 */
296 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
297 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
298 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
299 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
300
301 /*
302 * HW workaround, need to toggle enable bit off and on
303 * for 12bpc with pixel repeat.
304 *
305 * FIXME: BSpec says this should be done at the end of
306 * the modeset sequence, so not sure if this isn't too soon.
307 */
308 if (pipe_config->pipe_bpp > 24 &&
309 pipe_config->pixel_multiplier > 1) {
310 intel_de_write(display, intel_hdmi->hdmi_reg,
311 temp & ~SDVO_ENABLE);
312 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
313
314 /*
315 * HW workaround, need to write this twice for issue
316 * that may result in first write getting masked.
317 */
318 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
319 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
320 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
321 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
322 }
323 }
324
cpt_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)325 static void cpt_enable_hdmi(struct intel_atomic_state *state,
326 struct intel_encoder *encoder,
327 const struct intel_crtc_state *pipe_config,
328 const struct drm_connector_state *conn_state)
329 {
330 struct intel_display *display = to_intel_display(encoder);
331 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
332 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
333 enum pipe pipe = crtc->pipe;
334 u32 temp;
335
336 temp = intel_de_read(display, intel_hdmi->hdmi_reg);
337
338 temp |= SDVO_ENABLE;
339
340 /*
341 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
342 *
343 * The procedure for 12bpc is as follows:
344 * 1. disable HDMI clock gating
345 * 2. enable HDMI with 8bpc
346 * 3. enable HDMI with 12bpc
347 * 4. enable HDMI clock gating
348 */
349
350 if (pipe_config->pipe_bpp > 24) {
351 intel_de_rmw(display, TRANS_CHICKEN1(pipe),
352 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
353
354 temp &= ~SDVO_COLOR_FORMAT_MASK;
355 temp |= SDVO_COLOR_FORMAT_8bpc;
356 }
357
358 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
359 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
360
361 if (pipe_config->pipe_bpp > 24) {
362 temp &= ~SDVO_COLOR_FORMAT_MASK;
363 temp |= HDMI_COLOR_FORMAT_12bpc;
364
365 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
366 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
367
368 intel_de_rmw(display, TRANS_CHICKEN1(pipe),
369 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0);
370 }
371 }
372
vlv_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)373 static void vlv_enable_hdmi(struct intel_atomic_state *state,
374 struct intel_encoder *encoder,
375 const struct intel_crtc_state *pipe_config,
376 const struct drm_connector_state *conn_state)
377 {
378 }
379
intel_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)380 static void intel_disable_hdmi(struct intel_atomic_state *state,
381 struct intel_encoder *encoder,
382 const struct intel_crtc_state *old_crtc_state,
383 const struct drm_connector_state *old_conn_state)
384 {
385 struct intel_display *display = to_intel_display(encoder);
386 struct drm_i915_private *dev_priv = to_i915(display->drm);
387 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
388 struct intel_digital_port *dig_port =
389 hdmi_to_dig_port(intel_hdmi);
390 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
391 u32 temp;
392
393 temp = intel_de_read(display, intel_hdmi->hdmi_reg);
394
395 temp &= ~SDVO_ENABLE;
396 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
397 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
398
399 /*
400 * HW workaround for IBX, we need to move the port
401 * to transcoder A after disabling it to allow the
402 * matching DP port to be enabled on transcoder A.
403 */
404 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
405 /*
406 * We get CPU/PCH FIFO underruns on the other pipe when
407 * doing the workaround. Sweep them under the rug.
408 */
409 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
410 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
411
412 temp &= ~SDVO_PIPE_SEL_MASK;
413 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
414 /*
415 * HW workaround, need to write this twice for issue
416 * that may result in first write getting masked.
417 */
418 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
419 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
420 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
421 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
422
423 temp &= ~SDVO_ENABLE;
424 intel_de_write(display, intel_hdmi->hdmi_reg, temp);
425 intel_de_posting_read(display, intel_hdmi->hdmi_reg);
426
427 intel_wait_for_vblank_if_active(display, PIPE_A);
428 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
429 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
430 }
431
432 dig_port->set_infoframes(encoder,
433 false,
434 old_crtc_state, old_conn_state);
435
436 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
437 }
438
g4x_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)439 static void g4x_disable_hdmi(struct intel_atomic_state *state,
440 struct intel_encoder *encoder,
441 const struct intel_crtc_state *old_crtc_state,
442 const struct drm_connector_state *old_conn_state)
443 {
444 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
445 }
446
pch_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)447 static void pch_disable_hdmi(struct intel_atomic_state *state,
448 struct intel_encoder *encoder,
449 const struct intel_crtc_state *old_crtc_state,
450 const struct drm_connector_state *old_conn_state)
451 {
452 }
453
pch_post_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)454 static void pch_post_disable_hdmi(struct intel_atomic_state *state,
455 struct intel_encoder *encoder,
456 const struct intel_crtc_state *old_crtc_state,
457 const struct drm_connector_state *old_conn_state)
458 {
459 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
460 }
461
intel_hdmi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)462 static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
463 struct intel_encoder *encoder,
464 const struct intel_crtc_state *pipe_config,
465 const struct drm_connector_state *conn_state)
466 {
467 struct intel_digital_port *dig_port =
468 enc_to_dig_port(encoder);
469
470 intel_hdmi_prepare(encoder, pipe_config);
471
472 dig_port->set_infoframes(encoder,
473 pipe_config->has_infoframe,
474 pipe_config, conn_state);
475 }
476
vlv_hdmi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)477 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
478 struct intel_encoder *encoder,
479 const struct intel_crtc_state *pipe_config,
480 const struct drm_connector_state *conn_state)
481 {
482 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
483
484 vlv_phy_pre_encoder_enable(encoder, pipe_config);
485
486 /* HDMI 1.0V-2dB */
487 vlv_set_phy_signal_level(encoder, pipe_config,
488 0x2b245f5f, 0x00002000,
489 0x5578b83a, 0x2b247878);
490
491 dig_port->set_infoframes(encoder,
492 pipe_config->has_infoframe,
493 pipe_config, conn_state);
494
495 g4x_hdmi_enable_port(encoder, pipe_config);
496
497 vlv_wait_port_ready(encoder, 0x0);
498 }
499
vlv_hdmi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)500 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
501 struct intel_encoder *encoder,
502 const struct intel_crtc_state *pipe_config,
503 const struct drm_connector_state *conn_state)
504 {
505 intel_hdmi_prepare(encoder, pipe_config);
506
507 vlv_phy_pre_pll_enable(encoder, pipe_config);
508 }
509
chv_hdmi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)510 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
511 struct intel_encoder *encoder,
512 const struct intel_crtc_state *pipe_config,
513 const struct drm_connector_state *conn_state)
514 {
515 intel_hdmi_prepare(encoder, pipe_config);
516
517 chv_phy_pre_pll_enable(encoder, pipe_config);
518 }
519
chv_hdmi_post_pll_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)520 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
521 struct intel_encoder *encoder,
522 const struct intel_crtc_state *old_crtc_state,
523 const struct drm_connector_state *old_conn_state)
524 {
525 chv_phy_post_pll_disable(encoder, old_crtc_state);
526 }
527
vlv_hdmi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)528 static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
529 struct intel_encoder *encoder,
530 const struct intel_crtc_state *old_crtc_state,
531 const struct drm_connector_state *old_conn_state)
532 {
533 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
534 vlv_phy_reset_lanes(encoder, old_crtc_state);
535 }
536
chv_hdmi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)537 static void chv_hdmi_post_disable(struct intel_atomic_state *state,
538 struct intel_encoder *encoder,
539 const struct intel_crtc_state *old_crtc_state,
540 const struct drm_connector_state *old_conn_state)
541 {
542 struct intel_display *display = to_intel_display(encoder);
543 struct drm_i915_private *dev_priv = to_i915(display->drm);
544
545 vlv_dpio_get(dev_priv);
546
547 /* Assert data lane reset */
548 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
549
550 vlv_dpio_put(dev_priv);
551 }
552
chv_hdmi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)553 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
554 struct intel_encoder *encoder,
555 const struct intel_crtc_state *pipe_config,
556 const struct drm_connector_state *conn_state)
557 {
558 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
559
560 chv_phy_pre_encoder_enable(encoder, pipe_config);
561
562 /* FIXME: Program the support xxx V-dB */
563 /* Use 800mV-0dB */
564 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false);
565
566 dig_port->set_infoframes(encoder,
567 pipe_config->has_infoframe,
568 pipe_config, conn_state);
569
570 g4x_hdmi_enable_port(encoder, pipe_config);
571
572 vlv_wait_port_ready(encoder, 0x0);
573
574 /* Second common lane will stay alive on its own now */
575 chv_phy_release_cl2_override(encoder);
576 }
577
578 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
579 .destroy = intel_encoder_destroy,
580 };
581
582 static enum intel_hotplug_state
intel_hdmi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)583 intel_hdmi_hotplug(struct intel_encoder *encoder,
584 struct intel_connector *connector)
585 {
586 enum intel_hotplug_state state;
587
588 state = intel_encoder_hotplug(encoder, connector);
589
590 /*
591 * On many platforms the HDMI live state signal is known to be
592 * unreliable, so we can't use it to detect if a sink is connected or
593 * not. Instead we detect if it's connected based on whether we can
594 * read the EDID or not. That in turn has a problem during disconnect,
595 * since the HPD interrupt may be raised before the DDC lines get
596 * disconnected (due to how the required length of DDC vs. HPD
597 * connector pins are specified) and so we'll still be able to get a
598 * valid EDID. To solve this schedule another detection cycle if this
599 * time around we didn't detect any change in the sink's connection
600 * status.
601 */
602 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
603 state = INTEL_HOTPLUG_RETRY;
604
605 return state;
606 }
607
g4x_hdmi_connector_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)608 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector,
609 struct drm_atomic_state *state)
610 {
611 struct intel_display *display = to_intel_display(connector->dev);
612 struct drm_connector_list_iter conn_iter;
613 struct drm_connector *conn;
614 int ret;
615
616 ret = intel_digital_connector_atomic_check(connector, state);
617 if (ret)
618 return ret;
619
620 if (!display->platform.g4x)
621 return 0;
622
623 if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector))
624 return 0;
625
626 /*
627 * On g4x only one HDMI port can transmit infoframes/audio
628 * at any given time. Make sure all enabled HDMI ports are
629 * included in the state so that it's possible to select
630 * one of them for this duty.
631 *
632 * See also g4x_compute_has_hdmi_sink().
633 */
634 drm_connector_list_iter_begin(display->drm, &conn_iter);
635 drm_for_each_connector_iter(conn, &conn_iter) {
636 struct drm_connector_state *conn_state;
637 struct drm_crtc_state *crtc_state;
638 struct drm_crtc *crtc;
639
640 if (!connector_is_hdmi(conn))
641 continue;
642
643 drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n",
644 conn->base.id, conn->name);
645
646 conn_state = drm_atomic_get_connector_state(state, conn);
647 if (IS_ERR(conn_state)) {
648 ret = PTR_ERR(conn_state);
649 break;
650 }
651
652 crtc = conn_state->crtc;
653 if (!crtc)
654 continue;
655
656 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
657 crtc_state->mode_changed = true;
658
659 ret = drm_atomic_add_affected_planes(state, crtc);
660 if (ret)
661 break;
662 }
663 drm_connector_list_iter_end(&conn_iter);
664
665 return ret;
666 }
667
is_hdmi_port_valid(struct intel_display * display,enum port port)668 static bool is_hdmi_port_valid(struct intel_display *display, enum port port)
669 {
670 if (display->platform.g4x || display->platform.valleyview)
671 return port == PORT_B || port == PORT_C;
672 else
673 return port == PORT_B || port == PORT_C || port == PORT_D;
674 }
675
assert_hdmi_port_valid(struct intel_display * display,enum port port)676 static bool assert_hdmi_port_valid(struct intel_display *display, enum port port)
677 {
678 return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port),
679 "Platform does not support HDMI %c\n", port_name(port));
680 }
681
g4x_hdmi_init(struct intel_display * display,i915_reg_t hdmi_reg,enum port port)682 bool g4x_hdmi_init(struct intel_display *display,
683 i915_reg_t hdmi_reg, enum port port)
684 {
685 struct drm_i915_private *dev_priv = to_i915(display->drm);
686 const struct intel_bios_encoder_data *devdata;
687 struct intel_digital_port *dig_port;
688 struct intel_encoder *intel_encoder;
689 struct intel_connector *intel_connector;
690
691 if (!assert_port_valid(display, port))
692 return false;
693
694 if (!assert_hdmi_port_valid(display, port))
695 return false;
696
697 devdata = intel_bios_encoder_data_lookup(display, port);
698
699 /* FIXME bail? */
700 if (!devdata)
701 drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",
702 port_name(port));
703
704 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
705 if (!dig_port)
706 return false;
707
708 dig_port->aux_ch = AUX_CH_NONE;
709
710 intel_connector = intel_connector_alloc();
711 if (!intel_connector)
712 goto err_connector_alloc;
713
714 intel_encoder = &dig_port->base;
715
716 intel_encoder->devdata = devdata;
717
718 mutex_init(&dig_port->hdcp.mutex);
719
720 if (drm_encoder_init(display->drm, &intel_encoder->base,
721 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
722 "HDMI %c", port_name(port)))
723 goto err_encoder_init;
724
725 intel_encoder->hotplug = intel_hdmi_hotplug;
726 intel_encoder->compute_config = g4x_hdmi_compute_config;
727 if (HAS_PCH_SPLIT(dev_priv)) {
728 intel_encoder->disable = pch_disable_hdmi;
729 intel_encoder->post_disable = pch_post_disable_hdmi;
730 } else {
731 intel_encoder->disable = g4x_disable_hdmi;
732 }
733 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
734 intel_encoder->get_config = intel_hdmi_get_config;
735 if (display->platform.cherryview) {
736 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
737 intel_encoder->pre_enable = chv_hdmi_pre_enable;
738 intel_encoder->enable = vlv_enable_hdmi;
739 intel_encoder->post_disable = chv_hdmi_post_disable;
740 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
741 } else if (display->platform.valleyview) {
742 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
743 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
744 intel_encoder->enable = vlv_enable_hdmi;
745 intel_encoder->post_disable = vlv_hdmi_post_disable;
746 } else {
747 intel_encoder->pre_enable = intel_hdmi_pre_enable;
748 if (HAS_PCH_CPT(dev_priv))
749 intel_encoder->enable = cpt_enable_hdmi;
750 else if (HAS_PCH_IBX(dev_priv))
751 intel_encoder->enable = ibx_enable_hdmi;
752 else
753 intel_encoder->enable = g4x_enable_hdmi;
754 }
755 intel_encoder->audio_enable = g4x_hdmi_audio_enable;
756 intel_encoder->audio_disable = g4x_hdmi_audio_disable;
757 intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
758
759 intel_encoder->type = INTEL_OUTPUT_HDMI;
760 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
761 intel_encoder->port = port;
762 if (display->platform.cherryview) {
763 if (port == PORT_D)
764 intel_encoder->pipe_mask = BIT(PIPE_C);
765 else
766 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
767 } else {
768 intel_encoder->pipe_mask = ~0;
769 }
770 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG);
771 intel_encoder->hpd_pin = intel_hpd_pin_default(port);
772 /*
773 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
774 * to work on real hardware. And since g4x can send infoframes to
775 * only one port anyway, nothing is lost by allowing it.
776 */
777 if (display->platform.g4x)
778 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);
779
780 dig_port->hdmi.hdmi_reg = hdmi_reg;
781 dig_port->dp.output_reg = INVALID_MMIO_REG;
782 dig_port->max_lanes = 4;
783
784 intel_infoframe_init(dig_port);
785
786 if (!intel_hdmi_init_connector(dig_port, intel_connector))
787 goto err_init_connector;
788
789 return true;
790
791 err_init_connector:
792 drm_encoder_cleanup(&intel_encoder->base);
793 err_encoder_init:
794 kfree(intel_connector);
795 err_connector_alloc:
796 kfree(dig_port);
797
798 return false;
799 }
800