1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2020 Intel Corporation
4  *
5  * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
6  */
7 
8 #include <linux/string_helpers.h>
9 
10 #include "g4x_dp.h"
11 #include "i915_drv.h"
12 #include "i915_reg.h"
13 #include "intel_audio.h"
14 #include "intel_backlight.h"
15 #include "intel_connector.h"
16 #include "intel_crtc.h"
17 #include "intel_de.h"
18 #include "intel_display_power.h"
19 #include "intel_display_types.h"
20 #include "intel_dp.h"
21 #include "intel_dp_aux.h"
22 #include "intel_dp_link_training.h"
23 #include "intel_dp_test.h"
24 #include "intel_dpio_phy.h"
25 #include "intel_encoder.h"
26 #include "intel_fifo_underrun.h"
27 #include "intel_hdmi.h"
28 #include "intel_hotplug.h"
29 #include "intel_pch_display.h"
30 #include "intel_pps.h"
31 #include "vlv_sideband.h"
32 
33 static const struct dpll g4x_dpll[] = {
34 	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
35 	{ .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
36 };
37 
38 static const struct dpll pch_dpll[] = {
39 	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
40 	{ .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
41 };
42 
43 static const struct dpll vlv_dpll[] = {
44 	{ .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
45 	{ .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
46 };
47 
48 static const struct dpll chv_dpll[] = {
49 	/* m2 is .22 binary fixed point  */
50 	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
51 	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
52 };
53 
vlv_get_dpll(struct intel_display * display)54 const struct dpll *vlv_get_dpll(struct intel_display *display)
55 {
56 	return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0];
57 }
58 
g4x_dp_set_clock(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)59 static void g4x_dp_set_clock(struct intel_encoder *encoder,
60 			     struct intel_crtc_state *pipe_config)
61 {
62 	struct intel_display *display = to_intel_display(encoder);
63 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
64 	const struct dpll *divisor = NULL;
65 	int i, count = 0;
66 
67 	if (display->platform.g4x) {
68 		divisor = g4x_dpll;
69 		count = ARRAY_SIZE(g4x_dpll);
70 	} else if (HAS_PCH_SPLIT(dev_priv)) {
71 		divisor = pch_dpll;
72 		count = ARRAY_SIZE(pch_dpll);
73 	} else if (display->platform.cherryview) {
74 		divisor = chv_dpll;
75 		count = ARRAY_SIZE(chv_dpll);
76 	} else if (display->platform.valleyview) {
77 		divisor = vlv_dpll;
78 		count = ARRAY_SIZE(vlv_dpll);
79 	}
80 
81 	if (divisor && count) {
82 		for (i = 0; i < count; i++) {
83 			if (pipe_config->port_clock == divisor[i].dot) {
84 				pipe_config->dpll = divisor[i];
85 				pipe_config->clock_set = true;
86 				break;
87 			}
88 		}
89 	}
90 }
91 
intel_dp_prepare(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)92 static void intel_dp_prepare(struct intel_encoder *encoder,
93 			     const struct intel_crtc_state *pipe_config)
94 {
95 	struct intel_display *display = to_intel_display(encoder);
96 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
97 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
98 	enum port port = encoder->port;
99 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
100 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
101 
102 	intel_dp_set_link_params(intel_dp,
103 				 pipe_config->port_clock,
104 				 pipe_config->lane_count);
105 
106 	/*
107 	 * There are four kinds of DP registers:
108 	 * IBX PCH
109 	 * SNB CPU
110 	 * IVB CPU
111 	 * CPT PCH
112 	 *
113 	 * IBX PCH and CPU are the same for almost everything,
114 	 * except that the CPU DP PLL is configured in this
115 	 * register
116 	 *
117 	 * CPT PCH is quite different, having many bits moved
118 	 * to the TRANS_DP_CTL register instead. That
119 	 * configuration happens (oddly) in ilk_pch_enable
120 	 */
121 
122 	/* Preserve the BIOS-computed detected bit. This is
123 	 * supposed to be read-only.
124 	 */
125 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;
126 
127 	/* Handle DP bits in common between all three register formats */
128 	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
129 	intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
130 
131 	/* Split out the IBX/CPU vs CPT settings */
132 
133 	if (display->platform.ivybridge && port == PORT_A) {
134 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
135 			intel_dp->DP |= DP_SYNC_HS_HIGH;
136 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
137 			intel_dp->DP |= DP_SYNC_VS_HIGH;
138 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
139 
140 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
141 			intel_dp->DP |= DP_ENHANCED_FRAMING;
142 
143 		intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
144 	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
145 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
146 
147 		intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe),
148 			     TRANS_DP_ENH_FRAMING,
149 			     pipe_config->enhanced_framing ?
150 			     TRANS_DP_ENH_FRAMING : 0);
151 	} else {
152 		if (display->platform.g4x && pipe_config->limited_color_range)
153 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
154 
155 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
156 			intel_dp->DP |= DP_SYNC_HS_HIGH;
157 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
158 			intel_dp->DP |= DP_SYNC_VS_HIGH;
159 		intel_dp->DP |= DP_LINK_TRAIN_OFF;
160 
161 		if (pipe_config->enhanced_framing)
162 			intel_dp->DP |= DP_ENHANCED_FRAMING;
163 
164 		if (display->platform.cherryview)
165 			intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
166 		else
167 			intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
168 	}
169 }
170 
assert_dp_port(struct intel_dp * intel_dp,bool state)171 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
172 {
173 	struct intel_display *display = to_intel_display(intel_dp);
174 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
175 	bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;
176 
177 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
178 				 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
179 				 dig_port->base.base.base.id, dig_port->base.base.name,
180 				 str_on_off(state), str_on_off(cur_state));
181 }
182 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
183 
assert_edp_pll(struct intel_display * display,bool state)184 static void assert_edp_pll(struct intel_display *display, bool state)
185 {
186 	bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE;
187 
188 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
189 				 "eDP PLL state assertion failure (expected %s, current %s)\n",
190 				 str_on_off(state), str_on_off(cur_state));
191 }
192 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
193 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
194 
ilk_edp_pll_on(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)195 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
196 			   const struct intel_crtc_state *pipe_config)
197 {
198 	struct intel_display *display = to_intel_display(intel_dp);
199 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
200 
201 	assert_transcoder_disabled(display, pipe_config->cpu_transcoder);
202 	assert_dp_port_disabled(intel_dp);
203 	assert_edp_pll_disabled(display);
204 
205 	drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n",
206 		    pipe_config->port_clock);
207 
208 	intel_dp->DP &= ~DP_PLL_FREQ_MASK;
209 
210 	if (pipe_config->port_clock == 162000)
211 		intel_dp->DP |= DP_PLL_FREQ_162MHZ;
212 	else
213 		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
214 
215 	intel_de_write(display, DP_A, intel_dp->DP);
216 	intel_de_posting_read(display, DP_A);
217 	udelay(500);
218 
219 	/*
220 	 * [DevILK] Work around required when enabling DP PLL
221 	 * while a pipe is enabled going to FDI:
222 	 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
223 	 * 2. Program DP PLL enable
224 	 */
225 	if (display->platform.ironlake)
226 		intel_wait_for_vblank_if_active(display, !crtc->pipe);
227 
228 	intel_dp->DP |= DP_PLL_ENABLE;
229 
230 	intel_de_write(display, DP_A, intel_dp->DP);
231 	intel_de_posting_read(display, DP_A);
232 	udelay(200);
233 }
234 
ilk_edp_pll_off(struct intel_dp * intel_dp,const struct intel_crtc_state * old_crtc_state)235 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
236 			    const struct intel_crtc_state *old_crtc_state)
237 {
238 	struct intel_display *display = to_intel_display(intel_dp);
239 
240 	assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder);
241 	assert_dp_port_disabled(intel_dp);
242 	assert_edp_pll_enabled(display);
243 
244 	drm_dbg_kms(display->drm, "disabling eDP PLL\n");
245 
246 	intel_dp->DP &= ~DP_PLL_ENABLE;
247 
248 	intel_de_write(display, DP_A, intel_dp->DP);
249 	intel_de_posting_read(display, DP_A);
250 	udelay(200);
251 }
252 
cpt_dp_port_selected(struct intel_display * display,enum port port,enum pipe * pipe)253 static bool cpt_dp_port_selected(struct intel_display *display,
254 				 enum port port, enum pipe *pipe)
255 {
256 	enum pipe p;
257 
258 	for_each_pipe(display, p) {
259 		u32 val = intel_de_read(display, TRANS_DP_CTL(p));
260 
261 		if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
262 			*pipe = p;
263 			return true;
264 		}
265 	}
266 
267 	drm_dbg_kms(display->drm, "No pipe for DP port %c found\n",
268 		    port_name(port));
269 
270 	/* must initialize pipe to something for the asserts */
271 	*pipe = PIPE_A;
272 
273 	return false;
274 }
275 
g4x_dp_port_enabled(struct intel_display * display,i915_reg_t dp_reg,enum port port,enum pipe * pipe)276 bool g4x_dp_port_enabled(struct intel_display *display,
277 			 i915_reg_t dp_reg, enum port port,
278 			 enum pipe *pipe)
279 {
280 	struct drm_i915_private *dev_priv = to_i915(display->drm);
281 	bool ret;
282 	u32 val;
283 
284 	val = intel_de_read(display, dp_reg);
285 
286 	ret = val & DP_PORT_EN;
287 
288 	/* asserts want to know the pipe even if the port is disabled */
289 	if (display->platform.ivybridge && port == PORT_A)
290 		*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
291 	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
292 		ret &= cpt_dp_port_selected(display, port, pipe);
293 	else if (display->platform.cherryview)
294 		*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
295 	else
296 		*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
297 
298 	return ret;
299 }
300 
intel_dp_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)301 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
302 				  enum pipe *pipe)
303 {
304 	struct intel_display *display = to_intel_display(encoder);
305 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
306 	intel_wakeref_t wakeref;
307 	bool ret;
308 
309 	wakeref = intel_display_power_get_if_enabled(display,
310 						     encoder->power_domain);
311 	if (!wakeref)
312 		return false;
313 
314 	ret = g4x_dp_port_enabled(display, intel_dp->output_reg,
315 				  encoder->port, pipe);
316 
317 	intel_display_power_put(display, encoder->power_domain, wakeref);
318 
319 	return ret;
320 }
321 
g4x_dp_get_m_n(struct intel_crtc_state * crtc_state)322 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state)
323 {
324 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
325 
326 	if (crtc_state->has_pch_encoder) {
327 		intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n);
328 		intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2);
329 	} else {
330 		intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder,
331 					       &crtc_state->dp_m_n);
332 		intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder,
333 					       &crtc_state->dp_m2_n2);
334 	}
335 }
336 
intel_dp_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)337 static void intel_dp_get_config(struct intel_encoder *encoder,
338 				struct intel_crtc_state *pipe_config)
339 {
340 	struct intel_display *display = to_intel_display(encoder);
341 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
342 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
343 	u32 tmp, flags = 0;
344 	enum port port = encoder->port;
345 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
346 
347 	if (encoder->type == INTEL_OUTPUT_EDP)
348 		pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
349 	else
350 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
351 
352 	tmp = intel_de_read(display, intel_dp->output_reg);
353 
354 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
355 
356 	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
357 		u32 trans_dp = intel_de_read(display,
358 					     TRANS_DP_CTL(crtc->pipe));
359 
360 		if (trans_dp & TRANS_DP_ENH_FRAMING)
361 			pipe_config->enhanced_framing = true;
362 
363 		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
364 			flags |= DRM_MODE_FLAG_PHSYNC;
365 		else
366 			flags |= DRM_MODE_FLAG_NHSYNC;
367 
368 		if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
369 			flags |= DRM_MODE_FLAG_PVSYNC;
370 		else
371 			flags |= DRM_MODE_FLAG_NVSYNC;
372 	} else {
373 		if (tmp & DP_ENHANCED_FRAMING)
374 			pipe_config->enhanced_framing = true;
375 
376 		if (tmp & DP_SYNC_HS_HIGH)
377 			flags |= DRM_MODE_FLAG_PHSYNC;
378 		else
379 			flags |= DRM_MODE_FLAG_NHSYNC;
380 
381 		if (tmp & DP_SYNC_VS_HIGH)
382 			flags |= DRM_MODE_FLAG_PVSYNC;
383 		else
384 			flags |= DRM_MODE_FLAG_NVSYNC;
385 	}
386 
387 	pipe_config->hw.adjusted_mode.flags |= flags;
388 
389 	if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235)
390 		pipe_config->limited_color_range = true;
391 
392 	pipe_config->lane_count =
393 		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
394 
395 	g4x_dp_get_m_n(pipe_config);
396 
397 	if (port == PORT_A) {
398 		if ((intel_de_read(display, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
399 			pipe_config->port_clock = 162000;
400 		else
401 			pipe_config->port_clock = 270000;
402 	}
403 
404 	pipe_config->hw.adjusted_mode.crtc_clock =
405 		intel_dotclock_calculate(pipe_config->port_clock,
406 					 &pipe_config->dp_m_n);
407 
408 	if (intel_dp_is_edp(intel_dp))
409 		intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
410 
411 	intel_audio_codec_get_config(encoder, pipe_config);
412 }
413 
414 static void
intel_dp_link_down(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state)415 intel_dp_link_down(struct intel_encoder *encoder,
416 		   const struct intel_crtc_state *old_crtc_state)
417 {
418 	struct intel_display *display = to_intel_display(encoder);
419 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
420 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
421 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
422 	enum port port = encoder->port;
423 
424 	if (drm_WARN_ON(display->drm,
425 			(intel_de_read(display, intel_dp->output_reg) &
426 			 DP_PORT_EN) == 0))
427 		return;
428 
429 	drm_dbg_kms(display->drm, "\n");
430 
431 	if ((display->platform.ivybridge && port == PORT_A) ||
432 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
433 		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
434 		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
435 	} else {
436 		intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
437 		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
438 	}
439 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
440 	intel_de_posting_read(display, intel_dp->output_reg);
441 
442 	intel_dp->DP &= ~DP_PORT_EN;
443 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
444 	intel_de_posting_read(display, intel_dp->output_reg);
445 
446 	/*
447 	 * HW workaround for IBX, we need to move the port
448 	 * to transcoder A after disabling it to allow the
449 	 * matching HDMI port to be enabled on transcoder A.
450 	 */
451 	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
452 		/*
453 		 * We get CPU/PCH FIFO underruns on the other pipe when
454 		 * doing the workaround. Sweep them under the rug.
455 		 */
456 		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false);
457 		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false);
458 
459 		/* always enable with pattern 1 (as per spec) */
460 		intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
461 		intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
462 			DP_LINK_TRAIN_PAT_1;
463 		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
464 		intel_de_posting_read(display, intel_dp->output_reg);
465 
466 		intel_dp->DP &= ~DP_PORT_EN;
467 		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
468 		intel_de_posting_read(display, intel_dp->output_reg);
469 
470 		intel_wait_for_vblank_if_active(display, PIPE_A);
471 		intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true);
472 		intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true);
473 	}
474 
475 	msleep(intel_dp->pps.panel_power_down_delay);
476 
477 	if (display->platform.valleyview || display->platform.cherryview)
478 		vlv_pps_port_disable(encoder, old_crtc_state);
479 }
480 
g4x_dp_audio_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)481 static void g4x_dp_audio_enable(struct intel_encoder *encoder,
482 				const struct intel_crtc_state *crtc_state,
483 				const struct drm_connector_state *conn_state)
484 {
485 	struct intel_display *display = to_intel_display(encoder);
486 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
487 
488 	if (!crtc_state->has_audio)
489 		return;
490 
491 	/* Enable audio presence detect */
492 	intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
493 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
494 
495 	intel_audio_codec_enable(encoder, crtc_state, conn_state);
496 }
497 
g4x_dp_audio_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)498 static void g4x_dp_audio_disable(struct intel_encoder *encoder,
499 				 const struct intel_crtc_state *old_crtc_state,
500 				 const struct drm_connector_state *old_conn_state)
501 {
502 	struct intel_display *display = to_intel_display(encoder);
503 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
504 
505 	if (!old_crtc_state->has_audio)
506 		return;
507 
508 	intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
509 
510 	/* Disable audio presence detect */
511 	intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE;
512 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
513 }
514 
intel_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)515 static void intel_disable_dp(struct intel_atomic_state *state,
516 			     struct intel_encoder *encoder,
517 			     const struct intel_crtc_state *old_crtc_state,
518 			     const struct drm_connector_state *old_conn_state)
519 {
520 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
521 
522 	intel_dp->link_trained = false;
523 
524 	/*
525 	 * Make sure the panel is off before trying to change the mode.
526 	 * But also ensure that we have vdd while we switch off the panel.
527 	 */
528 	intel_pps_vdd_on(intel_dp);
529 	intel_edp_backlight_off(old_conn_state);
530 	intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
531 	intel_pps_off(intel_dp);
532 }
533 
g4x_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)534 static void g4x_disable_dp(struct intel_atomic_state *state,
535 			   struct intel_encoder *encoder,
536 			   const struct intel_crtc_state *old_crtc_state,
537 			   const struct drm_connector_state *old_conn_state)
538 {
539 	intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
540 }
541 
vlv_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)542 static void vlv_disable_dp(struct intel_atomic_state *state,
543 			   struct intel_encoder *encoder,
544 			   const struct intel_crtc_state *old_crtc_state,
545 			   const struct drm_connector_state *old_conn_state)
546 {
547 	intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
548 }
549 
g4x_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)550 static void g4x_post_disable_dp(struct intel_atomic_state *state,
551 				struct intel_encoder *encoder,
552 				const struct intel_crtc_state *old_crtc_state,
553 				const struct drm_connector_state *old_conn_state)
554 {
555 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
556 	enum port port = encoder->port;
557 
558 	/*
559 	 * Bspec does not list a specific disable sequence for g4x DP.
560 	 * Follow the ilk+ sequence (disable pipe before the port) for
561 	 * g4x DP as it does not suffer from underruns like the normal
562 	 * g4x modeset sequence (disable pipe after the port).
563 	 */
564 	intel_dp_link_down(encoder, old_crtc_state);
565 
566 	/* Only ilk+ has port A */
567 	if (port == PORT_A)
568 		ilk_edp_pll_off(intel_dp, old_crtc_state);
569 }
570 
vlv_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)571 static void vlv_post_disable_dp(struct intel_atomic_state *state,
572 				struct intel_encoder *encoder,
573 				const struct intel_crtc_state *old_crtc_state,
574 				const struct drm_connector_state *old_conn_state)
575 {
576 	intel_dp_link_down(encoder, old_crtc_state);
577 }
578 
chv_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)579 static void chv_post_disable_dp(struct intel_atomic_state *state,
580 				struct intel_encoder *encoder,
581 				const struct intel_crtc_state *old_crtc_state,
582 				const struct drm_connector_state *old_conn_state)
583 {
584 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
585 
586 	intel_dp_link_down(encoder, old_crtc_state);
587 
588 	vlv_dpio_get(dev_priv);
589 
590 	/* Assert data lane reset */
591 	chv_data_lane_soft_reset(encoder, old_crtc_state, true);
592 
593 	vlv_dpio_put(dev_priv);
594 }
595 
596 static void
cpt_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)597 cpt_set_link_train(struct intel_dp *intel_dp,
598 		   const struct intel_crtc_state *crtc_state,
599 		   u8 dp_train_pat)
600 {
601 	struct intel_display *display = to_intel_display(intel_dp);
602 
603 	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
604 
605 	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
606 	case DP_TRAINING_PATTERN_DISABLE:
607 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
608 		break;
609 	case DP_TRAINING_PATTERN_1:
610 		intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
611 		break;
612 	case DP_TRAINING_PATTERN_2:
613 		intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
614 		break;
615 	default:
616 		MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
617 		return;
618 	}
619 
620 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
621 	intel_de_posting_read(display, intel_dp->output_reg);
622 }
623 
624 static void
g4x_set_link_train(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,u8 dp_train_pat)625 g4x_set_link_train(struct intel_dp *intel_dp,
626 		   const struct intel_crtc_state *crtc_state,
627 		   u8 dp_train_pat)
628 {
629 	struct intel_display *display = to_intel_display(intel_dp);
630 
631 	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
632 
633 	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
634 	case DP_TRAINING_PATTERN_DISABLE:
635 		intel_dp->DP |= DP_LINK_TRAIN_OFF;
636 		break;
637 	case DP_TRAINING_PATTERN_1:
638 		intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
639 		break;
640 	case DP_TRAINING_PATTERN_2:
641 		intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
642 		break;
643 	default:
644 		MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
645 		return;
646 	}
647 
648 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
649 	intel_de_posting_read(display, intel_dp->output_reg);
650 }
651 
intel_dp_enable_port(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)652 static void intel_dp_enable_port(struct intel_dp *intel_dp,
653 				 const struct intel_crtc_state *crtc_state)
654 {
655 	struct intel_display *display = to_intel_display(intel_dp);
656 
657 	/* enable with pattern 1 (as per spec) */
658 
659 	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
660 					       DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
661 
662 	/*
663 	 * Magic for VLV/CHV. We _must_ first set up the register
664 	 * without actually enabling the port, and then do another
665 	 * write to enable the port. Otherwise link training will
666 	 * fail when the power sequencer is freshly used for this port.
667 	 */
668 	intel_dp->DP |= DP_PORT_EN;
669 
670 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
671 	intel_de_posting_read(display, intel_dp->output_reg);
672 }
673 
intel_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)674 static void intel_enable_dp(struct intel_atomic_state *state,
675 			    struct intel_encoder *encoder,
676 			    const struct intel_crtc_state *pipe_config,
677 			    const struct drm_connector_state *conn_state)
678 {
679 	struct intel_display *display = to_intel_display(state);
680 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
681 	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);
682 	intel_wakeref_t wakeref;
683 
684 	if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN))
685 		return;
686 
687 	with_intel_pps_lock(intel_dp, wakeref) {
688 		if (display->platform.valleyview || display->platform.cherryview)
689 			vlv_pps_port_enable_unlocked(encoder, pipe_config);
690 
691 		intel_dp_enable_port(intel_dp, pipe_config);
692 
693 		intel_pps_vdd_on_unlocked(intel_dp);
694 		intel_pps_on_unlocked(intel_dp);
695 		intel_pps_vdd_off_unlocked(intel_dp, true);
696 	}
697 
698 	if (display->platform.valleyview || display->platform.cherryview) {
699 		unsigned int lane_mask = 0x0;
700 
701 		if (display->platform.cherryview)
702 			lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
703 
704 		vlv_wait_port_ready(encoder, lane_mask);
705 	}
706 
707 	intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
708 	intel_dp_configure_protocol_converter(intel_dp, pipe_config);
709 	intel_dp_check_frl_training(intel_dp);
710 	intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
711 	intel_dp_start_link_train(state, intel_dp, pipe_config);
712 	intel_dp_stop_link_train(intel_dp, pipe_config);
713 }
714 
g4x_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)715 static void g4x_enable_dp(struct intel_atomic_state *state,
716 			  struct intel_encoder *encoder,
717 			  const struct intel_crtc_state *pipe_config,
718 			  const struct drm_connector_state *conn_state)
719 {
720 	intel_enable_dp(state, encoder, pipe_config, conn_state);
721 	intel_edp_backlight_on(pipe_config, conn_state);
722 }
723 
vlv_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)724 static void vlv_enable_dp(struct intel_atomic_state *state,
725 			  struct intel_encoder *encoder,
726 			  const struct intel_crtc_state *pipe_config,
727 			  const struct drm_connector_state *conn_state)
728 {
729 	intel_edp_backlight_on(pipe_config, conn_state);
730 }
731 
g4x_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)732 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
733 			      struct intel_encoder *encoder,
734 			      const struct intel_crtc_state *pipe_config,
735 			      const struct drm_connector_state *conn_state)
736 {
737 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
738 	enum port port = encoder->port;
739 
740 	intel_dp_prepare(encoder, pipe_config);
741 
742 	/* Only ilk+ has port A */
743 	if (port == PORT_A)
744 		ilk_edp_pll_on(intel_dp, pipe_config);
745 }
746 
vlv_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)747 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
748 			      struct intel_encoder *encoder,
749 			      const struct intel_crtc_state *pipe_config,
750 			      const struct drm_connector_state *conn_state)
751 {
752 	vlv_phy_pre_encoder_enable(encoder, pipe_config);
753 
754 	intel_enable_dp(state, encoder, pipe_config, conn_state);
755 }
756 
vlv_dp_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)757 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
758 				  struct intel_encoder *encoder,
759 				  const struct intel_crtc_state *pipe_config,
760 				  const struct drm_connector_state *conn_state)
761 {
762 	intel_dp_prepare(encoder, pipe_config);
763 
764 	vlv_phy_pre_pll_enable(encoder, pipe_config);
765 }
766 
chv_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)767 static void chv_pre_enable_dp(struct intel_atomic_state *state,
768 			      struct intel_encoder *encoder,
769 			      const struct intel_crtc_state *pipe_config,
770 			      const struct drm_connector_state *conn_state)
771 {
772 	chv_phy_pre_encoder_enable(encoder, pipe_config);
773 
774 	intel_enable_dp(state, encoder, pipe_config, conn_state);
775 
776 	/* Second common lane will stay alive on its own now */
777 	chv_phy_release_cl2_override(encoder);
778 }
779 
chv_dp_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state)780 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
781 				  struct intel_encoder *encoder,
782 				  const struct intel_crtc_state *pipe_config,
783 				  const struct drm_connector_state *conn_state)
784 {
785 	intel_dp_prepare(encoder, pipe_config);
786 
787 	chv_phy_pre_pll_enable(encoder, pipe_config);
788 }
789 
chv_dp_post_pll_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)790 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
791 				    struct intel_encoder *encoder,
792 				    const struct intel_crtc_state *old_crtc_state,
793 				    const struct drm_connector_state *old_conn_state)
794 {
795 	chv_phy_post_pll_disable(encoder, old_crtc_state);
796 }
797 
intel_dp_voltage_max_2(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)798 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
799 				 const struct intel_crtc_state *crtc_state)
800 {
801 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
802 }
803 
intel_dp_voltage_max_3(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)804 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
805 				 const struct intel_crtc_state *crtc_state)
806 {
807 	return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
808 }
809 
intel_dp_preemph_max_2(struct intel_dp * intel_dp)810 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
811 {
812 	return DP_TRAIN_PRE_EMPH_LEVEL_2;
813 }
814 
intel_dp_preemph_max_3(struct intel_dp * intel_dp)815 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
816 {
817 	return DP_TRAIN_PRE_EMPH_LEVEL_3;
818 }
819 
vlv_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)820 static void vlv_set_signal_levels(struct intel_encoder *encoder,
821 				  const struct intel_crtc_state *crtc_state)
822 {
823 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
824 	unsigned long demph_reg_value, preemph_reg_value,
825 		uniqtranscale_reg_value;
826 	u8 train_set = intel_dp->train_set[0];
827 
828 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
829 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
830 		preemph_reg_value = 0x0004000;
831 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
832 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
833 			demph_reg_value = 0x2B405555;
834 			uniqtranscale_reg_value = 0x552AB83A;
835 			break;
836 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
837 			demph_reg_value = 0x2B404040;
838 			uniqtranscale_reg_value = 0x5548B83A;
839 			break;
840 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
841 			demph_reg_value = 0x2B245555;
842 			uniqtranscale_reg_value = 0x5560B83A;
843 			break;
844 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
845 			demph_reg_value = 0x2B405555;
846 			uniqtranscale_reg_value = 0x5598DA3A;
847 			break;
848 		default:
849 			return;
850 		}
851 		break;
852 	case DP_TRAIN_PRE_EMPH_LEVEL_1:
853 		preemph_reg_value = 0x0002000;
854 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
855 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
856 			demph_reg_value = 0x2B404040;
857 			uniqtranscale_reg_value = 0x5552B83A;
858 			break;
859 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
860 			demph_reg_value = 0x2B404848;
861 			uniqtranscale_reg_value = 0x5580B83A;
862 			break;
863 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
864 			demph_reg_value = 0x2B404040;
865 			uniqtranscale_reg_value = 0x55ADDA3A;
866 			break;
867 		default:
868 			return;
869 		}
870 		break;
871 	case DP_TRAIN_PRE_EMPH_LEVEL_2:
872 		preemph_reg_value = 0x0000000;
873 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
874 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
875 			demph_reg_value = 0x2B305555;
876 			uniqtranscale_reg_value = 0x5570B83A;
877 			break;
878 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
879 			demph_reg_value = 0x2B2B4040;
880 			uniqtranscale_reg_value = 0x55ADDA3A;
881 			break;
882 		default:
883 			return;
884 		}
885 		break;
886 	case DP_TRAIN_PRE_EMPH_LEVEL_3:
887 		preemph_reg_value = 0x0006000;
888 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
889 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
890 			demph_reg_value = 0x1B405555;
891 			uniqtranscale_reg_value = 0x55ADDA3A;
892 			break;
893 		default:
894 			return;
895 		}
896 		break;
897 	default:
898 		return;
899 	}
900 
901 	vlv_set_phy_signal_level(encoder, crtc_state,
902 				 demph_reg_value, preemph_reg_value,
903 				 uniqtranscale_reg_value, 0);
904 }
905 
chv_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)906 static void chv_set_signal_levels(struct intel_encoder *encoder,
907 				  const struct intel_crtc_state *crtc_state)
908 {
909 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
910 	u32 deemph_reg_value, margin_reg_value;
911 	bool uniq_trans_scale = false;
912 	u8 train_set = intel_dp->train_set[0];
913 
914 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
915 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
916 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
917 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
918 			deemph_reg_value = 128;
919 			margin_reg_value = 52;
920 			break;
921 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
922 			deemph_reg_value = 128;
923 			margin_reg_value = 77;
924 			break;
925 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
926 			deemph_reg_value = 128;
927 			margin_reg_value = 102;
928 			break;
929 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
930 			deemph_reg_value = 128;
931 			margin_reg_value = 154;
932 			uniq_trans_scale = true;
933 			break;
934 		default:
935 			return;
936 		}
937 		break;
938 	case DP_TRAIN_PRE_EMPH_LEVEL_1:
939 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
940 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
941 			deemph_reg_value = 85;
942 			margin_reg_value = 78;
943 			break;
944 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
945 			deemph_reg_value = 85;
946 			margin_reg_value = 116;
947 			break;
948 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
949 			deemph_reg_value = 85;
950 			margin_reg_value = 154;
951 			break;
952 		default:
953 			return;
954 		}
955 		break;
956 	case DP_TRAIN_PRE_EMPH_LEVEL_2:
957 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
958 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
959 			deemph_reg_value = 64;
960 			margin_reg_value = 104;
961 			break;
962 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
963 			deemph_reg_value = 64;
964 			margin_reg_value = 154;
965 			break;
966 		default:
967 			return;
968 		}
969 		break;
970 	case DP_TRAIN_PRE_EMPH_LEVEL_3:
971 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
972 		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
973 			deemph_reg_value = 43;
974 			margin_reg_value = 154;
975 			break;
976 		default:
977 			return;
978 		}
979 		break;
980 	default:
981 		return;
982 	}
983 
984 	chv_set_phy_signal_level(encoder, crtc_state,
985 				 deemph_reg_value, margin_reg_value,
986 				 uniq_trans_scale);
987 }
988 
g4x_signal_levels(u8 train_set)989 static u32 g4x_signal_levels(u8 train_set)
990 {
991 	u32 signal_levels = 0;
992 
993 	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
994 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
995 	default:
996 		signal_levels |= DP_VOLTAGE_0_4;
997 		break;
998 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
999 		signal_levels |= DP_VOLTAGE_0_6;
1000 		break;
1001 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
1002 		signal_levels |= DP_VOLTAGE_0_8;
1003 		break;
1004 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1005 		signal_levels |= DP_VOLTAGE_1_2;
1006 		break;
1007 	}
1008 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1009 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
1010 	default:
1011 		signal_levels |= DP_PRE_EMPHASIS_0;
1012 		break;
1013 	case DP_TRAIN_PRE_EMPH_LEVEL_1:
1014 		signal_levels |= DP_PRE_EMPHASIS_3_5;
1015 		break;
1016 	case DP_TRAIN_PRE_EMPH_LEVEL_2:
1017 		signal_levels |= DP_PRE_EMPHASIS_6;
1018 		break;
1019 	case DP_TRAIN_PRE_EMPH_LEVEL_3:
1020 		signal_levels |= DP_PRE_EMPHASIS_9_5;
1021 		break;
1022 	}
1023 	return signal_levels;
1024 }
1025 
1026 static void
g4x_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1027 g4x_set_signal_levels(struct intel_encoder *encoder,
1028 		      const struct intel_crtc_state *crtc_state)
1029 {
1030 	struct intel_display *display = to_intel_display(encoder);
1031 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1032 	u8 train_set = intel_dp->train_set[0];
1033 	u32 signal_levels;
1034 
1035 	signal_levels = g4x_signal_levels(train_set);
1036 
1037 	drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1038 		    signal_levels);
1039 
1040 	intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
1041 	intel_dp->DP |= signal_levels;
1042 
1043 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1044 	intel_de_posting_read(display, intel_dp->output_reg);
1045 }
1046 
1047 /* SNB CPU eDP voltage swing and pre-emphasis control */
snb_cpu_edp_signal_levels(u8 train_set)1048 static u32 snb_cpu_edp_signal_levels(u8 train_set)
1049 {
1050 	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1051 					DP_TRAIN_PRE_EMPHASIS_MASK);
1052 
1053 	switch (signal_levels) {
1054 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1055 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1056 		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1057 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1058 		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1059 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1060 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1061 		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1062 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1063 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1064 		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1065 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1066 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1067 		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1068 	default:
1069 		MISSING_CASE(signal_levels);
1070 		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1071 	}
1072 }
1073 
1074 static void
snb_cpu_edp_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1075 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1076 			      const struct intel_crtc_state *crtc_state)
1077 {
1078 	struct intel_display *display = to_intel_display(encoder);
1079 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1080 	u8 train_set = intel_dp->train_set[0];
1081 	u32 signal_levels;
1082 
1083 	signal_levels = snb_cpu_edp_signal_levels(train_set);
1084 
1085 	drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1086 		    signal_levels);
1087 
1088 	intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1089 	intel_dp->DP |= signal_levels;
1090 
1091 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1092 	intel_de_posting_read(display, intel_dp->output_reg);
1093 }
1094 
1095 /* IVB CPU eDP voltage swing and pre-emphasis control */
ivb_cpu_edp_signal_levels(u8 train_set)1096 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
1097 {
1098 	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1099 					DP_TRAIN_PRE_EMPHASIS_MASK);
1100 
1101 	switch (signal_levels) {
1102 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1103 		return EDP_LINK_TRAIN_400MV_0DB_IVB;
1104 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1105 		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1106 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1107 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1108 		return EDP_LINK_TRAIN_400MV_6DB_IVB;
1109 
1110 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1111 		return EDP_LINK_TRAIN_600MV_0DB_IVB;
1112 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1113 		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1114 
1115 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1116 		return EDP_LINK_TRAIN_800MV_0DB_IVB;
1117 	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1118 		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1119 
1120 	default:
1121 		MISSING_CASE(signal_levels);
1122 		return EDP_LINK_TRAIN_500MV_0DB_IVB;
1123 	}
1124 }
1125 
1126 static void
ivb_cpu_edp_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1127 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
1128 			      const struct intel_crtc_state *crtc_state)
1129 {
1130 	struct intel_display *display = to_intel_display(encoder);
1131 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1132 	u8 train_set = intel_dp->train_set[0];
1133 	u32 signal_levels;
1134 
1135 	signal_levels = ivb_cpu_edp_signal_levels(train_set);
1136 
1137 	drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1138 		    signal_levels);
1139 
1140 	intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1141 	intel_dp->DP |= signal_levels;
1142 
1143 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);
1144 	intel_de_posting_read(display, intel_dp->output_reg);
1145 }
1146 
1147 /*
1148  * If display is now connected check links status,
1149  * there has been known issues of link loss triggering
1150  * long pulse.
1151  *
1152  * Some sinks (eg. ASUS PB287Q) seem to perform some
1153  * weird HPD ping pong during modesets. So we can apparently
1154  * end up with HPD going low during a modeset, and then
1155  * going back up soon after. And once that happens we must
1156  * retrain the link to get a picture. That's in case no
1157  * userspace component reacted to intermittent HPD dip.
1158  */
1159 static enum intel_hotplug_state
intel_dp_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)1160 intel_dp_hotplug(struct intel_encoder *encoder,
1161 		 struct intel_connector *connector)
1162 {
1163 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1164 	enum intel_hotplug_state state;
1165 
1166 	if (intel_dp_test_phy(intel_dp))
1167 		return INTEL_HOTPLUG_UNCHANGED;
1168 
1169 	state = intel_encoder_hotplug(encoder, connector);
1170 
1171 	intel_dp_check_link_state(intel_dp);
1172 
1173 	/*
1174 	 * Keeping it consistent with intel_ddi_hotplug() and
1175 	 * intel_hdmi_hotplug().
1176 	 */
1177 	if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
1178 		state = INTEL_HOTPLUG_RETRY;
1179 
1180 	return state;
1181 }
1182 
ibx_digital_port_connected(struct intel_encoder * encoder)1183 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
1184 {
1185 	struct intel_display *display = to_intel_display(encoder);
1186 	u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
1187 
1188 	return intel_de_read(display, SDEISR) & bit;
1189 }
1190 
g4x_digital_port_connected(struct intel_encoder * encoder)1191 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
1192 {
1193 	struct intel_display *display = to_intel_display(encoder);
1194 	u32 bit;
1195 
1196 	switch (encoder->hpd_pin) {
1197 	case HPD_PORT_B:
1198 		bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
1199 		break;
1200 	case HPD_PORT_C:
1201 		bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
1202 		break;
1203 	case HPD_PORT_D:
1204 		bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
1205 		break;
1206 	default:
1207 		MISSING_CASE(encoder->hpd_pin);
1208 		return false;
1209 	}
1210 
1211 	return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit;
1212 }
1213 
ilk_digital_port_connected(struct intel_encoder * encoder)1214 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
1215 {
1216 	struct intel_display *display = to_intel_display(encoder);
1217 	u32 bit = display->hotplug.hpd[encoder->hpd_pin];
1218 
1219 	return intel_de_read(display, DEISR) & bit;
1220 }
1221 
g4x_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)1222 static int g4x_dp_compute_config(struct intel_encoder *encoder,
1223 				 struct intel_crtc_state *crtc_state,
1224 				 struct drm_connector_state *conn_state)
1225 {
1226 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1227 	int ret;
1228 
1229 	if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A)
1230 		crtc_state->has_pch_encoder = true;
1231 
1232 	ret = intel_dp_compute_config(encoder, crtc_state, conn_state);
1233 	if (ret)
1234 		return ret;
1235 
1236 	g4x_dp_set_clock(encoder, crtc_state);
1237 
1238 	return 0;
1239 }
1240 
g4x_dp_suspend_complete(struct intel_encoder * encoder)1241 static void g4x_dp_suspend_complete(struct intel_encoder *encoder)
1242 {
1243 	/*
1244 	 * TODO: Move this to intel_dp_encoder_suspend(),
1245 	 * once modeset locking around that is removed.
1246 	 */
1247 	intel_encoder_link_check_flush_work(encoder);
1248 }
1249 
intel_dp_encoder_destroy(struct drm_encoder * encoder)1250 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1251 {
1252 	intel_dp_encoder_flush_work(encoder);
1253 
1254 	drm_encoder_cleanup(encoder);
1255 	kfree(enc_to_dig_port(to_intel_encoder(encoder)));
1256 }
1257 
intel_dp_encoder_reset(struct drm_encoder * encoder)1258 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
1259 {
1260 	struct intel_display *display = to_intel_display(encoder->dev);
1261 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
1262 
1263 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
1264 
1265 	intel_dp->reset_link_params = true;
1266 	intel_dp_invalidate_source_oui(intel_dp);
1267 
1268 	if (display->platform.valleyview || display->platform.cherryview)
1269 		vlv_pps_pipe_reset(intel_dp);
1270 
1271 	intel_pps_encoder_reset(intel_dp);
1272 }
1273 
1274 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1275 	.reset = intel_dp_encoder_reset,
1276 	.destroy = intel_dp_encoder_destroy,
1277 };
1278 
g4x_dp_init(struct intel_display * display,i915_reg_t output_reg,enum port port)1279 bool g4x_dp_init(struct intel_display *display,
1280 		 i915_reg_t output_reg, enum port port)
1281 {
1282 	struct drm_i915_private *dev_priv = to_i915(display->drm);
1283 	const struct intel_bios_encoder_data *devdata;
1284 	struct intel_digital_port *dig_port;
1285 	struct intel_encoder *intel_encoder;
1286 	struct drm_encoder *encoder;
1287 	struct intel_connector *intel_connector;
1288 
1289 	if (!assert_port_valid(display, port))
1290 		return false;
1291 
1292 	devdata = intel_bios_encoder_data_lookup(display, port);
1293 
1294 	/* FIXME bail? */
1295 	if (!devdata)
1296 		drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",
1297 			    port_name(port));
1298 
1299 	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
1300 	if (!dig_port)
1301 		return false;
1302 
1303 	dig_port->aux_ch = AUX_CH_NONE;
1304 
1305 	intel_connector = intel_connector_alloc();
1306 	if (!intel_connector)
1307 		goto err_connector_alloc;
1308 
1309 	intel_encoder = &dig_port->base;
1310 	encoder = &intel_encoder->base;
1311 
1312 	intel_encoder->devdata = devdata;
1313 
1314 	mutex_init(&dig_port->hdcp.mutex);
1315 
1316 	if (drm_encoder_init(display->drm, &intel_encoder->base,
1317 			     &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
1318 			     "DP %c", port_name(port)))
1319 		goto err_encoder_init;
1320 
1321 	intel_encoder_link_check_init(intel_encoder, intel_dp_link_check);
1322 
1323 	intel_encoder->hotplug = intel_dp_hotplug;
1324 	intel_encoder->compute_config = g4x_dp_compute_config;
1325 	intel_encoder->get_hw_state = intel_dp_get_hw_state;
1326 	intel_encoder->get_config = intel_dp_get_config;
1327 	intel_encoder->sync_state = intel_dp_sync_state;
1328 	intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
1329 	intel_encoder->update_pipe = intel_backlight_update;
1330 	intel_encoder->suspend = intel_dp_encoder_suspend;
1331 	intel_encoder->suspend_complete = g4x_dp_suspend_complete;
1332 	intel_encoder->shutdown = intel_dp_encoder_shutdown;
1333 	if (display->platform.cherryview) {
1334 		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
1335 		intel_encoder->pre_enable = chv_pre_enable_dp;
1336 		intel_encoder->enable = vlv_enable_dp;
1337 		intel_encoder->disable = vlv_disable_dp;
1338 		intel_encoder->post_disable = chv_post_disable_dp;
1339 		intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
1340 	} else if (display->platform.valleyview) {
1341 		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
1342 		intel_encoder->pre_enable = vlv_pre_enable_dp;
1343 		intel_encoder->enable = vlv_enable_dp;
1344 		intel_encoder->disable = vlv_disable_dp;
1345 		intel_encoder->post_disable = vlv_post_disable_dp;
1346 	} else {
1347 		intel_encoder->pre_enable = g4x_pre_enable_dp;
1348 		intel_encoder->enable = g4x_enable_dp;
1349 		intel_encoder->disable = g4x_disable_dp;
1350 		intel_encoder->post_disable = g4x_post_disable_dp;
1351 	}
1352 	intel_encoder->audio_enable = g4x_dp_audio_enable;
1353 	intel_encoder->audio_disable = g4x_dp_audio_disable;
1354 
1355 	if ((display->platform.ivybridge && port == PORT_A) ||
1356 	    (HAS_PCH_CPT(dev_priv) && port != PORT_A))
1357 		dig_port->dp.set_link_train = cpt_set_link_train;
1358 	else
1359 		dig_port->dp.set_link_train = g4x_set_link_train;
1360 
1361 	if (display->platform.cherryview)
1362 		intel_encoder->set_signal_levels = chv_set_signal_levels;
1363 	else if (display->platform.valleyview)
1364 		intel_encoder->set_signal_levels = vlv_set_signal_levels;
1365 	else if (display->platform.ivybridge && port == PORT_A)
1366 		intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;
1367 	else if (display->platform.sandybridge && port == PORT_A)
1368 		intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;
1369 	else
1370 		intel_encoder->set_signal_levels = g4x_set_signal_levels;
1371 
1372 	if (display->platform.valleyview || display->platform.cherryview ||
1373 	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
1374 		dig_port->dp.preemph_max = intel_dp_preemph_max_3;
1375 		dig_port->dp.voltage_max = intel_dp_voltage_max_3;
1376 	} else {
1377 		dig_port->dp.preemph_max = intel_dp_preemph_max_2;
1378 		dig_port->dp.voltage_max = intel_dp_voltage_max_2;
1379 	}
1380 
1381 	dig_port->dp.output_reg = output_reg;
1382 	dig_port->max_lanes = 4;
1383 
1384 	intel_encoder->type = INTEL_OUTPUT_DP;
1385 	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
1386 	if (display->platform.cherryview) {
1387 		if (port == PORT_D)
1388 			intel_encoder->pipe_mask = BIT(PIPE_C);
1389 		else
1390 			intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
1391 	} else {
1392 		intel_encoder->pipe_mask = ~0;
1393 	}
1394 	intel_encoder->cloneable = 0;
1395 	intel_encoder->port = port;
1396 	intel_encoder->hpd_pin = intel_hpd_pin_default(port);
1397 
1398 	dig_port->hpd_pulse = intel_dp_hpd_pulse;
1399 
1400 	if (HAS_GMCH(display)) {
1401 		dig_port->connected = g4x_digital_port_connected;
1402 	} else {
1403 		if (port == PORT_A)
1404 			dig_port->connected = ilk_digital_port_connected;
1405 		else
1406 			dig_port->connected = ibx_digital_port_connected;
1407 	}
1408 
1409 	if (port != PORT_A)
1410 		intel_infoframe_init(dig_port);
1411 
1412 	dig_port->aux_ch = intel_dp_aux_ch(intel_encoder);
1413 	if (dig_port->aux_ch == AUX_CH_NONE)
1414 		goto err_init_connector;
1415 
1416 	if (!intel_dp_init_connector(dig_port, intel_connector))
1417 		goto err_init_connector;
1418 
1419 	return true;
1420 
1421 err_init_connector:
1422 	drm_encoder_cleanup(encoder);
1423 err_encoder_init:
1424 	kfree(intel_connector);
1425 err_connector_alloc:
1426 	kfree(dig_port);
1427 	return false;
1428 }
1429