1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI SN65DSI83,84,85 driver
4 *
5 * Currently supported:
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
15 * (should be easy to add by someone who has the HW)
16 * - SN65DSI85
17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
18 * - Unsupported
19 * (should be easy to add by someone who has the HW)
20 *
21 * Copyright (C) 2021 Marek Vasut <marex@denx.de>
22 *
23 * Based on previous work of:
24 * Valentin Raevsky <valentin@compulab.co.il>
25 * Philippe Schenker <philippe.schenker@toradex.com>
26 */
27
28 #include <linux/bits.h>
29 #include <linux/clk.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/i2c.h>
32 #include <linux/media-bus-format.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_graph.h>
36 #include <linux/regmap.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/timer.h>
39 #include <linux/workqueue.h>
40
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_bridge.h>
43 #include <drm/drm_drv.h> /* DRM_MODESET_LOCK_ALL_BEGIN() needs drm_drv_uses_atomic_modeset() */
44 #include <drm/drm_mipi_dsi.h>
45 #include <drm/drm_of.h>
46 #include <drm/drm_print.h>
47 #include <drm/drm_probe_helper.h>
48
49 /* ID registers */
50 #define REG_ID(n) (0x00 + (n))
51 /* Reset and clock registers */
52 #define REG_RC_RESET 0x09
53 #define REG_RC_RESET_SOFT_RESET BIT(0)
54 #define REG_RC_LVDS_PLL 0x0a
55 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7)
56 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1)
57 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0)
58 #define REG_RC_DSI_CLK 0x0b
59 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3)
60 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3)
61 #define REG_RC_PLL_EN 0x0d
62 #define REG_RC_PLL_EN_PLL_EN BIT(0)
63 /* DSI registers */
64 #define REG_DSI_LANE 0x10
65 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */
66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */
67 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */
68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5)
69 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3)
70 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1)
71 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0)
72 #define REG_DSI_EQ 0x11
73 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6)
74 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2)
75 #define REG_DSI_CLK 0x12
76 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff)
77 /* LVDS registers */
78 #define REG_LVDS_FMT 0x18
79 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7)
80 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6)
81 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5)
82 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */
83 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3)
84 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2)
85 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1)
86 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0)
87 #define REG_LVDS_VCOM 0x19
88 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6)
89 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4)
90 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2)
91 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3)
92 #define REG_LVDS_LANE 0x1a
93 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6)
94 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5)
95 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4)
96 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1)
97 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0)
98 #define REG_LVDS_CM 0x1b
99 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4)
100 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3)
101 /* Video registers */
102 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20
103 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21
104 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24
105 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25
106 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28
107 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29
108 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c
109 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d
110 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
111 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
112 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34
113 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36
114 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38
115 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a
116 #define REG_VID_CHA_TEST_PATTERN 0x3c
117 /* IRQ registers */
118 #define REG_IRQ_GLOBAL 0xe0
119 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0)
120 #define REG_IRQ_EN 0xe1
121 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7)
122 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6)
123 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5)
124 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4)
125 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3)
126 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2)
127 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0)
128 #define REG_IRQ_STAT 0xe5
129 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7)
130 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6)
131 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5)
132 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4)
133 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3)
134 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2)
135 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0)
136
137 enum sn65dsi83_channel {
138 CHANNEL_A,
139 CHANNEL_B
140 };
141
142 enum sn65dsi83_lvds_term {
143 OHM_100,
144 OHM_200
145 };
146
147 enum sn65dsi83_model {
148 MODEL_SN65DSI83,
149 MODEL_SN65DSI84,
150 };
151
152 struct sn65dsi83 {
153 struct drm_bridge bridge;
154 struct device *dev;
155 struct regmap *regmap;
156 struct mipi_dsi_device *dsi;
157 struct drm_bridge *panel_bridge;
158 struct gpio_desc *enable_gpio;
159 struct regulator *vcc;
160 bool lvds_dual_link;
161 bool lvds_dual_link_even_odd_swap;
162 int lvds_vod_swing_conf[2];
163 int lvds_term_conf[2];
164 int irq;
165 struct delayed_work monitor_work;
166 struct work_struct reset_work;
167 };
168
169 static const struct regmap_range sn65dsi83_readable_ranges[] = {
170 regmap_reg_range(REG_ID(0), REG_ID(8)),
171 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
172 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
173 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
174 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
175 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
176 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
177 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
178 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
179 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
180 REG_VID_CHA_SYNC_DELAY_HIGH),
181 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
182 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
183 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
184 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
185 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
186 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
187 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
188 REG_VID_CHA_VERTICAL_BACK_PORCH),
189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
190 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
191 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
192 REG_VID_CHA_VERTICAL_FRONT_PORCH),
193 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
194 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
195 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
196 };
197
198 static const struct regmap_access_table sn65dsi83_readable_table = {
199 .yes_ranges = sn65dsi83_readable_ranges,
200 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
201 };
202
203 static const struct regmap_range sn65dsi83_writeable_ranges[] = {
204 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
205 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
206 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
207 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
208 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
209 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
210 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
211 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
212 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
213 REG_VID_CHA_SYNC_DELAY_HIGH),
214 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
215 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
216 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
217 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
218 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
219 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
220 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
221 REG_VID_CHA_VERTICAL_BACK_PORCH),
222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
223 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
224 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
225 REG_VID_CHA_VERTICAL_FRONT_PORCH),
226 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
227 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
228 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
229 };
230
231 static const struct regmap_access_table sn65dsi83_writeable_table = {
232 .yes_ranges = sn65dsi83_writeable_ranges,
233 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
234 };
235
236 static const struct regmap_range sn65dsi83_volatile_ranges[] = {
237 regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
238 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
239 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
240 };
241
242 static const struct regmap_access_table sn65dsi83_volatile_table = {
243 .yes_ranges = sn65dsi83_volatile_ranges,
244 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
245 };
246
247 static const struct regmap_config sn65dsi83_regmap_config = {
248 .reg_bits = 8,
249 .val_bits = 8,
250 .rd_table = &sn65dsi83_readable_table,
251 .wr_table = &sn65dsi83_writeable_table,
252 .volatile_table = &sn65dsi83_volatile_table,
253 .cache_type = REGCACHE_MAPLE,
254 .max_register = REG_IRQ_STAT,
255 };
256
257 static const int lvds_vod_swing_data_table[2][4][2] = {
258 { /* 100 Ohm */
259 { 180000, 313000 },
260 { 215000, 372000 },
261 { 250000, 430000 },
262 { 290000, 488000 },
263 },
264 { /* 200 Ohm */
265 { 150000, 261000 },
266 { 200000, 346000 },
267 { 250000, 428000 },
268 { 300000, 511000 },
269 },
270 };
271
272 static const int lvds_vod_swing_clock_table[2][4][2] = {
273 { /* 100 Ohm */
274 { 140000, 244000 },
275 { 168000, 290000 },
276 { 195000, 335000 },
277 { 226000, 381000 },
278 },
279 { /* 200 Ohm */
280 { 117000, 204000 },
281 { 156000, 270000 },
282 { 195000, 334000 },
283 { 234000, 399000 },
284 },
285 };
286
bridge_to_sn65dsi83(struct drm_bridge * bridge)287 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
288 {
289 return container_of(bridge, struct sn65dsi83, bridge);
290 }
291
sn65dsi83_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)292 static int sn65dsi83_attach(struct drm_bridge *bridge,
293 enum drm_bridge_attach_flags flags)
294 {
295 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
296
297 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
298 &ctx->bridge, flags);
299 }
300
sn65dsi83_detach(struct drm_bridge * bridge)301 static void sn65dsi83_detach(struct drm_bridge *bridge)
302 {
303 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
304
305 if (!ctx->dsi)
306 return;
307
308 ctx->dsi = NULL;
309 }
310
sn65dsi83_get_lvds_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)311 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
312 const struct drm_display_mode *mode)
313 {
314 /*
315 * The encoding of the LVDS_CLK_RANGE is as follows:
316 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
317 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
318 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
319 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
320 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
321 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
322 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
323 * the ends of the ranges are clamped to the supported range. Since
324 * sn65dsi83_mode_valid() already filters the valid modes and limits
325 * the clock to 25..154 MHz, the range calculation can be simplified
326 * as follows:
327 */
328 int mode_clock = mode->clock;
329
330 if (ctx->lvds_dual_link)
331 mode_clock /= 2;
332
333 return (mode_clock - 12500) / 25000;
334 }
335
sn65dsi83_get_dsi_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)336 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
337 const struct drm_display_mode *mode)
338 {
339 /*
340 * The encoding of the CHA_DSI_CLK_RANGE is as follows:
341 * 0x00 through 0x07 - Reserved
342 * 0x08 - 40 <= DSI_CLK < 45 MHz
343 * 0x09 - 45 <= DSI_CLK < 50 MHz
344 * ...
345 * 0x63 - 495 <= DSI_CLK < 500 MHz
346 * 0x64 - 500 MHz
347 * 0x65 through 0xFF - Reserved
348 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
349 * The DSI clock are calculated as:
350 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
351 * the 2 is there because the bus is DDR.
352 */
353 return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
354 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
355 ctx->dsi->lanes / 2, 40000U, 500000U), 5000U);
356 }
357
sn65dsi83_get_dsi_div(struct sn65dsi83 * ctx)358 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
359 {
360 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
361 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
362
363 dsi_div /= ctx->dsi->lanes;
364
365 if (!ctx->lvds_dual_link)
366 dsi_div /= 2;
367
368 return dsi_div - 1;
369 }
370
sn65dsi83_reset_pipe(struct sn65dsi83 * sn65dsi83)371 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83)
372 {
373 struct drm_device *dev = sn65dsi83->bridge.dev;
374 struct drm_modeset_acquire_ctx ctx;
375 int err;
376
377 /*
378 * Reset active outputs of the related CRTC.
379 *
380 * This way, drm core will reconfigure each components in the CRTC
381 * outputs path. In our case, this will force the previous component to
382 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83
383 * bridge.
384 *
385 * Keep the lock during the whole operation to be atomic.
386 */
387
388 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, err);
389
390 if (!sn65dsi83->bridge.encoder->crtc) {
391 /*
392 * No CRTC attached -> No CRTC active outputs to reset
393 * This can happen when the SN65DSI83 is reset. Simply do
394 * nothing without returning any errors.
395 */
396 err = 0;
397 goto end;
398 }
399
400 dev_warn(sn65dsi83->dev, "reset the pipe\n");
401
402 err = drm_atomic_helper_reset_crtc(sn65dsi83->bridge.encoder->crtc, &ctx);
403
404 end:
405 DRM_MODESET_LOCK_ALL_END(dev, ctx, err);
406
407 return err;
408 }
409
sn65dsi83_reset_work(struct work_struct * ws)410 static void sn65dsi83_reset_work(struct work_struct *ws)
411 {
412 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work);
413 int ret;
414
415 /* Reset the pipe */
416 ret = sn65dsi83_reset_pipe(ctx);
417 if (ret) {
418 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret));
419 return;
420 }
421 if (ctx->irq)
422 enable_irq(ctx->irq);
423 }
424
sn65dsi83_handle_errors(struct sn65dsi83 * ctx)425 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx)
426 {
427 unsigned int irq_stat;
428 int ret;
429
430 /*
431 * Schedule a reset in case of:
432 * - the bridge doesn't answer
433 * - the bridge signals an error
434 */
435
436 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat);
437 if (ret || irq_stat) {
438 /*
439 * IRQ acknowledged is not always possible (the bridge can be in
440 * a state where it doesn't answer anymore). To prevent an
441 * interrupt storm, disable interrupt. The interrupt will be
442 * after the reset.
443 */
444 if (ctx->irq)
445 disable_irq_nosync(ctx->irq);
446
447 schedule_work(&ctx->reset_work);
448 }
449 }
450
sn65dsi83_monitor_work(struct work_struct * work)451 static void sn65dsi83_monitor_work(struct work_struct *work)
452 {
453 struct sn65dsi83 *ctx = container_of(to_delayed_work(work),
454 struct sn65dsi83, monitor_work);
455
456 sn65dsi83_handle_errors(ctx);
457
458 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
459 }
460
sn65dsi83_monitor_start(struct sn65dsi83 * ctx)461 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx)
462 {
463 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
464 }
465
sn65dsi83_monitor_stop(struct sn65dsi83 * ctx)466 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx)
467 {
468 cancel_delayed_work_sync(&ctx->monitor_work);
469 }
470
sn65dsi83_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)471 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
472 struct drm_atomic_state *state)
473 {
474 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
475 const struct drm_bridge_state *bridge_state;
476 const struct drm_crtc_state *crtc_state;
477 const struct drm_display_mode *mode;
478 struct drm_connector *connector;
479 struct drm_crtc *crtc;
480 bool lvds_format_24bpp;
481 bool lvds_format_jeida;
482 unsigned int pval;
483 __le16 le16val;
484 u16 val;
485 int ret;
486
487 ret = regulator_enable(ctx->vcc);
488 if (ret) {
489 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret);
490 return;
491 }
492
493 /* Deassert reset */
494 gpiod_set_value_cansleep(ctx->enable_gpio, 1);
495 usleep_range(10000, 11000);
496
497 /* Get the LVDS format from the bridge state. */
498 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
499
500 switch (bridge_state->output_bus_cfg.format) {
501 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
502 lvds_format_24bpp = false;
503 lvds_format_jeida = true;
504 break;
505 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
506 lvds_format_24bpp = true;
507 lvds_format_jeida = true;
508 break;
509 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
510 lvds_format_24bpp = true;
511 lvds_format_jeida = false;
512 break;
513 default:
514 /*
515 * Some bridges still don't set the correct
516 * LVDS bus pixel format, use SPWG24 default
517 * format until those are fixed.
518 */
519 lvds_format_24bpp = true;
520 lvds_format_jeida = false;
521 dev_warn(ctx->dev,
522 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
523 bridge_state->output_bus_cfg.format);
524 break;
525 }
526
527 /*
528 * Retrieve the CRTC adjusted mode. This requires a little dance to go
529 * from the bridge to the encoder, to the connector and to the CRTC.
530 */
531 connector = drm_atomic_get_new_connector_for_encoder(state,
532 bridge->encoder);
533 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
534 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
535 mode = &crtc_state->adjusted_mode;
536
537 /* Clear reset, disable PLL */
538 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
539 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
540
541 /* Reference clock derived from DSI link clock. */
542 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
543 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
544 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
545 regmap_write(ctx->regmap, REG_DSI_CLK,
546 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
547 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
548 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
549
550 /* Set number of DSI lanes and LVDS link config. */
551 regmap_write(ctx->regmap, REG_DSI_LANE,
552 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
553 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) |
554 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
555 REG_DSI_LANE_CHB_DSI_LANES(3));
556 /* No equalization. */
557 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
558
559 /* Set up sync signal polarity. */
560 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
561 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
562 (mode->flags & DRM_MODE_FLAG_NVSYNC ?
563 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
564 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ?
565 REG_LVDS_FMT_DE_NEG_POLARITY : 0;
566
567 /* Set up bits-per-pixel, 18bpp or 24bpp. */
568 if (lvds_format_24bpp) {
569 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
570 if (ctx->lvds_dual_link)
571 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
572 }
573
574 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
575 if (lvds_format_jeida) {
576 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
577 if (ctx->lvds_dual_link)
578 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
579 }
580
581 /* Set up LVDS output config (DSI84,DSI85) */
582 if (!ctx->lvds_dual_link)
583 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
584
585 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
586 regmap_write(ctx->regmap, REG_LVDS_VCOM,
587 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) |
588 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B]));
589 regmap_write(ctx->regmap, REG_LVDS_LANE,
590 (ctx->lvds_dual_link_even_odd_swap ?
591 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
592 (ctx->lvds_term_conf[CHANNEL_A] ?
593 REG_LVDS_LANE_CHA_LVDS_TERM : 0) |
594 (ctx->lvds_term_conf[CHANNEL_B] ?
595 REG_LVDS_LANE_CHB_LVDS_TERM : 0));
596 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
597
598 le16val = cpu_to_le16(mode->hdisplay);
599 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
600 &le16val, 2);
601 le16val = cpu_to_le16(mode->vdisplay);
602 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
603 &le16val, 2);
604 /* 32 + 1 pixel clock to ensure proper operation */
605 le16val = cpu_to_le16(32 + 1);
606 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
607 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
608 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
609 &le16val, 2);
610 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
611 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
612 &le16val, 2);
613 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
614 mode->htotal - mode->hsync_end);
615 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
616 mode->vtotal - mode->vsync_end);
617 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
618 mode->hsync_start - mode->hdisplay);
619 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
620 mode->vsync_start - mode->vdisplay);
621 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
622
623 /* Enable PLL */
624 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
625 usleep_range(3000, 4000);
626 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
627 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
628 1000, 100000);
629 if (ret) {
630 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
631 /* On failure, disable PLL again and exit. */
632 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
633 return;
634 }
635
636 /* Trigger reset after CSR register update. */
637 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
638
639 /* Wait for 10ms after soft reset as specified in datasheet */
640 usleep_range(10000, 12000);
641 }
642
sn65dsi83_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)643 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
644 struct drm_atomic_state *state)
645 {
646 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
647 unsigned int pval;
648
649 /* Clear all errors that got asserted during initialization. */
650 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
651 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
652
653 /* Wait for 1ms and check for errors in status register */
654 usleep_range(1000, 1100);
655 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
656 if (pval)
657 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval);
658
659 if (ctx->irq) {
660 /* Enable irq to detect errors */
661 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN);
662 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff);
663 } else {
664 /* Use the polling task */
665 sn65dsi83_monitor_start(ctx);
666 }
667 }
668
sn65dsi83_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)669 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
670 struct drm_atomic_state *state)
671 {
672 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
673 int ret;
674
675 if (ctx->irq) {
676 /* Disable irq */
677 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0);
678 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0);
679 } else {
680 /* Stop the polling task */
681 sn65dsi83_monitor_stop(ctx);
682 }
683
684 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
685 gpiod_set_value_cansleep(ctx->enable_gpio, 0);
686 usleep_range(10000, 11000);
687
688 ret = regulator_disable(ctx->vcc);
689 if (ret)
690 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
691
692 regcache_mark_dirty(ctx->regmap);
693 }
694
695 static enum drm_mode_status
sn65dsi83_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)696 sn65dsi83_mode_valid(struct drm_bridge *bridge,
697 const struct drm_display_info *info,
698 const struct drm_display_mode *mode)
699 {
700 /* LVDS output clock range 25..154 MHz */
701 if (mode->clock < 25000)
702 return MODE_CLOCK_LOW;
703 if (mode->clock > 154000)
704 return MODE_CLOCK_HIGH;
705
706 return MODE_OK;
707 }
708
709 #define MAX_INPUT_SEL_FORMATS 1
710
711 static u32 *
sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)712 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
713 struct drm_bridge_state *bridge_state,
714 struct drm_crtc_state *crtc_state,
715 struct drm_connector_state *conn_state,
716 u32 output_fmt,
717 unsigned int *num_input_fmts)
718 {
719 u32 *input_fmts;
720
721 *num_input_fmts = 0;
722
723 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
724 GFP_KERNEL);
725 if (!input_fmts)
726 return NULL;
727
728 /* This is the DSI-end bus format */
729 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
730 *num_input_fmts = 1;
731
732 return input_fmts;
733 }
734
735 static const struct drm_bridge_funcs sn65dsi83_funcs = {
736 .attach = sn65dsi83_attach,
737 .detach = sn65dsi83_detach,
738 .atomic_enable = sn65dsi83_atomic_enable,
739 .atomic_pre_enable = sn65dsi83_atomic_pre_enable,
740 .atomic_disable = sn65dsi83_atomic_disable,
741 .mode_valid = sn65dsi83_mode_valid,
742
743 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
744 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
745 .atomic_reset = drm_atomic_helper_bridge_reset,
746 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
747 };
748
sn65dsi83_select_lvds_vod_swing(struct device * dev,u32 lvds_vod_swing_data[2],u32 lvds_vod_swing_clk[2],u8 lvds_term)749 static int sn65dsi83_select_lvds_vod_swing(struct device *dev,
750 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term)
751 {
752 int i;
753
754 for (i = 0; i <= 3; i++) {
755 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] &&
756 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] &&
757 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] &&
758 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1])
759 return i;
760 }
761
762 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n");
763 return -EINVAL;
764 }
765
sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 * ctx,int channel)766 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
767 {
768 struct device *dev = ctx->dev;
769 struct device_node *endpoint;
770 int endpoint_reg;
771 /* Set so the property can be freely selected if not defined */
772 u32 lvds_vod_swing_data[2] = { 0, 1000000 };
773 u32 lvds_vod_swing_clk[2] = { 0, 1000000 };
774 /* Set default near end terminataion to 200 Ohm */
775 u32 lvds_term = 200;
776 int lvds_vod_swing_conf;
777 int ret = 0;
778 int ret_data;
779 int ret_clock;
780
781 if (channel == CHANNEL_A)
782 endpoint_reg = 2;
783 else
784 endpoint_reg = 3;
785
786 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1);
787
788 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term);
789 if (lvds_term == 100)
790 ctx->lvds_term_conf[channel] = OHM_100;
791 else if (lvds_term == 200)
792 ctx->lvds_term_conf[channel] = OHM_200;
793 else {
794 ret = -EINVAL;
795 goto exit;
796 }
797
798 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt",
799 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data));
800 if (ret_data != 0 && ret_data != -EINVAL) {
801 ret = ret_data;
802 goto exit;
803 }
804
805 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt",
806 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk));
807 if (ret_clock != 0 && ret_clock != -EINVAL) {
808 ret = ret_clock;
809 goto exit;
810 }
811
812 /* Use default value if both properties are NOT defined. */
813 if (ret_data == -EINVAL && ret_clock == -EINVAL)
814 lvds_vod_swing_conf = 0x1;
815
816 /* Use lookup table if any of the two properties is defined. */
817 if (!ret_data || !ret_clock) {
818 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data,
819 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]);
820 if (lvds_vod_swing_conf < 0) {
821 ret = lvds_vod_swing_conf;
822 goto exit;
823 }
824 }
825
826 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf;
827 ret = 0;
828 exit:
829 of_node_put(endpoint);
830 return ret;
831 }
832
sn65dsi83_parse_dt(struct sn65dsi83 * ctx,enum sn65dsi83_model model)833 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
834 {
835 struct drm_bridge *panel_bridge;
836 struct device *dev = ctx->dev;
837 int ret;
838
839 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A);
840 if (ret < 0)
841 return ret;
842
843 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B);
844 if (ret < 0)
845 return ret;
846
847 ctx->lvds_dual_link = false;
848 ctx->lvds_dual_link_even_odd_swap = false;
849 if (model != MODEL_SN65DSI83) {
850 struct device_node *port2, *port3;
851 int dual_link;
852
853 port2 = of_graph_get_port_by_id(dev->of_node, 2);
854 port3 = of_graph_get_port_by_id(dev->of_node, 3);
855 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
856 of_node_put(port2);
857 of_node_put(port3);
858
859 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
860 ctx->lvds_dual_link = true;
861 /* Odd pixels to LVDS Channel A, even pixels to B */
862 ctx->lvds_dual_link_even_odd_swap = false;
863 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
864 ctx->lvds_dual_link = true;
865 /* Even pixels to LVDS Channel A, odd pixels to B */
866 ctx->lvds_dual_link_even_odd_swap = true;
867 }
868 }
869
870 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
871 if (IS_ERR(panel_bridge))
872 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n");
873
874 ctx->panel_bridge = panel_bridge;
875
876 ctx->vcc = devm_regulator_get(dev, "vcc");
877 if (IS_ERR(ctx->vcc))
878 return dev_err_probe(dev, PTR_ERR(ctx->vcc),
879 "Failed to get supply 'vcc'\n");
880
881 return 0;
882 }
883
sn65dsi83_host_attach(struct sn65dsi83 * ctx)884 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
885 {
886 struct device *dev = ctx->dev;
887 struct device_node *host_node;
888 struct device_node *endpoint;
889 struct mipi_dsi_device *dsi;
890 struct mipi_dsi_host *host;
891 const struct mipi_dsi_device_info info = {
892 .type = "sn65dsi83",
893 .channel = 0,
894 .node = NULL,
895 };
896 int dsi_lanes, ret;
897
898 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
899 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
900 host_node = of_graph_get_remote_port_parent(endpoint);
901 host = of_find_mipi_dsi_host_by_node(host_node);
902 of_node_put(host_node);
903 of_node_put(endpoint);
904
905 if (!host)
906 return -EPROBE_DEFER;
907
908 if (dsi_lanes < 0)
909 return dsi_lanes;
910
911 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
912 if (IS_ERR(dsi))
913 return dev_err_probe(dev, PTR_ERR(dsi),
914 "failed to create dsi device\n");
915
916 ctx->dsi = dsi;
917
918 dsi->lanes = dsi_lanes;
919 dsi->format = MIPI_DSI_FMT_RGB888;
920 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
921 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
922 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET;
923
924 ret = devm_mipi_dsi_attach(dev, dsi);
925 if (ret < 0) {
926 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
927 return ret;
928 }
929
930 return 0;
931 }
932
sn65dsi83_irq(int irq,void * data)933 static irqreturn_t sn65dsi83_irq(int irq, void *data)
934 {
935 struct sn65dsi83 *ctx = data;
936
937 sn65dsi83_handle_errors(ctx);
938 return IRQ_HANDLED;
939 }
940
sn65dsi83_probe(struct i2c_client * client)941 static int sn65dsi83_probe(struct i2c_client *client)
942 {
943 const struct i2c_device_id *id = i2c_client_get_device_id(client);
944 struct device *dev = &client->dev;
945 enum sn65dsi83_model model;
946 struct sn65dsi83 *ctx;
947 int ret;
948
949 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
950 if (!ctx)
951 return -ENOMEM;
952
953 ctx->dev = dev;
954 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work);
955 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work);
956
957 if (dev->of_node) {
958 model = (enum sn65dsi83_model)(uintptr_t)
959 of_device_get_match_data(dev);
960 } else {
961 model = id->driver_data;
962 }
963
964 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
965 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable",
966 GPIOD_OUT_LOW);
967 if (IS_ERR(ctx->enable_gpio))
968 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n");
969
970 usleep_range(10000, 11000);
971
972 ret = sn65dsi83_parse_dt(ctx, model);
973 if (ret)
974 return ret;
975
976 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
977 if (IS_ERR(ctx->regmap))
978 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n");
979
980 if (client->irq) {
981 ctx->irq = client->irq;
982 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq,
983 IRQF_ONESHOT, dev_name(ctx->dev), ctx);
984 if (ret)
985 return dev_err_probe(dev, ret, "failed to request irq\n");
986 }
987
988 dev_set_drvdata(dev, ctx);
989 i2c_set_clientdata(client, ctx);
990
991 ctx->bridge.funcs = &sn65dsi83_funcs;
992 ctx->bridge.of_node = dev->of_node;
993 ctx->bridge.pre_enable_prev_first = true;
994 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS;
995 drm_bridge_add(&ctx->bridge);
996
997 ret = sn65dsi83_host_attach(ctx);
998 if (ret) {
999 dev_err_probe(dev, ret, "failed to attach DSI host\n");
1000 goto err_remove_bridge;
1001 }
1002
1003 return 0;
1004
1005 err_remove_bridge:
1006 drm_bridge_remove(&ctx->bridge);
1007 return ret;
1008 }
1009
sn65dsi83_remove(struct i2c_client * client)1010 static void sn65dsi83_remove(struct i2c_client *client)
1011 {
1012 struct sn65dsi83 *ctx = i2c_get_clientdata(client);
1013
1014 drm_bridge_remove(&ctx->bridge);
1015 }
1016
1017 static const struct i2c_device_id sn65dsi83_id[] = {
1018 { "ti,sn65dsi83", MODEL_SN65DSI83 },
1019 { "ti,sn65dsi84", MODEL_SN65DSI84 },
1020 {},
1021 };
1022 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
1023
1024 static const struct of_device_id sn65dsi83_match_table[] = {
1025 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
1026 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
1027 {},
1028 };
1029 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
1030
1031 static struct i2c_driver sn65dsi83_driver = {
1032 .probe = sn65dsi83_probe,
1033 .remove = sn65dsi83_remove,
1034 .id_table = sn65dsi83_id,
1035 .driver = {
1036 .name = "sn65dsi83",
1037 .of_match_table = sn65dsi83_match_table,
1038 },
1039 };
1040 module_i2c_driver(sn65dsi83_driver);
1041
1042 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1043 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
1044 MODULE_LICENSE("GPL v2");
1045