1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TC358775 DSI to LVDS bridge driver
4 *
5 * Copyright (C) 2020 SMART Wireless Computing
6 * Author: Vinay Simha BN <simhavcs@gmail.com>
7 *
8 */
9 /* #define DEBUG */
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/kernel.h>
16 #include <linux/media-bus-format.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21
22 #include <linux/unaligned.h>
23
24 #include <drm/display/drm_dp_helper.h>
25 #include <drm/drm_atomic_helper.h>
26 #include <drm/drm_bridge.h>
27 #include <drm/drm_mipi_dsi.h>
28 #include <drm/drm_of.h>
29 #include <drm/drm_probe_helper.h>
30
31 #define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
32
33 /* Registers */
34
35 /* DSI D-PHY Layer Registers */
36 #define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
43 #define CLW_CNTRL 0x0040 /* Clock Lane Control */
44 #define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
45 #define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
46 #define D2W_CNTRL 0x004C /* Data Lane 2 Control */
47 #define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
48 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
49
50 /* DSI PPI Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
52 #define PPI_START_FUNCTION 1
53
54 #define PPI_BUSYPPI 0x0108
55 #define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */
56 #define PPI_LPTXTIMECNT 0x0114
57 #define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
59
60 /* Analog timer function enable */
61 #define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
62 #define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
63 #define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
64 #define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
65 #define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
66
67 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */
68 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
69 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
70 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
71
72 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
73 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
74 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
75 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
76 #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
77 #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
78 #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
79 #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
80 #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
81 #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
82 #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
83 #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
84 #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
85 #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
86 #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
87
88 #define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */
89 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
90 #define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
91 #define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
93 #define DSI_RX_START 1
94
95 #define DSI_BUSYDSI 0x0208
96 #define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
97 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
98 #define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
99
100 #define DSI_INTSTATUS 0x0220 /* Interrupt Status */
101 #define DSI_INTMASK 0x0224 /* Interrupt Mask */
102 #define DSI_INTCLR 0x0228 /* Interrupt Clear */
103 #define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */
104
105 #define DSIERRCNT 0x0300 /* DSI Error Count */
106 #define APLCTRL 0x0400 /* Application Layer Control */
107 #define RDPKTLN 0x0404 /* Command Read Packet Length */
108
109 #define VPCTRL 0x0450 /* Video Path Control */
110 #define EVTMODE BIT(5) /* Video event mode enable, tc35876x only */
111 #define HTIM1 0x0454 /* Horizontal Timing Control 1 */
112 #define HTIM2 0x0458 /* Horizontal Timing Control 2 */
113 #define VTIM1 0x045C /* Vertical Timing Control 1 */
114 #define VTIM2 0x0460 /* Vertical Timing Control 2 */
115 #define VFUEN 0x0464 /* Video Frame Timing Update Enable */
116 #define VFUEN_EN BIT(0) /* Upload Enable */
117
118 /* Mux Input Select for LVDS LINK Input */
119 #define LV_MX0003 0x0480 /* Bit 0 to 3 */
120 #define LV_MX0407 0x0484 /* Bit 4 to 7 */
121 #define LV_MX0811 0x0488 /* Bit 8 to 11 */
122 #define LV_MX1215 0x048C /* Bit 12 to 15 */
123 #define LV_MX1619 0x0490 /* Bit 16 to 19 */
124 #define LV_MX2023 0x0494 /* Bit 20 to 23 */
125 #define LV_MX2427 0x0498 /* Bit 24 to 27 */
126 #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
127 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
128
129 /* Input bit numbers used in mux registers */
130 enum {
131 LVI_R0,
132 LVI_R1,
133 LVI_R2,
134 LVI_R3,
135 LVI_R4,
136 LVI_R5,
137 LVI_R6,
138 LVI_R7,
139 LVI_G0,
140 LVI_G1,
141 LVI_G2,
142 LVI_G3,
143 LVI_G4,
144 LVI_G5,
145 LVI_G6,
146 LVI_G7,
147 LVI_B0,
148 LVI_B1,
149 LVI_B2,
150 LVI_B3,
151 LVI_B4,
152 LVI_B5,
153 LVI_B6,
154 LVI_B7,
155 LVI_HS,
156 LVI_VS,
157 LVI_DE,
158 LVI_L0
159 };
160
161 #define LVCFG 0x049C /* LVDS Configuration */
162 #define LVPHY0 0x04A0 /* LVDS PHY 0 */
163 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
164 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
165 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
166 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
167
168 #define LVPHY1 0x04A4 /* LVDS PHY 1 */
169 #define SYSSTAT 0x0500 /* System Status */
170 #define SYSRST 0x0504 /* System Reset */
171
172 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
173 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
174 #define SYS_RST_LCD BIT(2) /* Reset LCD controller */
175 #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
176 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
177 #define SYS_RST_REG BIT(5) /* Reset Register module */
178
179 /* GPIO Registers */
180 #define GPIOC 0x0520 /* GPIO Control */
181 #define GPIOO 0x0524 /* GPIO Output */
182 #define GPIOI 0x0528 /* GPIO Input */
183
184 /* I2C Registers */
185 #define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */
186 #define I2CMADDR 0x0544 /* I2C Master Addressing */
187 #define WDATAQ 0x0548 /* Write Data Queue */
188 #define RDATAQ 0x054C /* Read Data Queue */
189
190 /* Chip ID and Revision ID Register */
191 #define IDREG 0x0580
192
193 #define LPX_PERIOD 4
194 #define TTA_GET 0x40000
195 #define TTA_SURE 6
196 #define SINGLE_LINK 1
197 #define DUAL_LINK 2
198
199 #define TC358775XBG_ID 0x00007500
200
201 /* Debug Registers */
202 #define DEBUG00 0x05A0 /* Debug */
203 #define DEBUG01 0x05A4 /* LVDS Data */
204
205 #define DSI_CLEN_BIT BIT(0)
206 #define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */
207 #define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */
208 #define LVCFG_LVEN_BIT BIT(0)
209
210 #define L0EN BIT(1)
211
212 #define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000
213 #define TC358775_VPCTRL_VSDELAY__SHIFT 20
TC358775_VPCTRL_VSDELAY(uint32_t val)214 static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
215 {
216 return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
217 TC358775_VPCTRL_VSDELAY__MASK;
218 }
219
220 #define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100
221 #define TC358775_VPCTRL_OPXLFMT__SHIFT 8
TC358775_VPCTRL_OPXLFMT(uint32_t val)222 static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
223 {
224 return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
225 TC358775_VPCTRL_OPXLFMT__MASK;
226 }
227
228 #define TC358775_VPCTRL_MSF__MASK 0x00000001
229 #define TC358775_VPCTRL_MSF__SHIFT 0
TC358775_VPCTRL_MSF(uint32_t val)230 static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
231 {
232 return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
233 TC358775_VPCTRL_MSF__MASK;
234 }
235
236 #define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
237 #define TC358775_LVCFG_PCLKDIV__SHIFT 4
TC358775_LVCFG_PCLKDIV(uint32_t val)238 static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
239 {
240 return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
241 TC358775_LVCFG_PCLKDIV__MASK;
242 }
243
244 #define TC358775_LVCFG_LVDLINK__MASK 0x00000002
245 #define TC358775_LVCFG_LVDLINK__SHIFT 1
TC358775_LVCFG_LVDLINK(uint32_t val)246 static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
247 {
248 return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
249 TC358775_LVCFG_LVDLINK__MASK;
250 }
251
252 enum tc358775_ports {
253 TC358775_DSI_IN,
254 TC358775_LVDS_OUT0,
255 TC358775_LVDS_OUT1,
256 };
257
258 enum tc3587x5_type {
259 TC358765 = 0x65,
260 TC358775 = 0x75,
261 };
262
263 struct tc_data {
264 struct i2c_client *i2c;
265 struct device *dev;
266
267 struct drm_bridge bridge;
268 struct drm_bridge *panel_bridge;
269
270 struct device_node *host_node;
271 struct mipi_dsi_device *dsi;
272 u8 num_dsi_lanes;
273
274 struct regulator *vdd;
275 struct regulator *vddio;
276 struct gpio_desc *reset_gpio;
277 struct gpio_desc *stby_gpio;
278 u8 lvds_link; /* single-link or dual-link */
279 u8 bpc;
280
281 enum tc3587x5_type type;
282 };
283
bridge_to_tc(struct drm_bridge * b)284 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
285 {
286 return container_of(b, struct tc_data, bridge);
287 }
288
tc_bridge_pre_enable(struct drm_bridge * bridge)289 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
290 {
291 struct tc_data *tc = bridge_to_tc(bridge);
292 struct device *dev = &tc->dsi->dev;
293 int ret;
294
295 ret = regulator_enable(tc->vddio);
296 if (ret < 0)
297 dev_err(dev, "regulator vddio enable failed, %d\n", ret);
298 usleep_range(10000, 11000);
299
300 ret = regulator_enable(tc->vdd);
301 if (ret < 0)
302 dev_err(dev, "regulator vdd enable failed, %d\n", ret);
303 usleep_range(10000, 11000);
304
305 gpiod_set_value(tc->stby_gpio, 0);
306 usleep_range(10000, 11000);
307
308 gpiod_set_value(tc->reset_gpio, 0);
309 usleep_range(10, 20);
310 }
311
tc_bridge_post_disable(struct drm_bridge * bridge)312 static void tc_bridge_post_disable(struct drm_bridge *bridge)
313 {
314 struct tc_data *tc = bridge_to_tc(bridge);
315 struct device *dev = &tc->dsi->dev;
316 int ret;
317
318 gpiod_set_value(tc->reset_gpio, 1);
319 usleep_range(10, 20);
320
321 gpiod_set_value(tc->stby_gpio, 1);
322 usleep_range(10000, 11000);
323
324 ret = regulator_disable(tc->vdd);
325 if (ret < 0)
326 dev_err(dev, "regulator vdd disable failed, %d\n", ret);
327 usleep_range(10000, 11000);
328
329 ret = regulator_disable(tc->vddio);
330 if (ret < 0)
331 dev_err(dev, "regulator vddio disable failed, %d\n", ret);
332 usleep_range(10000, 11000);
333 }
334
d2l_read(struct i2c_client * i2c,u16 addr,u32 * val)335 static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
336 {
337 int ret;
338 u8 buf_addr[2];
339
340 put_unaligned_be16(addr, buf_addr);
341 ret = i2c_master_send(i2c, buf_addr, sizeof(buf_addr));
342 if (ret < 0)
343 goto fail;
344
345 ret = i2c_master_recv(i2c, (u8 *)val, sizeof(*val));
346 if (ret < 0)
347 goto fail;
348
349 pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
350 return;
351
352 fail:
353 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
354 ret, addr);
355 }
356
d2l_write(struct i2c_client * i2c,u16 addr,u32 val)357 static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
358 {
359 u8 data[6];
360 int ret;
361
362 put_unaligned_be16(addr, data);
363 put_unaligned_le32(val, data + 2);
364
365 ret = i2c_master_send(i2c, data, ARRAY_SIZE(data));
366 if (ret < 0)
367 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
368 ret, addr);
369 }
370
371 /* helper function to access bus_formats */
get_connector(struct drm_encoder * encoder)372 static struct drm_connector *get_connector(struct drm_encoder *encoder)
373 {
374 struct drm_device *dev = encoder->dev;
375 struct drm_connector *connector;
376
377 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
378 if (connector->encoder == encoder)
379 return connector;
380
381 return NULL;
382 }
383
tc_bridge_enable(struct drm_bridge * bridge)384 static void tc_bridge_enable(struct drm_bridge *bridge)
385 {
386 struct tc_data *tc = bridge_to_tc(bridge);
387 u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
388 u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
389 u32 val = 0;
390 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
391 struct drm_display_mode *mode;
392 struct drm_connector *connector = get_connector(bridge->encoder);
393
394 mode = &bridge->encoder->crtc->state->adjusted_mode;
395
396 hback_porch = mode->htotal - mode->hsync_end;
397 hsync_len = mode->hsync_end - mode->hsync_start;
398 vback_porch = mode->vtotal - mode->vsync_end;
399 vsync_len = mode->vsync_end - mode->vsync_start;
400
401 htime1 = (hback_porch << 16) + hsync_len;
402 vtime1 = (vback_porch << 16) + vsync_len;
403
404 hfront_porch = mode->hsync_start - mode->hdisplay;
405 hactive = mode->hdisplay;
406 vfront_porch = mode->vsync_start - mode->vdisplay;
407 vactive = mode->vdisplay;
408
409 htime2 = (hfront_porch << 16) + hactive;
410 vtime2 = (vfront_porch << 16) + vactive;
411
412 d2l_read(tc->i2c, IDREG, &val);
413
414 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
415 (val >> 8) & 0xFF, val & 0xFF);
416
417 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
418 SYS_RST_LCD | SYS_RST_I2CM);
419 usleep_range(30000, 40000);
420
421 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
422 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
423 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
424 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
425 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
426 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
427
428 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
429 d2l_write(tc->i2c, PPI_LANEENABLE, val);
430 d2l_write(tc->i2c, DSI_LANEENABLE, val);
431
432 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
433 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
434
435 /* Video event mode vs pulse mode bit, does not exist for tc358775 */
436 if (tc->type == TC358765)
437 val = EVTMODE;
438 else
439 val = 0;
440
441 if (tc->bpc == 8)
442 val |= TC358775_VPCTRL_OPXLFMT(1);
443 else /* bpc = 6; */
444 val |= TC358775_VPCTRL_MSF(1);
445
446 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
447 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);
448 byteclk = dsiclk / 4;
449 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
450 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
451 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
452 tc->num_dsi_lanes);
453
454 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
455
456 val |= TC358775_VPCTRL_VSDELAY(vsdelay);
457 d2l_write(tc->i2c, VPCTRL, val);
458
459 d2l_write(tc->i2c, HTIM1, htime1);
460 d2l_write(tc->i2c, VTIM1, vtime1);
461 d2l_write(tc->i2c, HTIM2, htime2);
462 d2l_write(tc->i2c, VTIM2, vtime2);
463
464 d2l_write(tc->i2c, VFUEN, VFUEN_EN);
465 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
466 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
467
468 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
469 connector->display_info.bus_formats[0],
470 tc->bpc);
471 if (connector->display_info.bus_formats[0] ==
472 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
473 /* VESA-24 */
474 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
475 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
476 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
477 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
478 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
479 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
480 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
481 } else {
482 /* JEIDA-18 and JEIDA-24 */
483 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5));
484 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2));
485 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1));
486 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2));
487 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4));
488 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0));
489 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0));
490 }
491
492 d2l_write(tc->i2c, VFUEN, VFUEN_EN);
493
494 val = LVCFG_LVEN_BIT;
495 if (tc->lvds_link == DUAL_LINK) {
496 val |= TC358775_LVCFG_LVDLINK(1);
497 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
498 } else {
499 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
500 }
501 d2l_write(tc->i2c, LVCFG, val);
502 }
503
504 static enum drm_mode_status
tc_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)505 tc_mode_valid(struct drm_bridge *bridge,
506 const struct drm_display_info *info,
507 const struct drm_display_mode *mode)
508 {
509 struct tc_data *tc = bridge_to_tc(bridge);
510
511 /*
512 * Maximum pixel clock speed 135MHz for single-link
513 * 270MHz for dual-link
514 */
515 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
516 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
517 return MODE_CLOCK_HIGH;
518
519 switch (info->bus_formats[0]) {
520 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
521 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
522 /* RGB888 */
523 tc->bpc = 8;
524 break;
525 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
526 /* RGB666 */
527 tc->bpc = 6;
528 break;
529 default:
530 dev_warn(tc->dev,
531 "unsupported LVDS bus format 0x%04x\n",
532 info->bus_formats[0]);
533 return MODE_NOMODE;
534 }
535
536 return MODE_OK;
537 }
538
tc358775_parse_dt(struct device_node * np,struct tc_data * tc)539 static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
540 {
541 struct device_node *endpoint;
542 struct device_node *remote;
543 int dsi_lanes = -1;
544
545 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
546 TC358775_DSI_IN, -1);
547 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
548
549 /* Quirk old dtb: Use data lanes from the DSI host side instead of bridge */
550 if (dsi_lanes == -EINVAL || dsi_lanes == -ENODEV) {
551 remote = of_graph_get_remote_endpoint(endpoint);
552 dsi_lanes = drm_of_get_data_lanes_count(remote, 1, 4);
553 of_node_put(remote);
554 if (dsi_lanes >= 1)
555 dev_warn(tc->dev, "no dsi-lanes for the bridge, using host lanes\n");
556 }
557
558 of_node_put(endpoint);
559
560 if (dsi_lanes < 0)
561 return dsi_lanes;
562
563 tc->num_dsi_lanes = dsi_lanes;
564
565 tc->host_node = of_graph_get_remote_node(np, 0, 0);
566 if (!tc->host_node)
567 return -ENODEV;
568
569 of_node_put(tc->host_node);
570
571 tc->lvds_link = SINGLE_LINK;
572 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node,
573 TC358775_LVDS_OUT1, -1);
574 if (endpoint) {
575 remote = of_graph_get_remote_port_parent(endpoint);
576 of_node_put(endpoint);
577
578 if (remote) {
579 if (of_device_is_available(remote))
580 tc->lvds_link = DUAL_LINK;
581 of_node_put(remote);
582 }
583 }
584
585 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
586 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
587
588 return 0;
589 }
590
tc_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)591 static int tc_bridge_attach(struct drm_bridge *bridge,
592 enum drm_bridge_attach_flags flags)
593 {
594 struct tc_data *tc = bridge_to_tc(bridge);
595
596 /* Attach the panel-bridge to the dsi bridge */
597 return drm_bridge_attach(bridge->encoder, tc->panel_bridge,
598 &tc->bridge, flags);
599 }
600
601 static const struct drm_bridge_funcs tc_bridge_funcs = {
602 .attach = tc_bridge_attach,
603 .pre_enable = tc_bridge_pre_enable,
604 .enable = tc_bridge_enable,
605 .mode_valid = tc_mode_valid,
606 .post_disable = tc_bridge_post_disable,
607 };
608
tc_attach_host(struct tc_data * tc)609 static int tc_attach_host(struct tc_data *tc)
610 {
611 struct device *dev = &tc->i2c->dev;
612 struct mipi_dsi_host *host;
613 struct mipi_dsi_device *dsi;
614 int ret;
615 const struct mipi_dsi_device_info info = { .type = "tc358775",
616 .channel = 0,
617 .node = NULL,
618 };
619
620 host = of_find_mipi_dsi_host_by_node(tc->host_node);
621 if (!host)
622 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n");
623
624 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
625 if (IS_ERR(dsi)) {
626 dev_err(dev, "failed to create dsi device\n");
627 return PTR_ERR(dsi);
628 }
629
630 tc->dsi = dsi;
631
632 dsi->lanes = tc->num_dsi_lanes;
633 dsi->format = MIPI_DSI_FMT_RGB888;
634 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
635 MIPI_DSI_MODE_LPM;
636
637 /*
638 * The hs_rate and lp_rate are data rate values. The HS mode is
639 * differential, while the LP mode is single ended. As the HS mode
640 * uses DDR, the DSI clock frequency is half the hs_rate. The 10 Mbs
641 * data rate for LP mode is not specified in the bridge data sheet,
642 * but seems to be part of the MIPI DSI spec.
643 */
644 if (tc->type == TC358765)
645 dsi->hs_rate = 800000000;
646 else
647 dsi->hs_rate = 1000000000;
648 dsi->lp_rate = 10000000;
649
650 ret = devm_mipi_dsi_attach(dev, dsi);
651 if (ret < 0) {
652 dev_err(dev, "failed to attach dsi to host\n");
653 return ret;
654 }
655
656 return 0;
657 }
658
tc_probe(struct i2c_client * client)659 static int tc_probe(struct i2c_client *client)
660 {
661 struct device *dev = &client->dev;
662 struct tc_data *tc;
663 int ret;
664
665 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
666 if (!tc)
667 return -ENOMEM;
668
669 tc->dev = dev;
670 tc->i2c = client;
671 tc->type = (enum tc3587x5_type)(unsigned long)of_device_get_match_data(dev);
672
673 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
674 TC358775_LVDS_OUT0, 0);
675 if (IS_ERR(tc->panel_bridge))
676 return PTR_ERR(tc->panel_bridge);
677
678 ret = tc358775_parse_dt(dev->of_node, tc);
679 if (ret)
680 return ret;
681
682 tc->vddio = devm_regulator_get(dev, "vddio-supply");
683 if (IS_ERR(tc->vddio)) {
684 ret = PTR_ERR(tc->vddio);
685 dev_err(dev, "vddio-supply not found\n");
686 return ret;
687 }
688
689 tc->vdd = devm_regulator_get(dev, "vdd-supply");
690 if (IS_ERR(tc->vdd)) {
691 ret = PTR_ERR(tc->vdd);
692 dev_err(dev, "vdd-supply not found\n");
693 return ret;
694 }
695
696 tc->stby_gpio = devm_gpiod_get_optional(dev, "stby", GPIOD_OUT_HIGH);
697 if (IS_ERR(tc->stby_gpio))
698 return PTR_ERR(tc->stby_gpio);
699
700 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
701 if (IS_ERR(tc->reset_gpio)) {
702 ret = PTR_ERR(tc->reset_gpio);
703 dev_err(dev, "cannot get reset-gpios %d\n", ret);
704 return ret;
705 }
706
707 tc->bridge.funcs = &tc_bridge_funcs;
708 tc->bridge.of_node = dev->of_node;
709 tc->bridge.pre_enable_prev_first = true;
710 drm_bridge_add(&tc->bridge);
711
712 i2c_set_clientdata(client, tc);
713
714 ret = tc_attach_host(tc);
715 if (ret)
716 goto err_bridge_remove;
717
718 return 0;
719
720 err_bridge_remove:
721 drm_bridge_remove(&tc->bridge);
722 return ret;
723 }
724
tc_remove(struct i2c_client * client)725 static void tc_remove(struct i2c_client *client)
726 {
727 struct tc_data *tc = i2c_get_clientdata(client);
728
729 drm_bridge_remove(&tc->bridge);
730 }
731
732 static const struct i2c_device_id tc358775_i2c_ids[] = {
733 { "tc358765", TC358765, },
734 { "tc358775", TC358775, },
735 { }
736 };
737 MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
738
739 static const struct of_device_id tc358775_of_ids[] = {
740 { .compatible = "toshiba,tc358765", .data = (void *)TC358765, },
741 { .compatible = "toshiba,tc358775", .data = (void *)TC358775, },
742 { }
743 };
744 MODULE_DEVICE_TABLE(of, tc358775_of_ids);
745
746 static struct i2c_driver tc358775_driver = {
747 .driver = {
748 .name = "tc358775",
749 .of_match_table = tc358775_of_ids,
750 },
751 .id_table = tc358775_i2c_ids,
752 .probe = tc_probe,
753 .remove = tc_remove,
754 };
755 module_i2c_driver(tc358775_driver);
756
757 MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
758 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
759 MODULE_LICENSE("GPL v2");
760