1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2020 BayLibre, SAS
4  * Author: Phong LE <ple@baylibre.com>
5  * Copyright (C) 2018-2019, Artem Mygaiev
6  * Copyright (C) 2017, Fresco Logic, Incorporated.
7  *
8  */
9 
10 #include <linux/media-bus-format.h>
11 #include <linux/module.h>
12 #include <linux/device.h>
13 #include <linux/interrupt.h>
14 #include <linux/i2c.h>
15 #include <linux/bitfield.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 #include <linux/of_graph.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/regulator/consumer.h>
22 
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_bridge.h>
25 #include <drm/drm_edid.h>
26 #include <drm/drm_modes.h>
27 #include <drm/drm_print.h>
28 #include <drm/drm_probe_helper.h>
29 
30 #include <sound/hdmi-codec.h>
31 
32 #define IT66121_VENDOR_ID0_REG			0x00
33 #define IT66121_VENDOR_ID1_REG			0x01
34 #define IT66121_DEVICE_ID0_REG			0x02
35 #define IT66121_DEVICE_ID1_REG			0x03
36 
37 #define IT66121_REVISION_MASK			GENMASK(7, 4)
38 #define IT66121_DEVICE_ID1_MASK			GENMASK(3, 0)
39 
40 #define IT66121_MASTER_SEL_REG			0x10
41 #define IT66121_MASTER_SEL_HOST			BIT(0)
42 
43 #define IT66121_AFE_DRV_REG			0x61
44 #define IT66121_AFE_DRV_RST			BIT(4)
45 #define IT66121_AFE_DRV_PWD			BIT(5)
46 
47 #define IT66121_INPUT_MODE_REG			0x70
48 #define IT66121_INPUT_MODE_RGB			(0 << 6)
49 #define IT66121_INPUT_MODE_YUV422		BIT(6)
50 #define IT66121_INPUT_MODE_YUV444		(2 << 6)
51 #define IT66121_INPUT_MODE_CCIR656		BIT(4)
52 #define IT66121_INPUT_MODE_SYNCEMB		BIT(3)
53 #define IT66121_INPUT_MODE_DDR			BIT(2)
54 
55 #define IT66121_INPUT_CSC_REG			0x72
56 #define IT66121_INPUT_CSC_ENDITHER		BIT(7)
57 #define IT66121_INPUT_CSC_ENUDFILTER		BIT(6)
58 #define IT66121_INPUT_CSC_DNFREE_GO		BIT(5)
59 #define IT66121_INPUT_CSC_RGB_TO_YUV		0x02
60 #define IT66121_INPUT_CSC_YUV_TO_RGB		0x03
61 #define IT66121_INPUT_CSC_NO_CONV		0x00
62 
63 #define IT66121_AFE_XP_REG			0x62
64 #define IT66121_AFE_XP_GAINBIT			BIT(7)
65 #define IT66121_AFE_XP_PWDPLL			BIT(6)
66 #define IT66121_AFE_XP_ENI			BIT(5)
67 #define IT66121_AFE_XP_ENO			BIT(4)
68 #define IT66121_AFE_XP_RESETB			BIT(3)
69 #define IT66121_AFE_XP_PWDI			BIT(2)
70 #define IT6610_AFE_XP_BYPASS			BIT(0)
71 
72 #define IT66121_AFE_IP_REG			0x64
73 #define IT66121_AFE_IP_GAINBIT			BIT(7)
74 #define IT66121_AFE_IP_PWDPLL			BIT(6)
75 #define IT66121_AFE_IP_CKSEL_05			(0 << 4)
76 #define IT66121_AFE_IP_CKSEL_1			BIT(4)
77 #define IT66121_AFE_IP_CKSEL_2			(2 << 4)
78 #define IT66121_AFE_IP_CKSEL_2OR4		(3 << 4)
79 #define IT66121_AFE_IP_ER0			BIT(3)
80 #define IT66121_AFE_IP_RESETB			BIT(2)
81 #define IT66121_AFE_IP_ENC			BIT(1)
82 #define IT66121_AFE_IP_EC1			BIT(0)
83 
84 #define IT66121_AFE_XP_EC1_REG			0x68
85 #define IT66121_AFE_XP_EC1_LOWCLK		BIT(4)
86 
87 #define IT66121_SW_RST_REG			0x04
88 #define IT66121_SW_RST_REF			BIT(5)
89 #define IT66121_SW_RST_AREF			BIT(4)
90 #define IT66121_SW_RST_VID			BIT(3)
91 #define IT66121_SW_RST_AUD			BIT(2)
92 #define IT66121_SW_RST_HDCP			BIT(0)
93 
94 #define IT66121_DDC_COMMAND_REG			0x15
95 #define IT66121_DDC_COMMAND_BURST_READ		0x0
96 #define IT66121_DDC_COMMAND_EDID_READ		0x3
97 #define IT66121_DDC_COMMAND_FIFO_CLR		0x9
98 #define IT66121_DDC_COMMAND_SCL_PULSE		0xA
99 #define IT66121_DDC_COMMAND_ABORT		0xF
100 
101 #define IT66121_HDCP_REG			0x20
102 #define IT66121_HDCP_CPDESIRED			BIT(0)
103 #define IT66121_HDCP_EN1P1FEAT			BIT(1)
104 
105 #define IT66121_INT_STATUS1_REG			0x06
106 #define IT66121_INT_STATUS1_AUD_OVF		BIT(7)
107 #define IT66121_INT_STATUS1_DDC_NOACK		BIT(5)
108 #define IT66121_INT_STATUS1_DDC_FIFOERR		BIT(4)
109 #define IT66121_INT_STATUS1_DDC_BUSHANG		BIT(2)
110 #define IT66121_INT_STATUS1_RX_SENS_STATUS	BIT(1)
111 #define IT66121_INT_STATUS1_HPD_STATUS		BIT(0)
112 
113 #define IT66121_DDC_HEADER_REG			0x11
114 #define IT66121_DDC_HEADER_HDCP			0x74
115 #define IT66121_DDC_HEADER_EDID			0xA0
116 
117 #define IT66121_DDC_OFFSET_REG			0x12
118 #define IT66121_DDC_BYTE_REG			0x13
119 #define IT66121_DDC_SEGMENT_REG			0x14
120 #define IT66121_DDC_RD_FIFO_REG			0x17
121 
122 #define IT66121_CLK_BANK_REG			0x0F
123 #define IT66121_CLK_BANK_PWROFF_RCLK		BIT(6)
124 #define IT66121_CLK_BANK_PWROFF_ACLK		BIT(5)
125 #define IT66121_CLK_BANK_PWROFF_TXCLK		BIT(4)
126 #define IT66121_CLK_BANK_PWROFF_CRCLK		BIT(3)
127 #define IT66121_CLK_BANK_0			0
128 #define IT66121_CLK_BANK_1			1
129 
130 #define IT66121_INT_REG				0x05
131 #define IT66121_INT_ACTIVE_HIGH			BIT(7)
132 #define IT66121_INT_OPEN_DRAIN			BIT(6)
133 #define IT66121_INT_TX_CLK_OFF			BIT(0)
134 
135 #define IT66121_INT_MASK1_REG			0x09
136 #define IT66121_INT_MASK1_AUD_OVF		BIT(7)
137 #define IT66121_INT_MASK1_DDC_NOACK		BIT(5)
138 #define IT66121_INT_MASK1_DDC_FIFOERR		BIT(4)
139 #define IT66121_INT_MASK1_DDC_BUSHANG		BIT(2)
140 #define IT66121_INT_MASK1_RX_SENS		BIT(1)
141 #define IT66121_INT_MASK1_HPD			BIT(0)
142 
143 #define IT66121_INT_CLR1_REG			0x0C
144 #define IT66121_INT_CLR1_PKTACP			BIT(7)
145 #define IT66121_INT_CLR1_PKTNULL		BIT(6)
146 #define IT66121_INT_CLR1_PKTGEN			BIT(5)
147 #define IT66121_INT_CLR1_KSVLISTCHK		BIT(4)
148 #define IT66121_INT_CLR1_AUTHDONE		BIT(3)
149 #define IT66121_INT_CLR1_AUTHFAIL		BIT(2)
150 #define IT66121_INT_CLR1_RX_SENS		BIT(1)
151 #define IT66121_INT_CLR1_HPD			BIT(0)
152 
153 #define IT66121_AV_MUTE_REG			0xC1
154 #define IT66121_AV_MUTE_ON			BIT(0)
155 #define IT66121_AV_MUTE_BLUESCR			BIT(1)
156 
157 #define IT66121_PKT_CTS_CTRL_REG		0xC5
158 #define IT66121_PKT_CTS_CTRL_SEL		BIT(1)
159 
160 #define IT66121_PKT_GEN_CTRL_REG		0xC6
161 #define IT66121_PKT_GEN_CTRL_ON			BIT(0)
162 #define IT66121_PKT_GEN_CTRL_RPT		BIT(1)
163 
164 #define IT66121_AVIINFO_DB1_REG			0x158
165 #define IT66121_AVIINFO_DB2_REG			0x159
166 #define IT66121_AVIINFO_DB3_REG			0x15A
167 #define IT66121_AVIINFO_DB4_REG			0x15B
168 #define IT66121_AVIINFO_DB5_REG			0x15C
169 #define IT66121_AVIINFO_CSUM_REG		0x15D
170 #define IT66121_AVIINFO_DB6_REG			0x15E
171 #define IT66121_AVIINFO_DB7_REG			0x15F
172 #define IT66121_AVIINFO_DB8_REG			0x160
173 #define IT66121_AVIINFO_DB9_REG			0x161
174 #define IT66121_AVIINFO_DB10_REG		0x162
175 #define IT66121_AVIINFO_DB11_REG		0x163
176 #define IT66121_AVIINFO_DB12_REG		0x164
177 #define IT66121_AVIINFO_DB13_REG		0x165
178 
179 #define IT66121_AVI_INFO_PKT_REG		0xCD
180 #define IT66121_AVI_INFO_PKT_ON			BIT(0)
181 #define IT66121_AVI_INFO_PKT_RPT		BIT(1)
182 
183 #define IT66121_HDMI_MODE_REG			0xC0
184 #define IT66121_HDMI_MODE_HDMI			BIT(0)
185 
186 #define IT66121_SYS_STATUS_REG			0x0E
187 #define IT66121_SYS_STATUS_ACTIVE_IRQ		BIT(7)
188 #define IT66121_SYS_STATUS_HPDETECT		BIT(6)
189 #define IT66121_SYS_STATUS_SENDECTECT		BIT(5)
190 #define IT66121_SYS_STATUS_VID_STABLE		BIT(4)
191 #define IT66121_SYS_STATUS_AUD_CTS_CLR		BIT(1)
192 #define IT66121_SYS_STATUS_CLEAR_IRQ		BIT(0)
193 
194 #define IT66121_DDC_STATUS_REG			0x16
195 #define IT66121_DDC_STATUS_TX_DONE		BIT(7)
196 #define IT66121_DDC_STATUS_ACTIVE		BIT(6)
197 #define IT66121_DDC_STATUS_NOACK		BIT(5)
198 #define IT66121_DDC_STATUS_WAIT_BUS		BIT(4)
199 #define IT66121_DDC_STATUS_ARBI_LOSE		BIT(3)
200 #define IT66121_DDC_STATUS_FIFO_FULL		BIT(2)
201 #define IT66121_DDC_STATUS_FIFO_EMPTY		BIT(1)
202 #define IT66121_DDC_STATUS_FIFO_VALID		BIT(0)
203 
204 #define IT66121_EDID_SLEEP_US			20000
205 #define IT66121_EDID_TIMEOUT_US			200000
206 #define IT66121_EDID_FIFO_SIZE			32
207 
208 #define IT66121_CLK_CTRL0_REG			0x58
209 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING	BIT(4)
210 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK		GENMASK(3, 2)
211 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS	(0 << 2)
212 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS	BIT(2)
213 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS	(2 << 2)
214 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS	(3 << 2)
215 #define IT66121_CLK_CTRL0_AUTO_IPCLK		BIT(0)
216 #define IT66121_CLK_STATUS1_REG			0x5E
217 #define IT66121_CLK_STATUS2_REG			0x5F
218 
219 #define IT66121_AUD_CTRL0_REG			0xE0
220 #define IT66121_AUD_SWL				(3 << 6)
221 #define IT66121_AUD_16BIT			(0 << 6)
222 #define IT66121_AUD_18BIT			BIT(6)
223 #define IT66121_AUD_20BIT			(2 << 6)
224 #define IT66121_AUD_24BIT			(3 << 6)
225 #define IT66121_AUD_SPDIFTC			BIT(5)
226 #define IT66121_AUD_SPDIF			BIT(4)
227 #define IT66121_AUD_I2S				(0 << 4)
228 #define IT66121_AUD_EN_I2S3			BIT(3)
229 #define IT66121_AUD_EN_I2S2			BIT(2)
230 #define IT66121_AUD_EN_I2S1			BIT(1)
231 #define IT66121_AUD_EN_I2S0			BIT(0)
232 #define IT66121_AUD_CTRL0_AUD_SEL		BIT(4)
233 
234 #define IT66121_AUD_CTRL1_REG			0xE1
235 #define IT66121_AUD_FIFOMAP_REG			0xE2
236 #define IT66121_AUD_CTRL3_REG			0xE3
237 #define IT66121_AUD_SRCVALID_FLAT_REG		0xE4
238 #define IT66121_AUD_FLAT_SRC0			BIT(4)
239 #define IT66121_AUD_FLAT_SRC1			BIT(5)
240 #define IT66121_AUD_FLAT_SRC2			BIT(6)
241 #define IT66121_AUD_FLAT_SRC3			BIT(7)
242 #define IT66121_AUD_HDAUDIO_REG			0xE5
243 
244 #define IT66121_AUD_PKT_CTS0_REG		0x130
245 #define IT66121_AUD_PKT_CTS1_REG		0x131
246 #define IT66121_AUD_PKT_CTS2_REG		0x132
247 #define IT66121_AUD_PKT_N0_REG			0x133
248 #define IT66121_AUD_PKT_N1_REG			0x134
249 #define IT66121_AUD_PKT_N2_REG			0x135
250 
251 #define IT66121_AUD_CHST_MODE_REG		0x191
252 #define IT66121_AUD_CHST_CAT_REG		0x192
253 #define IT66121_AUD_CHST_SRCNUM_REG		0x193
254 #define IT66121_AUD_CHST_CHTNUM_REG		0x194
255 #define IT66121_AUD_CHST_CA_FS_REG		0x198
256 #define IT66121_AUD_CHST_OFS_WL_REG		0x199
257 
258 #define IT66121_AUD_PKT_CTS_CNT0_REG		0x1A0
259 #define IT66121_AUD_PKT_CTS_CNT1_REG		0x1A1
260 #define IT66121_AUD_PKT_CTS_CNT2_REG		0x1A2
261 
262 #define IT66121_AUD_FS_22P05K			0x4
263 #define IT66121_AUD_FS_44P1K			0x0
264 #define IT66121_AUD_FS_88P2K			0x8
265 #define IT66121_AUD_FS_176P4K			0xC
266 #define IT66121_AUD_FS_24K			0x6
267 #define IT66121_AUD_FS_48K			0x2
268 #define IT66121_AUD_FS_96K			0xA
269 #define IT66121_AUD_FS_192K			0xE
270 #define IT66121_AUD_FS_768K			0x9
271 #define IT66121_AUD_FS_32K			0x3
272 #define IT66121_AUD_FS_OTHER			0x1
273 
274 #define IT66121_AUD_SWL_21BIT			0xD
275 #define IT66121_AUD_SWL_24BIT			0xB
276 #define IT66121_AUD_SWL_23BIT			0x9
277 #define IT66121_AUD_SWL_22BIT			0x5
278 #define IT66121_AUD_SWL_20BIT			0x3
279 #define IT66121_AUD_SWL_17BIT			0xC
280 #define IT66121_AUD_SWL_19BIT			0x8
281 #define IT66121_AUD_SWL_18BIT			0x4
282 #define IT66121_AUD_SWL_16BIT			0x2
283 #define IT66121_AUD_SWL_NOT_INDICATED		0x0
284 
285 #define IT66121_AFE_CLK_HIGH			80000 /* Khz */
286 
287 enum chip_id {
288 	ID_IT6610,
289 	ID_IT66121,
290 };
291 
292 struct it66121_chip_info {
293 	enum chip_id id;
294 	u16 vid, pid;
295 };
296 
297 struct it66121_ctx {
298 	struct regmap *regmap;
299 	struct drm_bridge bridge;
300 	struct drm_bridge *next_bridge;
301 	struct drm_connector *connector;
302 	struct device *dev;
303 	struct gpio_desc *gpio_reset;
304 	struct i2c_client *client;
305 	u32 bus_width;
306 	struct mutex lock; /* Protects fields below and device registers */
307 	struct hdmi_avi_infoframe hdmi_avi_infoframe;
308 	struct {
309 		struct platform_device *pdev;
310 		u8 ch_enable;
311 		u8 fs;
312 		u8 swl;
313 		bool auto_cts;
314 	} audio;
315 	const struct it66121_chip_info *info;
316 };
317 
318 static const struct regmap_range_cfg it66121_regmap_banks[] = {
319 	{
320 		.name = "it66121",
321 		.range_min = 0x00,
322 		.range_max = 0x1FF,
323 		.selector_reg = IT66121_CLK_BANK_REG,
324 		.selector_mask = 0x1,
325 		.selector_shift = 0,
326 		.window_start = 0x00,
327 		.window_len = 0x100,
328 	},
329 };
330 
331 static const struct regmap_config it66121_regmap_config = {
332 	.val_bits = 8,
333 	.reg_bits = 8,
334 	.max_register = 0x1FF,
335 	.ranges = it66121_regmap_banks,
336 	.num_ranges = ARRAY_SIZE(it66121_regmap_banks),
337 };
338 
it66121_hw_reset(struct it66121_ctx * ctx)339 static void it66121_hw_reset(struct it66121_ctx *ctx)
340 {
341 	gpiod_set_value(ctx->gpio_reset, 1);
342 	msleep(20);
343 	gpiod_set_value(ctx->gpio_reset, 0);
344 }
345 
it66121_preamble_ddc(struct it66121_ctx * ctx)346 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx)
347 {
348 	return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST);
349 }
350 
it66121_fire_afe(struct it66121_ctx * ctx)351 static inline int it66121_fire_afe(struct it66121_ctx *ctx)
352 {
353 	return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0);
354 }
355 
356 /* TOFIX: Handle YCbCr Input & Output */
it66121_configure_input(struct it66121_ctx * ctx)357 static int it66121_configure_input(struct it66121_ctx *ctx)
358 {
359 	int ret;
360 	u8 mode = IT66121_INPUT_MODE_RGB;
361 
362 	if (ctx->bus_width == 12)
363 		mode |= IT66121_INPUT_MODE_DDR;
364 
365 	ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode);
366 	if (ret)
367 		return ret;
368 
369 	return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV);
370 }
371 
372 /**
373  * it66121_configure_afe() - Configure the analog front end
374  * @ctx: it66121_ctx object
375  * @mode: mode to configure
376  *
377  * RETURNS:
378  * zero if success, a negative error code otherwise.
379  */
it66121_configure_afe(struct it66121_ctx * ctx,const struct drm_display_mode * mode)380 static int it66121_configure_afe(struct it66121_ctx *ctx,
381 				 const struct drm_display_mode *mode)
382 {
383 	int ret;
384 
385 	ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG,
386 			   IT66121_AFE_DRV_RST);
387 	if (ret)
388 		return ret;
389 
390 	if (mode->clock > IT66121_AFE_CLK_HIGH) {
391 		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
392 					IT66121_AFE_XP_GAINBIT |
393 					IT66121_AFE_XP_ENO,
394 					IT66121_AFE_XP_GAINBIT);
395 		if (ret)
396 			return ret;
397 
398 		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
399 					IT66121_AFE_IP_GAINBIT |
400 					IT66121_AFE_IP_ER0,
401 					IT66121_AFE_IP_GAINBIT);
402 		if (ret)
403 			return ret;
404 
405 		if (ctx->info->id == ID_IT66121) {
406 			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
407 						IT66121_AFE_IP_EC1, 0);
408 			if (ret)
409 				return ret;
410 
411 			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
412 						IT66121_AFE_XP_EC1_LOWCLK, 0x80);
413 			if (ret)
414 				return ret;
415 		}
416 	} else {
417 		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
418 					IT66121_AFE_XP_GAINBIT |
419 					IT66121_AFE_XP_ENO,
420 					IT66121_AFE_XP_ENO);
421 		if (ret)
422 			return ret;
423 
424 		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
425 					IT66121_AFE_IP_GAINBIT |
426 					IT66121_AFE_IP_ER0,
427 					IT66121_AFE_IP_ER0);
428 		if (ret)
429 			return ret;
430 
431 		if (ctx->info->id == ID_IT66121) {
432 			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
433 						IT66121_AFE_IP_EC1,
434 						IT66121_AFE_IP_EC1);
435 			if (ret)
436 				return ret;
437 
438 			ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG,
439 						IT66121_AFE_XP_EC1_LOWCLK,
440 						IT66121_AFE_XP_EC1_LOWCLK);
441 			if (ret)
442 				return ret;
443 		}
444 	}
445 
446 	/* Clear reset flags */
447 	ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
448 				IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0);
449 	if (ret)
450 		return ret;
451 
452 	if (ctx->info->id == ID_IT6610) {
453 		ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
454 					IT6610_AFE_XP_BYPASS,
455 					IT6610_AFE_XP_BYPASS);
456 		if (ret)
457 			return ret;
458 	}
459 
460 	return it66121_fire_afe(ctx);
461 }
462 
it66121_wait_ddc_ready(struct it66121_ctx * ctx)463 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx)
464 {
465 	int ret, val;
466 	u32 error = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS |
467 		    IT66121_DDC_STATUS_ARBI_LOSE;
468 	u32 done = IT66121_DDC_STATUS_TX_DONE;
469 
470 	ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val,
471 				       val & (error | done), IT66121_EDID_SLEEP_US,
472 				       IT66121_EDID_TIMEOUT_US);
473 	if (ret)
474 		return ret;
475 
476 	if (val & error)
477 		return -EAGAIN;
478 
479 	return 0;
480 }
481 
it66121_abort_ddc_ops(struct it66121_ctx * ctx)482 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx)
483 {
484 	int ret;
485 	unsigned int swreset, cpdesire;
486 
487 	ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset);
488 	if (ret)
489 		return ret;
490 
491 	ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire);
492 	if (ret)
493 		return ret;
494 
495 	ret = regmap_write(ctx->regmap, IT66121_HDCP_REG,
496 			   cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF));
497 	if (ret)
498 		return ret;
499 
500 	ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG,
501 			   (swreset | IT66121_SW_RST_HDCP));
502 	if (ret)
503 		return ret;
504 
505 	ret = it66121_preamble_ddc(ctx);
506 	if (ret)
507 		return ret;
508 
509 	ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
510 			   IT66121_DDC_COMMAND_ABORT);
511 	if (ret)
512 		return ret;
513 
514 	return it66121_wait_ddc_ready(ctx);
515 }
516 
it66121_get_edid_block(void * context,u8 * buf,unsigned int block,size_t len)517 static int it66121_get_edid_block(void *context, u8 *buf,
518 				  unsigned int block, size_t len)
519 {
520 	struct it66121_ctx *ctx = context;
521 	int remain = len;
522 	int offset = 0;
523 	int ret, cnt;
524 
525 	offset = (block % 2) * len;
526 	block = block / 2;
527 
528 	while (remain > 0) {
529 		cnt = (remain > IT66121_EDID_FIFO_SIZE) ?
530 				IT66121_EDID_FIFO_SIZE : remain;
531 
532 		ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
533 				   IT66121_DDC_COMMAND_FIFO_CLR);
534 		if (ret)
535 			return ret;
536 
537 		ret = it66121_wait_ddc_ready(ctx);
538 		if (ret)
539 			return ret;
540 
541 		ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset);
542 		if (ret)
543 			return ret;
544 
545 		ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt);
546 		if (ret)
547 			return ret;
548 
549 		ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block);
550 		if (ret)
551 			return ret;
552 
553 		ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG,
554 				   IT66121_DDC_COMMAND_EDID_READ);
555 		if (ret)
556 			return ret;
557 
558 		offset += cnt;
559 		remain -= cnt;
560 
561 		ret = it66121_wait_ddc_ready(ctx);
562 		if (ret) {
563 			it66121_abort_ddc_ops(ctx);
564 			return ret;
565 		}
566 
567 		ret = regmap_noinc_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG,
568 					buf, cnt);
569 		if (ret)
570 			return ret;
571 
572 		buf += cnt;
573 	}
574 
575 	return 0;
576 }
577 
it66121_is_hpd_detect(struct it66121_ctx * ctx)578 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx)
579 {
580 	int val;
581 
582 	if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val))
583 		return false;
584 
585 	return val & IT66121_SYS_STATUS_HPDETECT;
586 }
587 
it66121_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)588 static int it66121_bridge_attach(struct drm_bridge *bridge,
589 				 enum drm_bridge_attach_flags flags)
590 {
591 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
592 	int ret;
593 
594 	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
595 		return -EINVAL;
596 
597 	ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags);
598 	if (ret)
599 		return ret;
600 
601 	if (ctx->info->id == ID_IT66121) {
602 		ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
603 					IT66121_CLK_BANK_PWROFF_RCLK, 0);
604 		if (ret)
605 			return ret;
606 	}
607 
608 	ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG,
609 				IT66121_INT_TX_CLK_OFF, 0);
610 	if (ret)
611 		return ret;
612 
613 	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
614 				IT66121_AFE_DRV_PWD, 0);
615 	if (ret)
616 		return ret;
617 
618 	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
619 				IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0);
620 	if (ret)
621 		return ret;
622 
623 	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
624 				IT66121_AFE_IP_PWDPLL, 0);
625 	if (ret)
626 		return ret;
627 
628 	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG,
629 				IT66121_AFE_DRV_RST, 0);
630 	if (ret)
631 		return ret;
632 
633 	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG,
634 				IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB);
635 	if (ret)
636 		return ret;
637 
638 	ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG,
639 				IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB);
640 	if (ret)
641 		return ret;
642 
643 	ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
644 				IT66121_SW_RST_REF,
645 				IT66121_SW_RST_REF);
646 	if (ret)
647 		return ret;
648 
649 	/* Per programming manual, sleep here for bridge to settle */
650 	msleep(50);
651 
652 	return 0;
653 }
654 
it66121_set_mute(struct it66121_ctx * ctx,bool mute)655 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute)
656 {
657 	int ret;
658 	unsigned int val = 0;
659 
660 	if (mute)
661 		val = IT66121_AV_MUTE_ON;
662 
663 	ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val);
664 	if (ret)
665 		return ret;
666 
667 	return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG,
668 			    IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT);
669 }
670 
671 #define MAX_OUTPUT_SEL_FORMATS	1
672 
it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)673 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
674 						      struct drm_bridge_state *bridge_state,
675 						      struct drm_crtc_state *crtc_state,
676 						      struct drm_connector_state *conn_state,
677 						      unsigned int *num_output_fmts)
678 {
679 	u32 *output_fmts;
680 
681 	output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
682 			      GFP_KERNEL);
683 	if (!output_fmts)
684 		return NULL;
685 
686 	/* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */
687 	output_fmts[0] =  MEDIA_BUS_FMT_RGB888_1X24;
688 	*num_output_fmts = 1;
689 
690 	return output_fmts;
691 }
692 
693 #define MAX_INPUT_SEL_FORMATS	1
694 
it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)695 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
696 						     struct drm_bridge_state *bridge_state,
697 						     struct drm_crtc_state *crtc_state,
698 						     struct drm_connector_state *conn_state,
699 						     u32 output_fmt,
700 						     unsigned int *num_input_fmts)
701 {
702 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
703 	u32 *input_fmts;
704 
705 	*num_input_fmts = 0;
706 
707 	input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
708 			     GFP_KERNEL);
709 	if (!input_fmts)
710 		return NULL;
711 
712 	if (ctx->bus_width == 12)
713 		/* IT66121FN Datasheet specifies Little-Endian ordering */
714 		input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE;
715 	else
716 		/* TOFIX support more input bus formats in 24bit width */
717 		input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
718 	*num_input_fmts = 1;
719 
720 	return input_fmts;
721 }
722 
it66121_bridge_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)723 static void it66121_bridge_enable(struct drm_bridge *bridge,
724 				  struct drm_atomic_state *state)
725 {
726 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
727 
728 	ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
729 
730 	it66121_set_mute(ctx, false);
731 }
732 
it66121_bridge_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)733 static void it66121_bridge_disable(struct drm_bridge *bridge,
734 				   struct drm_atomic_state *state)
735 {
736 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
737 
738 	it66121_set_mute(ctx, true);
739 
740 	ctx->connector = NULL;
741 }
742 
it66121_bridge_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)743 static int it66121_bridge_check(struct drm_bridge *bridge,
744 				struct drm_bridge_state *bridge_state,
745 				struct drm_crtc_state *crtc_state,
746 				struct drm_connector_state *conn_state)
747 {
748 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
749 
750 	if (ctx->info->id == ID_IT6610) {
751 		/* The IT6610 only supports these settings */
752 		bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH |
753 			DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
754 		bridge_state->input_bus_cfg.flags &=
755 			~DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
756 	}
757 
758 	return 0;
759 }
760 
761 static
it66121_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)762 void it66121_bridge_mode_set(struct drm_bridge *bridge,
763 			     const struct drm_display_mode *mode,
764 			     const struct drm_display_mode *adjusted_mode)
765 {
766 	u8 buf[HDMI_INFOFRAME_SIZE(AVI)];
767 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
768 	int ret;
769 
770 	mutex_lock(&ctx->lock);
771 
772 	ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector,
773 						       adjusted_mode);
774 	if (ret) {
775 		DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret);
776 		goto unlock;
777 	}
778 
779 	ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf));
780 	if (ret < 0) {
781 		DRM_ERROR("Failed to pack infoframe: %d\n", ret);
782 		goto unlock;
783 	}
784 
785 	/* Write new AVI infoframe packet */
786 	ret = regmap_bulk_write(ctx->regmap, IT66121_AVIINFO_DB1_REG,
787 				&buf[HDMI_INFOFRAME_HEADER_SIZE],
788 				HDMI_AVI_INFOFRAME_SIZE);
789 	if (ret)
790 		goto unlock;
791 
792 	if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3]))
793 		goto unlock;
794 
795 	/* Enable AVI infoframe */
796 	if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG,
797 			 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT))
798 		goto unlock;
799 
800 	/* Set TX mode to HDMI */
801 	if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI))
802 		goto unlock;
803 
804 	if (ctx->info->id == ID_IT66121 &&
805 	    regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
806 			      IT66121_CLK_BANK_PWROFF_TXCLK,
807 			      IT66121_CLK_BANK_PWROFF_TXCLK)) {
808 		goto unlock;
809 	}
810 
811 	if (it66121_configure_input(ctx))
812 		goto unlock;
813 
814 	if (it66121_configure_afe(ctx, adjusted_mode))
815 		goto unlock;
816 
817 	if (ctx->info->id == ID_IT66121 &&
818 	    regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG,
819 			      IT66121_CLK_BANK_PWROFF_TXCLK, 0)) {
820 		goto unlock;
821 	}
822 
823 unlock:
824 	mutex_unlock(&ctx->lock);
825 }
826 
it66121_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)827 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge,
828 						      const struct drm_display_info *info,
829 						      const struct drm_display_mode *mode)
830 {
831 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
832 	unsigned long max_clock;
833 
834 	max_clock = (ctx->bus_width == 12) ? 74250 : 148500;
835 
836 	if (mode->clock > max_clock)
837 		return MODE_CLOCK_HIGH;
838 
839 	if (mode->clock < 25000)
840 		return MODE_CLOCK_LOW;
841 
842 	return MODE_OK;
843 }
844 
it66121_bridge_detect(struct drm_bridge * bridge)845 static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge)
846 {
847 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
848 
849 	return it66121_is_hpd_detect(ctx) ? connector_status_connected
850 					  : connector_status_disconnected;
851 }
852 
it66121_bridge_hpd_enable(struct drm_bridge * bridge)853 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge)
854 {
855 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
856 	int ret;
857 
858 	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0);
859 	if (ret)
860 		dev_err(ctx->dev, "failed to enable HPD IRQ\n");
861 }
862 
it66121_bridge_hpd_disable(struct drm_bridge * bridge)863 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge)
864 {
865 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
866 	int ret;
867 
868 	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
869 				IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD);
870 	if (ret)
871 		dev_err(ctx->dev, "failed to disable HPD IRQ\n");
872 }
873 
it66121_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)874 static const struct drm_edid *it66121_bridge_edid_read(struct drm_bridge *bridge,
875 						       struct drm_connector *connector)
876 {
877 	struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge);
878 	const struct drm_edid *drm_edid;
879 	int ret;
880 
881 	mutex_lock(&ctx->lock);
882 	ret = it66121_preamble_ddc(ctx);
883 	if (ret) {
884 		drm_edid = NULL;
885 		goto out_unlock;
886 	}
887 
888 	ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG,
889 			   IT66121_DDC_HEADER_EDID);
890 	if (ret) {
891 		drm_edid = NULL;
892 		goto out_unlock;
893 	}
894 
895 	drm_edid = drm_edid_read_custom(connector, it66121_get_edid_block, ctx);
896 
897 out_unlock:
898 	mutex_unlock(&ctx->lock);
899 
900 	return drm_edid;
901 }
902 
903 static const struct drm_bridge_funcs it66121_bridge_funcs = {
904 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
905 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
906 	.atomic_reset = drm_atomic_helper_bridge_reset,
907 	.attach = it66121_bridge_attach,
908 	.atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts,
909 	.atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts,
910 	.atomic_enable = it66121_bridge_enable,
911 	.atomic_disable = it66121_bridge_disable,
912 	.atomic_check = it66121_bridge_check,
913 	.mode_set = it66121_bridge_mode_set,
914 	.mode_valid = it66121_bridge_mode_valid,
915 	.detect = it66121_bridge_detect,
916 	.edid_read = it66121_bridge_edid_read,
917 	.hpd_enable = it66121_bridge_hpd_enable,
918 	.hpd_disable = it66121_bridge_hpd_disable,
919 };
920 
it66121_irq_threaded_handler(int irq,void * dev_id)921 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id)
922 {
923 	int ret;
924 	unsigned int val;
925 	struct it66121_ctx *ctx = dev_id;
926 	struct device *dev = ctx->dev;
927 	enum drm_connector_status status;
928 	bool event = false;
929 
930 	mutex_lock(&ctx->lock);
931 
932 	ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val);
933 	if (ret)
934 		goto unlock;
935 
936 	if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ))
937 		goto unlock;
938 
939 	ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val);
940 	if (ret) {
941 		dev_err(dev, "Cannot read STATUS1_REG %d\n", ret);
942 	} else if (val & IT66121_INT_STATUS1_HPD_STATUS) {
943 		regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG,
944 				  IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD);
945 
946 		status = it66121_is_hpd_detect(ctx) ? connector_status_connected
947 			: connector_status_disconnected;
948 
949 		event = true;
950 	}
951 
952 	regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG,
953 			  IT66121_SYS_STATUS_CLEAR_IRQ,
954 			  IT66121_SYS_STATUS_CLEAR_IRQ);
955 
956 unlock:
957 	mutex_unlock(&ctx->lock);
958 
959 	if (event)
960 		drm_bridge_hpd_notify(&ctx->bridge, status);
961 
962 	return IRQ_HANDLED;
963 }
964 
it661221_set_chstat(struct it66121_ctx * ctx,u8 iec60958_chstat[])965 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[])
966 {
967 	int ret;
968 
969 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C);
970 	if (ret)
971 		return ret;
972 
973 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]);
974 	if (ret)
975 		return ret;
976 
977 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F);
978 	if (ret)
979 		return ret;
980 
981 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG,
982 			   (iec60958_chstat[2] >> 4) & 0x0F);
983 	if (ret)
984 		return ret;
985 
986 	ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]);
987 	if (ret)
988 		return ret;
989 
990 	return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]);
991 }
992 
it661221_set_lpcm_audio(struct it66121_ctx * ctx,u8 audio_src_num,u8 audio_swl)993 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl)
994 {
995 	int ret;
996 	unsigned int audio_enable = 0;
997 	unsigned int audio_format = 0;
998 
999 	switch (audio_swl) {
1000 	case 16:
1001 		audio_enable |= IT66121_AUD_16BIT;
1002 		break;
1003 	case 18:
1004 		audio_enable |= IT66121_AUD_18BIT;
1005 		break;
1006 	case 20:
1007 		audio_enable |= IT66121_AUD_20BIT;
1008 		break;
1009 	case 24:
1010 	default:
1011 		audio_enable |= IT66121_AUD_24BIT;
1012 		break;
1013 	}
1014 
1015 	audio_format |= 0x40;
1016 	switch (audio_src_num) {
1017 	case 4:
1018 		audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1019 				IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1020 		break;
1021 	case 3:
1022 		audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 |
1023 				IT66121_AUD_EN_I2S0;
1024 		break;
1025 	case 2:
1026 		audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0;
1027 		break;
1028 	case 1:
1029 	default:
1030 		audio_format &= ~0x40;
1031 		audio_enable |= IT66121_AUD_EN_I2S0;
1032 		break;
1033 	}
1034 
1035 	audio_format |= 0x01;
1036 	ctx->audio.ch_enable = audio_enable;
1037 
1038 	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0);
1039 	if (ret)
1040 		return ret;
1041 
1042 	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format);
1043 	if (ret)
1044 		return ret;
1045 
1046 	ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4);
1047 	if (ret)
1048 		return ret;
1049 
1050 	ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00);
1051 	if (ret)
1052 		return ret;
1053 
1054 	ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00);
1055 	if (ret)
1056 		return ret;
1057 
1058 	return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00);
1059 }
1060 
it661221_set_ncts(struct it66121_ctx * ctx,u8 fs)1061 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs)
1062 {
1063 	int ret;
1064 	unsigned int n;
1065 
1066 	switch (fs) {
1067 	case IT66121_AUD_FS_32K:
1068 		n = 4096;
1069 		break;
1070 	case IT66121_AUD_FS_44P1K:
1071 		n = 6272;
1072 		break;
1073 	case IT66121_AUD_FS_48K:
1074 		n = 6144;
1075 		break;
1076 	case IT66121_AUD_FS_88P2K:
1077 		n = 12544;
1078 		break;
1079 	case IT66121_AUD_FS_96K:
1080 		n = 12288;
1081 		break;
1082 	case IT66121_AUD_FS_176P4K:
1083 		n = 25088;
1084 		break;
1085 	case IT66121_AUD_FS_192K:
1086 		n = 24576;
1087 		break;
1088 	case IT66121_AUD_FS_768K:
1089 		n = 24576;
1090 		break;
1091 	default:
1092 		n = 6144;
1093 		break;
1094 	}
1095 
1096 	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF));
1097 	if (ret)
1098 		return ret;
1099 
1100 	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF));
1101 	if (ret)
1102 		return ret;
1103 
1104 	ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF));
1105 	if (ret)
1106 		return ret;
1107 
1108 	if (ctx->audio.auto_cts) {
1109 		u8 loop_cnt = 255;
1110 		u8 cts_stable_cnt = 0;
1111 		unsigned int sum_cts = 0;
1112 		unsigned int cts = 0;
1113 		unsigned int last_cts = 0;
1114 		unsigned int diff;
1115 		unsigned int val;
1116 
1117 		while (loop_cnt--) {
1118 			msleep(30);
1119 			regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val);
1120 			cts = val << 12;
1121 			regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val);
1122 			cts |= val << 4;
1123 			regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val);
1124 			cts |= val >> 4;
1125 			if (cts == 0) {
1126 				continue;
1127 			} else {
1128 				if (last_cts > cts)
1129 					diff = last_cts - cts;
1130 				else
1131 					diff = cts - last_cts;
1132 				last_cts = cts;
1133 				if (diff < 5) {
1134 					cts_stable_cnt++;
1135 					sum_cts += cts;
1136 				} else {
1137 					cts_stable_cnt = 0;
1138 					sum_cts = 0;
1139 					continue;
1140 				}
1141 
1142 				if (cts_stable_cnt >= 32) {
1143 					last_cts = (sum_cts >> 5);
1144 					break;
1145 				}
1146 			}
1147 		}
1148 
1149 		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF));
1150 		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF));
1151 		regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F));
1152 	}
1153 
1154 	ret = regmap_write(ctx->regmap, 0xF8, 0xC3);
1155 	if (ret)
1156 		return ret;
1157 
1158 	ret = regmap_write(ctx->regmap, 0xF8, 0xA5);
1159 	if (ret)
1160 		return ret;
1161 
1162 	if (ctx->audio.auto_cts) {
1163 		ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1164 					IT66121_PKT_CTS_CTRL_SEL,
1165 					1);
1166 	} else {
1167 		ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG,
1168 					IT66121_PKT_CTS_CTRL_SEL,
1169 					0);
1170 	}
1171 
1172 	if (ret)
1173 		return ret;
1174 
1175 	return regmap_write(ctx->regmap, 0xF8, 0xFF);
1176 }
1177 
it661221_audio_output_enable(struct it66121_ctx * ctx,bool enable)1178 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable)
1179 {
1180 	int ret;
1181 
1182 	if (enable) {
1183 		ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1184 					IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1185 					0);
1186 		if (ret)
1187 			return ret;
1188 
1189 		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1190 					IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1191 					IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1192 					ctx->audio.ch_enable);
1193 	} else {
1194 		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1195 					IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 |
1196 					IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0,
1197 					ctx->audio.ch_enable & 0xF0);
1198 		if (ret)
1199 			return ret;
1200 
1201 		ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG,
1202 					IT66121_SW_RST_AUD | IT66121_SW_RST_AREF,
1203 					IT66121_SW_RST_AUD | IT66121_SW_RST_AREF);
1204 	}
1205 
1206 	return ret;
1207 }
1208 
it661221_audio_ch_enable(struct it66121_ctx * ctx,bool enable)1209 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable)
1210 {
1211 	int ret;
1212 
1213 	if (enable) {
1214 		ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0);
1215 		if (ret)
1216 			return ret;
1217 
1218 		ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable);
1219 	} else {
1220 		ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0);
1221 	}
1222 
1223 	return ret;
1224 }
1225 
it66121_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)1226 static int it66121_audio_hw_params(struct device *dev, void *data,
1227 				   struct hdmi_codec_daifmt *daifmt,
1228 				   struct hdmi_codec_params *params)
1229 {
1230 	u8 fs;
1231 	u8 swl;
1232 	int ret;
1233 	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1234 	static u8 iec60958_chstat[5];
1235 	unsigned int channels = params->channels;
1236 	unsigned int sample_rate = params->sample_rate;
1237 	unsigned int sample_width = params->sample_width;
1238 
1239 	mutex_lock(&ctx->lock);
1240 	dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__,
1241 		daifmt->fmt, sample_rate, sample_width, channels);
1242 
1243 	switch (daifmt->fmt) {
1244 	case HDMI_I2S:
1245 		dev_dbg(dev, "Using HDMI I2S\n");
1246 		break;
1247 	default:
1248 		dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt);
1249 		ret = -EINVAL;
1250 		goto out;
1251 	}
1252 
1253 	// Set audio clock recovery (N/CTS)
1254 	ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG,
1255 			   IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING |
1256 			   IT66121_CLK_CTRL0_EXT_MCLK_256FS |
1257 			   IT66121_CLK_CTRL0_AUTO_IPCLK);
1258 	if (ret)
1259 		goto out;
1260 
1261 	ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG,
1262 				IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection
1263 	if (ret)
1264 		goto out;
1265 
1266 	switch (sample_rate) {
1267 	case 44100L:
1268 		fs = IT66121_AUD_FS_44P1K;
1269 		break;
1270 	case 88200L:
1271 		fs = IT66121_AUD_FS_88P2K;
1272 		break;
1273 	case 176400L:
1274 		fs = IT66121_AUD_FS_176P4K;
1275 		break;
1276 	case 32000L:
1277 		fs = IT66121_AUD_FS_32K;
1278 		break;
1279 	case 48000L:
1280 		fs = IT66121_AUD_FS_48K;
1281 		break;
1282 	case 96000L:
1283 		fs = IT66121_AUD_FS_96K;
1284 		break;
1285 	case 192000L:
1286 		fs = IT66121_AUD_FS_192K;
1287 		break;
1288 	case 768000L:
1289 		fs = IT66121_AUD_FS_768K;
1290 		break;
1291 	default:
1292 		fs = IT66121_AUD_FS_48K;
1293 		break;
1294 	}
1295 
1296 	ctx->audio.fs = fs;
1297 	ret = it661221_set_ncts(ctx, fs);
1298 	if (ret) {
1299 		dev_err(dev, "Failed to set N/CTS: %d\n", ret);
1300 		goto out;
1301 	}
1302 
1303 	// Set audio format register (except audio channel enable)
1304 	ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width);
1305 	if (ret) {
1306 		dev_err(dev, "Failed to set LPCM audio: %d\n", ret);
1307 		goto out;
1308 	}
1309 
1310 	// Set audio channel status
1311 	iec60958_chstat[0] = 0;
1312 	if ((channels + 1) / 2 == 1)
1313 		iec60958_chstat[0] |= 0x1;
1314 	iec60958_chstat[0] &= ~(1 << 1);
1315 	iec60958_chstat[1] = 0;
1316 	iec60958_chstat[2] = (channels + 1) / 2;
1317 	iec60958_chstat[2] |= (channels << 4) & 0xF0;
1318 	iec60958_chstat[3] = fs;
1319 
1320 	switch (sample_width) {
1321 	case 21L:
1322 		swl = IT66121_AUD_SWL_21BIT;
1323 		break;
1324 	case 24L:
1325 		swl = IT66121_AUD_SWL_24BIT;
1326 		break;
1327 	case 23L:
1328 		swl = IT66121_AUD_SWL_23BIT;
1329 		break;
1330 	case 22L:
1331 		swl = IT66121_AUD_SWL_22BIT;
1332 		break;
1333 	case 20L:
1334 		swl = IT66121_AUD_SWL_20BIT;
1335 		break;
1336 	case 17L:
1337 		swl = IT66121_AUD_SWL_17BIT;
1338 		break;
1339 	case 19L:
1340 		swl = IT66121_AUD_SWL_19BIT;
1341 		break;
1342 	case 18L:
1343 		swl = IT66121_AUD_SWL_18BIT;
1344 		break;
1345 	case 16L:
1346 		swl = IT66121_AUD_SWL_16BIT;
1347 		break;
1348 	default:
1349 		swl = IT66121_AUD_SWL_NOT_INDICATED;
1350 		break;
1351 	}
1352 
1353 	iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl;
1354 	ret = it661221_set_chstat(ctx, iec60958_chstat);
1355 	if (ret) {
1356 		dev_err(dev, "Failed to set channel status: %d\n", ret);
1357 		goto out;
1358 	}
1359 
1360 	// Enable audio channel enable while input clock stable (if SPDIF).
1361 	ret = it661221_audio_ch_enable(ctx, true);
1362 	if (ret) {
1363 		dev_err(dev, "Failed to enable audio channel: %d\n", ret);
1364 		goto out;
1365 	}
1366 
1367 	ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG,
1368 				IT66121_INT_MASK1_AUD_OVF,
1369 				0);
1370 	if (ret)
1371 		goto out;
1372 
1373 	dev_dbg(dev, "HDMI audio enabled.\n");
1374 out:
1375 	mutex_unlock(&ctx->lock);
1376 
1377 	return ret;
1378 }
1379 
it66121_audio_startup(struct device * dev,void * data)1380 static int it66121_audio_startup(struct device *dev, void *data)
1381 {
1382 	int ret;
1383 	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1384 
1385 	dev_dbg(dev, "%s\n", __func__);
1386 
1387 	mutex_lock(&ctx->lock);
1388 	ret = it661221_audio_output_enable(ctx, true);
1389 	if (ret)
1390 		dev_err(dev, "Failed to enable audio output: %d\n", ret);
1391 
1392 	mutex_unlock(&ctx->lock);
1393 
1394 	return ret;
1395 }
1396 
it66121_audio_shutdown(struct device * dev,void * data)1397 static void it66121_audio_shutdown(struct device *dev, void *data)
1398 {
1399 	int ret;
1400 	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1401 
1402 	dev_dbg(dev, "%s\n", __func__);
1403 
1404 	mutex_lock(&ctx->lock);
1405 	ret = it661221_audio_output_enable(ctx, false);
1406 	if (ret)
1407 		dev_err(dev, "Failed to disable audio output: %d\n", ret);
1408 
1409 	mutex_unlock(&ctx->lock);
1410 }
1411 
it66121_audio_mute(struct device * dev,void * data,bool enable,int direction)1412 static int it66121_audio_mute(struct device *dev, void *data,
1413 			      bool enable, int direction)
1414 {
1415 	int ret;
1416 	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1417 
1418 	dev_dbg(dev, "%s: enable=%s, direction=%d\n",
1419 		__func__, enable ? "true" : "false", direction);
1420 
1421 	mutex_lock(&ctx->lock);
1422 
1423 	if (enable) {
1424 		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1425 					IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1426 					IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1427 					IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1428 					IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3);
1429 	} else {
1430 		ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG,
1431 					IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 |
1432 					IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3,
1433 					0);
1434 	}
1435 
1436 	mutex_unlock(&ctx->lock);
1437 
1438 	return ret;
1439 }
1440 
it66121_audio_get_eld(struct device * dev,void * data,u8 * buf,size_t len)1441 static int it66121_audio_get_eld(struct device *dev, void *data,
1442 				 u8 *buf, size_t len)
1443 {
1444 	struct it66121_ctx *ctx = dev_get_drvdata(dev);
1445 
1446 	mutex_lock(&ctx->lock);
1447 	if (!ctx->connector) {
1448 		/* Pass en empty ELD if connector not available */
1449 		dev_dbg(dev, "No connector present, passing empty EDID data");
1450 		memset(buf, 0, len);
1451 	} else {
1452 		mutex_lock(&ctx->connector->eld_mutex);
1453 		memcpy(buf, ctx->connector->eld,
1454 		       min(sizeof(ctx->connector->eld), len));
1455 		mutex_unlock(&ctx->connector->eld_mutex);
1456 	}
1457 	mutex_unlock(&ctx->lock);
1458 
1459 	return 0;
1460 }
1461 
1462 static const struct hdmi_codec_ops it66121_audio_codec_ops = {
1463 	.hw_params = it66121_audio_hw_params,
1464 	.audio_startup = it66121_audio_startup,
1465 	.audio_shutdown = it66121_audio_shutdown,
1466 	.mute_stream = it66121_audio_mute,
1467 	.get_eld = it66121_audio_get_eld,
1468 };
1469 
it66121_audio_codec_init(struct it66121_ctx * ctx,struct device * dev)1470 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev)
1471 {
1472 	struct hdmi_codec_pdata codec_data = {
1473 		.ops = &it66121_audio_codec_ops,
1474 		.i2s = 1, /* Only i2s support for now */
1475 		.spdif = 0,
1476 		.max_i2s_channels = 8,
1477 		.no_capture_mute = 1,
1478 	};
1479 
1480 	dev_dbg(dev, "%s\n", __func__);
1481 
1482 	if (!of_property_present(dev->of_node, "#sound-dai-cells")) {
1483 		dev_info(dev, "No \"#sound-dai-cells\", no audio\n");
1484 		return 0;
1485 	}
1486 
1487 	ctx->audio.pdev = platform_device_register_data(dev,
1488 							HDMI_CODEC_DRV_NAME,
1489 							PLATFORM_DEVID_AUTO,
1490 							&codec_data,
1491 							sizeof(codec_data));
1492 
1493 	if (IS_ERR(ctx->audio.pdev)) {
1494 		dev_err(dev, "Failed to initialize HDMI audio codec: %d\n",
1495 			PTR_ERR_OR_ZERO(ctx->audio.pdev));
1496 	}
1497 
1498 	return PTR_ERR_OR_ZERO(ctx->audio.pdev);
1499 }
1500 
1501 static const char * const it66121_supplies[] = {
1502 	"vcn33", "vcn18", "vrf12"
1503 };
1504 
it66121_probe(struct i2c_client * client)1505 static int it66121_probe(struct i2c_client *client)
1506 {
1507 	u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 };
1508 	struct device_node *ep;
1509 	int ret;
1510 	struct it66121_ctx *ctx;
1511 	struct device *dev = &client->dev;
1512 
1513 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1514 		dev_err(dev, "I2C check functionality failed.\n");
1515 		return -ENXIO;
1516 	}
1517 
1518 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1519 	if (!ctx)
1520 		return -ENOMEM;
1521 
1522 	ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0);
1523 	if (!ep)
1524 		return -EINVAL;
1525 
1526 	ctx->dev = dev;
1527 	ctx->client = client;
1528 	ctx->info = i2c_get_match_data(client);
1529 
1530 	of_property_read_u32(ep, "bus-width", &ctx->bus_width);
1531 	of_node_put(ep);
1532 
1533 	if (ctx->bus_width != 12 && ctx->bus_width != 24)
1534 		return -EINVAL;
1535 
1536 	ep = of_graph_get_remote_node(dev->of_node, 1, -1);
1537 	if (!ep) {
1538 		dev_err(ctx->dev, "The endpoint is unconnected\n");
1539 		return -EINVAL;
1540 	}
1541 
1542 	ctx->next_bridge = of_drm_find_bridge(ep);
1543 	of_node_put(ep);
1544 	if (!ctx->next_bridge) {
1545 		dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n");
1546 		return -EPROBE_DEFER;
1547 	}
1548 
1549 	i2c_set_clientdata(client, ctx);
1550 	mutex_init(&ctx->lock);
1551 
1552 	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it66121_supplies),
1553 					     it66121_supplies);
1554 	if (ret) {
1555 		dev_err(dev, "Failed to enable power supplies\n");
1556 		return ret;
1557 	}
1558 
1559 	it66121_hw_reset(ctx);
1560 
1561 	ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config);
1562 	if (IS_ERR(ctx->regmap))
1563 		return PTR_ERR(ctx->regmap);
1564 
1565 	regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]);
1566 	regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]);
1567 	regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]);
1568 	regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]);
1569 
1570 	/* Revision is shared with DEVICE_ID1 */
1571 	revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]);
1572 	device_ids[1] &= IT66121_DEVICE_ID1_MASK;
1573 
1574 	if ((vendor_ids[1] << 8 | vendor_ids[0]) != ctx->info->vid ||
1575 	    (device_ids[1] << 8 | device_ids[0]) != ctx->info->pid) {
1576 		return -ENODEV;
1577 	}
1578 
1579 	ctx->bridge.funcs = &it66121_bridge_funcs;
1580 	ctx->bridge.of_node = dev->of_node;
1581 	ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1582 	ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID;
1583 	if (client->irq > 0) {
1584 		ctx->bridge.ops |= DRM_BRIDGE_OP_HPD;
1585 
1586 		ret = devm_request_threaded_irq(dev, client->irq, NULL,
1587 						it66121_irq_threaded_handler,
1588 						IRQF_ONESHOT, dev_name(dev),
1589 						ctx);
1590 		if (ret < 0) {
1591 			dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret);
1592 			return ret;
1593 		}
1594 	}
1595 
1596 	it66121_audio_codec_init(ctx, dev);
1597 
1598 	drm_bridge_add(&ctx->bridge);
1599 
1600 	dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id);
1601 
1602 	return 0;
1603 }
1604 
it66121_remove(struct i2c_client * client)1605 static void it66121_remove(struct i2c_client *client)
1606 {
1607 	struct it66121_ctx *ctx = i2c_get_clientdata(client);
1608 
1609 	drm_bridge_remove(&ctx->bridge);
1610 	mutex_destroy(&ctx->lock);
1611 }
1612 
1613 static const struct it66121_chip_info it66121_chip_info = {
1614 	.id = ID_IT66121,
1615 	.vid = 0x4954,
1616 	.pid = 0x0612,
1617 };
1618 
1619 static const struct it66121_chip_info it6610_chip_info = {
1620 	.id = ID_IT6610,
1621 	.vid = 0xca00,
1622 	.pid = 0x0611,
1623 };
1624 
1625 static const struct of_device_id it66121_dt_match[] = {
1626 	{ .compatible = "ite,it66121", &it66121_chip_info },
1627 	{ .compatible = "ite,it6610", &it6610_chip_info },
1628 	{ }
1629 };
1630 MODULE_DEVICE_TABLE(of, it66121_dt_match);
1631 
1632 static const struct i2c_device_id it66121_id[] = {
1633 	{ "it66121", (kernel_ulong_t) &it66121_chip_info },
1634 	{ "it6610", (kernel_ulong_t) &it6610_chip_info },
1635 	{ }
1636 };
1637 MODULE_DEVICE_TABLE(i2c, it66121_id);
1638 
1639 static struct i2c_driver it66121_driver = {
1640 	.driver = {
1641 		.name	= "it66121",
1642 		.of_match_table = it66121_dt_match,
1643 	},
1644 	.probe = it66121_probe,
1645 	.remove = it66121_remove,
1646 	.id_table = it66121_id,
1647 };
1648 
1649 module_i2c_driver(it66121_driver);
1650 
1651 MODULE_AUTHOR("Phong LE");
1652 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver");
1653 MODULE_LICENSE("GPL v2");
1654