1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29 #include <linux/delay.h>
30 #include <linux/pci.h>
31
32 #include <drm/drm_print.h>
33
34 #include "ast_dram_tables.h"
35 #include "ast_drv.h"
36
37 static void ast_post_chip_2300(struct ast_device *ast);
38 static void ast_post_chip_2500(struct ast_device *ast);
39
40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
42
ast_set_def_ext_reg(struct ast_device * ast)43 static void ast_set_def_ext_reg(struct ast_device *ast)
44 {
45 u8 i, index, reg;
46 const u8 *ext_reg_info;
47
48 /* reset scratch */
49 for (i = 0x81; i <= 0x9f; i++)
50 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
51
52 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
53 ext_reg_info = extreginfo_ast2300;
54 else
55 ext_reg_info = extreginfo;
56
57 index = 0xa0;
58 while (*ext_reg_info != 0xff) {
59 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
60 index++;
61 ext_reg_info++;
62 }
63
64 /* disable standard IO/MEM decode if secondary */
65 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
66
67 /* Set Ext. Default */
68 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
69 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
70
71 /* Enable RAMDAC for A1 */
72 reg = 0x04;
73 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
74 reg |= 0x20;
75 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
76 }
77
__ast_mindwm(void __iomem * regs,u32 r)78 static u32 __ast_mindwm(void __iomem *regs, u32 r)
79 {
80 u32 data;
81
82 __ast_write32(regs, 0xf004, r & 0xffff0000);
83 __ast_write32(regs, 0xf000, 0x1);
84
85 do {
86 data = __ast_read32(regs, 0xf004) & 0xffff0000;
87 } while (data != (r & 0xffff0000));
88
89 return __ast_read32(regs, 0x10000 + (r & 0x0000ffff));
90 }
91
__ast_moutdwm(void __iomem * regs,u32 r,u32 v)92 static void __ast_moutdwm(void __iomem *regs, u32 r, u32 v)
93 {
94 u32 data;
95
96 __ast_write32(regs, 0xf004, r & 0xffff0000);
97 __ast_write32(regs, 0xf000, 0x1);
98
99 do {
100 data = __ast_read32(regs, 0xf004) & 0xffff0000;
101 } while (data != (r & 0xffff0000));
102
103 __ast_write32(regs, 0x10000 + (r & 0x0000ffff), v);
104 }
105
ast_mindwm(struct ast_device * ast,u32 r)106 u32 ast_mindwm(struct ast_device *ast, u32 r)
107 {
108 return __ast_mindwm(ast->regs, r);
109 }
110
ast_moutdwm(struct ast_device * ast,u32 r,u32 v)111 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
112 {
113 __ast_moutdwm(ast->regs, r, v);
114 }
115
116 /*
117 * AST2100/2150 DLL CBR Setting
118 */
119 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
120 #define CBR_PASSNUM_AST2150 5
121 #define CBR_THRESHOLD_AST2150 10
122 #define CBR_THRESHOLD2_AST2150 10
123 #define TIMEOUT_AST2150 5000000
124
125 #define CBR_PATNUM_AST2150 8
126
127 static const u32 pattern_AST2150[14] = {
128 0xFF00FF00,
129 0xCC33CC33,
130 0xAA55AA55,
131 0xFFFE0001,
132 0x683501FE,
133 0x0F1929B0,
134 0x2D0B4346,
135 0x60767F02,
136 0x6FBE36A6,
137 0x3A253035,
138 0x3019686D,
139 0x41C6167E,
140 0x620152BF,
141 0x20F050E0
142 };
143
mmctestburst2_ast2150(struct ast_device * ast,u32 datagen)144 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
145 {
146 u32 data, timeout;
147
148 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
149 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
150 timeout = 0;
151 do {
152 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
153 if (++timeout > TIMEOUT_AST2150) {
154 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
155 return 0xffffffff;
156 }
157 } while (!data);
158 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
159 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
160 timeout = 0;
161 do {
162 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
163 if (++timeout > TIMEOUT_AST2150) {
164 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
165 return 0xffffffff;
166 }
167 } while (!data);
168 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
170 return data;
171 }
172
173 #if 0 /* unused in DDX driver - here for completeness */
174 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
175 {
176 u32 data, timeout;
177
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
180 timeout = 0;
181 do {
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
183 if (++timeout > TIMEOUT_AST2150) {
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
185 return 0xffffffff;
186 }
187 } while (!data);
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
190 return data;
191 }
192 #endif
193
cbrtest_ast2150(struct ast_device * ast)194 static int cbrtest_ast2150(struct ast_device *ast)
195 {
196 int i;
197
198 for (i = 0; i < 8; i++)
199 if (mmctestburst2_ast2150(ast, i))
200 return 0;
201 return 1;
202 }
203
cbrscan_ast2150(struct ast_device * ast,int busw)204 static int cbrscan_ast2150(struct ast_device *ast, int busw)
205 {
206 u32 patcnt, loop;
207
208 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
209 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
210 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
211 if (cbrtest_ast2150(ast))
212 break;
213 }
214 if (loop == CBR_PASSNUM_AST2150)
215 return 0;
216 }
217 return 1;
218 }
219
220
cbrdlli_ast2150(struct ast_device * ast,int busw)221 static void cbrdlli_ast2150(struct ast_device *ast, int busw)
222 {
223 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
224
225 cbr_start:
226 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
227 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
228 passcnt = 0;
229
230 for (dlli = 0; dlli < 100; dlli++) {
231 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
232 data = cbrscan_ast2150(ast, busw);
233 if (data != 0) {
234 if (data & 0x1) {
235 if (dll_min[0] > dlli)
236 dll_min[0] = dlli;
237 if (dll_max[0] < dlli)
238 dll_max[0] = dlli;
239 }
240 passcnt++;
241 } else if (passcnt >= CBR_THRESHOLD_AST2150)
242 goto cbr_start;
243 }
244 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
245 goto cbr_start;
246
247 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
248 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
249 }
250
251
252
ast_init_dram_reg(struct ast_device * ast)253 static void ast_init_dram_reg(struct ast_device *ast)
254 {
255 u8 j;
256 u32 data, temp, i;
257 const struct ast_dramstruct *dram_reg_info;
258
259 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
260
261 if ((j & 0x80) == 0) { /* VGA only */
262 if (IS_AST_GEN1(ast)) {
263 dram_reg_info = ast2000_dram_table_data;
264 ast_write32(ast, 0xf004, 0x1e6e0000);
265 ast_write32(ast, 0xf000, 0x1);
266 ast_write32(ast, 0x10100, 0xa8);
267
268 do {
269 ;
270 } while (ast_read32(ast, 0x10100) != 0xa8);
271 } else { /* GEN2/GEN3 */
272 if (ast->chip == AST2100 || ast->chip == AST2200)
273 dram_reg_info = ast2100_dram_table_data;
274 else
275 dram_reg_info = ast1100_dram_table_data;
276
277 ast_write32(ast, 0xf004, 0x1e6e0000);
278 ast_write32(ast, 0xf000, 0x1);
279 ast_write32(ast, 0x12000, 0x1688A8A8);
280 do {
281 ;
282 } while (ast_read32(ast, 0x12000) != 0x01);
283
284 ast_write32(ast, 0x10000, 0xfc600309);
285 do {
286 ;
287 } while (ast_read32(ast, 0x10000) != 0x01);
288 }
289
290 while (dram_reg_info->index != 0xffff) {
291 if (dram_reg_info->index == 0xff00) {/* delay fn */
292 for (i = 0; i < 15; i++)
293 udelay(dram_reg_info->data);
294 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
295 data = dram_reg_info->data;
296 if (ast->dram_type == AST_DRAM_1Gx16)
297 data = 0x00000d89;
298 else if (ast->dram_type == AST_DRAM_1Gx32)
299 data = 0x00000c8d;
300
301 temp = ast_read32(ast, 0x12070);
302 temp &= 0xc;
303 temp <<= 2;
304 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
305 } else
306 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
307 dram_reg_info++;
308 }
309
310 /* AST 2100/2150 DRAM calibration */
311 data = ast_read32(ast, 0x10120);
312 if (data == 0x5061) { /* 266Mhz */
313 data = ast_read32(ast, 0x10004);
314 if (data & 0x40)
315 cbrdlli_ast2150(ast, 16); /* 16 bits */
316 else
317 cbrdlli_ast2150(ast, 32); /* 32 bits */
318 }
319
320 switch (AST_GEN(ast)) {
321 case 1:
322 temp = ast_read32(ast, 0x10140);
323 ast_write32(ast, 0x10140, temp | 0x40);
324 break;
325 case 2:
326 case 3:
327 temp = ast_read32(ast, 0x1200c);
328 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
329 temp = ast_read32(ast, 0x12040);
330 ast_write32(ast, 0x12040, temp | 0x40);
331 break;
332 default:
333 break;
334 }
335 }
336
337 /* wait ready */
338 do {
339 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
340 } while ((j & 0x40) == 0);
341 }
342
ast_post_gpu(struct ast_device * ast)343 int ast_post_gpu(struct ast_device *ast)
344 {
345 int ret;
346
347 ast_set_def_ext_reg(ast);
348
349 if (AST_GEN(ast) >= 7) {
350 if (ast->tx_chip == AST_TX_ASTDP) {
351 ret = ast_dp_launch(ast);
352 if (ret)
353 return ret;
354 }
355 } else if (AST_GEN(ast) >= 6) {
356 if (ast->config_mode == ast_use_p2a) {
357 ast_post_chip_2500(ast);
358 } else {
359 if (ast->tx_chip == AST_TX_SIL164) {
360 /* Enable DVO */
361 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
362 }
363 }
364 } else if (AST_GEN(ast) >= 4) {
365 if (ast->config_mode == ast_use_p2a) {
366 ast_post_chip_2300(ast);
367 ast_init_3rdtx(ast);
368 } else {
369 if (ast->tx_chip == AST_TX_SIL164) {
370 /* Enable DVO */
371 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
372 }
373 }
374 } else {
375 if (ast->config_mode == ast_use_p2a) {
376 ast_init_dram_reg(ast);
377 } else {
378 if (ast->tx_chip == AST_TX_SIL164) {
379 /* Enable DVO */
380 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
381 }
382 }
383 }
384
385 return 0;
386 }
387
388 /* AST 2300 DRAM settings */
389 #define AST_DDR3 0
390 #define AST_DDR2 1
391
392 struct ast2300_dram_param {
393 u32 dram_type;
394 u32 dram_chipid;
395 u32 dram_freq;
396 u32 vram_size;
397 u32 odt;
398 u32 wodt;
399 u32 rodt;
400 u32 dram_config;
401 u32 reg_PERIOD;
402 u32 reg_MADJ;
403 u32 reg_SADJ;
404 u32 reg_MRS;
405 u32 reg_EMRS;
406 u32 reg_AC1;
407 u32 reg_AC2;
408 u32 reg_DQSIC;
409 u32 reg_DRV;
410 u32 reg_IOZ;
411 u32 reg_DQIDLY;
412 u32 reg_FREQ;
413 u32 madj_max;
414 u32 dll2_finetune_step;
415 };
416
417 /*
418 * DQSI DLL CBR Setting
419 */
420 #define CBR_SIZE0 ((1 << 10) - 1)
421 #define CBR_SIZE1 ((4 << 10) - 1)
422 #define CBR_SIZE2 ((64 << 10) - 1)
423 #define CBR_PASSNUM 5
424 #define CBR_PASSNUM2 5
425 #define CBR_THRESHOLD 10
426 #define CBR_THRESHOLD2 10
427 #define TIMEOUT 5000000
428 #define CBR_PATNUM 8
429
430 static const u32 pattern[8] = {
431 0xFF00FF00,
432 0xCC33CC33,
433 0xAA55AA55,
434 0x88778877,
435 0x92CC4D6E,
436 0x543D3CDE,
437 0xF1E843C7,
438 0x7C61D253
439 };
440
mmc_test(struct ast_device * ast,u32 datagen,u8 test_ctl)441 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
442 {
443 u32 data, timeout;
444
445 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
446 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
447 timeout = 0;
448 do {
449 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
450 if (data & 0x2000)
451 return false;
452 if (++timeout > TIMEOUT) {
453 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
454 return false;
455 }
456 } while (!data);
457 ast_moutdwm(ast, 0x1e6e0070, 0x0);
458 return true;
459 }
460
mmc_test2(struct ast_device * ast,u32 datagen,u8 test_ctl)461 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
462 {
463 u32 data, timeout;
464
465 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
466 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
467 timeout = 0;
468 do {
469 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
470 if (++timeout > TIMEOUT) {
471 ast_moutdwm(ast, 0x1e6e0070, 0x0);
472 return 0xffffffff;
473 }
474 } while (!data);
475 data = ast_mindwm(ast, 0x1e6e0078);
476 data = (data | (data >> 16)) & 0xffff;
477 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
478 return data;
479 }
480
481
mmc_test_burst(struct ast_device * ast,u32 datagen)482 static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
483 {
484 return mmc_test(ast, datagen, 0xc1);
485 }
486
mmc_test_burst2(struct ast_device * ast,u32 datagen)487 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
488 {
489 return mmc_test2(ast, datagen, 0x41);
490 }
491
mmc_test_single(struct ast_device * ast,u32 datagen)492 static bool mmc_test_single(struct ast_device *ast, u32 datagen)
493 {
494 return mmc_test(ast, datagen, 0xc5);
495 }
496
mmc_test_single2(struct ast_device * ast,u32 datagen)497 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
498 {
499 return mmc_test2(ast, datagen, 0x05);
500 }
501
mmc_test_single_2500(struct ast_device * ast,u32 datagen)502 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
503 {
504 return mmc_test(ast, datagen, 0x85);
505 }
506
cbr_test(struct ast_device * ast)507 static int cbr_test(struct ast_device *ast)
508 {
509 u32 data;
510 int i;
511 data = mmc_test_single2(ast, 0);
512 if ((data & 0xff) && (data & 0xff00))
513 return 0;
514 for (i = 0; i < 8; i++) {
515 data = mmc_test_burst2(ast, i);
516 if ((data & 0xff) && (data & 0xff00))
517 return 0;
518 }
519 if (!data)
520 return 3;
521 else if (data & 0xff)
522 return 2;
523 return 1;
524 }
525
cbr_scan(struct ast_device * ast)526 static int cbr_scan(struct ast_device *ast)
527 {
528 u32 data, data2, patcnt, loop;
529
530 data2 = 3;
531 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
532 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
533 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
534 if ((data = cbr_test(ast)) != 0) {
535 data2 &= data;
536 if (!data2)
537 return 0;
538 break;
539 }
540 }
541 if (loop == CBR_PASSNUM2)
542 return 0;
543 }
544 return data2;
545 }
546
cbr_test2(struct ast_device * ast)547 static u32 cbr_test2(struct ast_device *ast)
548 {
549 u32 data;
550
551 data = mmc_test_burst2(ast, 0);
552 if (data == 0xffff)
553 return 0;
554 data |= mmc_test_single2(ast, 0);
555 if (data == 0xffff)
556 return 0;
557
558 return ~data & 0xffff;
559 }
560
cbr_scan2(struct ast_device * ast)561 static u32 cbr_scan2(struct ast_device *ast)
562 {
563 u32 data, data2, patcnt, loop;
564
565 data2 = 0xffff;
566 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
567 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
568 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
569 if ((data = cbr_test2(ast)) != 0) {
570 data2 &= data;
571 if (!data2)
572 return 0;
573 break;
574 }
575 }
576 if (loop == CBR_PASSNUM2)
577 return 0;
578 }
579 return data2;
580 }
581
cbr_test3(struct ast_device * ast)582 static bool cbr_test3(struct ast_device *ast)
583 {
584 if (!mmc_test_burst(ast, 0))
585 return false;
586 if (!mmc_test_single(ast, 0))
587 return false;
588 return true;
589 }
590
cbr_scan3(struct ast_device * ast)591 static bool cbr_scan3(struct ast_device *ast)
592 {
593 u32 patcnt, loop;
594
595 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
596 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
597 for (loop = 0; loop < 2; loop++) {
598 if (cbr_test3(ast))
599 break;
600 }
601 if (loop == 2)
602 return false;
603 }
604 return true;
605 }
606
finetuneDQI_L(struct ast_device * ast,struct ast2300_dram_param * param)607 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
608 {
609 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
610 bool status = false;
611 FINETUNE_START:
612 for (cnt = 0; cnt < 16; cnt++) {
613 dllmin[cnt] = 0xff;
614 dllmax[cnt] = 0x0;
615 }
616 passcnt = 0;
617 for (dlli = 0; dlli < 76; dlli++) {
618 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
619 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
620 data = cbr_scan2(ast);
621 if (data != 0) {
622 mask = 0x00010001;
623 for (cnt = 0; cnt < 16; cnt++) {
624 if (data & mask) {
625 if (dllmin[cnt] > dlli) {
626 dllmin[cnt] = dlli;
627 }
628 if (dllmax[cnt] < dlli) {
629 dllmax[cnt] = dlli;
630 }
631 }
632 mask <<= 1;
633 }
634 passcnt++;
635 } else if (passcnt >= CBR_THRESHOLD2) {
636 break;
637 }
638 }
639 gold_sadj[0] = 0x0;
640 passcnt = 0;
641 for (cnt = 0; cnt < 16; cnt++) {
642 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
643 gold_sadj[0] += dllmin[cnt];
644 passcnt++;
645 }
646 }
647 if (retry++ > 10)
648 goto FINETUNE_DONE;
649 if (passcnt != 16) {
650 goto FINETUNE_START;
651 }
652 status = true;
653 FINETUNE_DONE:
654 gold_sadj[0] = gold_sadj[0] >> 4;
655 gold_sadj[1] = gold_sadj[0];
656
657 data = 0;
658 for (cnt = 0; cnt < 8; cnt++) {
659 data >>= 3;
660 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
661 dlli = dllmin[cnt];
662 if (gold_sadj[0] >= dlli) {
663 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
664 if (dlli > 3) {
665 dlli = 3;
666 }
667 } else {
668 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
669 if (dlli > 4) {
670 dlli = 4;
671 }
672 dlli = (8 - dlli) & 0x7;
673 }
674 data |= dlli << 21;
675 }
676 }
677 ast_moutdwm(ast, 0x1E6E0080, data);
678
679 data = 0;
680 for (cnt = 8; cnt < 16; cnt++) {
681 data >>= 3;
682 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
683 dlli = dllmin[cnt];
684 if (gold_sadj[1] >= dlli) {
685 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
686 if (dlli > 3) {
687 dlli = 3;
688 } else {
689 dlli = (dlli - 1) & 0x7;
690 }
691 } else {
692 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
693 dlli += 1;
694 if (dlli > 4) {
695 dlli = 4;
696 }
697 dlli = (8 - dlli) & 0x7;
698 }
699 data |= dlli << 21;
700 }
701 }
702 ast_moutdwm(ast, 0x1E6E0084, data);
703 return status;
704 } /* finetuneDQI_L */
705
finetuneDQSI(struct ast_device * ast)706 static void finetuneDQSI(struct ast_device *ast)
707 {
708 u32 dlli, dqsip, dqidly;
709 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
710 u32 g_dqidly, g_dqsip, g_margin, g_side;
711 u16 pass[32][2][2];
712 char tag[2][76];
713
714 /* Disable DQI CBR */
715 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
716 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
717 reg_mcr18 &= 0x0000ffff;
718 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
719
720 for (dlli = 0; dlli < 76; dlli++) {
721 tag[0][dlli] = 0x0;
722 tag[1][dlli] = 0x0;
723 }
724 for (dqidly = 0; dqidly < 32; dqidly++) {
725 pass[dqidly][0][0] = 0xff;
726 pass[dqidly][0][1] = 0x0;
727 pass[dqidly][1][0] = 0xff;
728 pass[dqidly][1][1] = 0x0;
729 }
730 for (dqidly = 0; dqidly < 32; dqidly++) {
731 passcnt[0] = passcnt[1] = 0;
732 for (dqsip = 0; dqsip < 2; dqsip++) {
733 ast_moutdwm(ast, 0x1E6E000C, 0);
734 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
735 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
736 for (dlli = 0; dlli < 76; dlli++) {
737 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
738 ast_moutdwm(ast, 0x1E6E0070, 0);
739 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
740 if (cbr_scan3(ast)) {
741 if (dlli == 0)
742 break;
743 passcnt[dqsip]++;
744 tag[dqsip][dlli] = 'P';
745 if (dlli < pass[dqidly][dqsip][0])
746 pass[dqidly][dqsip][0] = (u16) dlli;
747 if (dlli > pass[dqidly][dqsip][1])
748 pass[dqidly][dqsip][1] = (u16) dlli;
749 } else if (passcnt[dqsip] >= 5)
750 break;
751 else {
752 pass[dqidly][dqsip][0] = 0xff;
753 pass[dqidly][dqsip][1] = 0x0;
754 }
755 }
756 }
757 if (passcnt[0] == 0 && passcnt[1] == 0)
758 dqidly++;
759 }
760 /* Search margin */
761 g_dqidly = g_dqsip = g_margin = g_side = 0;
762
763 for (dqidly = 0; dqidly < 32; dqidly++) {
764 for (dqsip = 0; dqsip < 2; dqsip++) {
765 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
766 continue;
767 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
768 if ((diff+2) < g_margin)
769 continue;
770 passcnt[0] = passcnt[1] = 0;
771 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
772 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
773 if (passcnt[0] > passcnt[1])
774 passcnt[0] = passcnt[1];
775 passcnt[1] = 0;
776 if (passcnt[0] > g_side)
777 passcnt[1] = passcnt[0] - g_side;
778 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
779 g_margin = diff;
780 g_dqidly = dqidly;
781 g_dqsip = dqsip;
782 g_side = passcnt[0];
783 } else if (passcnt[1] > 1 && g_side < 8) {
784 if (diff > g_margin)
785 g_margin = diff;
786 g_dqidly = dqidly;
787 g_dqsip = dqsip;
788 g_side = passcnt[0];
789 }
790 }
791 }
792 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
793 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
794
795 }
cbr_dll2(struct ast_device * ast,struct ast2300_dram_param * param)796 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
797 {
798 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
799 bool status = false;
800
801 finetuneDQSI(ast);
802 if (finetuneDQI_L(ast, param) == false)
803 return status;
804
805 CBR_START2:
806 dllmin[0] = dllmin[1] = 0xff;
807 dllmax[0] = dllmax[1] = 0x0;
808 passcnt = 0;
809 for (dlli = 0; dlli < 76; dlli++) {
810 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
811 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
812 data = cbr_scan(ast);
813 if (data != 0) {
814 if (data & 0x1) {
815 if (dllmin[0] > dlli) {
816 dllmin[0] = dlli;
817 }
818 if (dllmax[0] < dlli) {
819 dllmax[0] = dlli;
820 }
821 }
822 if (data & 0x2) {
823 if (dllmin[1] > dlli) {
824 dllmin[1] = dlli;
825 }
826 if (dllmax[1] < dlli) {
827 dllmax[1] = dlli;
828 }
829 }
830 passcnt++;
831 } else if (passcnt >= CBR_THRESHOLD) {
832 break;
833 }
834 }
835 if (retry++ > 10)
836 goto CBR_DONE2;
837 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
838 goto CBR_START2;
839 }
840 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
841 goto CBR_START2;
842 }
843 status = true;
844 CBR_DONE2:
845 dlli = (dllmin[1] + dllmax[1]) >> 1;
846 dlli <<= 8;
847 dlli += (dllmin[0] + dllmax[0]) >> 1;
848 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
849 return status;
850 } /* CBRDLL2 */
851
get_ddr3_info(struct ast_device * ast,struct ast2300_dram_param * param)852 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
853 {
854 u32 trap, trap_AC2, trap_MRS;
855
856 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
857
858 /* Ger trap info */
859 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
860 trap_AC2 = 0x00020000 + (trap << 16);
861 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
862 trap_MRS = 0x00000010 + (trap << 4);
863 trap_MRS |= ((trap & 0x2) << 18);
864
865 param->reg_MADJ = 0x00034C4C;
866 param->reg_SADJ = 0x00001800;
867 param->reg_DRV = 0x000000F0;
868 param->reg_PERIOD = param->dram_freq;
869 param->rodt = 0;
870
871 switch (param->dram_freq) {
872 case 336:
873 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
874 param->wodt = 0;
875 param->reg_AC1 = 0x22202725;
876 param->reg_AC2 = 0xAA007613 | trap_AC2;
877 param->reg_DQSIC = 0x000000BA;
878 param->reg_MRS = 0x04001400 | trap_MRS;
879 param->reg_EMRS = 0x00000000;
880 param->reg_IOZ = 0x00000023;
881 param->reg_DQIDLY = 0x00000074;
882 param->reg_FREQ = 0x00004DC0;
883 param->madj_max = 96;
884 param->dll2_finetune_step = 3;
885 switch (param->dram_chipid) {
886 default:
887 case AST_DRAM_512Mx16:
888 case AST_DRAM_1Gx16:
889 param->reg_AC2 = 0xAA007613 | trap_AC2;
890 break;
891 case AST_DRAM_2Gx16:
892 param->reg_AC2 = 0xAA00761C | trap_AC2;
893 break;
894 case AST_DRAM_4Gx16:
895 param->reg_AC2 = 0xAA007636 | trap_AC2;
896 break;
897 }
898 break;
899 default:
900 case 396:
901 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
902 param->wodt = 1;
903 param->reg_AC1 = 0x33302825;
904 param->reg_AC2 = 0xCC009617 | trap_AC2;
905 param->reg_DQSIC = 0x000000E2;
906 param->reg_MRS = 0x04001600 | trap_MRS;
907 param->reg_EMRS = 0x00000000;
908 param->reg_IOZ = 0x00000034;
909 param->reg_DRV = 0x000000FA;
910 param->reg_DQIDLY = 0x00000089;
911 param->reg_FREQ = 0x00005040;
912 param->madj_max = 96;
913 param->dll2_finetune_step = 4;
914
915 switch (param->dram_chipid) {
916 default:
917 case AST_DRAM_512Mx16:
918 case AST_DRAM_1Gx16:
919 param->reg_AC2 = 0xCC009617 | trap_AC2;
920 break;
921 case AST_DRAM_2Gx16:
922 param->reg_AC2 = 0xCC009622 | trap_AC2;
923 break;
924 case AST_DRAM_4Gx16:
925 param->reg_AC2 = 0xCC00963F | trap_AC2;
926 break;
927 }
928 break;
929
930 case 408:
931 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
932 param->wodt = 1;
933 param->reg_AC1 = 0x33302825;
934 param->reg_AC2 = 0xCC009617 | trap_AC2;
935 param->reg_DQSIC = 0x000000E2;
936 param->reg_MRS = 0x04001600 | trap_MRS;
937 param->reg_EMRS = 0x00000000;
938 param->reg_IOZ = 0x00000023;
939 param->reg_DRV = 0x000000FA;
940 param->reg_DQIDLY = 0x00000089;
941 param->reg_FREQ = 0x000050C0;
942 param->madj_max = 96;
943 param->dll2_finetune_step = 4;
944
945 switch (param->dram_chipid) {
946 default:
947 case AST_DRAM_512Mx16:
948 case AST_DRAM_1Gx16:
949 param->reg_AC2 = 0xCC009617 | trap_AC2;
950 break;
951 case AST_DRAM_2Gx16:
952 param->reg_AC2 = 0xCC009622 | trap_AC2;
953 break;
954 case AST_DRAM_4Gx16:
955 param->reg_AC2 = 0xCC00963F | trap_AC2;
956 break;
957 }
958
959 break;
960 case 456:
961 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
962 param->wodt = 0;
963 param->reg_AC1 = 0x33302926;
964 param->reg_AC2 = 0xCD44961A;
965 param->reg_DQSIC = 0x000000FC;
966 param->reg_MRS = 0x00081830;
967 param->reg_EMRS = 0x00000000;
968 param->reg_IOZ = 0x00000045;
969 param->reg_DQIDLY = 0x00000097;
970 param->reg_FREQ = 0x000052C0;
971 param->madj_max = 88;
972 param->dll2_finetune_step = 4;
973 break;
974 case 504:
975 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
976 param->wodt = 1;
977 param->reg_AC1 = 0x33302926;
978 param->reg_AC2 = 0xDE44A61D;
979 param->reg_DQSIC = 0x00000117;
980 param->reg_MRS = 0x00081A30;
981 param->reg_EMRS = 0x00000000;
982 param->reg_IOZ = 0x070000BB;
983 param->reg_DQIDLY = 0x000000A0;
984 param->reg_FREQ = 0x000054C0;
985 param->madj_max = 79;
986 param->dll2_finetune_step = 4;
987 break;
988 case 528:
989 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
990 param->wodt = 1;
991 param->rodt = 1;
992 param->reg_AC1 = 0x33302926;
993 param->reg_AC2 = 0xEF44B61E;
994 param->reg_DQSIC = 0x00000125;
995 param->reg_MRS = 0x00081A30;
996 param->reg_EMRS = 0x00000040;
997 param->reg_DRV = 0x000000F5;
998 param->reg_IOZ = 0x00000023;
999 param->reg_DQIDLY = 0x00000088;
1000 param->reg_FREQ = 0x000055C0;
1001 param->madj_max = 76;
1002 param->dll2_finetune_step = 3;
1003 break;
1004 case 576:
1005 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1006 param->reg_MADJ = 0x00136868;
1007 param->reg_SADJ = 0x00004534;
1008 param->wodt = 1;
1009 param->rodt = 1;
1010 param->reg_AC1 = 0x33302A37;
1011 param->reg_AC2 = 0xEF56B61E;
1012 param->reg_DQSIC = 0x0000013F;
1013 param->reg_MRS = 0x00101A50;
1014 param->reg_EMRS = 0x00000040;
1015 param->reg_DRV = 0x000000FA;
1016 param->reg_IOZ = 0x00000023;
1017 param->reg_DQIDLY = 0x00000078;
1018 param->reg_FREQ = 0x000057C0;
1019 param->madj_max = 136;
1020 param->dll2_finetune_step = 3;
1021 break;
1022 case 600:
1023 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1024 param->reg_MADJ = 0x00136868;
1025 param->reg_SADJ = 0x00004534;
1026 param->wodt = 1;
1027 param->rodt = 1;
1028 param->reg_AC1 = 0x32302A37;
1029 param->reg_AC2 = 0xDF56B61F;
1030 param->reg_DQSIC = 0x0000014D;
1031 param->reg_MRS = 0x00101A50;
1032 param->reg_EMRS = 0x00000004;
1033 param->reg_DRV = 0x000000F5;
1034 param->reg_IOZ = 0x00000023;
1035 param->reg_DQIDLY = 0x00000078;
1036 param->reg_FREQ = 0x000058C0;
1037 param->madj_max = 132;
1038 param->dll2_finetune_step = 3;
1039 break;
1040 case 624:
1041 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1042 param->reg_MADJ = 0x00136868;
1043 param->reg_SADJ = 0x00004534;
1044 param->wodt = 1;
1045 param->rodt = 1;
1046 param->reg_AC1 = 0x32302A37;
1047 param->reg_AC2 = 0xEF56B621;
1048 param->reg_DQSIC = 0x0000015A;
1049 param->reg_MRS = 0x02101A50;
1050 param->reg_EMRS = 0x00000004;
1051 param->reg_DRV = 0x000000F5;
1052 param->reg_IOZ = 0x00000034;
1053 param->reg_DQIDLY = 0x00000078;
1054 param->reg_FREQ = 0x000059C0;
1055 param->madj_max = 128;
1056 param->dll2_finetune_step = 3;
1057 break;
1058 } /* switch freq */
1059
1060 switch (param->dram_chipid) {
1061 case AST_DRAM_512Mx16:
1062 param->dram_config = 0x130;
1063 break;
1064 default:
1065 case AST_DRAM_1Gx16:
1066 param->dram_config = 0x131;
1067 break;
1068 case AST_DRAM_2Gx16:
1069 param->dram_config = 0x132;
1070 break;
1071 case AST_DRAM_4Gx16:
1072 param->dram_config = 0x133;
1073 break;
1074 } /* switch size */
1075
1076 switch (param->vram_size) {
1077 default:
1078 case AST_VIDMEM_SIZE_8M:
1079 param->dram_config |= 0x00;
1080 break;
1081 case AST_VIDMEM_SIZE_16M:
1082 param->dram_config |= 0x04;
1083 break;
1084 case AST_VIDMEM_SIZE_32M:
1085 param->dram_config |= 0x08;
1086 break;
1087 case AST_VIDMEM_SIZE_64M:
1088 param->dram_config |= 0x0c;
1089 break;
1090 }
1091
1092 }
1093
ddr3_init(struct ast_device * ast,struct ast2300_dram_param * param)1094 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1095 {
1096 u32 data, data2, retry = 0;
1097
1098 ddr3_init_start:
1099 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1100 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1101 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1102 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1103 udelay(10);
1104 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1105 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1106 udelay(10);
1107 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1108 udelay(10);
1109
1110 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1111 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1112 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1113 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1114 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1115 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1116 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1117 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1118 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1119 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1120 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1121 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1122 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1123 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1124 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1125 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1126 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1127 ast_moutdwm(ast, 0x1E6E0054, 0);
1128 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1129 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1130 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1131 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1132 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1133 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1134 /* Wait MCLK2X lock to MCLK */
1135 do {
1136 data = ast_mindwm(ast, 0x1E6E001C);
1137 } while (!(data & 0x08000000));
1138 data = ast_mindwm(ast, 0x1E6E001C);
1139 data = (data >> 8) & 0xff;
1140 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1141 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1142 if ((data2 & 0xff) > param->madj_max) {
1143 break;
1144 }
1145 ast_moutdwm(ast, 0x1E6E0064, data2);
1146 if (data2 & 0x00100000) {
1147 data2 = ((data2 & 0xff) >> 3) + 3;
1148 } else {
1149 data2 = ((data2 & 0xff) >> 2) + 5;
1150 }
1151 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1152 data2 += data & 0xff;
1153 data = data | (data2 << 8);
1154 ast_moutdwm(ast, 0x1E6E0068, data);
1155 udelay(10);
1156 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1157 udelay(10);
1158 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1159 ast_moutdwm(ast, 0x1E6E0018, data);
1160 data = data | 0x200;
1161 ast_moutdwm(ast, 0x1E6E0018, data);
1162 do {
1163 data = ast_mindwm(ast, 0x1E6E001C);
1164 } while (!(data & 0x08000000));
1165
1166 data = ast_mindwm(ast, 0x1E6E001C);
1167 data = (data >> 8) & 0xff;
1168 }
1169 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1170 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1171 ast_moutdwm(ast, 0x1E6E0018, data);
1172
1173 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1174 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1175 udelay(50);
1176 /* Mode Register Setting */
1177 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1178 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1179 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1180 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1181 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1182 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1183 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1184 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1185 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1186
1187 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1188 data = 0;
1189 if (param->wodt) {
1190 data = 0x300;
1191 }
1192 if (param->rodt) {
1193 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1194 }
1195 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1196
1197 /* Calibrate the DQSI delay */
1198 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1199 goto ddr3_init_start;
1200
1201 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1202 /* ECC Memory Initialization */
1203 #ifdef ECC
1204 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1205 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1206 do {
1207 data = ast_mindwm(ast, 0x1E6E0070);
1208 } while (!(data & 0x00001000));
1209 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1210 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1211 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1212 #endif
1213
1214
1215 }
1216
get_ddr2_info(struct ast_device * ast,struct ast2300_dram_param * param)1217 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1218 {
1219 u32 trap, trap_AC2, trap_MRS;
1220
1221 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1222
1223 /* Ger trap info */
1224 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1225 trap_AC2 = (trap << 20) | (trap << 16);
1226 trap_AC2 += 0x00110000;
1227 trap_MRS = 0x00000040 | (trap << 4);
1228
1229
1230 param->reg_MADJ = 0x00034C4C;
1231 param->reg_SADJ = 0x00001800;
1232 param->reg_DRV = 0x000000F0;
1233 param->reg_PERIOD = param->dram_freq;
1234 param->rodt = 0;
1235
1236 switch (param->dram_freq) {
1237 case 264:
1238 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1239 param->wodt = 0;
1240 param->reg_AC1 = 0x11101513;
1241 param->reg_AC2 = 0x78117011;
1242 param->reg_DQSIC = 0x00000092;
1243 param->reg_MRS = 0x00000842;
1244 param->reg_EMRS = 0x00000000;
1245 param->reg_DRV = 0x000000F0;
1246 param->reg_IOZ = 0x00000034;
1247 param->reg_DQIDLY = 0x0000005A;
1248 param->reg_FREQ = 0x00004AC0;
1249 param->madj_max = 138;
1250 param->dll2_finetune_step = 3;
1251 break;
1252 case 336:
1253 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1254 param->wodt = 1;
1255 param->reg_AC1 = 0x22202613;
1256 param->reg_AC2 = 0xAA009016 | trap_AC2;
1257 param->reg_DQSIC = 0x000000BA;
1258 param->reg_MRS = 0x00000A02 | trap_MRS;
1259 param->reg_EMRS = 0x00000040;
1260 param->reg_DRV = 0x000000FA;
1261 param->reg_IOZ = 0x00000034;
1262 param->reg_DQIDLY = 0x00000074;
1263 param->reg_FREQ = 0x00004DC0;
1264 param->madj_max = 96;
1265 param->dll2_finetune_step = 3;
1266 switch (param->dram_chipid) {
1267 default:
1268 case AST_DRAM_512Mx16:
1269 param->reg_AC2 = 0xAA009012 | trap_AC2;
1270 break;
1271 case AST_DRAM_1Gx16:
1272 param->reg_AC2 = 0xAA009016 | trap_AC2;
1273 break;
1274 case AST_DRAM_2Gx16:
1275 param->reg_AC2 = 0xAA009023 | trap_AC2;
1276 break;
1277 case AST_DRAM_4Gx16:
1278 param->reg_AC2 = 0xAA00903B | trap_AC2;
1279 break;
1280 }
1281 break;
1282 default:
1283 case 396:
1284 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1285 param->wodt = 1;
1286 param->rodt = 0;
1287 param->reg_AC1 = 0x33302714;
1288 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1289 param->reg_DQSIC = 0x000000E2;
1290 param->reg_MRS = 0x00000C02 | trap_MRS;
1291 param->reg_EMRS = 0x00000040;
1292 param->reg_DRV = 0x000000FA;
1293 param->reg_IOZ = 0x00000034;
1294 param->reg_DQIDLY = 0x00000089;
1295 param->reg_FREQ = 0x00005040;
1296 param->madj_max = 96;
1297 param->dll2_finetune_step = 4;
1298
1299 switch (param->dram_chipid) {
1300 case AST_DRAM_512Mx16:
1301 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1302 break;
1303 default:
1304 case AST_DRAM_1Gx16:
1305 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1306 break;
1307 case AST_DRAM_2Gx16:
1308 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1309 break;
1310 case AST_DRAM_4Gx16:
1311 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1312 break;
1313 }
1314
1315 break;
1316
1317 case 408:
1318 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1319 param->wodt = 1;
1320 param->rodt = 0;
1321 param->reg_AC1 = 0x33302714;
1322 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1323 param->reg_DQSIC = 0x000000E2;
1324 param->reg_MRS = 0x00000C02 | trap_MRS;
1325 param->reg_EMRS = 0x00000040;
1326 param->reg_DRV = 0x000000FA;
1327 param->reg_IOZ = 0x00000034;
1328 param->reg_DQIDLY = 0x00000089;
1329 param->reg_FREQ = 0x000050C0;
1330 param->madj_max = 96;
1331 param->dll2_finetune_step = 4;
1332
1333 switch (param->dram_chipid) {
1334 case AST_DRAM_512Mx16:
1335 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1336 break;
1337 default:
1338 case AST_DRAM_1Gx16:
1339 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1340 break;
1341 case AST_DRAM_2Gx16:
1342 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1343 break;
1344 case AST_DRAM_4Gx16:
1345 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1346 break;
1347 }
1348
1349 break;
1350 case 456:
1351 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1352 param->wodt = 0;
1353 param->reg_AC1 = 0x33302815;
1354 param->reg_AC2 = 0xCD44B01E;
1355 param->reg_DQSIC = 0x000000FC;
1356 param->reg_MRS = 0x00000E72;
1357 param->reg_EMRS = 0x00000000;
1358 param->reg_DRV = 0x00000000;
1359 param->reg_IOZ = 0x00000034;
1360 param->reg_DQIDLY = 0x00000097;
1361 param->reg_FREQ = 0x000052C0;
1362 param->madj_max = 88;
1363 param->dll2_finetune_step = 3;
1364 break;
1365 case 504:
1366 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1367 param->wodt = 1;
1368 param->rodt = 1;
1369 param->reg_AC1 = 0x33302815;
1370 param->reg_AC2 = 0xDE44C022;
1371 param->reg_DQSIC = 0x00000117;
1372 param->reg_MRS = 0x00000E72;
1373 param->reg_EMRS = 0x00000040;
1374 param->reg_DRV = 0x0000000A;
1375 param->reg_IOZ = 0x00000045;
1376 param->reg_DQIDLY = 0x000000A0;
1377 param->reg_FREQ = 0x000054C0;
1378 param->madj_max = 79;
1379 param->dll2_finetune_step = 3;
1380 break;
1381 case 528:
1382 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1383 param->wodt = 1;
1384 param->rodt = 1;
1385 param->reg_AC1 = 0x33302815;
1386 param->reg_AC2 = 0xEF44D024;
1387 param->reg_DQSIC = 0x00000125;
1388 param->reg_MRS = 0x00000E72;
1389 param->reg_EMRS = 0x00000004;
1390 param->reg_DRV = 0x000000F9;
1391 param->reg_IOZ = 0x00000045;
1392 param->reg_DQIDLY = 0x000000A7;
1393 param->reg_FREQ = 0x000055C0;
1394 param->madj_max = 76;
1395 param->dll2_finetune_step = 3;
1396 break;
1397 case 552:
1398 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1399 param->wodt = 1;
1400 param->rodt = 1;
1401 param->reg_AC1 = 0x43402915;
1402 param->reg_AC2 = 0xFF44E025;
1403 param->reg_DQSIC = 0x00000132;
1404 param->reg_MRS = 0x00000E72;
1405 param->reg_EMRS = 0x00000040;
1406 param->reg_DRV = 0x0000000A;
1407 param->reg_IOZ = 0x00000045;
1408 param->reg_DQIDLY = 0x000000AD;
1409 param->reg_FREQ = 0x000056C0;
1410 param->madj_max = 76;
1411 param->dll2_finetune_step = 3;
1412 break;
1413 case 576:
1414 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1415 param->wodt = 1;
1416 param->rodt = 1;
1417 param->reg_AC1 = 0x43402915;
1418 param->reg_AC2 = 0xFF44E027;
1419 param->reg_DQSIC = 0x0000013F;
1420 param->reg_MRS = 0x00000E72;
1421 param->reg_EMRS = 0x00000004;
1422 param->reg_DRV = 0x000000F5;
1423 param->reg_IOZ = 0x00000045;
1424 param->reg_DQIDLY = 0x000000B3;
1425 param->reg_FREQ = 0x000057C0;
1426 param->madj_max = 76;
1427 param->dll2_finetune_step = 3;
1428 break;
1429 }
1430
1431 switch (param->dram_chipid) {
1432 case AST_DRAM_512Mx16:
1433 param->dram_config = 0x100;
1434 break;
1435 default:
1436 case AST_DRAM_1Gx16:
1437 param->dram_config = 0x121;
1438 break;
1439 case AST_DRAM_2Gx16:
1440 param->dram_config = 0x122;
1441 break;
1442 case AST_DRAM_4Gx16:
1443 param->dram_config = 0x123;
1444 break;
1445 } /* switch size */
1446
1447 switch (param->vram_size) {
1448 default:
1449 case AST_VIDMEM_SIZE_8M:
1450 param->dram_config |= 0x00;
1451 break;
1452 case AST_VIDMEM_SIZE_16M:
1453 param->dram_config |= 0x04;
1454 break;
1455 case AST_VIDMEM_SIZE_32M:
1456 param->dram_config |= 0x08;
1457 break;
1458 case AST_VIDMEM_SIZE_64M:
1459 param->dram_config |= 0x0c;
1460 break;
1461 }
1462 }
1463
ddr2_init(struct ast_device * ast,struct ast2300_dram_param * param)1464 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1465 {
1466 u32 data, data2, retry = 0;
1467
1468 ddr2_init_start:
1469 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1470 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1471 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1472 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1473 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1474 udelay(10);
1475 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1476 udelay(10);
1477
1478 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1479 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1480 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1481 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1482 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1483 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1484 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1485 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1486 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1487 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1488 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1489 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1490 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1491 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1492 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1493 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1494 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1495 ast_moutdwm(ast, 0x1E6E0054, 0);
1496 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1497 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1498 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1499 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1500 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1501 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1502
1503 /* Wait MCLK2X lock to MCLK */
1504 do {
1505 data = ast_mindwm(ast, 0x1E6E001C);
1506 } while (!(data & 0x08000000));
1507 data = ast_mindwm(ast, 0x1E6E001C);
1508 data = (data >> 8) & 0xff;
1509 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1510 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1511 if ((data2 & 0xff) > param->madj_max) {
1512 break;
1513 }
1514 ast_moutdwm(ast, 0x1E6E0064, data2);
1515 if (data2 & 0x00100000) {
1516 data2 = ((data2 & 0xff) >> 3) + 3;
1517 } else {
1518 data2 = ((data2 & 0xff) >> 2) + 5;
1519 }
1520 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1521 data2 += data & 0xff;
1522 data = data | (data2 << 8);
1523 ast_moutdwm(ast, 0x1E6E0068, data);
1524 udelay(10);
1525 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1526 udelay(10);
1527 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1528 ast_moutdwm(ast, 0x1E6E0018, data);
1529 data = data | 0x200;
1530 ast_moutdwm(ast, 0x1E6E0018, data);
1531 do {
1532 data = ast_mindwm(ast, 0x1E6E001C);
1533 } while (!(data & 0x08000000));
1534
1535 data = ast_mindwm(ast, 0x1E6E001C);
1536 data = (data >> 8) & 0xff;
1537 }
1538 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1539 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1540 ast_moutdwm(ast, 0x1E6E0018, data);
1541
1542 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1543 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1544 udelay(50);
1545 /* Mode Register Setting */
1546 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1547 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1548 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1549 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1550 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1551 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1552
1553 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1554 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1555 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1556 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1557 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1558 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1559 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1560
1561 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1562 data = 0;
1563 if (param->wodt) {
1564 data = 0x500;
1565 }
1566 if (param->rodt) {
1567 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1568 }
1569 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1570 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1571
1572 /* Calibrate the DQSI delay */
1573 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1574 goto ddr2_init_start;
1575
1576 /* ECC Memory Initialization */
1577 #ifdef ECC
1578 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1579 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1580 do {
1581 data = ast_mindwm(ast, 0x1E6E0070);
1582 } while (!(data & 0x00001000));
1583 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1584 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1585 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1586 #endif
1587
1588 }
1589
ast_post_chip_2300(struct ast_device * ast)1590 static void ast_post_chip_2300(struct ast_device *ast)
1591 {
1592 struct ast2300_dram_param param;
1593 u32 temp;
1594 u8 reg;
1595
1596 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1597 if ((reg & 0x80) == 0) {/* vga only */
1598 ast_write32(ast, 0xf004, 0x1e6e0000);
1599 ast_write32(ast, 0xf000, 0x1);
1600 ast_write32(ast, 0x12000, 0x1688a8a8);
1601 do {
1602 ;
1603 } while (ast_read32(ast, 0x12000) != 0x1);
1604
1605 ast_write32(ast, 0x10000, 0xfc600309);
1606 do {
1607 ;
1608 } while (ast_read32(ast, 0x10000) != 0x1);
1609
1610 /* Slow down CPU/AHB CLK in VGA only mode */
1611 temp = ast_read32(ast, 0x12008);
1612 temp |= 0x73;
1613 ast_write32(ast, 0x12008, temp);
1614
1615 param.dram_freq = 396;
1616 param.dram_type = AST_DDR3;
1617 temp = ast_mindwm(ast, 0x1e6e2070);
1618 if (temp & 0x01000000)
1619 param.dram_type = AST_DDR2;
1620 switch (temp & 0x18000000) {
1621 case 0:
1622 param.dram_chipid = AST_DRAM_512Mx16;
1623 break;
1624 default:
1625 case 0x08000000:
1626 param.dram_chipid = AST_DRAM_1Gx16;
1627 break;
1628 case 0x10000000:
1629 param.dram_chipid = AST_DRAM_2Gx16;
1630 break;
1631 case 0x18000000:
1632 param.dram_chipid = AST_DRAM_4Gx16;
1633 break;
1634 }
1635 switch (temp & 0x0c) {
1636 default:
1637 case 0x00:
1638 param.vram_size = AST_VIDMEM_SIZE_8M;
1639 break;
1640
1641 case 0x04:
1642 param.vram_size = AST_VIDMEM_SIZE_16M;
1643 break;
1644
1645 case 0x08:
1646 param.vram_size = AST_VIDMEM_SIZE_32M;
1647 break;
1648
1649 case 0x0c:
1650 param.vram_size = AST_VIDMEM_SIZE_64M;
1651 break;
1652 }
1653
1654 if (param.dram_type == AST_DDR3) {
1655 get_ddr3_info(ast, ¶m);
1656 ddr3_init(ast, ¶m);
1657 } else {
1658 get_ddr2_info(ast, ¶m);
1659 ddr2_init(ast, ¶m);
1660 }
1661
1662 temp = ast_mindwm(ast, 0x1e6e2040);
1663 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1664 }
1665
1666 /* wait ready */
1667 do {
1668 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1669 } while ((reg & 0x40) == 0);
1670 }
1671
cbr_test_2500(struct ast_device * ast)1672 static bool cbr_test_2500(struct ast_device *ast)
1673 {
1674 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1675 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1676 if (!mmc_test_burst(ast, 0))
1677 return false;
1678 if (!mmc_test_single_2500(ast, 0))
1679 return false;
1680 return true;
1681 }
1682
ddr_test_2500(struct ast_device * ast)1683 static bool ddr_test_2500(struct ast_device *ast)
1684 {
1685 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1686 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1687 if (!mmc_test_burst(ast, 0))
1688 return false;
1689 if (!mmc_test_burst(ast, 1))
1690 return false;
1691 if (!mmc_test_burst(ast, 2))
1692 return false;
1693 if (!mmc_test_burst(ast, 3))
1694 return false;
1695 if (!mmc_test_single_2500(ast, 0))
1696 return false;
1697 return true;
1698 }
1699
ddr_init_common_2500(struct ast_device * ast)1700 static void ddr_init_common_2500(struct ast_device *ast)
1701 {
1702 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1703 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1704 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1705 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1706 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1707 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1708 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1709 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1710 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1711 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1712 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1713 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1714 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1715 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1716 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1717 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1718 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1719 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1720 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1721 }
1722
ddr_phy_init_2500(struct ast_device * ast)1723 static void ddr_phy_init_2500(struct ast_device *ast)
1724 {
1725 u32 data, pass, timecnt;
1726
1727 pass = 0;
1728 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1729 while (!pass) {
1730 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1731 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1732 if (!data)
1733 break;
1734 }
1735 if (timecnt != TIMEOUT) {
1736 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1737 if (!data)
1738 pass = 1;
1739 }
1740 if (!pass) {
1741 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1742 udelay(10); /* delay 10 us */
1743 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1744 }
1745 }
1746
1747 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1748 }
1749
1750 /*
1751 * Check DRAM Size
1752 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1753 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1754 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1755 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1756 */
check_dram_size_2500(struct ast_device * ast,u32 tRFC)1757 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1758 {
1759 u32 reg_04, reg_14;
1760
1761 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1762 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1763
1764 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1765 ast_moutdwm(ast, 0x90100000, 0x35363738);
1766 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1767 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1768
1769 /* Check 8Gbit */
1770 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1771 reg_04 |= 0x03;
1772 reg_14 |= (tRFC >> 24) & 0xFF;
1773 /* Check 4Gbit */
1774 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1775 reg_04 |= 0x02;
1776 reg_14 |= (tRFC >> 16) & 0xFF;
1777 /* Check 2Gbit */
1778 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1779 reg_04 |= 0x01;
1780 reg_14 |= (tRFC >> 8) & 0xFF;
1781 } else {
1782 reg_14 |= tRFC & 0xFF;
1783 }
1784 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1785 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1786 }
1787
enable_cache_2500(struct ast_device * ast)1788 static void enable_cache_2500(struct ast_device *ast)
1789 {
1790 u32 reg_04, data;
1791
1792 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1793 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1794
1795 do
1796 data = ast_mindwm(ast, 0x1E6E0004);
1797 while (!(data & 0x80000));
1798 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1799 }
1800
set_mpll_2500(struct ast_device * ast)1801 static void set_mpll_2500(struct ast_device *ast)
1802 {
1803 u32 addr, data, param;
1804
1805 /* Reset MMC */
1806 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1807 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1808 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1809 ast_moutdwm(ast, addr, 0x0);
1810 addr += 4;
1811 }
1812 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1813
1814 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1815 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1816 if (data) {
1817 /* CLKIN = 25MHz */
1818 param = 0x930023E0;
1819 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1820 } else {
1821 /* CLKIN = 24MHz */
1822 param = 0x93002400;
1823 }
1824 ast_moutdwm(ast, 0x1E6E2020, param);
1825 udelay(100);
1826 }
1827
reset_mmc_2500(struct ast_device * ast)1828 static void reset_mmc_2500(struct ast_device *ast)
1829 {
1830 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1831 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1832 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1833 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1834 mdelay(100);
1835 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1836 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1837 }
1838
ddr3_init_2500(struct ast_device * ast,const u32 * ddr_table)1839 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1840 {
1841
1842 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1843 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1844 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1845 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1846 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1847 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1848 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1849 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1850
1851 /* DDR PHY Setting */
1852 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1853 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1854 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1855 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1856 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1857 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1858 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1859 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1860 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1861 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1862 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1863 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1864 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1865 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1866
1867 /* Controller Setting */
1868 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1869
1870 /* Wait DDR PHY init done */
1871 ddr_phy_init_2500(ast);
1872
1873 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1874 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1875 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1876
1877 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1878 enable_cache_2500(ast);
1879 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1880 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1881 }
1882
ddr4_init_2500(struct ast_device * ast,const u32 * ddr_table)1883 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1884 {
1885 u32 data, data2, pass, retrycnt;
1886 u32 ddr_vref, phy_vref;
1887 u32 min_ddr_vref = 0, min_phy_vref = 0;
1888 u32 max_ddr_vref = 0, max_phy_vref = 0;
1889
1890 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1891 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1892 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1893 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1894 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1895 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1896 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1897 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1898
1899 /* DDR PHY Setting */
1900 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1901 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1902 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1903 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1904 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1905 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1906 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1907 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1908 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1909 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1910 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1911 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1912 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1913 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1914 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1915
1916 /* Controller Setting */
1917 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1918
1919 /* Train PHY Vref first */
1920 pass = 0;
1921
1922 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1923 max_phy_vref = 0x0;
1924 pass = 0;
1925 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1926 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1927 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1928 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1929 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1930 /* Fire DFI Init */
1931 ddr_phy_init_2500(ast);
1932 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1933 if (cbr_test_2500(ast)) {
1934 pass++;
1935 data = ast_mindwm(ast, 0x1E6E03D0);
1936 data2 = data >> 8;
1937 data = data & 0xff;
1938 if (data > data2)
1939 data = data2;
1940 if (max_phy_vref < data) {
1941 max_phy_vref = data;
1942 min_phy_vref = phy_vref;
1943 }
1944 } else if (pass > 0)
1945 break;
1946 }
1947 }
1948 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1949
1950 /* Train DDR Vref next */
1951 pass = 0;
1952
1953 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1954 min_ddr_vref = 0xFF;
1955 max_ddr_vref = 0x0;
1956 pass = 0;
1957 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1958 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1959 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1960 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1961 /* Fire DFI Init */
1962 ddr_phy_init_2500(ast);
1963 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1964 if (cbr_test_2500(ast)) {
1965 pass++;
1966 if (min_ddr_vref > ddr_vref)
1967 min_ddr_vref = ddr_vref;
1968 if (max_ddr_vref < ddr_vref)
1969 max_ddr_vref = ddr_vref;
1970 } else if (pass != 0)
1971 break;
1972 }
1973 }
1974
1975 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1976 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1977 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1978 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1979
1980 /* Wait DDR PHY init done */
1981 ddr_phy_init_2500(ast);
1982
1983 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1984 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1985 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1986
1987 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1988 enable_cache_2500(ast);
1989 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1990 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1991 }
1992
ast_dram_init_2500(struct ast_device * ast)1993 static bool ast_dram_init_2500(struct ast_device *ast)
1994 {
1995 u32 data;
1996 u32 max_tries = 5;
1997
1998 do {
1999 if (max_tries-- == 0)
2000 return false;
2001 set_mpll_2500(ast);
2002 reset_mmc_2500(ast);
2003 ddr_init_common_2500(ast);
2004
2005 data = ast_mindwm(ast, 0x1E6E2070);
2006 if (data & 0x01000000)
2007 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
2008 else
2009 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
2010 } while (!ddr_test_2500(ast));
2011
2012 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
2013
2014 /* Patch code */
2015 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
2016 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
2017
2018 return true;
2019 }
2020
ast_patch_ahb_2500(void __iomem * regs)2021 void ast_patch_ahb_2500(void __iomem *regs)
2022 {
2023 u32 data;
2024
2025 /* Clear bus lock condition */
2026 __ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
2027 __ast_moutdwm(regs, 0x1e600084, 0x00010000);
2028 __ast_moutdwm(regs, 0x1e600088, 0x00000000);
2029 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2030
2031 data = __ast_mindwm(regs, 0x1e6e2070);
2032 if (data & 0x08000000) { /* check fast reset */
2033 /*
2034 * If "Fast restet" is enabled for ARM-ICE debugger,
2035 * then WDT needs to enable, that
2036 * WDT04 is WDT#1 Reload reg.
2037 * WDT08 is WDT#1 counter restart reg to avoid system deadlock
2038 * WDT0C is WDT#1 control reg
2039 * [6:5]:= 01:Full chip
2040 * [4]:= 1:1MHz clock source
2041 * [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2042 * [0]:= 1:WDT enable
2043 */
2044 __ast_moutdwm(regs, 0x1E785004, 0x00000010);
2045 __ast_moutdwm(regs, 0x1E785008, 0x00004755);
2046 __ast_moutdwm(regs, 0x1E78500c, 0x00000033);
2047 udelay(1000);
2048 }
2049
2050 do {
2051 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2052 data = __ast_mindwm(regs, 0x1e6e2000);
2053 } while (data != 1);
2054
2055 __ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
2056 }
2057
ast_post_chip_2500(struct ast_device * ast)2058 void ast_post_chip_2500(struct ast_device *ast)
2059 {
2060 struct drm_device *dev = &ast->base;
2061 u32 temp;
2062 u8 reg;
2063
2064 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2065 if ((reg & AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2066 /* Clear bus lock condition */
2067 ast_patch_ahb_2500(ast->regs);
2068
2069 /* Disable watchdog */
2070 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2071 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2072
2073 /*
2074 * Reset USB port to patch USB unknown device issue
2075 * SCU90 is Multi-function Pin Control #5
2076 * [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2077 * port).
2078 * SCU94 is Multi-function Pin Control #6
2079 * [14:13]:= 1x:USB2.0 Host2 controller
2080 * SCU70 is Hardware Strap reg
2081 * [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2082 * [18]: 0(24)/1(48) MHz)
2083 * SCU7C is Write clear reg to SCU70
2084 * [23]:= write 1 and then SCU70[23] will be clear as 0b.
2085 */
2086 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2087 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2088 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2089 ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2090 mdelay(100);
2091 ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2092 }
2093 /* Modify eSPI reset pin */
2094 temp = ast_mindwm(ast, 0x1E6E2070);
2095 if (temp & 0x02000000)
2096 ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2097
2098 /* Slow down CPU/AHB CLK in VGA only mode */
2099 temp = ast_read32(ast, 0x12008);
2100 temp |= 0x73;
2101 ast_write32(ast, 0x12008, temp);
2102
2103 if (!ast_dram_init_2500(ast))
2104 drm_err(dev, "DRAM init failed !\n");
2105
2106 temp = ast_mindwm(ast, 0x1e6e2040);
2107 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2108 }
2109
2110 /* wait ready */
2111 do {
2112 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2113 } while ((reg & 0x40) == 0);
2114 }
2115