1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #define SWSMU_CODE_LAYER_L2
25 
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_7.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_7_ppt.h"
39 #include "smu_v13_0_7_pptable.h"
40 #include "smu_v13_0_7_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45 
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49 
50 /*
51  * DO NOT use these for err/warn/info/debug messages.
52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53  * They are more MGPU friendly.
54  */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59 
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61 
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 	FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
65 	FEATURE_MASK(FEATURE_DPM_UCLK_BIT)	 | \
66 	FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
67 	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
68 	FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	 | \
69 	FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70 
71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7   0x3b10028
72 
73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE	0x4000
74 
75 #define PP_OD_FEATURE_GFXCLK_FMIN			0
76 #define PP_OD_FEATURE_GFXCLK_FMAX			1
77 #define PP_OD_FEATURE_UCLK_FMIN				2
78 #define PP_OD_FEATURE_UCLK_FMAX				3
79 #define PP_OD_FEATURE_GFX_VF_CURVE			4
80 #define PP_OD_FEATURE_FAN_CURVE_TEMP			5
81 #define PP_OD_FEATURE_FAN_CURVE_PWM			6
82 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT		7
83 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET		8
84 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE		9
85 #define PP_OD_FEATURE_FAN_MINIMUM_PWM			10
86 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE		11
87 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP		12
88 
89 #define LINK_SPEED_MAX					3
90 
91 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
92 	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage,                 1),
93 	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion,               1),
94 	MSG_MAP(GetDriverIfVersion,		PPSMC_MSG_GetDriverIfVersion,          1),
95 	MSG_MAP(SetAllowedFeaturesMaskLow,	PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
96 	MSG_MAP(SetAllowedFeaturesMaskHigh,	PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
97 	MSG_MAP(EnableAllSmuFeatures,		PPSMC_MSG_EnableAllSmuFeatures,        0),
98 	MSG_MAP(DisableAllSmuFeatures,		PPSMC_MSG_DisableAllSmuFeatures,       0),
99 	MSG_MAP(EnableSmuFeaturesLow,		PPSMC_MSG_EnableSmuFeaturesLow,        1),
100 	MSG_MAP(EnableSmuFeaturesHigh,		PPSMC_MSG_EnableSmuFeaturesHigh,       1),
101 	MSG_MAP(DisableSmuFeaturesLow,		PPSMC_MSG_DisableSmuFeaturesLow,       1),
102 	MSG_MAP(DisableSmuFeaturesHigh,		PPSMC_MSG_DisableSmuFeaturesHigh,      1),
103 	MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
104 	MSG_MAP(GetEnabledSmuFeaturesHigh,	PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
105 	MSG_MAP(SetWorkloadMask,		PPSMC_MSG_SetWorkloadMask,             1),
106 	MSG_MAP(SetPptLimit,			PPSMC_MSG_SetPptLimit,                 0),
107 	MSG_MAP(SetDriverDramAddrHigh,		PPSMC_MSG_SetDriverDramAddrHigh,       1),
108 	MSG_MAP(SetDriverDramAddrLow,		PPSMC_MSG_SetDriverDramAddrLow,        1),
109 	MSG_MAP(SetToolsDramAddrHigh,		PPSMC_MSG_SetToolsDramAddrHigh,        0),
110 	MSG_MAP(SetToolsDramAddrLow,		PPSMC_MSG_SetToolsDramAddrLow,         0),
111 	MSG_MAP(TransferTableSmu2Dram,		PPSMC_MSG_TransferTableSmu2Dram,       1),
112 	MSG_MAP(TransferTableDram2Smu,		PPSMC_MSG_TransferTableDram2Smu,       0),
113 	MSG_MAP(UseDefaultPPTable,		PPSMC_MSG_UseDefaultPPTable,           0),
114 	MSG_MAP(RunDcBtc,			PPSMC_MSG_RunDcBtc,                    0),
115 	MSG_MAP(EnterBaco,			PPSMC_MSG_EnterBaco,                   0),
116 	MSG_MAP(ExitBaco,           PPSMC_MSG_ExitBaco,        			   0),
117 	MSG_MAP(SetSoftMinByFreq,		PPSMC_MSG_SetSoftMinByFreq,            1),
118 	MSG_MAP(SetSoftMaxByFreq,		PPSMC_MSG_SetSoftMaxByFreq,            1),
119 	MSG_MAP(SetHardMinByFreq,		PPSMC_MSG_SetHardMinByFreq,            1),
120 	MSG_MAP(SetHardMaxByFreq,		PPSMC_MSG_SetHardMaxByFreq,            0),
121 	MSG_MAP(GetMinDpmFreq,			PPSMC_MSG_GetMinDpmFreq,               1),
122 	MSG_MAP(GetMaxDpmFreq,			PPSMC_MSG_GetMaxDpmFreq,               1),
123 	MSG_MAP(GetDpmFreqByIndex,		PPSMC_MSG_GetDpmFreqByIndex,           1),
124 	MSG_MAP(PowerUpVcn,				PPSMC_MSG_PowerUpVcn,                  0),
125 	MSG_MAP(PowerDownVcn,			PPSMC_MSG_PowerDownVcn,                0),
126 	MSG_MAP(PowerUpJpeg,			PPSMC_MSG_PowerUpJpeg,                 0),
127 	MSG_MAP(PowerDownJpeg,			PPSMC_MSG_PowerDownJpeg,               0),
128 	MSG_MAP(GetDcModeMaxDpmFreq,		PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
129 	MSG_MAP(OverridePcieParameters,		PPSMC_MSG_OverridePcieParameters,      0),
130 	MSG_MAP(ReenableAcDcInterrupt,		PPSMC_MSG_ReenableAcDcInterrupt,       0),
131 	MSG_MAP(AllowIHHostInterrupt,		PPSMC_MSG_AllowIHHostInterrupt,       0),
132 	MSG_MAP(DramLogSetDramAddrHigh,		PPSMC_MSG_DramLogSetDramAddrHigh,      0),
133 	MSG_MAP(DramLogSetDramAddrLow,		PPSMC_MSG_DramLogSetDramAddrLow,       0),
134 	MSG_MAP(DramLogSetDramSize,		PPSMC_MSG_DramLogSetDramSize,          0),
135 	MSG_MAP(AllowGfxOff,			PPSMC_MSG_AllowGfxOff,                 0),
136 	MSG_MAP(DisallowGfxOff,			PPSMC_MSG_DisallowGfxOff,              0),
137 	MSG_MAP(Mode1Reset,             PPSMC_MSG_Mode1Reset,                  0),
138 	MSG_MAP(PrepareMp1ForUnload,		PPSMC_MSG_PrepareMp1ForUnload,         0),
139 	MSG_MAP(SetMGpuFanBoostLimitRpm,	PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
140 	MSG_MAP(DFCstateControl,		PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
141 	MSG_MAP(ArmD3,				PPSMC_MSG_ArmD3,                       0),
142 	MSG_MAP(AllowGpo,			PPSMC_MSG_SetGpoAllow,           0),
143 	MSG_MAP(GetPptLimit,			PPSMC_MSG_GetPptLimit,                 0),
144 	MSG_MAP(NotifyPowerSource,		PPSMC_MSG_NotifyPowerSource,           0),
145 	MSG_MAP(EnableUCLKShadow,		PPSMC_MSG_EnableUCLKShadow,            0),
146 };
147 
148 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
149 	CLK_MAP(GFXCLK,		PPCLK_GFXCLK),
150 	CLK_MAP(SCLK,		PPCLK_GFXCLK),
151 	CLK_MAP(SOCCLK,		PPCLK_SOCCLK),
152 	CLK_MAP(FCLK,		PPCLK_FCLK),
153 	CLK_MAP(UCLK,		PPCLK_UCLK),
154 	CLK_MAP(MCLK,		PPCLK_UCLK),
155 	CLK_MAP(VCLK,		PPCLK_VCLK_0),
156 	CLK_MAP(VCLK1,		PPCLK_VCLK_1),
157 	CLK_MAP(DCLK,		PPCLK_DCLK_0),
158 	CLK_MAP(DCLK1,		PPCLK_DCLK_1),
159 	CLK_MAP(DCEFCLK,	PPCLK_DCFCLK),
160 };
161 
162 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
163 	FEA_MAP(FW_DATA_READ),
164 	FEA_MAP(DPM_GFXCLK),
165 	FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
166 	FEA_MAP(DPM_UCLK),
167 	FEA_MAP(DPM_FCLK),
168 	FEA_MAP(DPM_SOCCLK),
169 	FEA_MAP(DPM_MP0CLK),
170 	FEA_MAP(DPM_LINK),
171 	FEA_MAP(DPM_DCN),
172 	FEA_MAP(VMEMP_SCALING),
173 	FEA_MAP(VDDIO_MEM_SCALING),
174 	FEA_MAP(DS_GFXCLK),
175 	FEA_MAP(DS_SOCCLK),
176 	FEA_MAP(DS_FCLK),
177 	FEA_MAP(DS_LCLK),
178 	FEA_MAP(DS_DCFCLK),
179 	FEA_MAP(DS_UCLK),
180 	FEA_MAP(GFX_ULV),
181 	FEA_MAP(FW_DSTATE),
182 	FEA_MAP(GFXOFF),
183 	FEA_MAP(BACO),
184 	FEA_MAP(MM_DPM),
185 	FEA_MAP(SOC_MPCLK_DS),
186 	FEA_MAP(BACO_MPCLK_DS),
187 	FEA_MAP(THROTTLERS),
188 	FEA_MAP(SMARTSHIFT),
189 	FEA_MAP(GTHR),
190 	FEA_MAP(ACDC),
191 	FEA_MAP(VR0HOT),
192 	FEA_MAP(FW_CTF),
193 	FEA_MAP(FAN_CONTROL),
194 	FEA_MAP(GFX_DCS),
195 	FEA_MAP(GFX_READ_MARGIN),
196 	FEA_MAP(LED_DISPLAY),
197 	FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
198 	FEA_MAP(OUT_OF_BAND_MONITOR),
199 	FEA_MAP(OPTIMIZED_VMIN),
200 	FEA_MAP(GFX_IMU),
201 	FEA_MAP(BOOT_TIME_CAL),
202 	FEA_MAP(GFX_PCC_DFLL),
203 	FEA_MAP(SOC_CG),
204 	FEA_MAP(DF_CSTATE),
205 	FEA_MAP(GFX_EDC),
206 	FEA_MAP(BOOT_POWER_OPT),
207 	FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
208 	FEA_MAP(DS_VCN),
209 	FEA_MAP(BACO_CG),
210 	FEA_MAP(MEM_TEMP_READ),
211 	FEA_MAP(ATHUB_MMHUB_PG),
212 	FEA_MAP(SOC_PCC),
213 	[SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
214 	[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
215 	[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
216 };
217 
218 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
219 	TAB_MAP(PPTABLE),
220 	TAB_MAP(WATERMARKS),
221 	TAB_MAP(AVFS_PSM_DEBUG),
222 	TAB_MAP(PMSTATUSLOG),
223 	TAB_MAP(SMU_METRICS),
224 	TAB_MAP(DRIVER_SMU_CONFIG),
225 	TAB_MAP(ACTIVITY_MONITOR_COEFF),
226 	[SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
227 	TAB_MAP(OVERDRIVE),
228 	TAB_MAP(WIFIBAND),
229 };
230 
231 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
232 	PWR_MAP(AC),
233 	PWR_MAP(DC),
234 };
235 
236 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
237 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
238 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
239 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
240 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
241 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
242 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
243 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
244 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D,		WORKLOAD_PPLIB_WINDOW_3D_BIT),
245 };
246 
247 static const uint8_t smu_v13_0_7_throttler_map[] = {
248 	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
249 	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
250 	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
251 	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
252 	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
253 	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
254 	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
255 	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
256 	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
257 	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
258 	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
259 	[THROTTLER_TEMP_VR_MEM0_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
260 	[THROTTLER_TEMP_VR_MEM1_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
261 	[THROTTLER_TEMP_LIQUID0_BIT]	= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
262 	[THROTTLER_TEMP_LIQUID1_BIT]	= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
263 	[THROTTLER_GFX_APCC_PLUS_BIT]	= (SMU_THROTTLER_APCC_BIT),
264 	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
265 };
266 
267 static int
smu_v13_0_7_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)268 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
269 				  uint32_t *feature_mask, uint32_t num)
270 {
271 	struct amdgpu_device *adev = smu->adev;
272 
273 	if (num > 2)
274 		return -EINVAL;
275 
276 	memset(feature_mask, 0, sizeof(uint32_t) * num);
277 
278 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
279 
280 	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
281 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
282 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
283 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
284 	}
285 
286 	if (adev->pm.pp_feature & PP_GFXOFF_MASK)
287 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
288 
289 	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
290 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
291 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
292 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
293 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
294 	}
295 
296 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
297 
298 	if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
299 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
300 
301 	if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
302 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
303 
304 	if (adev->pm.pp_feature & PP_ULV_MASK)
305 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
306 
307 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
308 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
309 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
310 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
311 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
312 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
313 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
314 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
315 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
316 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
317 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
318 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
319 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
320 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
321 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
322 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
323 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
324 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
325 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
326 
327 	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
328 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
329 
330 	if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
331 	    (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
332 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
333 
334 	return 0;
335 }
336 
smu_v13_0_7_check_powerplay_table(struct smu_context * smu)337 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
338 {
339 	struct smu_table_context *table_context = &smu->smu_table;
340 	struct smu_13_0_7_powerplay_table *powerplay_table =
341 		table_context->power_play_table;
342 	struct smu_baco_context *smu_baco = &smu->smu_baco;
343 	PPTable_t *smc_pptable = table_context->driver_pptable;
344 	BoardTable_t *BoardTable = &smc_pptable->BoardTable;
345 	const OverDriveLimits_t * const overdrive_upperlimits =
346 				&smc_pptable->SkuTable.OverDriveLimitsBasicMax;
347 	const OverDriveLimits_t * const overdrive_lowerlimits =
348 				&smc_pptable->SkuTable.OverDriveLimitsMin;
349 
350 	if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
351 		smu->dc_controlled_by_gpio = true;
352 
353 	if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO) {
354 		smu_baco->platform_support = true;
355 
356 		if ((powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
357 					&& (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
358 			smu_baco->maco_support = true;
359 	}
360 
361 	if (!overdrive_lowerlimits->FeatureCtrlMask ||
362 	    !overdrive_upperlimits->FeatureCtrlMask)
363 		smu->od_enabled = false;
364 
365 	table_context->thermal_controller_type =
366 		powerplay_table->thermal_controller_type;
367 
368 	/*
369 	 * Instead of having its own buffer space and get overdrive_table copied,
370 	 * smu->od_settings just points to the actual overdrive_table
371 	 */
372 	smu->od_settings = &powerplay_table->overdrive_table;
373 
374 	return 0;
375 }
376 
smu_v13_0_7_store_powerplay_table(struct smu_context * smu)377 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
378 {
379 	struct smu_table_context *table_context = &smu->smu_table;
380 	struct smu_13_0_7_powerplay_table *powerplay_table =
381 		table_context->power_play_table;
382 	struct amdgpu_device *adev = smu->adev;
383 
384 	if (adev->pdev->device == 0x51)
385 		powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
386 
387 	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
388 	       sizeof(PPTable_t));
389 
390 	return 0;
391 }
392 
smu_v13_0_7_check_fw_status(struct smu_context * smu)393 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
394 {
395 	struct amdgpu_device *adev = smu->adev;
396 	uint32_t mp1_fw_flags;
397 
398 	mp1_fw_flags = RREG32_PCIE(MP1_Public |
399 				   (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
400 
401 	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
402 			MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
403 		return 0;
404 
405 	return -EIO;
406 }
407 
408 #ifndef atom_smc_dpm_info_table_13_0_7
409 struct atom_smc_dpm_info_table_13_0_7 {
410 	struct atom_common_table_header table_header;
411 	BoardTable_t BoardTable;
412 };
413 #endif
414 
smu_v13_0_7_append_powerplay_table(struct smu_context * smu)415 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
416 {
417 	struct smu_table_context *table_context = &smu->smu_table;
418 
419 	PPTable_t *smc_pptable = table_context->driver_pptable;
420 
421 	struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
422 
423 	BoardTable_t *BoardTable = &smc_pptable->BoardTable;
424 
425 	int index, ret;
426 
427 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
428 	smc_dpm_info);
429 
430 	ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
431 			(uint8_t **)&smc_dpm_table);
432 	if (ret)
433 		return ret;
434 
435 	memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
436 
437 	return 0;
438 }
439 
smu_v13_0_7_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)440 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
441 					     void **table,
442 					     uint32_t *size)
443 {
444 	struct smu_table_context *smu_table = &smu->smu_table;
445 	void *combo_pptable = smu_table->combo_pptable;
446 	int ret = 0;
447 
448 	ret = smu_cmn_get_combo_pptable(smu);
449 	if (ret)
450 		return ret;
451 
452 	*table = combo_pptable;
453 	*size = sizeof(struct smu_13_0_7_powerplay_table);
454 
455 	return 0;
456 }
457 
smu_v13_0_7_setup_pptable(struct smu_context * smu)458 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
459 {
460 	struct smu_table_context *smu_table = &smu->smu_table;
461 	struct amdgpu_device *adev = smu->adev;
462 	int ret = 0;
463 
464 	/*
465 	 * With SCPM enabled, the pptable used will be signed. It cannot
466 	 * be used directly by driver. To get the raw pptable, we need to
467 	 * rely on the combo pptable(and its revelant SMU message).
468 	 */
469 	ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
470 						&smu_table->power_play_table,
471 						&smu_table->power_play_table_size);
472 	if (ret)
473 		return ret;
474 
475 	ret = smu_v13_0_7_store_powerplay_table(smu);
476 	if (ret)
477 		return ret;
478 
479 	/*
480 	 * With SCPM enabled, the operation below will be handled
481 	 * by PSP. Driver involvment is unnecessary and useless.
482 	 */
483 	if (!adev->scpm_enabled) {
484 		ret = smu_v13_0_7_append_powerplay_table(smu);
485 		if (ret)
486 			return ret;
487 	}
488 
489 	ret = smu_v13_0_7_check_powerplay_table(smu);
490 	if (ret)
491 		return ret;
492 
493 	return ret;
494 }
495 
smu_v13_0_7_tables_init(struct smu_context * smu)496 static int smu_v13_0_7_tables_init(struct smu_context *smu)
497 {
498 	struct smu_table_context *smu_table = &smu->smu_table;
499 	struct smu_table *tables = smu_table->tables;
500 
501 	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
502 		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 
504 	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
505 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
506 	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
507 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
508 	SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
509 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
510 	SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
511 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
512 	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
513 		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
514 	SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
515 		       sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
516 		       AMDGPU_GEM_DOMAIN_VRAM);
517 	SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
518 			PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
519 	SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
520 		       sizeof(WifiBandEntryTable_t), PAGE_SIZE,
521 		       AMDGPU_GEM_DOMAIN_VRAM);
522 
523 	smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
524 	if (!smu_table->metrics_table)
525 		goto err0_out;
526 	smu_table->metrics_time = 0;
527 
528 	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
529 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
530 	if (!smu_table->gpu_metrics_table)
531 		goto err1_out;
532 
533 	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
534 	if (!smu_table->watermarks_table)
535 		goto err2_out;
536 
537 	return 0;
538 
539 err2_out:
540 	kfree(smu_table->gpu_metrics_table);
541 err1_out:
542 	kfree(smu_table->metrics_table);
543 err0_out:
544 	return -ENOMEM;
545 }
546 
smu_v13_0_7_allocate_dpm_context(struct smu_context * smu)547 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
548 {
549 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
550 
551 	smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
552 				       GFP_KERNEL);
553 	if (!smu_dpm->dpm_context)
554 		return -ENOMEM;
555 
556 	smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
557 
558 	return 0;
559 }
560 
smu_v13_0_7_init_smc_tables(struct smu_context * smu)561 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
562 {
563 	int ret = 0;
564 
565 	ret = smu_v13_0_7_tables_init(smu);
566 	if (ret)
567 		return ret;
568 
569 	ret = smu_v13_0_7_allocate_dpm_context(smu);
570 	if (ret)
571 		return ret;
572 
573 	return smu_v13_0_init_smc_tables(smu);
574 }
575 
smu_v13_0_7_set_default_dpm_table(struct smu_context * smu)576 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
577 {
578 	struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
579 	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
580 	SkuTable_t *skutable = &driver_ppt->SkuTable;
581 	struct smu_13_0_dpm_table *dpm_table;
582 	struct smu_13_0_pcie_table *pcie_table;
583 	uint32_t link_level;
584 	int ret = 0;
585 
586 	/* socclk dpm table setup */
587 	dpm_table = &dpm_context->dpm_tables.soc_table;
588 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
589 		ret = smu_v13_0_set_single_dpm_table(smu,
590 						     SMU_SOCCLK,
591 						     dpm_table);
592 		if (ret)
593 			return ret;
594 	} else {
595 		dpm_table->count = 1;
596 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
597 		dpm_table->dpm_levels[0].enabled = true;
598 		dpm_table->min = dpm_table->dpm_levels[0].value;
599 		dpm_table->max = dpm_table->dpm_levels[0].value;
600 	}
601 
602 	/* gfxclk dpm table setup */
603 	dpm_table = &dpm_context->dpm_tables.gfx_table;
604 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
605 		ret = smu_v13_0_set_single_dpm_table(smu,
606 						     SMU_GFXCLK,
607 						     dpm_table);
608 		if (ret)
609 			return ret;
610 
611 		if (skutable->DriverReportedClocks.GameClockAc &&
612 			(dpm_table->dpm_levels[dpm_table->count - 1].value >
613 			skutable->DriverReportedClocks.GameClockAc)) {
614 			dpm_table->dpm_levels[dpm_table->count - 1].value =
615 				skutable->DriverReportedClocks.GameClockAc;
616 			dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
617 		}
618 	} else {
619 		dpm_table->count = 1;
620 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
621 		dpm_table->dpm_levels[0].enabled = true;
622 		dpm_table->min = dpm_table->dpm_levels[0].value;
623 		dpm_table->max = dpm_table->dpm_levels[0].value;
624 	}
625 
626 	/* uclk dpm table setup */
627 	dpm_table = &dpm_context->dpm_tables.uclk_table;
628 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
629 		ret = smu_v13_0_set_single_dpm_table(smu,
630 						     SMU_UCLK,
631 						     dpm_table);
632 		if (ret)
633 			return ret;
634 	} else {
635 		dpm_table->count = 1;
636 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
637 		dpm_table->dpm_levels[0].enabled = true;
638 		dpm_table->min = dpm_table->dpm_levels[0].value;
639 		dpm_table->max = dpm_table->dpm_levels[0].value;
640 	}
641 
642 	/* fclk dpm table setup */
643 	dpm_table = &dpm_context->dpm_tables.fclk_table;
644 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
645 		ret = smu_v13_0_set_single_dpm_table(smu,
646 						     SMU_FCLK,
647 						     dpm_table);
648 		if (ret)
649 			return ret;
650 	} else {
651 		dpm_table->count = 1;
652 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
653 		dpm_table->dpm_levels[0].enabled = true;
654 		dpm_table->min = dpm_table->dpm_levels[0].value;
655 		dpm_table->max = dpm_table->dpm_levels[0].value;
656 	}
657 
658 	/* vclk dpm table setup */
659 	dpm_table = &dpm_context->dpm_tables.vclk_table;
660 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
661 		ret = smu_v13_0_set_single_dpm_table(smu,
662 						     SMU_VCLK,
663 						     dpm_table);
664 		if (ret)
665 			return ret;
666 	} else {
667 		dpm_table->count = 1;
668 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
669 		dpm_table->dpm_levels[0].enabled = true;
670 		dpm_table->min = dpm_table->dpm_levels[0].value;
671 		dpm_table->max = dpm_table->dpm_levels[0].value;
672 	}
673 
674 	/* dclk dpm table setup */
675 	dpm_table = &dpm_context->dpm_tables.dclk_table;
676 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
677 		ret = smu_v13_0_set_single_dpm_table(smu,
678 						     SMU_DCLK,
679 						     dpm_table);
680 		if (ret)
681 			return ret;
682 	} else {
683 		dpm_table->count = 1;
684 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
685 		dpm_table->dpm_levels[0].enabled = true;
686 		dpm_table->min = dpm_table->dpm_levels[0].value;
687 		dpm_table->max = dpm_table->dpm_levels[0].value;
688 	}
689 
690 	/* lclk dpm table setup */
691 	pcie_table = &dpm_context->dpm_tables.pcie_table;
692 	pcie_table->num_of_link_levels = 0;
693 	for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
694 		if (!skutable->PcieGenSpeed[link_level] &&
695 		    !skutable->PcieLaneCount[link_level] &&
696 		    !skutable->LclkFreq[link_level])
697 			continue;
698 
699 		pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
700 					skutable->PcieGenSpeed[link_level];
701 		pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
702 					skutable->PcieLaneCount[link_level];
703 		pcie_table->clk_freq[pcie_table->num_of_link_levels] =
704 					skutable->LclkFreq[link_level];
705 		pcie_table->num_of_link_levels++;
706 	}
707 
708 	/* dcefclk dpm table setup */
709 	dpm_table = &dpm_context->dpm_tables.dcef_table;
710 	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
711 		ret = smu_v13_0_set_single_dpm_table(smu,
712 						     SMU_DCEFCLK,
713 						     dpm_table);
714 		if (ret)
715 			return ret;
716 	} else {
717 		dpm_table->count = 1;
718 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
719 		dpm_table->dpm_levels[0].enabled = true;
720 		dpm_table->min = dpm_table->dpm_levels[0].value;
721 		dpm_table->max = dpm_table->dpm_levels[0].value;
722 	}
723 
724 	return 0;
725 }
726 
smu_v13_0_7_is_dpm_running(struct smu_context * smu)727 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
728 {
729 	int ret = 0;
730 	uint64_t feature_enabled;
731 
732 	ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
733 	if (ret)
734 		return false;
735 
736 	return !!(feature_enabled & SMC_DPM_FEATURE);
737 }
738 
smu_v13_0_7_get_throttler_status(SmuMetrics_t * metrics)739 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
740 {
741 	uint32_t throttler_status = 0;
742 	int i;
743 
744 	for (i = 0; i < THROTTLER_COUNT; i++)
745 		throttler_status |=
746 			(metrics->ThrottlingPercentage[i] ? 1U << i : 0);
747 
748 	return throttler_status;
749 }
750 
751 #define SMU_13_0_7_BUSY_THRESHOLD	15
smu_v13_0_7_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)752 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
753 					    MetricsMember_t member,
754 					    uint32_t *value)
755 {
756 	struct smu_table_context *smu_table = &smu->smu_table;
757 	SmuMetrics_t *metrics =
758 		&(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
759 	int ret = 0;
760 
761 	ret = smu_cmn_get_metrics_table(smu,
762 					NULL,
763 					false);
764 	if (ret)
765 		return ret;
766 
767 	switch (member) {
768 	case METRICS_CURR_GFXCLK:
769 		*value = metrics->CurrClock[PPCLK_GFXCLK];
770 		break;
771 	case METRICS_CURR_SOCCLK:
772 		*value = metrics->CurrClock[PPCLK_SOCCLK];
773 		break;
774 	case METRICS_CURR_UCLK:
775 		*value = metrics->CurrClock[PPCLK_UCLK];
776 		break;
777 	case METRICS_CURR_VCLK:
778 		*value = metrics->CurrClock[PPCLK_VCLK_0];
779 		break;
780 	case METRICS_CURR_VCLK1:
781 		*value = metrics->CurrClock[PPCLK_VCLK_1];
782 		break;
783 	case METRICS_CURR_DCLK:
784 		*value = metrics->CurrClock[PPCLK_DCLK_0];
785 		break;
786 	case METRICS_CURR_DCLK1:
787 		*value = metrics->CurrClock[PPCLK_DCLK_1];
788 		break;
789 	case METRICS_CURR_FCLK:
790 		*value = metrics->CurrClock[PPCLK_FCLK];
791 		break;
792 	case METRICS_CURR_DCEFCLK:
793 		*value = metrics->CurrClock[PPCLK_DCFCLK];
794 		break;
795 	case METRICS_AVERAGE_GFXCLK:
796 		*value = metrics->AverageGfxclkFrequencyPreDs;
797 		break;
798 	case METRICS_AVERAGE_FCLK:
799 		if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
800 			*value = metrics->AverageFclkFrequencyPostDs;
801 		else
802 			*value = metrics->AverageFclkFrequencyPreDs;
803 		break;
804 	case METRICS_AVERAGE_UCLK:
805 		if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
806 			*value = metrics->AverageMemclkFrequencyPostDs;
807 		else
808 			*value = metrics->AverageMemclkFrequencyPreDs;
809 		break;
810 	case METRICS_AVERAGE_VCNACTIVITY:
811 		*value = max(metrics->Vcn0ActivityPercentage,
812 			     metrics->Vcn1ActivityPercentage);
813 		break;
814 	case METRICS_AVERAGE_VCLK:
815 		*value = metrics->AverageVclk0Frequency;
816 		break;
817 	case METRICS_AVERAGE_DCLK:
818 		*value = metrics->AverageDclk0Frequency;
819 		break;
820 	case METRICS_AVERAGE_VCLK1:
821 		*value = metrics->AverageVclk1Frequency;
822 		break;
823 	case METRICS_AVERAGE_DCLK1:
824 		*value = metrics->AverageDclk1Frequency;
825 		break;
826 	case METRICS_AVERAGE_GFXACTIVITY:
827 		*value = metrics->AverageGfxActivity;
828 		break;
829 	case METRICS_AVERAGE_MEMACTIVITY:
830 		*value = metrics->AverageUclkActivity;
831 		break;
832 	case METRICS_AVERAGE_SOCKETPOWER:
833 		*value = metrics->AverageSocketPower << 8;
834 		break;
835 	case METRICS_TEMPERATURE_EDGE:
836 		*value = metrics->AvgTemperature[TEMP_EDGE] *
837 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
838 		break;
839 	case METRICS_TEMPERATURE_HOTSPOT:
840 		*value = metrics->AvgTemperature[TEMP_HOTSPOT] *
841 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
842 		break;
843 	case METRICS_TEMPERATURE_MEM:
844 		*value = metrics->AvgTemperature[TEMP_MEM] *
845 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
846 		break;
847 	case METRICS_TEMPERATURE_VRGFX:
848 		*value = metrics->AvgTemperature[TEMP_VR_GFX] *
849 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
850 		break;
851 	case METRICS_TEMPERATURE_VRSOC:
852 		*value = metrics->AvgTemperature[TEMP_VR_SOC] *
853 			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
854 		break;
855 	case METRICS_THROTTLER_STATUS:
856 		*value = smu_v13_0_7_get_throttler_status(metrics);
857 		break;
858 	case METRICS_CURR_FANSPEED:
859 		*value = metrics->AvgFanRpm;
860 		break;
861 	case METRICS_CURR_FANPWM:
862 		*value = metrics->AvgFanPwm;
863 		break;
864 	case METRICS_VOLTAGE_VDDGFX:
865 		*value = metrics->AvgVoltage[SVI_PLANE_GFX];
866 		break;
867 	case METRICS_PCIE_RATE:
868 		*value = metrics->PcieRate;
869 		break;
870 	case METRICS_PCIE_WIDTH:
871 		*value = metrics->PcieWidth;
872 		break;
873 	default:
874 		*value = UINT_MAX;
875 		break;
876 	}
877 
878 	return ret;
879 }
880 
smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)881 static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu,
882 					     enum smu_clk_type clk_type,
883 					     uint32_t *min,
884 					     uint32_t *max)
885 {
886 	struct smu_13_0_dpm_context *dpm_context =
887 		smu->smu_dpm.dpm_context;
888 	struct smu_13_0_dpm_table *dpm_table;
889 
890 	switch (clk_type) {
891 	case SMU_MCLK:
892 	case SMU_UCLK:
893 		/* uclk dpm table */
894 		dpm_table = &dpm_context->dpm_tables.uclk_table;
895 		break;
896 	case SMU_GFXCLK:
897 	case SMU_SCLK:
898 		/* gfxclk dpm table */
899 		dpm_table = &dpm_context->dpm_tables.gfx_table;
900 		break;
901 	case SMU_SOCCLK:
902 		/* socclk dpm table */
903 		dpm_table = &dpm_context->dpm_tables.soc_table;
904 		break;
905 	case SMU_FCLK:
906 		/* fclk dpm table */
907 		dpm_table = &dpm_context->dpm_tables.fclk_table;
908 		break;
909 	case SMU_VCLK:
910 	case SMU_VCLK1:
911 		/* vclk dpm table */
912 		dpm_table = &dpm_context->dpm_tables.vclk_table;
913 		break;
914 	case SMU_DCLK:
915 	case SMU_DCLK1:
916 		/* dclk dpm table */
917 		dpm_table = &dpm_context->dpm_tables.dclk_table;
918 		break;
919 	default:
920 		dev_err(smu->adev->dev, "Unsupported clock type!\n");
921 		return -EINVAL;
922 	}
923 
924 	if (min)
925 		*min = dpm_table->min;
926 	if (max)
927 		*max = dpm_table->max;
928 
929 	return 0;
930 }
931 
smu_v13_0_7_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)932 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
933 				   enum amd_pp_sensors sensor,
934 				   void *data,
935 				   uint32_t *size)
936 {
937 	struct smu_table_context *table_context = &smu->smu_table;
938 	PPTable_t *smc_pptable = table_context->driver_pptable;
939 	int ret = 0;
940 
941 	switch (sensor) {
942 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
943 		*(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
944 		*size = 4;
945 		break;
946 	case AMDGPU_PP_SENSOR_MEM_LOAD:
947 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
948 						       METRICS_AVERAGE_MEMACTIVITY,
949 						       (uint32_t *)data);
950 		*size = 4;
951 		break;
952 	case AMDGPU_PP_SENSOR_GPU_LOAD:
953 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
954 						       METRICS_AVERAGE_GFXACTIVITY,
955 						       (uint32_t *)data);
956 		*size = 4;
957 		break;
958 	case AMDGPU_PP_SENSOR_VCN_LOAD:
959 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
960 						       METRICS_AVERAGE_VCNACTIVITY,
961 						       (uint32_t *)data);
962 		*size = 4;
963 		break;
964 	case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
965 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
966 						       METRICS_AVERAGE_SOCKETPOWER,
967 						       (uint32_t *)data);
968 		*size = 4;
969 		break;
970 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
971 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
972 						       METRICS_TEMPERATURE_HOTSPOT,
973 						       (uint32_t *)data);
974 		*size = 4;
975 		break;
976 	case AMDGPU_PP_SENSOR_EDGE_TEMP:
977 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
978 						       METRICS_TEMPERATURE_EDGE,
979 						       (uint32_t *)data);
980 		*size = 4;
981 		break;
982 	case AMDGPU_PP_SENSOR_MEM_TEMP:
983 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
984 						       METRICS_TEMPERATURE_MEM,
985 						       (uint32_t *)data);
986 		*size = 4;
987 		break;
988 	case AMDGPU_PP_SENSOR_GFX_MCLK:
989 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
990 						       METRICS_CURR_UCLK,
991 						       (uint32_t *)data);
992 		*(uint32_t *)data *= 100;
993 		*size = 4;
994 		break;
995 	case AMDGPU_PP_SENSOR_GFX_SCLK:
996 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
997 						       METRICS_AVERAGE_GFXCLK,
998 						       (uint32_t *)data);
999 		*(uint32_t *)data *= 100;
1000 		*size = 4;
1001 		break;
1002 	case AMDGPU_PP_SENSOR_VDDGFX:
1003 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
1004 						       METRICS_VOLTAGE_VDDGFX,
1005 						       (uint32_t *)data);
1006 		*size = 4;
1007 		break;
1008 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1009 	default:
1010 		ret = -EOPNOTSUPP;
1011 		break;
1012 	}
1013 
1014 	return ret;
1015 }
1016 
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1017 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
1018 						     enum smu_clk_type clk_type,
1019 						     uint32_t *value)
1020 {
1021 	MetricsMember_t member_type;
1022 	int clk_id = 0;
1023 
1024 	clk_id = smu_cmn_to_asic_specific_index(smu,
1025 						CMN2ASIC_MAPPING_CLK,
1026 						clk_type);
1027 	if (clk_id < 0)
1028 		return -EINVAL;
1029 
1030 	switch (clk_id) {
1031 	case PPCLK_GFXCLK:
1032 		member_type = METRICS_AVERAGE_GFXCLK;
1033 		break;
1034 	case PPCLK_UCLK:
1035 		member_type = METRICS_CURR_UCLK;
1036 		break;
1037 	case PPCLK_FCLK:
1038 		member_type = METRICS_CURR_FCLK;
1039 		break;
1040 	case PPCLK_SOCCLK:
1041 		member_type = METRICS_CURR_SOCCLK;
1042 		break;
1043 	case PPCLK_VCLK_0:
1044 		member_type = METRICS_CURR_VCLK;
1045 		break;
1046 	case PPCLK_DCLK_0:
1047 		member_type = METRICS_CURR_DCLK;
1048 		break;
1049 	case PPCLK_VCLK_1:
1050 		member_type = METRICS_CURR_VCLK1;
1051 		break;
1052 	case PPCLK_DCLK_1:
1053 		member_type = METRICS_CURR_DCLK1;
1054 		break;
1055 	case PPCLK_DCFCLK:
1056 		member_type = METRICS_CURR_DCEFCLK;
1057 		break;
1058 	default:
1059 		return -EINVAL;
1060 	}
1061 
1062 	return smu_v13_0_7_get_smu_metrics_data(smu,
1063 						member_type,
1064 						value);
1065 }
1066 
smu_v13_0_7_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1067 static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu,
1068 						int od_feature_bit)
1069 {
1070 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1071 	const OverDriveLimits_t * const overdrive_upperlimits =
1072 				&pptable->SkuTable.OverDriveLimitsBasicMax;
1073 
1074 	return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1075 }
1076 
smu_v13_0_7_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1077 static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu,
1078 					      int od_feature_bit,
1079 					      int32_t *min,
1080 					      int32_t *max)
1081 {
1082 	PPTable_t *pptable = smu->smu_table.driver_pptable;
1083 	const OverDriveLimits_t * const overdrive_upperlimits =
1084 				&pptable->SkuTable.OverDriveLimitsBasicMax;
1085 	const OverDriveLimits_t * const overdrive_lowerlimits =
1086 				&pptable->SkuTable.OverDriveLimitsMin;
1087 	int32_t od_min_setting, od_max_setting;
1088 
1089 	switch (od_feature_bit) {
1090 	case PP_OD_FEATURE_GFXCLK_FMIN:
1091 		od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1092 		od_max_setting = overdrive_upperlimits->GfxclkFmin;
1093 		break;
1094 	case PP_OD_FEATURE_GFXCLK_FMAX:
1095 		od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1096 		od_max_setting = overdrive_upperlimits->GfxclkFmax;
1097 		break;
1098 	case PP_OD_FEATURE_UCLK_FMIN:
1099 		od_min_setting = overdrive_lowerlimits->UclkFmin;
1100 		od_max_setting = overdrive_upperlimits->UclkFmin;
1101 		break;
1102 	case PP_OD_FEATURE_UCLK_FMAX:
1103 		od_min_setting = overdrive_lowerlimits->UclkFmax;
1104 		od_max_setting = overdrive_upperlimits->UclkFmax;
1105 		break;
1106 	case PP_OD_FEATURE_GFX_VF_CURVE:
1107 		od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1108 		od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1109 		break;
1110 	case PP_OD_FEATURE_FAN_CURVE_TEMP:
1111 		od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1112 		od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1113 		break;
1114 	case PP_OD_FEATURE_FAN_CURVE_PWM:
1115 		od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1116 		od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1117 		break;
1118 	case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1119 		od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1120 		od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1121 		break;
1122 	case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1123 		od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1124 		od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1125 		break;
1126 	case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1127 		od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1128 		od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1129 		break;
1130 	case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1131 		od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1132 		od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1133 		break;
1134 	case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1135 		od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1136 		od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1137 		break;
1138 	case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1139 		od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1140 		od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1141 		break;
1142 	default:
1143 		od_min_setting = od_max_setting = INT_MAX;
1144 		break;
1145 	}
1146 
1147 	if (min)
1148 		*min = od_min_setting;
1149 	if (max)
1150 		*max = od_max_setting;
1151 }
1152 
smu_v13_0_7_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1153 static void smu_v13_0_7_dump_od_table(struct smu_context *smu,
1154 				      OverDriveTableExternal_t *od_table)
1155 {
1156 	struct amdgpu_device *adev = smu->adev;
1157 
1158 	dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1159 						     od_table->OverDriveTable.GfxclkFmax);
1160 	dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1161 						   od_table->OverDriveTable.UclkFmax);
1162 }
1163 
smu_v13_0_7_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1164 static int smu_v13_0_7_get_overdrive_table(struct smu_context *smu,
1165 					   OverDriveTableExternal_t *od_table)
1166 {
1167 	int ret = 0;
1168 
1169 	ret = smu_cmn_update_table(smu,
1170 				   SMU_TABLE_OVERDRIVE,
1171 				   0,
1172 				   (void *)od_table,
1173 				   false);
1174 	if (ret)
1175 		dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1176 
1177 	return ret;
1178 }
1179 
smu_v13_0_7_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1180 static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu,
1181 					      OverDriveTableExternal_t *od_table)
1182 {
1183 	int ret = 0;
1184 
1185 	ret = smu_cmn_update_table(smu,
1186 				   SMU_TABLE_OVERDRIVE,
1187 				   0,
1188 				   (void *)od_table,
1189 				   true);
1190 	if (ret)
1191 		dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1192 
1193 	return ret;
1194 }
1195 
smu_v13_0_7_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1196 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
1197 					enum smu_clk_type clk_type,
1198 					char *buf)
1199 {
1200 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1201 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1202 	OverDriveTableExternal_t *od_table =
1203 		(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1204 	struct smu_13_0_dpm_table *single_dpm_table;
1205 	struct smu_13_0_pcie_table *pcie_table;
1206 	uint32_t gen_speed, lane_width;
1207 	int i, curr_freq, size = 0;
1208 	int32_t min_value, max_value;
1209 	int ret = 0;
1210 
1211 	smu_cmn_get_sysfs_buf(&buf, &size);
1212 
1213 	if (amdgpu_ras_intr_triggered()) {
1214 		size += sysfs_emit_at(buf, size, "unavailable\n");
1215 		return size;
1216 	}
1217 
1218 	switch (clk_type) {
1219 	case SMU_SCLK:
1220 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1221 		break;
1222 	case SMU_MCLK:
1223 		single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1224 		break;
1225 	case SMU_SOCCLK:
1226 		single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1227 		break;
1228 	case SMU_FCLK:
1229 		single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1230 		break;
1231 	case SMU_VCLK:
1232 	case SMU_VCLK1:
1233 		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1234 		break;
1235 	case SMU_DCLK:
1236 	case SMU_DCLK1:
1237 		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1238 		break;
1239 	case SMU_DCEFCLK:
1240 		single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1241 		break;
1242 	default:
1243 		break;
1244 	}
1245 
1246 	switch (clk_type) {
1247 	case SMU_SCLK:
1248 	case SMU_MCLK:
1249 	case SMU_SOCCLK:
1250 	case SMU_FCLK:
1251 	case SMU_VCLK:
1252 	case SMU_VCLK1:
1253 	case SMU_DCLK:
1254 	case SMU_DCLK1:
1255 	case SMU_DCEFCLK:
1256 		ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1257 		if (ret) {
1258 			dev_err(smu->adev->dev, "Failed to get current clock freq!");
1259 			return ret;
1260 		}
1261 
1262 		if (single_dpm_table->is_fine_grained) {
1263 			/*
1264 			 * For fine grained dpms, there are only two dpm levels:
1265 			 *   - level 0 -> min clock freq
1266 			 *   - level 1 -> max clock freq
1267 			 * And the current clock frequency can be any value between them.
1268 			 * So, if the current clock frequency is not at level 0 or level 1,
1269 			 * we will fake it as three dpm levels:
1270 			 *   - level 0 -> min clock freq
1271 			 *   - level 1 -> current actual clock freq
1272 			 *   - level 2 -> max clock freq
1273 			 */
1274 			if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1275 			     (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1276 				size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1277 						single_dpm_table->dpm_levels[0].value);
1278 				size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1279 						curr_freq);
1280 				size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1281 						single_dpm_table->dpm_levels[1].value);
1282 			} else {
1283 				size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1284 						single_dpm_table->dpm_levels[0].value,
1285 						single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1286 				size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1287 						single_dpm_table->dpm_levels[1].value,
1288 						single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1289 			}
1290 		} else {
1291 			for (i = 0; i < single_dpm_table->count; i++)
1292 				size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1293 						i, single_dpm_table->dpm_levels[i].value,
1294 						single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1295 		}
1296 		break;
1297 	case SMU_PCIE:
1298 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
1299 						       METRICS_PCIE_RATE,
1300 						       &gen_speed);
1301 		if (ret)
1302 			return ret;
1303 
1304 		ret = smu_v13_0_7_get_smu_metrics_data(smu,
1305 						       METRICS_PCIE_WIDTH,
1306 						       &lane_width);
1307 		if (ret)
1308 			return ret;
1309 
1310 		pcie_table = &(dpm_context->dpm_tables.pcie_table);
1311 		for (i = 0; i < pcie_table->num_of_link_levels; i++)
1312 			size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1313 					(pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1314 					(pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1315 					(pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1316 					(pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1317 					(pcie_table->pcie_lane[i] == 1) ? "x1" :
1318 					(pcie_table->pcie_lane[i] == 2) ? "x2" :
1319 					(pcie_table->pcie_lane[i] == 3) ? "x4" :
1320 					(pcie_table->pcie_lane[i] == 4) ? "x8" :
1321 					(pcie_table->pcie_lane[i] == 5) ? "x12" :
1322 					(pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1323 					pcie_table->clk_freq[i],
1324 					(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1325 					(lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1326 					"*" : "");
1327 		break;
1328 
1329 	case SMU_OD_SCLK:
1330 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1331 							 PP_OD_FEATURE_GFXCLK_BIT))
1332 			break;
1333 
1334 		size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1335 		size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1336 					od_table->OverDriveTable.GfxclkFmin,
1337 					od_table->OverDriveTable.GfxclkFmax);
1338 		break;
1339 
1340 	case SMU_OD_MCLK:
1341 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1342 							 PP_OD_FEATURE_UCLK_BIT))
1343 			break;
1344 
1345 		size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1346 		size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1347 					od_table->OverDriveTable.UclkFmin,
1348 					od_table->OverDriveTable.UclkFmax);
1349 		break;
1350 
1351 	case SMU_OD_VDDGFX_OFFSET:
1352 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1353 							 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1354 			break;
1355 
1356 		size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1357 		size += sysfs_emit_at(buf, size, "%dmV\n",
1358 				      od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1359 		break;
1360 
1361 	case SMU_OD_FAN_CURVE:
1362 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1363 							 PP_OD_FEATURE_FAN_CURVE_BIT))
1364 			break;
1365 
1366 		size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1367 		for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1368 			size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1369 						i,
1370 						(int)od_table->OverDriveTable.FanLinearTempPoints[i],
1371 						(int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1372 
1373 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1374 		smu_v13_0_7_get_od_setting_limits(smu,
1375 						  PP_OD_FEATURE_FAN_CURVE_TEMP,
1376 						  &min_value,
1377 						  &max_value);
1378 		size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1379 				      min_value, max_value);
1380 
1381 		smu_v13_0_7_get_od_setting_limits(smu,
1382 						  PP_OD_FEATURE_FAN_CURVE_PWM,
1383 						  &min_value,
1384 						  &max_value);
1385 		size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1386 				      min_value, max_value);
1387 
1388 		break;
1389 
1390 	case SMU_OD_ACOUSTIC_LIMIT:
1391 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1392 							 PP_OD_FEATURE_FAN_CURVE_BIT))
1393 			break;
1394 
1395 		size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1396 		size += sysfs_emit_at(buf, size, "%d\n",
1397 					(int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1398 
1399 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1400 		smu_v13_0_7_get_od_setting_limits(smu,
1401 						  PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1402 						  &min_value,
1403 						  &max_value);
1404 		size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1405 				      min_value, max_value);
1406 		break;
1407 
1408 	case SMU_OD_ACOUSTIC_TARGET:
1409 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1410 							 PP_OD_FEATURE_FAN_CURVE_BIT))
1411 			break;
1412 
1413 		size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1414 		size += sysfs_emit_at(buf, size, "%d\n",
1415 					(int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1416 
1417 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1418 		smu_v13_0_7_get_od_setting_limits(smu,
1419 						  PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1420 						  &min_value,
1421 						  &max_value);
1422 		size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1423 				      min_value, max_value);
1424 		break;
1425 
1426 	case SMU_OD_FAN_TARGET_TEMPERATURE:
1427 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1428 							 PP_OD_FEATURE_FAN_CURVE_BIT))
1429 			break;
1430 
1431 		size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1432 		size += sysfs_emit_at(buf, size, "%d\n",
1433 					(int)od_table->OverDriveTable.FanTargetTemperature);
1434 
1435 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1436 		smu_v13_0_7_get_od_setting_limits(smu,
1437 						  PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1438 						  &min_value,
1439 						  &max_value);
1440 		size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1441 				      min_value, max_value);
1442 		break;
1443 
1444 	case SMU_OD_FAN_MINIMUM_PWM:
1445 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1446 							 PP_OD_FEATURE_FAN_CURVE_BIT))
1447 			break;
1448 
1449 		size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1450 		size += sysfs_emit_at(buf, size, "%d\n",
1451 					(int)od_table->OverDriveTable.FanMinimumPwm);
1452 
1453 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1454 		smu_v13_0_7_get_od_setting_limits(smu,
1455 						  PP_OD_FEATURE_FAN_MINIMUM_PWM,
1456 						  &min_value,
1457 						  &max_value);
1458 		size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1459 				      min_value, max_value);
1460 		break;
1461 
1462 	case SMU_OD_FAN_ZERO_RPM_ENABLE:
1463 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1464 							 PP_OD_FEATURE_ZERO_FAN_BIT))
1465 			break;
1466 
1467 		size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1468 		size += sysfs_emit_at(buf, size, "%d\n",
1469 					(int)od_table->OverDriveTable.FanZeroRpmEnable);
1470 
1471 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1472 		smu_v13_0_7_get_od_setting_limits(smu,
1473 						  PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1474 						  &min_value,
1475 						  &max_value);
1476 		size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1477 				      min_value, max_value);
1478 		break;
1479 
1480 	case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1481 		if (!smu_v13_0_7_is_od_feature_supported(smu,
1482 							 PP_OD_FEATURE_ZERO_FAN_BIT))
1483 			break;
1484 
1485 		size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1486 		size += sysfs_emit_at(buf, size, "%d\n",
1487 					(int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1488 
1489 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1490 		smu_v13_0_7_get_od_setting_limits(smu,
1491 						  PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1492 						  &min_value,
1493 						  &max_value);
1494 		size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1495 				      min_value, max_value);
1496 		break;
1497 
1498 	case SMU_OD_RANGE:
1499 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1500 		    !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1501 		    !smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1502 			break;
1503 
1504 		size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1505 
1506 		if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1507 			smu_v13_0_7_get_od_setting_limits(smu,
1508 							  PP_OD_FEATURE_GFXCLK_FMIN,
1509 							  &min_value,
1510 							  NULL);
1511 			smu_v13_0_7_get_od_setting_limits(smu,
1512 							  PP_OD_FEATURE_GFXCLK_FMAX,
1513 							  NULL,
1514 							  &max_value);
1515 			size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1516 					      min_value, max_value);
1517 		}
1518 
1519 		if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1520 			smu_v13_0_7_get_od_setting_limits(smu,
1521 							  PP_OD_FEATURE_UCLK_FMIN,
1522 							  &min_value,
1523 							  NULL);
1524 			smu_v13_0_7_get_od_setting_limits(smu,
1525 							  PP_OD_FEATURE_UCLK_FMAX,
1526 							  NULL,
1527 							  &max_value);
1528 			size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1529 					      min_value, max_value);
1530 		}
1531 
1532 		if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1533 			smu_v13_0_7_get_od_setting_limits(smu,
1534 							  PP_OD_FEATURE_GFX_VF_CURVE,
1535 							  &min_value,
1536 							  &max_value);
1537 			size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1538 					      min_value, max_value);
1539 		}
1540 		break;
1541 
1542 	default:
1543 		break;
1544 	}
1545 
1546 	return size;
1547 }
1548 
smu_v13_0_7_od_restore_table_single(struct smu_context * smu,long input)1549 static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input)
1550 {
1551 	struct smu_table_context *table_context = &smu->smu_table;
1552 	OverDriveTableExternal_t *boot_overdrive_table =
1553 		(OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1554 	OverDriveTableExternal_t *od_table =
1555 		(OverDriveTableExternal_t *)table_context->overdrive_table;
1556 	struct amdgpu_device *adev = smu->adev;
1557 	int i;
1558 
1559 	switch (input) {
1560 	case PP_OD_EDIT_FAN_CURVE:
1561 		for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1562 			od_table->OverDriveTable.FanLinearTempPoints[i] =
1563 					boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1564 			od_table->OverDriveTable.FanLinearPwmPoints[i] =
1565 					boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1566 		}
1567 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1568 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1569 		break;
1570 	case PP_OD_EDIT_ACOUSTIC_LIMIT:
1571 		od_table->OverDriveTable.AcousticLimitRpmThreshold =
1572 					boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1573 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1574 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1575 		break;
1576 	case PP_OD_EDIT_ACOUSTIC_TARGET:
1577 		od_table->OverDriveTable.AcousticTargetRpmThreshold =
1578 					boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1579 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1580 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1581 		break;
1582 	case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1583 		od_table->OverDriveTable.FanTargetTemperature =
1584 					boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1585 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1586 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1587 		break;
1588 	case PP_OD_EDIT_FAN_MINIMUM_PWM:
1589 		od_table->OverDriveTable.FanMinimumPwm =
1590 					boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1591 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1592 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1593 		break;
1594 	case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1595 		od_table->OverDriveTable.FanZeroRpmEnable =
1596 					boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1597 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1598 		break;
1599 	case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1600 		od_table->OverDriveTable.FanZeroRpmStopTemp =
1601 					boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1602 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1603 		break;
1604 	default:
1605 		dev_info(adev->dev, "Invalid table index: %ld\n", input);
1606 		return -EINVAL;
1607 	}
1608 
1609 	return 0;
1610 }
1611 
smu_v13_0_7_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1612 static int smu_v13_0_7_od_edit_dpm_table(struct smu_context *smu,
1613 					 enum PP_OD_DPM_TABLE_COMMAND type,
1614 					 long input[],
1615 					 uint32_t size)
1616 {
1617 	struct smu_table_context *table_context = &smu->smu_table;
1618 	OverDriveTableExternal_t *od_table =
1619 		(OverDriveTableExternal_t *)table_context->overdrive_table;
1620 	struct amdgpu_device *adev = smu->adev;
1621 	uint32_t offset_of_voltageoffset;
1622 	int32_t minimum, maximum;
1623 	uint32_t feature_ctrlmask;
1624 	int i, ret = 0;
1625 
1626 	switch (type) {
1627 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
1628 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1629 			dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1630 			return -ENOTSUPP;
1631 		}
1632 
1633 		for (i = 0; i < size; i += 2) {
1634 			if (i + 2 > size) {
1635 				dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1636 				return -EINVAL;
1637 			}
1638 
1639 			switch (input[i]) {
1640 			case 0:
1641 				smu_v13_0_7_get_od_setting_limits(smu,
1642 								  PP_OD_FEATURE_GFXCLK_FMIN,
1643 								  &minimum,
1644 								  &maximum);
1645 				if (input[i + 1] < minimum ||
1646 				    input[i + 1] > maximum) {
1647 					dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1648 						input[i + 1], minimum, maximum);
1649 					return -EINVAL;
1650 				}
1651 
1652 				od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1653 				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1654 				break;
1655 
1656 			case 1:
1657 				smu_v13_0_7_get_od_setting_limits(smu,
1658 								  PP_OD_FEATURE_GFXCLK_FMAX,
1659 								  &minimum,
1660 								  &maximum);
1661 				if (input[i + 1] < minimum ||
1662 				    input[i + 1] > maximum) {
1663 					dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1664 						input[i + 1], minimum, maximum);
1665 					return -EINVAL;
1666 				}
1667 
1668 				od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1669 				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1670 				break;
1671 
1672 			default:
1673 				dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1674 				dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1675 				return -EINVAL;
1676 			}
1677 		}
1678 
1679 		if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1680 			dev_err(adev->dev,
1681 				"Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1682 				(uint32_t)od_table->OverDriveTable.GfxclkFmin,
1683 				(uint32_t)od_table->OverDriveTable.GfxclkFmax);
1684 			return -EINVAL;
1685 		}
1686 		break;
1687 
1688 	case PP_OD_EDIT_MCLK_VDDC_TABLE:
1689 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1690 			dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1691 			return -ENOTSUPP;
1692 		}
1693 
1694 		for (i = 0; i < size; i += 2) {
1695 			if (i + 2 > size) {
1696 				dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1697 				return -EINVAL;
1698 			}
1699 
1700 			switch (input[i]) {
1701 			case 0:
1702 				smu_v13_0_7_get_od_setting_limits(smu,
1703 								  PP_OD_FEATURE_UCLK_FMIN,
1704 								  &minimum,
1705 								  &maximum);
1706 				if (input[i + 1] < minimum ||
1707 				    input[i + 1] > maximum) {
1708 					dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1709 						input[i + 1], minimum, maximum);
1710 					return -EINVAL;
1711 				}
1712 
1713 				od_table->OverDriveTable.UclkFmin = input[i + 1];
1714 				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1715 				break;
1716 
1717 			case 1:
1718 				smu_v13_0_7_get_od_setting_limits(smu,
1719 								  PP_OD_FEATURE_UCLK_FMAX,
1720 								  &minimum,
1721 								  &maximum);
1722 				if (input[i + 1] < minimum ||
1723 				    input[i + 1] > maximum) {
1724 					dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1725 						input[i + 1], minimum, maximum);
1726 					return -EINVAL;
1727 				}
1728 
1729 				od_table->OverDriveTable.UclkFmax = input[i + 1];
1730 				od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1731 				break;
1732 
1733 			default:
1734 				dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1735 				dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1736 				return -EINVAL;
1737 			}
1738 		}
1739 
1740 		if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1741 			dev_err(adev->dev,
1742 				"Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1743 				(uint32_t)od_table->OverDriveTable.UclkFmin,
1744 				(uint32_t)od_table->OverDriveTable.UclkFmax);
1745 			return -EINVAL;
1746 		}
1747 		break;
1748 
1749 	case PP_OD_EDIT_VDDGFX_OFFSET:
1750 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1751 			dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1752 			return -ENOTSUPP;
1753 		}
1754 
1755 		smu_v13_0_7_get_od_setting_limits(smu,
1756 						  PP_OD_FEATURE_GFX_VF_CURVE,
1757 						  &minimum,
1758 						  &maximum);
1759 		if (input[0] < minimum ||
1760 		    input[0] > maximum) {
1761 			dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1762 				 input[0], minimum, maximum);
1763 			return -EINVAL;
1764 		}
1765 
1766 		for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1767 			od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1768 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1769 		break;
1770 
1771 	case PP_OD_EDIT_FAN_CURVE:
1772 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1773 			dev_warn(adev->dev, "Fan curve setting not supported!\n");
1774 			return -ENOTSUPP;
1775 		}
1776 
1777 		if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1778 		    input[0] < 0)
1779 			return -EINVAL;
1780 
1781 		smu_v13_0_7_get_od_setting_limits(smu,
1782 						  PP_OD_FEATURE_FAN_CURVE_TEMP,
1783 						  &minimum,
1784 						  &maximum);
1785 		if (input[1] < minimum ||
1786 		    input[1] > maximum) {
1787 			dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1788 				 input[1], minimum, maximum);
1789 			return -EINVAL;
1790 		}
1791 
1792 		smu_v13_0_7_get_od_setting_limits(smu,
1793 						  PP_OD_FEATURE_FAN_CURVE_PWM,
1794 						  &minimum,
1795 						  &maximum);
1796 		if (input[2] < minimum ||
1797 		    input[2] > maximum) {
1798 			dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1799 				 input[2], minimum, maximum);
1800 			return -EINVAL;
1801 		}
1802 
1803 		od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1804 		od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1805 		od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1806 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1807 		break;
1808 
1809 	case PP_OD_EDIT_ACOUSTIC_LIMIT:
1810 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1811 			dev_warn(adev->dev, "Fan curve setting not supported!\n");
1812 			return -ENOTSUPP;
1813 		}
1814 
1815 		smu_v13_0_7_get_od_setting_limits(smu,
1816 						  PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1817 						  &minimum,
1818 						  &maximum);
1819 		if (input[0] < minimum ||
1820 		    input[0] > maximum) {
1821 			dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1822 				 input[0], minimum, maximum);
1823 			return -EINVAL;
1824 		}
1825 
1826 		od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1827 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1828 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1829 		break;
1830 
1831 	case PP_OD_EDIT_ACOUSTIC_TARGET:
1832 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1833 			dev_warn(adev->dev, "Fan curve setting not supported!\n");
1834 			return -ENOTSUPP;
1835 		}
1836 
1837 		smu_v13_0_7_get_od_setting_limits(smu,
1838 						  PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1839 						  &minimum,
1840 						  &maximum);
1841 		if (input[0] < minimum ||
1842 		    input[0] > maximum) {
1843 			dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1844 				 input[0], minimum, maximum);
1845 			return -EINVAL;
1846 		}
1847 
1848 		od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1849 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1850 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1851 		break;
1852 
1853 	case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1854 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1855 			dev_warn(adev->dev, "Fan curve setting not supported!\n");
1856 			return -ENOTSUPP;
1857 		}
1858 
1859 		smu_v13_0_7_get_od_setting_limits(smu,
1860 						  PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1861 						  &minimum,
1862 						  &maximum);
1863 		if (input[0] < minimum ||
1864 		    input[0] > maximum) {
1865 			dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1866 				 input[0], minimum, maximum);
1867 			return -EINVAL;
1868 		}
1869 
1870 		od_table->OverDriveTable.FanTargetTemperature = input[0];
1871 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1872 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1873 		break;
1874 
1875 	case PP_OD_EDIT_FAN_MINIMUM_PWM:
1876 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1877 			dev_warn(adev->dev, "Fan curve setting not supported!\n");
1878 			return -ENOTSUPP;
1879 		}
1880 
1881 		smu_v13_0_7_get_od_setting_limits(smu,
1882 						  PP_OD_FEATURE_FAN_MINIMUM_PWM,
1883 						  &minimum,
1884 						  &maximum);
1885 		if (input[0] < minimum ||
1886 		    input[0] > maximum) {
1887 			dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1888 				 input[0], minimum, maximum);
1889 			return -EINVAL;
1890 		}
1891 
1892 		od_table->OverDriveTable.FanMinimumPwm = input[0];
1893 		od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1894 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1895 		break;
1896 
1897 	case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1898 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1899 			dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1900 			return -ENOTSUPP;
1901 		}
1902 
1903 		smu_v13_0_7_get_od_setting_limits(smu,
1904 						  PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1905 						  &minimum,
1906 						  &maximum);
1907 		if (input[0] < minimum ||
1908 		    input[0] > maximum) {
1909 			dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1910 				 input[0], minimum, maximum);
1911 			return -EINVAL;
1912 		}
1913 
1914 		od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1915 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1916 		break;
1917 
1918 	case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1919 		if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1920 			dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1921 			return -ENOTSUPP;
1922 		}
1923 
1924 		smu_v13_0_7_get_od_setting_limits(smu,
1925 						  PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1926 						  &minimum,
1927 						  &maximum);
1928 		if (input[0] < minimum ||
1929 		    input[0] > maximum) {
1930 			dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1931 				 input[0], minimum, maximum);
1932 			return -EINVAL;
1933 		}
1934 
1935 		od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1936 		od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1937 		break;
1938 
1939 	case PP_OD_RESTORE_DEFAULT_TABLE:
1940 		if (size == 1) {
1941 			ret = smu_v13_0_7_od_restore_table_single(smu, input[0]);
1942 			if (ret)
1943 				return ret;
1944 		} else {
1945 			feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1946 			memcpy(od_table,
1947 					table_context->boot_overdrive_table,
1948 					sizeof(OverDriveTableExternal_t));
1949 			od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1950 		}
1951 		fallthrough;
1952 
1953 	case PP_OD_COMMIT_DPM_TABLE:
1954 		/*
1955 		 * The member below instructs PMFW the settings focused in
1956 		 * this single operation.
1957 		 * `uint32_t FeatureCtrlMask;`
1958 		 * It does not contain actual informations about user's custom
1959 		 * settings. Thus we do not cache it.
1960 		 */
1961 		offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1962 		if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1963 			   table_context->user_overdrive_table + offset_of_voltageoffset,
1964 			   sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1965 			smu_v13_0_7_dump_od_table(smu, od_table);
1966 
1967 			ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
1968 			if (ret) {
1969 				dev_err(adev->dev, "Failed to upload overdrive table!\n");
1970 				return ret;
1971 			}
1972 
1973 			od_table->OverDriveTable.FeatureCtrlMask = 0;
1974 			memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1975 			       (u8 *)od_table + offset_of_voltageoffset,
1976 			       sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1977 
1978 			if (!memcmp(table_context->user_overdrive_table,
1979 				    table_context->boot_overdrive_table,
1980 				    sizeof(OverDriveTableExternal_t)))
1981 				smu->user_dpm_profile.user_od = false;
1982 			else
1983 				smu->user_dpm_profile.user_od = true;
1984 		}
1985 		break;
1986 
1987 	default:
1988 		return -ENOSYS;
1989 	}
1990 
1991 	return ret;
1992 }
1993 
smu_v13_0_7_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1994 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1995 					enum smu_clk_type clk_type,
1996 					uint32_t mask)
1997 {
1998 	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1999 	struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2000 	struct smu_13_0_dpm_table *single_dpm_table;
2001 	uint32_t soft_min_level, soft_max_level;
2002 	uint32_t min_freq, max_freq;
2003 	int ret = 0;
2004 
2005 	soft_min_level = mask ? (ffs(mask) - 1) : 0;
2006 	soft_max_level = mask ? (fls(mask) - 1) : 0;
2007 
2008 	switch (clk_type) {
2009 	case SMU_GFXCLK:
2010 	case SMU_SCLK:
2011 		single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
2012 		break;
2013 	case SMU_MCLK:
2014 	case SMU_UCLK:
2015 		single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
2016 		break;
2017 	case SMU_SOCCLK:
2018 		single_dpm_table = &(dpm_context->dpm_tables.soc_table);
2019 		break;
2020 	case SMU_FCLK:
2021 		single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
2022 		break;
2023 	case SMU_VCLK:
2024 	case SMU_VCLK1:
2025 		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
2026 		break;
2027 	case SMU_DCLK:
2028 	case SMU_DCLK1:
2029 		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
2030 		break;
2031 	default:
2032 		break;
2033 	}
2034 
2035 	switch (clk_type) {
2036 	case SMU_GFXCLK:
2037 	case SMU_SCLK:
2038 	case SMU_MCLK:
2039 	case SMU_UCLK:
2040 	case SMU_SOCCLK:
2041 	case SMU_FCLK:
2042 	case SMU_VCLK:
2043 	case SMU_VCLK1:
2044 	case SMU_DCLK:
2045 	case SMU_DCLK1:
2046 		if (single_dpm_table->is_fine_grained) {
2047 			/* There is only 2 levels for fine grained DPM */
2048 			soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2049 			soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2050 		} else {
2051 			if ((soft_max_level >= single_dpm_table->count) ||
2052 			    (soft_min_level >= single_dpm_table->count))
2053 				return -EINVAL;
2054 		}
2055 
2056 		min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2057 		max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2058 
2059 		ret = smu_v13_0_set_soft_freq_limited_range(smu,
2060 							    clk_type,
2061 							    min_freq,
2062 							    max_freq,
2063 							    false);
2064 		break;
2065 	case SMU_DCEFCLK:
2066 	case SMU_PCIE:
2067 	default:
2068 		break;
2069 	}
2070 
2071 	return ret;
2072 }
2073 
2074 static const struct smu_temperature_range smu13_thermal_policy[] = {
2075 	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2076 	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2077 };
2078 
smu_v13_0_7_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2079 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
2080 						     struct smu_temperature_range *range)
2081 {
2082 	struct smu_table_context *table_context = &smu->smu_table;
2083 	struct smu_13_0_7_powerplay_table *powerplay_table =
2084 		table_context->power_play_table;
2085 	PPTable_t *pptable = smu->smu_table.driver_pptable;
2086 
2087 	if (!range)
2088 		return -EINVAL;
2089 
2090 	memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2091 
2092 	range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2093 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2094 	range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2095 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2096 	range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2097 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2098 	range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2099 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2100 	range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2101 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2102 	range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2103 		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2104 	range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2105 	range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2106 
2107 	return 0;
2108 }
2109 
smu_v13_0_7_get_gpu_metrics(struct smu_context * smu,void ** table)2110 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
2111 					   void **table)
2112 {
2113 	struct smu_table_context *smu_table = &smu->smu_table;
2114 	struct gpu_metrics_v1_3 *gpu_metrics =
2115 		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2116 	SmuMetricsExternal_t metrics_ext;
2117 	SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2118 	int ret = 0;
2119 
2120 	ret = smu_cmn_get_metrics_table(smu,
2121 					&metrics_ext,
2122 					true);
2123 	if (ret)
2124 		return ret;
2125 
2126 	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2127 
2128 	gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2129 	gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2130 	gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2131 	gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2132 	gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2133 	gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2134 					     metrics->AvgTemperature[TEMP_VR_MEM1]);
2135 
2136 	gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2137 	gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2138 	gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2139 					       metrics->Vcn1ActivityPercentage);
2140 
2141 	gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2142 	gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2143 
2144 	if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2145 		gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2146 	else
2147 		gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2148 
2149 	if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
2150 		gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2151 	else
2152 		gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2153 
2154 	gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2155 	gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2156 	gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2157 	gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2158 
2159 	gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
2160 	gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2161 	gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2162 	gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2163 	gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2164 	gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2165 	gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2166 
2167 	gpu_metrics->throttle_status =
2168 			smu_v13_0_7_get_throttler_status(metrics);
2169 	gpu_metrics->indep_throttle_status =
2170 			smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2171 							   smu_v13_0_7_throttler_map);
2172 
2173 	gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2174 
2175 	gpu_metrics->pcie_link_width = metrics->PcieWidth;
2176 	if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2177 		gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2178 	else
2179 		gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2180 
2181 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2182 
2183 	gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2184 	gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2185 	gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2186 
2187 	*table = (void *)gpu_metrics;
2188 
2189 	return sizeof(struct gpu_metrics_v1_3);
2190 }
2191 
smu_v13_0_7_set_supported_od_feature_mask(struct smu_context * smu)2192 static void smu_v13_0_7_set_supported_od_feature_mask(struct smu_context *smu)
2193 {
2194 	struct amdgpu_device *adev = smu->adev;
2195 
2196 	if (smu_v13_0_7_is_od_feature_supported(smu,
2197 						PP_OD_FEATURE_FAN_CURVE_BIT))
2198 		adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2199 					    OD_OPS_SUPPORT_FAN_CURVE_SET |
2200 					    OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2201 					    OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2202 					    OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2203 					    OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2204 					    OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2205 					    OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2206 					    OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2207 					    OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2208 					    OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2209 					    OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2210 					    OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2211 					    OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2212 }
2213 
smu_v13_0_7_set_default_od_settings(struct smu_context * smu)2214 static int smu_v13_0_7_set_default_od_settings(struct smu_context *smu)
2215 {
2216 	OverDriveTableExternal_t *od_table =
2217 		(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2218 	OverDriveTableExternal_t *boot_od_table =
2219 		(OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2220 	OverDriveTableExternal_t *user_od_table =
2221 		(OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2222 	OverDriveTableExternal_t user_od_table_bak;
2223 	int ret = 0;
2224 	int i;
2225 
2226 	ret = smu_v13_0_7_get_overdrive_table(smu, boot_od_table);
2227 	if (ret)
2228 		return ret;
2229 
2230 	smu_v13_0_7_dump_od_table(smu, boot_od_table);
2231 
2232 	memcpy(od_table,
2233 	       boot_od_table,
2234 	       sizeof(OverDriveTableExternal_t));
2235 
2236 	/*
2237 	 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2238 	 * but we have to preserve user defined values in "user_od_table".
2239 	 */
2240 	if (!smu->adev->in_suspend) {
2241 		memcpy(user_od_table,
2242 		       boot_od_table,
2243 		       sizeof(OverDriveTableExternal_t));
2244 		smu->user_dpm_profile.user_od = false;
2245 	} else if (smu->user_dpm_profile.user_od) {
2246 		memcpy(&user_od_table_bak,
2247 		       user_od_table,
2248 		       sizeof(OverDriveTableExternal_t));
2249 		memcpy(user_od_table,
2250 		       boot_od_table,
2251 		       sizeof(OverDriveTableExternal_t));
2252 		user_od_table->OverDriveTable.GfxclkFmin =
2253 				user_od_table_bak.OverDriveTable.GfxclkFmin;
2254 		user_od_table->OverDriveTable.GfxclkFmax =
2255 				user_od_table_bak.OverDriveTable.GfxclkFmax;
2256 		user_od_table->OverDriveTable.UclkFmin =
2257 				user_od_table_bak.OverDriveTable.UclkFmin;
2258 		user_od_table->OverDriveTable.UclkFmax =
2259 				user_od_table_bak.OverDriveTable.UclkFmax;
2260 		for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2261 			user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2262 				user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2263 		for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2264 			user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2265 				user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2266 			user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2267 				user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2268 		}
2269 		user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2270 			user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2271 		user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2272 			user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2273 		user_od_table->OverDriveTable.FanTargetTemperature =
2274 			user_od_table_bak.OverDriveTable.FanTargetTemperature;
2275 		user_od_table->OverDriveTable.FanMinimumPwm =
2276 			user_od_table_bak.OverDriveTable.FanMinimumPwm;
2277 		user_od_table->OverDriveTable.FanZeroRpmEnable =
2278 			user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2279 		user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2280 			user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2281 	}
2282 
2283 	smu_v13_0_7_set_supported_od_feature_mask(smu);
2284 
2285 	return 0;
2286 }
2287 
smu_v13_0_7_restore_user_od_settings(struct smu_context * smu)2288 static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu)
2289 {
2290 	struct smu_table_context *table_context = &smu->smu_table;
2291 	OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2292 	OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2293 	int res;
2294 
2295 	user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2296 							BIT(PP_OD_FEATURE_UCLK_BIT) |
2297 							BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2298 							BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2299 	res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table);
2300 	user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2301 	if (res == 0)
2302 		memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2303 
2304 	return res;
2305 }
2306 
smu_v13_0_7_populate_umd_state_clk(struct smu_context * smu)2307 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
2308 {
2309 	struct smu_13_0_dpm_context *dpm_context =
2310 				smu->smu_dpm.dpm_context;
2311 	struct smu_13_0_dpm_table *gfx_table =
2312 				&dpm_context->dpm_tables.gfx_table;
2313 	struct smu_13_0_dpm_table *mem_table =
2314 				&dpm_context->dpm_tables.uclk_table;
2315 	struct smu_13_0_dpm_table *soc_table =
2316 				&dpm_context->dpm_tables.soc_table;
2317 	struct smu_13_0_dpm_table *vclk_table =
2318 				&dpm_context->dpm_tables.vclk_table;
2319 	struct smu_13_0_dpm_table *dclk_table =
2320 				&dpm_context->dpm_tables.dclk_table;
2321 	struct smu_13_0_dpm_table *fclk_table =
2322 				&dpm_context->dpm_tables.fclk_table;
2323 	struct smu_umd_pstate_table *pstate_table =
2324 				&smu->pstate_table;
2325 	struct smu_table_context *table_context = &smu->smu_table;
2326 	PPTable_t *pptable = table_context->driver_pptable;
2327 	DriverReportedClocks_t driver_clocks =
2328 		pptable->SkuTable.DriverReportedClocks;
2329 
2330 	pstate_table->gfxclk_pstate.min = gfx_table->min;
2331 	if (driver_clocks.GameClockAc &&
2332 		(driver_clocks.GameClockAc < gfx_table->max))
2333 		pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2334 	else
2335 		pstate_table->gfxclk_pstate.peak = gfx_table->max;
2336 
2337 	pstate_table->uclk_pstate.min = mem_table->min;
2338 	pstate_table->uclk_pstate.peak = mem_table->max;
2339 
2340 	pstate_table->socclk_pstate.min = soc_table->min;
2341 	pstate_table->socclk_pstate.peak = soc_table->max;
2342 
2343 	pstate_table->vclk_pstate.min = vclk_table->min;
2344 	pstate_table->vclk_pstate.peak = vclk_table->max;
2345 
2346 	pstate_table->dclk_pstate.min = dclk_table->min;
2347 	pstate_table->dclk_pstate.peak = dclk_table->max;
2348 
2349 	pstate_table->fclk_pstate.min = fclk_table->min;
2350 	pstate_table->fclk_pstate.peak = fclk_table->max;
2351 
2352 	if (driver_clocks.BaseClockAc &&
2353 		driver_clocks.BaseClockAc < gfx_table->max)
2354 		pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2355 	else
2356 		pstate_table->gfxclk_pstate.standard = gfx_table->max;
2357 	pstate_table->uclk_pstate.standard = mem_table->max;
2358 	pstate_table->socclk_pstate.standard = soc_table->min;
2359 	pstate_table->vclk_pstate.standard = vclk_table->min;
2360 	pstate_table->dclk_pstate.standard = dclk_table->min;
2361 	pstate_table->fclk_pstate.standard = fclk_table->min;
2362 
2363 	return 0;
2364 }
2365 
smu_v13_0_7_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2366 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
2367 					 uint32_t *speed)
2368 {
2369 	int ret;
2370 
2371 	if (!speed)
2372 		return -EINVAL;
2373 
2374 	ret = smu_v13_0_7_get_smu_metrics_data(smu,
2375 					       METRICS_CURR_FANPWM,
2376 					       speed);
2377 	if (ret) {
2378 		dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2379 		return ret;
2380 	}
2381 
2382 	/* Convert the PMFW output which is in percent to pwm(255) based */
2383 	*speed = min(*speed * 255 / 100, (uint32_t)255);
2384 
2385 	return 0;
2386 }
2387 
smu_v13_0_7_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2388 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
2389 					 uint32_t *speed)
2390 {
2391 	if (!speed)
2392 		return -EINVAL;
2393 
2394 	return smu_v13_0_7_get_smu_metrics_data(smu,
2395 						METRICS_CURR_FANSPEED,
2396 						speed);
2397 }
2398 
smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context * smu)2399 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
2400 {
2401 	struct smu_table_context *table_context = &smu->smu_table;
2402 	PPTable_t *pptable = table_context->driver_pptable;
2403 	SkuTable_t *skutable = &pptable->SkuTable;
2404 
2405 	/*
2406 	 * Skip the MGpuFanBoost setting for those ASICs
2407 	 * which do not support it
2408 	 */
2409 	if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2410 		return 0;
2411 
2412 	return smu_cmn_send_smc_msg_with_param(smu,
2413 					       SMU_MSG_SetMGpuFanBoostLimitRpm,
2414 					       0,
2415 					       NULL);
2416 }
2417 
smu_v13_0_7_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2418 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
2419 						uint32_t *current_power_limit,
2420 						uint32_t *default_power_limit,
2421 						uint32_t *max_power_limit,
2422 						uint32_t *min_power_limit)
2423 {
2424 	struct smu_table_context *table_context = &smu->smu_table;
2425 	struct smu_13_0_7_powerplay_table *powerplay_table =
2426 		(struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
2427 	PPTable_t *pptable = table_context->driver_pptable;
2428 	SkuTable_t *skutable = &pptable->SkuTable;
2429 	uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2430 	uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2431 
2432 	if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2433 		power_limit = smu->adev->pm.ac_power ?
2434 			      skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2435 			      skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2436 
2437 	if (current_power_limit)
2438 		*current_power_limit = power_limit;
2439 	if (default_power_limit)
2440 		*default_power_limit = power_limit;
2441 
2442 	if (powerplay_table) {
2443 		if (smu->od_enabled &&
2444 				(smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT))) {
2445 			od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2446 			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2447 		} else if (smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2448 			od_percent_upper = 0;
2449 			od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
2450 		}
2451 	}
2452 
2453 	dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2454 					od_percent_upper, od_percent_lower, power_limit);
2455 
2456 	if (max_power_limit) {
2457 		*max_power_limit = msg_limit * (100 + od_percent_upper);
2458 		*max_power_limit /= 100;
2459 	}
2460 
2461 	if (min_power_limit) {
2462 		*min_power_limit = power_limit * (100 - od_percent_lower);
2463 		*min_power_limit /= 100;
2464 	}
2465 
2466 	return 0;
2467 }
2468 
smu_v13_0_7_get_power_profile_mode(struct smu_context * smu,char * buf)2469 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
2470 {
2471 	DpmActivityMonitorCoeffIntExternal_t *activity_monitor_external;
2472 	uint32_t i, j, size = 0;
2473 	int16_t workload_type = 0;
2474 	int result = 0;
2475 
2476 	if (!buf)
2477 		return -EINVAL;
2478 
2479 	activity_monitor_external = kcalloc(PP_SMC_POWER_PROFILE_COUNT,
2480 					    sizeof(*activity_monitor_external),
2481 					    GFP_KERNEL);
2482 	if (!activity_monitor_external)
2483 		return -ENOMEM;
2484 
2485 	size += sysfs_emit_at(buf, size, "                              ");
2486 	for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
2487 		size += sysfs_emit_at(buf, size, "%d %-14s%s", i, amdgpu_pp_profile_name[i],
2488 			(i == smu->power_profile_mode) ? "* " : "  ");
2489 
2490 	size += sysfs_emit_at(buf, size, "\n");
2491 
2492 	for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
2493 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2494 		workload_type = smu_cmn_to_asic_specific_index(smu,
2495 							       CMN2ASIC_MAPPING_WORKLOAD,
2496 							       i);
2497 		if (workload_type == -ENOTSUPP)
2498 			continue;
2499 		else if (workload_type < 0) {
2500 			result = -EINVAL;
2501 			goto out;
2502 		}
2503 
2504 		result = smu_cmn_update_table(smu,
2505 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
2506 					  (void *)(&activity_monitor_external[i]), false);
2507 		if (result) {
2508 			dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2509 			goto out;
2510 		}
2511 	}
2512 
2513 #define PRINT_DPM_MONITOR(field)									\
2514 do {													\
2515 	size += sysfs_emit_at(buf, size, "%-30s", #field);						\
2516 	for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++)						\
2517 		size += sysfs_emit_at(buf, size, "%-18d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field);		\
2518 	size += sysfs_emit_at(buf, size, "\n");								\
2519 } while (0)
2520 
2521 	PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
2522 	PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
2523 	PRINT_DPM_MONITOR(Gfx_FPS);
2524 	PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
2525 	PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
2526 	PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
2527 	PRINT_DPM_MONITOR(Gfx_BoosterFreq);
2528 	PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
2529 	PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
2530 	PRINT_DPM_MONITOR(Fclk_FPS);
2531 	PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
2532 	PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
2533 	PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
2534 	PRINT_DPM_MONITOR(Fclk_BoosterFreq);
2535 #undef PRINT_DPM_MONITOR
2536 
2537 	result = size;
2538 out:
2539 	kfree(activity_monitor_external);
2540 	return result;
2541 }
2542 
2543 #define SMU_13_0_7_CUSTOM_PARAMS_COUNT 8
2544 #define SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT 2
2545 #define SMU_13_0_7_CUSTOM_PARAMS_SIZE (SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_7_CUSTOM_PARAMS_COUNT * sizeof(long))
2546 
smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2547 static int smu_v13_0_7_set_power_profile_mode_coeff(struct smu_context *smu,
2548 						    long *input)
2549 {
2550 
2551 	DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2552 	DpmActivityMonitorCoeffInt_t *activity_monitor =
2553 		&(activity_monitor_external.DpmActivityMonitorCoeffInt);
2554 	int ret, idx;
2555 
2556 	ret = smu_cmn_update_table(smu,
2557 				   SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2558 				   (void *)(&activity_monitor_external), false);
2559 	if (ret) {
2560 		dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2561 		return ret;
2562 	}
2563 
2564 	idx = 0 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2565 	if (input[idx]) {
2566 		/* Gfxclk */
2567 		activity_monitor->Gfx_ActiveHystLimit = input[idx + 1];
2568 		activity_monitor->Gfx_IdleHystLimit = input[idx + 2];
2569 		activity_monitor->Gfx_FPS = input[idx + 3];
2570 		activity_monitor->Gfx_MinActiveFreqType = input[idx + 4];
2571 		activity_monitor->Gfx_BoosterFreqType = input[idx + 5];
2572 		activity_monitor->Gfx_MinActiveFreq = input[idx + 6];
2573 		activity_monitor->Gfx_BoosterFreq = input[idx + 7];
2574 	}
2575 	idx = 1 * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2576 	if (input[idx]) {
2577 		/* Fclk */
2578 		activity_monitor->Fclk_ActiveHystLimit = input[idx + 1];
2579 		activity_monitor->Fclk_IdleHystLimit = input[idx + 2];
2580 		activity_monitor->Fclk_FPS = input[idx + 3];
2581 		activity_monitor->Fclk_MinActiveFreqType = input[idx + 4];
2582 		activity_monitor->Fclk_BoosterFreqType = input[idx + 5];
2583 		activity_monitor->Fclk_MinActiveFreq = input[idx + 6];
2584 		activity_monitor->Fclk_BoosterFreq = input[idx + 7];
2585 	}
2586 
2587 	ret = smu_cmn_update_table(smu,
2588 				   SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2589 				   (void *)(&activity_monitor_external), true);
2590 	if (ret) {
2591 		dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2592 		return ret;
2593 	}
2594 
2595 	return ret;
2596 }
2597 
smu_v13_0_7_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2598 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu,
2599 					      u32 workload_mask,
2600 					      long *custom_params,
2601 					      u32 custom_params_max_idx)
2602 {
2603 	u32 backend_workload_mask = 0;
2604 	int ret, idx = -1, i;
2605 
2606 	smu_cmn_get_backend_workload_mask(smu, workload_mask,
2607 					  &backend_workload_mask);
2608 
2609 	if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2610 		if (!smu->custom_profile_params) {
2611 			smu->custom_profile_params =
2612 				kzalloc(SMU_13_0_7_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2613 			if (!smu->custom_profile_params)
2614 				return -ENOMEM;
2615 		}
2616 		if (custom_params && custom_params_max_idx) {
2617 			if (custom_params_max_idx != SMU_13_0_7_CUSTOM_PARAMS_COUNT)
2618 				return -EINVAL;
2619 			if (custom_params[0] >= SMU_13_0_7_CUSTOM_PARAMS_CLOCK_COUNT)
2620 				return -EINVAL;
2621 			idx = custom_params[0] * SMU_13_0_7_CUSTOM_PARAMS_COUNT;
2622 			smu->custom_profile_params[idx] = 1;
2623 			for (i = 1; i < custom_params_max_idx; i++)
2624 				smu->custom_profile_params[idx + i] = custom_params[i];
2625 		}
2626 		ret = smu_v13_0_7_set_power_profile_mode_coeff(smu,
2627 							       smu->custom_profile_params);
2628 		if (ret) {
2629 			if (idx != -1)
2630 				smu->custom_profile_params[idx] = 0;
2631 			return ret;
2632 		}
2633 	} else if (smu->custom_profile_params) {
2634 		memset(smu->custom_profile_params, 0, SMU_13_0_7_CUSTOM_PARAMS_SIZE);
2635 	}
2636 
2637 	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2638 					      backend_workload_mask, NULL);
2639 
2640 	if (ret) {
2641 		dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2642 			workload_mask);
2643 		if (idx != -1)
2644 			smu->custom_profile_params[idx] = 0;
2645 		return ret;
2646 	}
2647 
2648 	return ret;
2649 }
2650 
smu_v13_0_7_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2651 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
2652 				     enum pp_mp1_state mp1_state)
2653 {
2654 	int ret;
2655 
2656 	switch (mp1_state) {
2657 	case PP_MP1_STATE_UNLOAD:
2658 		ret = smu_cmn_set_mp1_state(smu, mp1_state);
2659 		break;
2660 	default:
2661 		/* Ignore others */
2662 		ret = 0;
2663 	}
2664 
2665 	return ret;
2666 }
2667 
smu_v13_0_7_is_mode1_reset_supported(struct smu_context * smu)2668 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
2669 {
2670 	struct amdgpu_device *adev = smu->adev;
2671 
2672 	/* SRIOV does not support SMU mode1 reset */
2673 	if (amdgpu_sriov_vf(adev))
2674 		return false;
2675 
2676 	return true;
2677 }
2678 
smu_v13_0_7_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2679 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
2680 				     enum pp_df_cstate state)
2681 {
2682 	return smu_cmn_send_smc_msg_with_param(smu,
2683 					       SMU_MSG_DFCstateControl,
2684 					       state,
2685 					       NULL);
2686 }
2687 
smu_v13_0_7_wbrf_support_check(struct smu_context * smu)2688 static bool smu_v13_0_7_wbrf_support_check(struct smu_context *smu)
2689 {
2690 	return smu->smc_fw_version > 0x00524600;
2691 }
2692 
smu_v13_0_7_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)2693 static int smu_v13_0_7_set_power_limit(struct smu_context *smu,
2694 				       enum smu_ppt_limit_type limit_type,
2695 				       uint32_t limit)
2696 {
2697 	PPTable_t *pptable = smu->smu_table.driver_pptable;
2698 	SkuTable_t *skutable = &pptable->SkuTable;
2699 	uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2700 	struct smu_table_context *table_context = &smu->smu_table;
2701 	OverDriveTableExternal_t *od_table =
2702 		(OverDriveTableExternal_t *)table_context->overdrive_table;
2703 	int ret = 0;
2704 
2705 	if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2706 		return -EINVAL;
2707 
2708 	if (limit <= msg_limit) {
2709 		if (smu->current_power_limit > msg_limit) {
2710 			od_table->OverDriveTable.Ppt = 0;
2711 			od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2712 
2713 			ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2714 			if (ret) {
2715 				dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2716 				return ret;
2717 			}
2718 		}
2719 		return smu_v13_0_set_power_limit(smu, limit_type, limit);
2720 	} else if (smu->od_enabled) {
2721 		ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
2722 		if (ret)
2723 			return ret;
2724 
2725 		od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
2726 		od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
2727 
2728 		ret = smu_v13_0_7_upload_overdrive_table(smu, od_table);
2729 		if (ret) {
2730 		  dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
2731 		  return ret;
2732 		}
2733 
2734 		smu->current_power_limit = limit;
2735 	} else {
2736 		return -EINVAL;
2737 	}
2738 
2739 	return 0;
2740 }
2741 
2742 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
2743 	.get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
2744 	.set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
2745 	.is_dpm_running = smu_v13_0_7_is_dpm_running,
2746 	.init_microcode = smu_v13_0_init_microcode,
2747 	.load_microcode = smu_v13_0_load_microcode,
2748 	.fini_microcode = smu_v13_0_fini_microcode,
2749 	.init_smc_tables = smu_v13_0_7_init_smc_tables,
2750 	.fini_smc_tables = smu_v13_0_fini_smc_tables,
2751 	.init_power = smu_v13_0_init_power,
2752 	.fini_power = smu_v13_0_fini_power,
2753 	.check_fw_status = smu_v13_0_7_check_fw_status,
2754 	.setup_pptable = smu_v13_0_7_setup_pptable,
2755 	.check_fw_version = smu_v13_0_check_fw_version,
2756 	.write_pptable = smu_cmn_write_pptable,
2757 	.set_driver_table_location = smu_v13_0_set_driver_table_location,
2758 	.system_features_control = smu_v13_0_system_features_control,
2759 	.set_allowed_mask = smu_v13_0_set_allowed_mask,
2760 	.get_enabled_mask = smu_cmn_get_enabled_mask,
2761 	.dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
2762 	.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
2763 	.init_pptable_microcode = smu_v13_0_init_pptable_microcode,
2764 	.populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
2765 	.get_dpm_ultimate_freq = smu_v13_0_7_get_dpm_ultimate_freq,
2766 	.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
2767 	.read_sensor = smu_v13_0_7_read_sensor,
2768 	.feature_is_enabled = smu_cmn_feature_is_enabled,
2769 	.print_clk_levels = smu_v13_0_7_print_clk_levels,
2770 	.force_clk_levels = smu_v13_0_7_force_clk_levels,
2771 	.update_pcie_parameters = smu_v13_0_update_pcie_parameters,
2772 	.get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
2773 	.register_irq_handler = smu_v13_0_register_irq_handler,
2774 	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2775 	.disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2776 	.notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
2777 	.get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
2778 	.set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
2779 	.set_default_od_settings = smu_v13_0_7_set_default_od_settings,
2780 	.restore_user_od_settings = smu_v13_0_7_restore_user_od_settings,
2781 	.od_edit_dpm_table = smu_v13_0_7_od_edit_dpm_table,
2782 	.set_performance_level = smu_v13_0_set_performance_level,
2783 	.gfx_off_control = smu_v13_0_gfx_off_control,
2784 	.get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
2785 	.get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
2786 	.set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
2787 	.set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
2788 	.get_fan_control_mode = smu_v13_0_get_fan_control_mode,
2789 	.set_fan_control_mode = smu_v13_0_set_fan_control_mode,
2790 	.enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
2791 	.get_power_limit = smu_v13_0_7_get_power_limit,
2792 	.set_power_limit = smu_v13_0_7_set_power_limit,
2793 	.set_power_source = smu_v13_0_set_power_source,
2794 	.get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
2795 	.set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
2796 	.set_tool_table_location = smu_v13_0_set_tool_table_location,
2797 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2798 	.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2799 	.get_bamaco_support = smu_v13_0_get_bamaco_support,
2800 	.baco_enter = smu_v13_0_baco_enter,
2801 	.baco_exit = smu_v13_0_baco_exit,
2802 	.mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
2803 	.mode1_reset = smu_v13_0_mode1_reset,
2804 	.set_mp1_state = smu_v13_0_7_set_mp1_state,
2805 	.set_df_cstate = smu_v13_0_7_set_df_cstate,
2806 	.gpo_control = smu_v13_0_gpo_control,
2807 	.is_asic_wbrf_supported = smu_v13_0_7_wbrf_support_check,
2808 	.enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
2809 	.set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
2810 	.interrupt_work = smu_v13_0_interrupt_work,
2811 };
2812 
smu_v13_0_7_set_ppt_funcs(struct smu_context * smu)2813 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
2814 {
2815 	smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
2816 	smu->message_map = smu_v13_0_7_message_map;
2817 	smu->clock_map = smu_v13_0_7_clk_map;
2818 	smu->feature_map = smu_v13_0_7_feature_mask_map;
2819 	smu->table_map = smu_v13_0_7_table_map;
2820 	smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
2821 	smu->workload_map = smu_v13_0_7_workload_map;
2822 	smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION;
2823 	smu_v13_0_set_smu_mailbox_registers(smu);
2824 }
2825