1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "smu_v13_0_12_pmfw.h"
30 #include "smu_v13_0_6_ppt.h"
31 #include "smu_v13_0_12_ppsmc.h"
32 #include "smu_v13_0.h"
33 #include "amdgpu_xgmi.h"
34 #include "amdgpu_fru_eeprom.h"
35 #include <linux/pci.h>
36 #include "smu_cmn.h"
37
38 #undef MP1_Public
39 #undef smnMP1_FIRMWARE_FLAGS
40
41 /*
42 * DO NOT use these for err/warn/info/debug messages.
43 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
44 * They are more MGPU friendly.
45 */
46 #undef pr_err
47 #undef pr_warn
48 #undef pr_info
49 #undef pr_debug
50
51 #define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \
52 [smu_feature] = { 1, (smu_13_0_12_feature) }
53
54 #define FEATURE_MASK(feature) (1ULL << feature)
55 #define SMC_DPM_FEATURE \
56 (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
57 FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK))
58
59 #define NUM_JPEG_RINGS_FW 10
60 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \
61 (ARRAY_SIZE(gpu_metrics->xcp_stats[0].jpeg_busy) / 4)
62
63 const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = {
64 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
65 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
66 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
67 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
68 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
69 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
70 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
71 SMU_13_0_12_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
72 SMU_13_0_12_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
73 SMU_13_0_12_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
74 SMU_13_0_12_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
75 SMU_13_0_12_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
76 SMU_13_0_12_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
77 SMU_13_0_12_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, FEATURE_SOC_PCC),
78 SMU_13_0_12_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
79 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN),
80 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK),
81 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK),
82 SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK),
83 SMU_13_0_12_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_PIT),
84 };
85
86 // clang-format off
87 const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] = {
88 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
89 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
90 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
91 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
92 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
93 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
94 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
95 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
96 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
97 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
98 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
99 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
100 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
101 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
102 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
103 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
107 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
108 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
109 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI),
110 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
111 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
112 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
113 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
114 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
115 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
116 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
117 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
118 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
119 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
120 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
121 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
122 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
123 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
124 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
125 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
126 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
127 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
128 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
129 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
130 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
131 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
132 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
133 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
134 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
135 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
136 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
137 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
138 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
139 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
140 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1),
141 };
142
smu_v13_0_12_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)143 static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu,
144 uint64_t *feature_mask)
145 {
146 int ret;
147
148 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
149
150 if (ret == -EIO) {
151 *feature_mask = 0;
152 ret = 0;
153 }
154
155 return ret;
156 }
157
smu_v13_0_12_fru_get_product_info(struct smu_context * smu,StaticMetricsTable_t * static_metrics)158 static int smu_v13_0_12_fru_get_product_info(struct smu_context *smu,
159 StaticMetricsTable_t *static_metrics)
160 {
161 struct amdgpu_fru_info *fru_info;
162 struct amdgpu_device *adev = smu->adev;
163
164 if (!adev->fru_info) {
165 adev->fru_info = kzalloc(sizeof(*adev->fru_info), GFP_KERNEL);
166 if (!adev->fru_info)
167 return -ENOMEM;
168 }
169
170 fru_info = adev->fru_info;
171 strscpy(fru_info->product_number, static_metrics->ProductInfo.ModelNumber,
172 sizeof(fru_info->product_number));
173 strscpy(fru_info->product_name, static_metrics->ProductInfo.Name,
174 sizeof(fru_info->product_name));
175 strscpy(fru_info->serial, static_metrics->ProductInfo.Serial,
176 sizeof(fru_info->serial));
177 strscpy(fru_info->manufacturer_name, static_metrics->ProductInfo.ManufacturerName,
178 sizeof(fru_info->manufacturer_name));
179 strscpy(fru_info->fru_id, static_metrics->ProductInfo.FruId,
180 sizeof(fru_info->fru_id));
181
182 return 0;
183 }
184
smu_v13_0_12_get_max_metrics_size(void)185 int smu_v13_0_12_get_max_metrics_size(void)
186 {
187 return max(sizeof(StaticMetricsTable_t), sizeof(MetricsTable_t));
188 }
189
smu_v13_0_12_get_static_metrics_table(struct smu_context * smu)190 static int smu_v13_0_12_get_static_metrics_table(struct smu_context *smu)
191 {
192 struct smu_table_context *smu_table = &smu->smu_table;
193 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
194 struct smu_table *table = &smu_table->driver_table;
195 int ret;
196
197 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL);
198 if (ret) {
199 dev_info(smu->adev->dev,
200 "Failed to export static metrics table!\n");
201 return ret;
202 }
203
204 amdgpu_asic_invalidate_hdp(smu->adev, NULL);
205 memcpy(smu_table->metrics_table, table->cpu_addr, table_size);
206
207 return 0;
208 }
209
smu_v13_0_12_setup_driver_pptable(struct smu_context * smu)210 int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu)
211 {
212 struct smu_table_context *smu_table = &smu->smu_table;
213 StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table;
214 struct PPTable_t *pptable =
215 (struct PPTable_t *)smu_table->driver_pptable;
216 uint32_t table_version;
217 int ret, i;
218
219 if (!pptable->Init) {
220 ret = smu_v13_0_12_get_static_metrics_table(smu);
221 if (ret)
222 return ret;
223
224 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
225 &table_version);
226 if (ret)
227 return ret;
228 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
229 table_version;
230
231 pptable->MaxSocketPowerLimit =
232 SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit);
233 pptable->MaxGfxclkFrequency =
234 SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency);
235 pptable->MinGfxclkFrequency =
236 SMUQ10_ROUND(static_metrics->MinGfxclkFrequency);
237
238 for (i = 0; i < 4; ++i) {
239 pptable->FclkFrequencyTable[i] =
240 SMUQ10_ROUND(static_metrics->FclkFrequencyTable[i]);
241 pptable->UclkFrequencyTable[i] =
242 SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]);
243 pptable->SocclkFrequencyTable[i] =
244 SMUQ10_ROUND(static_metrics->SocclkFrequencyTable[i]);
245 pptable->VclkFrequencyTable[i] =
246 SMUQ10_ROUND(static_metrics->VclkFrequencyTable[i]);
247 pptable->DclkFrequencyTable[i] =
248 SMUQ10_ROUND(static_metrics->DclkFrequencyTable[i]);
249 pptable->LclkFrequencyTable[i] =
250 SMUQ10_ROUND(static_metrics->LclkFrequencyTable[i]);
251 }
252
253 /* use AID0 serial number by default */
254 pptable->PublicSerialNumber_AID =
255 static_metrics->PublicSerialNumber_AID[0];
256 ret = smu_v13_0_12_fru_get_product_info(smu, static_metrics);
257 if (ret)
258 return ret;
259
260 pptable->Init = true;
261 }
262
263 return 0;
264 }
265
smu_v13_0_12_is_dpm_running(struct smu_context * smu)266 bool smu_v13_0_12_is_dpm_running(struct smu_context *smu)
267 {
268 int ret;
269 uint64_t feature_enabled;
270
271 ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled);
272
273 if (ret)
274 return false;
275
276 return !!(feature_enabled & SMC_DPM_FEATURE);
277 }
278
smu_v13_0_12_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)279 int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu,
280 MetricsMember_t member,
281 uint32_t *value)
282 {
283 struct smu_table_context *smu_table = &smu->smu_table;
284 MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table;
285 struct amdgpu_device *adev = smu->adev;
286 int ret = 0;
287 int xcc_id;
288
289 /* For clocks with multiple instances, only report the first one */
290 switch (member) {
291 case METRICS_CURR_GFXCLK:
292 case METRICS_AVERAGE_GFXCLK:
293 xcc_id = GET_INST(GC, 0);
294 *value = SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]);
295 break;
296 case METRICS_CURR_SOCCLK:
297 case METRICS_AVERAGE_SOCCLK:
298 *value = SMUQ10_ROUND(metrics->SocclkFrequency[0]);
299 break;
300 case METRICS_CURR_UCLK:
301 case METRICS_AVERAGE_UCLK:
302 *value = SMUQ10_ROUND(metrics->UclkFrequency);
303 break;
304 case METRICS_CURR_VCLK:
305 *value = SMUQ10_ROUND(metrics->VclkFrequency[0]);
306 break;
307 case METRICS_CURR_DCLK:
308 *value = SMUQ10_ROUND(metrics->DclkFrequency[0]);
309 break;
310 case METRICS_CURR_FCLK:
311 *value = SMUQ10_ROUND(metrics->FclkFrequency);
312 break;
313 case METRICS_AVERAGE_GFXACTIVITY:
314 *value = SMUQ10_ROUND(metrics->SocketGfxBusy);
315 break;
316 case METRICS_AVERAGE_MEMACTIVITY:
317 *value = SMUQ10_ROUND(metrics->DramBandwidthUtilization);
318 break;
319 case METRICS_CURR_SOCKETPOWER:
320 *value = SMUQ10_ROUND(metrics->SocketPower) << 8;
321 break;
322 case METRICS_TEMPERATURE_HOTSPOT:
323 *value = SMUQ10_ROUND(metrics->MaxSocketTemperature) *
324 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
325 break;
326 case METRICS_TEMPERATURE_MEM:
327 *value = SMUQ10_ROUND(metrics->MaxHbmTemperature) *
328 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
329 break;
330 /* This is the max of all VRs and not just SOC VR.
331 * No need to define another data type for the same.
332 */
333 case METRICS_TEMPERATURE_VRSOC:
334 *value = SMUQ10_ROUND(metrics->MaxVrTemperature) *
335 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
336 break;
337 default:
338 *value = UINT_MAX;
339 break;
340 }
341
342 return ret;
343 }
344
smu_v13_0_12_get_gpu_metrics(struct smu_context * smu,void ** table)345 ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table)
346 {
347 struct smu_table_context *smu_table = &smu->smu_table;
348 struct gpu_metrics_v1_7 *gpu_metrics =
349 (struct gpu_metrics_v1_7 *)smu_table->gpu_metrics_table;
350 int ret = 0, xcc_id, inst, i, j, k, idx;
351 struct amdgpu_device *adev = smu->adev;
352 u8 num_jpeg_rings_gpu_metrics;
353 MetricsTable_t *metrics;
354 struct amdgpu_xcp *xcp;
355 u32 inst_mask;
356
357 metrics = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL);
358 memcpy(metrics, smu_table->metrics_table, sizeof(MetricsTable_t));
359
360 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 7);
361
362 gpu_metrics->temperature_hotspot =
363 SMUQ10_ROUND(metrics->MaxSocketTemperature);
364 /* Individual HBM stack temperature is not reported */
365 gpu_metrics->temperature_mem =
366 SMUQ10_ROUND(metrics->MaxHbmTemperature);
367 /* Reports max temperature of all voltage rails */
368 gpu_metrics->temperature_vrsoc =
369 SMUQ10_ROUND(metrics->MaxVrTemperature);
370
371 gpu_metrics->average_gfx_activity =
372 SMUQ10_ROUND(metrics->SocketGfxBusy);
373 gpu_metrics->average_umc_activity =
374 SMUQ10_ROUND(metrics->DramBandwidthUtilization);
375
376 gpu_metrics->mem_max_bandwidth =
377 SMUQ10_ROUND(metrics->MaxDramBandwidth);
378
379 gpu_metrics->curr_socket_power =
380 SMUQ10_ROUND(metrics->SocketPower);
381 /* Energy counter reported in 15.259uJ (2^-16) units */
382 gpu_metrics->energy_accumulator = metrics->SocketEnergyAcc;
383
384 for (i = 0; i < MAX_GFX_CLKS; i++) {
385 xcc_id = GET_INST(GC, i);
386 if (xcc_id >= 0)
387 gpu_metrics->current_gfxclk[i] =
388 SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]);
389
390 if (i < MAX_CLKS) {
391 gpu_metrics->current_socclk[i] =
392 SMUQ10_ROUND(metrics->SocclkFrequency[i]);
393 inst = GET_INST(VCN, i);
394 if (inst >= 0) {
395 gpu_metrics->current_vclk0[i] =
396 SMUQ10_ROUND(metrics->VclkFrequency[inst]);
397 gpu_metrics->current_dclk0[i] =
398 SMUQ10_ROUND(metrics->DclkFrequency[inst]);
399 }
400 }
401 }
402
403 gpu_metrics->current_uclk = SMUQ10_ROUND(metrics->UclkFrequency);
404
405 /* Total accumulated cycle counter */
406 gpu_metrics->accumulation_counter = metrics->AccumulationCounter;
407
408 /* Accumulated throttler residencies */
409 gpu_metrics->prochot_residency_acc = metrics->ProchotResidencyAcc;
410 gpu_metrics->ppt_residency_acc = metrics->PptResidencyAcc;
411 gpu_metrics->socket_thm_residency_acc = metrics->SocketThmResidencyAcc;
412 gpu_metrics->vr_thm_residency_acc = metrics->VrThmResidencyAcc;
413 gpu_metrics->hbm_thm_residency_acc = metrics->HbmThmResidencyAcc;
414
415 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
416 gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0);
417
418 gpu_metrics->pcie_link_width = metrics->PCIeLinkWidth;
419 gpu_metrics->pcie_link_speed =
420 pcie_gen_to_speed(metrics->PCIeLinkSpeed);
421 gpu_metrics->pcie_bandwidth_acc =
422 SMUQ10_ROUND(metrics->PcieBandwidthAcc[0]);
423 gpu_metrics->pcie_bandwidth_inst =
424 SMUQ10_ROUND(metrics->PcieBandwidth[0]);
425 gpu_metrics->pcie_l0_to_recov_count_acc = metrics->PCIeL0ToRecoveryCountAcc;
426 gpu_metrics->pcie_replay_count_acc = metrics->PCIenReplayAAcc;
427 gpu_metrics->pcie_replay_rover_count_acc =
428 metrics->PCIenReplayARolloverCountAcc;
429 gpu_metrics->pcie_nak_sent_count_acc = metrics->PCIeNAKSentCountAcc;
430 gpu_metrics->pcie_nak_rcvd_count_acc = metrics->PCIeNAKReceivedCountAcc;
431 gpu_metrics->pcie_lc_perf_other_end_recovery = metrics->PCIeOtherEndRecoveryAcc;
432
433 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
434
435 gpu_metrics->gfx_activity_acc = SMUQ10_ROUND(metrics->SocketGfxBusyAcc);
436 gpu_metrics->mem_activity_acc = SMUQ10_ROUND(metrics->DramBandwidthUtilizationAcc);
437
438 for (i = 0; i < NUM_XGMI_LINKS; i++) {
439 gpu_metrics->xgmi_read_data_acc[i] =
440 SMUQ10_ROUND(metrics->XgmiReadDataSizeAcc[i]);
441 gpu_metrics->xgmi_write_data_acc[i] =
442 SMUQ10_ROUND(metrics->XgmiWriteDataSizeAcc[i]);
443 ret = amdgpu_get_xgmi_link_status(adev, i);
444 if (ret >= 0)
445 gpu_metrics->xgmi_link_status[i] = ret;
446 }
447
448 gpu_metrics->num_partition = adev->xcp_mgr->num_xcps;
449
450 num_jpeg_rings_gpu_metrics = NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics);
451 for_each_xcp(adev->xcp_mgr, xcp, i) {
452 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
453 idx = 0;
454 for_each_inst(k, inst_mask) {
455 /* Both JPEG and VCN has same instances */
456 inst = GET_INST(VCN, k);
457
458 for (j = 0; j < num_jpeg_rings_gpu_metrics; ++j) {
459 gpu_metrics->xcp_stats[i].jpeg_busy
460 [(idx * num_jpeg_rings_gpu_metrics) + j] =
461 SMUQ10_ROUND(metrics->JpegBusy
462 [(inst * NUM_JPEG_RINGS_FW) + j]);
463 }
464 gpu_metrics->xcp_stats[i].vcn_busy[idx] =
465 SMUQ10_ROUND(metrics->VcnBusy[inst]);
466 idx++;
467 }
468
469 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
470 idx = 0;
471 for_each_inst(k, inst_mask) {
472 inst = GET_INST(GC, k);
473 gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
474 SMUQ10_ROUND(metrics->GfxBusy[inst]);
475 gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
476 SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);
477 idx++;
478 }
479 }
480
481 gpu_metrics->xgmi_link_width = metrics->XgmiWidth;
482 gpu_metrics->xgmi_link_speed = metrics->XgmiBitrate;
483
484 gpu_metrics->firmware_timestamp = metrics->Timestamp;
485
486 *table = (void *)gpu_metrics;
487 kfree(metrics);
488
489 return sizeof(*gpu_metrics);
490 }
491