1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_0_ppt.h"
39 #include "smu_v13_0_0_pptable.h"
40 #include "smu_v13_0_0_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
72
73 #define mmMP1_SMN_C2PMSG_66 0x0282
74 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
75
76 #define mmMP1_SMN_C2PMSG_82 0x0292
77 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
78
79 #define mmMP1_SMN_C2PMSG_90 0x029a
80 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
81
82 #define mmMP1_SMN_C2PMSG_75 0x028b
83 #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0
84
85 #define mmMP1_SMN_C2PMSG_53 0x0275
86 #define mmMP1_SMN_C2PMSG_53_BASE_IDX 0
87
88 #define mmMP1_SMN_C2PMSG_54 0x0276
89 #define mmMP1_SMN_C2PMSG_54_BASE_IDX 0
90
91 #define DEBUGSMC_MSG_Mode1Reset 2
92
93 /*
94 * SMU_v13_0_10 supports ECCTABLE since version 80.34.0,
95 * use this to check ECCTABLE feature whether support
96 */
97 #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION 0x00502200
98
99 #define PP_OD_FEATURE_GFXCLK_FMIN 0
100 #define PP_OD_FEATURE_GFXCLK_FMAX 1
101 #define PP_OD_FEATURE_UCLK_FMIN 2
102 #define PP_OD_FEATURE_UCLK_FMAX 3
103 #define PP_OD_FEATURE_GFX_VF_CURVE 4
104 #define PP_OD_FEATURE_FAN_CURVE_TEMP 5
105 #define PP_OD_FEATURE_FAN_CURVE_PWM 6
106 #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT 7
107 #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8
108 #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9
109 #define PP_OD_FEATURE_FAN_MINIMUM_PWM 10
110 #define PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE 11
111 #define PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP 12
112
113 #define LINK_SPEED_MAX 3
114
115 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
116 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
117 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
118 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
119 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
120 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
121 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
122 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
123 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
124 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
125 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
126 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
127 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
128 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
129 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0),
130 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
131 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
132 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
133 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
134 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
135 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
136 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
137 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
138 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
139 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
140 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
141 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
142 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
143 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
144 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
145 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
146 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
147 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
148 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
149 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
150 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
151 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
152 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 0),
153 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
154 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
155 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
156 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
157 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
158 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
159 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
160 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
161 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
162 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
163 MSG_MAP(Mode2Reset, PPSMC_MSG_Mode2Reset, 0),
164 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
165 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
166 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
167 MSG_MAP(SetNumBadMemoryPagesRetired, PPSMC_MSG_SetNumBadMemoryPagesRetired, 0),
168 MSG_MAP(SetBadMemoryPagesRetiredFlagsPerChannel,
169 PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, 0),
170 MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0),
171 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
172 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
173 MSG_MAP(DALNotPresent, PPSMC_MSG_DALNotPresent, 0),
174 MSG_MAP(EnableUCLKShadow, PPSMC_MSG_EnableUCLKShadow, 0),
175 };
176
177 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
178 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
179 CLK_MAP(SCLK, PPCLK_GFXCLK),
180 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
181 CLK_MAP(FCLK, PPCLK_FCLK),
182 CLK_MAP(UCLK, PPCLK_UCLK),
183 CLK_MAP(MCLK, PPCLK_UCLK),
184 CLK_MAP(VCLK, PPCLK_VCLK_0),
185 CLK_MAP(VCLK1, PPCLK_VCLK_1),
186 CLK_MAP(DCLK, PPCLK_DCLK_0),
187 CLK_MAP(DCLK1, PPCLK_DCLK_1),
188 CLK_MAP(DCEFCLK, PPCLK_DCFCLK),
189 };
190
191 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
192 FEA_MAP(FW_DATA_READ),
193 FEA_MAP(DPM_GFXCLK),
194 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
195 FEA_MAP(DPM_UCLK),
196 FEA_MAP(DPM_FCLK),
197 FEA_MAP(DPM_SOCCLK),
198 FEA_MAP(DPM_MP0CLK),
199 FEA_MAP(DPM_LINK),
200 FEA_MAP(DPM_DCN),
201 FEA_MAP(VMEMP_SCALING),
202 FEA_MAP(VDDIO_MEM_SCALING),
203 FEA_MAP(DS_GFXCLK),
204 FEA_MAP(DS_SOCCLK),
205 FEA_MAP(DS_FCLK),
206 FEA_MAP(DS_LCLK),
207 FEA_MAP(DS_DCFCLK),
208 FEA_MAP(DS_UCLK),
209 FEA_MAP(GFX_ULV),
210 FEA_MAP(FW_DSTATE),
211 FEA_MAP(GFXOFF),
212 FEA_MAP(BACO),
213 FEA_MAP(MM_DPM),
214 FEA_MAP(SOC_MPCLK_DS),
215 FEA_MAP(BACO_MPCLK_DS),
216 FEA_MAP(THROTTLERS),
217 FEA_MAP(SMARTSHIFT),
218 FEA_MAP(GTHR),
219 FEA_MAP(ACDC),
220 FEA_MAP(VR0HOT),
221 FEA_MAP(FW_CTF),
222 FEA_MAP(FAN_CONTROL),
223 FEA_MAP(GFX_DCS),
224 FEA_MAP(GFX_READ_MARGIN),
225 FEA_MAP(LED_DISPLAY),
226 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
227 FEA_MAP(OUT_OF_BAND_MONITOR),
228 FEA_MAP(OPTIMIZED_VMIN),
229 FEA_MAP(GFX_IMU),
230 FEA_MAP(BOOT_TIME_CAL),
231 FEA_MAP(GFX_PCC_DFLL),
232 FEA_MAP(SOC_CG),
233 FEA_MAP(DF_CSTATE),
234 FEA_MAP(GFX_EDC),
235 FEA_MAP(BOOT_POWER_OPT),
236 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
237 FEA_MAP(DS_VCN),
238 FEA_MAP(BACO_CG),
239 FEA_MAP(MEM_TEMP_READ),
240 FEA_MAP(ATHUB_MMHUB_PG),
241 FEA_MAP(SOC_PCC),
242 [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
243 [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
244 [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
245 };
246
247 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
248 TAB_MAP(PPTABLE),
249 TAB_MAP(WATERMARKS),
250 TAB_MAP(AVFS_PSM_DEBUG),
251 TAB_MAP(PMSTATUSLOG),
252 TAB_MAP(SMU_METRICS),
253 TAB_MAP(DRIVER_SMU_CONFIG),
254 TAB_MAP(ACTIVITY_MONITOR_COEFF),
255 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
256 TAB_MAP(I2C_COMMANDS),
257 TAB_MAP(ECCINFO),
258 TAB_MAP(OVERDRIVE),
259 TAB_MAP(WIFIBAND),
260 };
261
262 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
263 PWR_MAP(AC),
264 PWR_MAP(DC),
265 };
266
267 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
268 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
269 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
270 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
271 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
272 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
273 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
274 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
275 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
276 };
277
278 static const uint8_t smu_v13_0_0_throttler_map[] = {
279 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
280 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
281 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
282 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
283 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
284 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
285 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
286 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
287 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
288 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
289 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
290 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
291 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
292 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
293 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
294 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
295 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
296 };
297
298 static int
smu_v13_0_0_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)299 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
300 uint32_t *feature_mask, uint32_t num)
301 {
302 struct amdgpu_device *adev = smu->adev;
303
304 if (num > 2)
305 return -EINVAL;
306
307 memset(feature_mask, 0xff, sizeof(uint32_t) * num);
308
309 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
310 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
311 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
312 }
313
314 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
315 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
316 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
317
318 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
320
321 /* PMFW 78.58 contains a critical fix for gfxoff feature */
322 if ((smu->smc_fw_version < 0x004e3a00) ||
323 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
324 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
325
326 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
327 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
328 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
329 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
330 }
331
332 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
333 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
334
335 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
336 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
337 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
338 }
339
340 if (!(adev->pm.pp_feature & PP_ULV_MASK))
341 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
342
343 return 0;
344 }
345
smu_v13_0_0_check_powerplay_table(struct smu_context * smu)346 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
347 {
348 struct smu_table_context *table_context = &smu->smu_table;
349 struct smu_13_0_0_powerplay_table *powerplay_table =
350 table_context->power_play_table;
351 struct smu_baco_context *smu_baco = &smu->smu_baco;
352 PPTable_t *pptable = smu->smu_table.driver_pptable;
353 const OverDriveLimits_t * const overdrive_upperlimits =
354 &pptable->SkuTable.OverDriveLimitsBasicMax;
355 const OverDriveLimits_t * const overdrive_lowerlimits =
356 &pptable->SkuTable.OverDriveLimitsMin;
357
358 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
359 smu->dc_controlled_by_gpio = true;
360
361 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO) {
362 smu_baco->platform_support = true;
363
364 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
365 smu_baco->maco_support = true;
366 }
367
368 if (!overdrive_lowerlimits->FeatureCtrlMask ||
369 !overdrive_upperlimits->FeatureCtrlMask)
370 smu->od_enabled = false;
371
372 table_context->thermal_controller_type =
373 powerplay_table->thermal_controller_type;
374
375 /*
376 * Instead of having its own buffer space and get overdrive_table copied,
377 * smu->od_settings just points to the actual overdrive_table
378 */
379 smu->od_settings = &powerplay_table->overdrive_table;
380
381 smu->adev->pm.no_fan =
382 !(pptable->SkuTable.FeaturesToRun[0] & (1 << FEATURE_FAN_CONTROL_BIT));
383
384 return 0;
385 }
386
smu_v13_0_0_store_powerplay_table(struct smu_context * smu)387 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
388 {
389 struct smu_table_context *table_context = &smu->smu_table;
390 struct smu_13_0_0_powerplay_table *powerplay_table =
391 table_context->power_play_table;
392
393 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
394 sizeof(PPTable_t));
395
396 return 0;
397 }
398
399 #ifndef atom_smc_dpm_info_table_13_0_0
400 struct atom_smc_dpm_info_table_13_0_0 {
401 struct atom_common_table_header table_header;
402 BoardTable_t BoardTable;
403 };
404 #endif
405
smu_v13_0_0_append_powerplay_table(struct smu_context * smu)406 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
407 {
408 struct smu_table_context *table_context = &smu->smu_table;
409 PPTable_t *smc_pptable = table_context->driver_pptable;
410 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
411 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
412 int index, ret;
413
414 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
415 smc_dpm_info);
416
417 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
418 (uint8_t **)&smc_dpm_table);
419 if (ret)
420 return ret;
421
422 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
423
424 return 0;
425 }
426
smu_v13_0_0_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)427 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
428 void **table,
429 uint32_t *size)
430 {
431 struct smu_table_context *smu_table = &smu->smu_table;
432 void *combo_pptable = smu_table->combo_pptable;
433 int ret = 0;
434
435 ret = smu_cmn_get_combo_pptable(smu);
436 if (ret)
437 return ret;
438
439 *table = combo_pptable;
440 *size = sizeof(struct smu_13_0_0_powerplay_table);
441
442 return 0;
443 }
444
smu_v13_0_0_setup_pptable(struct smu_context * smu)445 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
446 {
447 struct smu_table_context *smu_table = &smu->smu_table;
448 struct amdgpu_device *adev = smu->adev;
449 int ret = 0;
450
451 if (amdgpu_sriov_vf(smu->adev))
452 return 0;
453
454 ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
455 &smu_table->power_play_table,
456 &smu_table->power_play_table_size);
457 if (ret)
458 return ret;
459
460 ret = smu_v13_0_0_store_powerplay_table(smu);
461 if (ret)
462 return ret;
463
464 /*
465 * With SCPM enabled, the operation below will be handled
466 * by PSP. Driver involvment is unnecessary and useless.
467 */
468 if (!adev->scpm_enabled) {
469 ret = smu_v13_0_0_append_powerplay_table(smu);
470 if (ret)
471 return ret;
472 }
473
474 ret = smu_v13_0_0_check_powerplay_table(smu);
475 if (ret)
476 return ret;
477
478 return ret;
479 }
480
smu_v13_0_0_tables_init(struct smu_context * smu)481 static int smu_v13_0_0_tables_init(struct smu_context *smu)
482 {
483 struct smu_table_context *smu_table = &smu->smu_table;
484 struct smu_table *tables = smu_table->tables;
485
486 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
487 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
488 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
489 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
490 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
491 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
492 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
493 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
494 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTableExternal_t),
495 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
496 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
497 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
498 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
499 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
500 AMDGPU_GEM_DOMAIN_VRAM);
501 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_WIFIBAND,
506 sizeof(WifiBandEntryTable_t), PAGE_SIZE,
507 AMDGPU_GEM_DOMAIN_VRAM);
508
509 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
510 if (!smu_table->metrics_table)
511 goto err0_out;
512 smu_table->metrics_time = 0;
513
514 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
515 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
516 if (!smu_table->gpu_metrics_table)
517 goto err1_out;
518
519 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
520 if (!smu_table->watermarks_table)
521 goto err2_out;
522
523 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
524 if (!smu_table->ecc_table)
525 goto err3_out;
526
527 return 0;
528
529 err3_out:
530 kfree(smu_table->watermarks_table);
531 err2_out:
532 kfree(smu_table->gpu_metrics_table);
533 err1_out:
534 kfree(smu_table->metrics_table);
535 err0_out:
536 return -ENOMEM;
537 }
538
smu_v13_0_0_allocate_dpm_context(struct smu_context * smu)539 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
540 {
541 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
542
543 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
544 GFP_KERNEL);
545 if (!smu_dpm->dpm_context)
546 return -ENOMEM;
547
548 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
549
550 return 0;
551 }
552
smu_v13_0_0_init_smc_tables(struct smu_context * smu)553 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
554 {
555 int ret = 0;
556
557 ret = smu_v13_0_0_tables_init(smu);
558 if (ret)
559 return ret;
560
561 ret = smu_v13_0_0_allocate_dpm_context(smu);
562 if (ret)
563 return ret;
564
565 return smu_v13_0_init_smc_tables(smu);
566 }
567
smu_v13_0_0_set_default_dpm_table(struct smu_context * smu)568 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
569 {
570 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
571 struct smu_table_context *table_context = &smu->smu_table;
572 PPTable_t *pptable = table_context->driver_pptable;
573 SkuTable_t *skutable = &pptable->SkuTable;
574 struct smu_13_0_dpm_table *dpm_table;
575 struct smu_13_0_pcie_table *pcie_table;
576 uint32_t link_level;
577 int ret = 0;
578
579 /* socclk dpm table setup */
580 dpm_table = &dpm_context->dpm_tables.soc_table;
581 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
582 ret = smu_v13_0_set_single_dpm_table(smu,
583 SMU_SOCCLK,
584 dpm_table);
585 if (ret)
586 return ret;
587 } else {
588 dpm_table->count = 1;
589 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
590 dpm_table->dpm_levels[0].enabled = true;
591 dpm_table->min = dpm_table->dpm_levels[0].value;
592 dpm_table->max = dpm_table->dpm_levels[0].value;
593 }
594
595 /* gfxclk dpm table setup */
596 dpm_table = &dpm_context->dpm_tables.gfx_table;
597 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
598 ret = smu_v13_0_set_single_dpm_table(smu,
599 SMU_GFXCLK,
600 dpm_table);
601 if (ret)
602 return ret;
603
604 /*
605 * Update the reported maximum shader clock to the value
606 * which can be guarded to be achieved on all cards. This
607 * is aligned with Window setting. And considering that value
608 * might be not the peak frequency the card can achieve, it
609 * is normal some real-time clock frequency can overtake this
610 * labelled maximum clock frequency(for example in pp_dpm_sclk
611 * sysfs output).
612 */
613 if (skutable->DriverReportedClocks.GameClockAc &&
614 (dpm_table->dpm_levels[dpm_table->count - 1].value >
615 skutable->DriverReportedClocks.GameClockAc)) {
616 dpm_table->dpm_levels[dpm_table->count - 1].value =
617 skutable->DriverReportedClocks.GameClockAc;
618 dpm_table->max = skutable->DriverReportedClocks.GameClockAc;
619 }
620 } else {
621 dpm_table->count = 1;
622 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
623 dpm_table->dpm_levels[0].enabled = true;
624 dpm_table->min = dpm_table->dpm_levels[0].value;
625 dpm_table->max = dpm_table->dpm_levels[0].value;
626 }
627
628 /* uclk dpm table setup */
629 dpm_table = &dpm_context->dpm_tables.uclk_table;
630 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
631 ret = smu_v13_0_set_single_dpm_table(smu,
632 SMU_UCLK,
633 dpm_table);
634 if (ret)
635 return ret;
636 } else {
637 dpm_table->count = 1;
638 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
639 dpm_table->dpm_levels[0].enabled = true;
640 dpm_table->min = dpm_table->dpm_levels[0].value;
641 dpm_table->max = dpm_table->dpm_levels[0].value;
642 }
643
644 /* fclk dpm table setup */
645 dpm_table = &dpm_context->dpm_tables.fclk_table;
646 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
647 ret = smu_v13_0_set_single_dpm_table(smu,
648 SMU_FCLK,
649 dpm_table);
650 if (ret)
651 return ret;
652 } else {
653 dpm_table->count = 1;
654 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
655 dpm_table->dpm_levels[0].enabled = true;
656 dpm_table->min = dpm_table->dpm_levels[0].value;
657 dpm_table->max = dpm_table->dpm_levels[0].value;
658 }
659
660 /* vclk dpm table setup */
661 dpm_table = &dpm_context->dpm_tables.vclk_table;
662 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
663 ret = smu_v13_0_set_single_dpm_table(smu,
664 SMU_VCLK,
665 dpm_table);
666 if (ret)
667 return ret;
668 } else {
669 dpm_table->count = 1;
670 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
671 dpm_table->dpm_levels[0].enabled = true;
672 dpm_table->min = dpm_table->dpm_levels[0].value;
673 dpm_table->max = dpm_table->dpm_levels[0].value;
674 }
675
676 /* dclk dpm table setup */
677 dpm_table = &dpm_context->dpm_tables.dclk_table;
678 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
679 ret = smu_v13_0_set_single_dpm_table(smu,
680 SMU_DCLK,
681 dpm_table);
682 if (ret)
683 return ret;
684 } else {
685 dpm_table->count = 1;
686 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
687 dpm_table->dpm_levels[0].enabled = true;
688 dpm_table->min = dpm_table->dpm_levels[0].value;
689 dpm_table->max = dpm_table->dpm_levels[0].value;
690 }
691
692 /* lclk dpm table setup */
693 pcie_table = &dpm_context->dpm_tables.pcie_table;
694 pcie_table->num_of_link_levels = 0;
695 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
696 if (!skutable->PcieGenSpeed[link_level] &&
697 !skutable->PcieLaneCount[link_level] &&
698 !skutable->LclkFreq[link_level])
699 continue;
700
701 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
702 skutable->PcieGenSpeed[link_level];
703 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
704 skutable->PcieLaneCount[link_level];
705 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
706 skutable->LclkFreq[link_level];
707 pcie_table->num_of_link_levels++;
708 }
709
710 /* dcefclk dpm table setup */
711 dpm_table = &dpm_context->dpm_tables.dcef_table;
712 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) {
713 ret = smu_v13_0_set_single_dpm_table(smu,
714 SMU_DCEFCLK,
715 dpm_table);
716 if (ret)
717 return ret;
718 } else {
719 dpm_table->count = 1;
720 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
721 dpm_table->dpm_levels[0].enabled = true;
722 dpm_table->min = dpm_table->dpm_levels[0].value;
723 dpm_table->max = dpm_table->dpm_levels[0].value;
724 }
725
726 return 0;
727 }
728
smu_v13_0_0_is_dpm_running(struct smu_context * smu)729 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
730 {
731 int ret = 0;
732 uint64_t feature_enabled;
733
734 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
735 if (ret)
736 return false;
737
738 return !!(feature_enabled & SMC_DPM_FEATURE);
739 }
740
smu_v13_0_0_system_features_control(struct smu_context * smu,bool en)741 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
742 bool en)
743 {
744 return smu_v13_0_system_features_control(smu, en);
745 }
746
smu_v13_0_get_throttler_status(SmuMetrics_t * metrics)747 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
748 {
749 uint32_t throttler_status = 0;
750 int i;
751
752 for (i = 0; i < THROTTLER_COUNT; i++)
753 throttler_status |=
754 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
755
756 return throttler_status;
757 }
758
759 #define SMU_13_0_0_BUSY_THRESHOLD 15
smu_v13_0_0_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)760 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
761 MetricsMember_t member,
762 uint32_t *value)
763 {
764 struct smu_table_context *smu_table = &smu->smu_table;
765 SmuMetrics_t *metrics =
766 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
767 int ret = 0;
768
769 ret = smu_cmn_get_metrics_table(smu,
770 NULL,
771 false);
772 if (ret)
773 return ret;
774
775 switch (member) {
776 case METRICS_CURR_GFXCLK:
777 *value = metrics->CurrClock[PPCLK_GFXCLK];
778 break;
779 case METRICS_CURR_SOCCLK:
780 *value = metrics->CurrClock[PPCLK_SOCCLK];
781 break;
782 case METRICS_CURR_UCLK:
783 *value = metrics->CurrClock[PPCLK_UCLK];
784 break;
785 case METRICS_CURR_VCLK:
786 *value = metrics->CurrClock[PPCLK_VCLK_0];
787 break;
788 case METRICS_CURR_VCLK1:
789 *value = metrics->CurrClock[PPCLK_VCLK_1];
790 break;
791 case METRICS_CURR_DCLK:
792 *value = metrics->CurrClock[PPCLK_DCLK_0];
793 break;
794 case METRICS_CURR_DCLK1:
795 *value = metrics->CurrClock[PPCLK_DCLK_1];
796 break;
797 case METRICS_CURR_FCLK:
798 *value = metrics->CurrClock[PPCLK_FCLK];
799 break;
800 case METRICS_CURR_DCEFCLK:
801 *value = metrics->CurrClock[PPCLK_DCFCLK];
802 break;
803 case METRICS_AVERAGE_GFXCLK:
804 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
805 *value = metrics->AverageGfxclkFrequencyPostDs;
806 else
807 *value = metrics->AverageGfxclkFrequencyPreDs;
808 break;
809 case METRICS_AVERAGE_FCLK:
810 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
811 *value = metrics->AverageFclkFrequencyPostDs;
812 else
813 *value = metrics->AverageFclkFrequencyPreDs;
814 break;
815 case METRICS_AVERAGE_UCLK:
816 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
817 *value = metrics->AverageMemclkFrequencyPostDs;
818 else
819 *value = metrics->AverageMemclkFrequencyPreDs;
820 break;
821 case METRICS_AVERAGE_VCLK:
822 *value = metrics->AverageVclk0Frequency;
823 break;
824 case METRICS_AVERAGE_DCLK:
825 *value = metrics->AverageDclk0Frequency;
826 break;
827 case METRICS_AVERAGE_VCLK1:
828 *value = metrics->AverageVclk1Frequency;
829 break;
830 case METRICS_AVERAGE_DCLK1:
831 *value = metrics->AverageDclk1Frequency;
832 break;
833 case METRICS_AVERAGE_GFXACTIVITY:
834 *value = metrics->AverageGfxActivity;
835 break;
836 case METRICS_AVERAGE_MEMACTIVITY:
837 *value = metrics->AverageUclkActivity;
838 break;
839 case METRICS_AVERAGE_VCNACTIVITY:
840 *value = max(metrics->Vcn0ActivityPercentage,
841 metrics->Vcn1ActivityPercentage);
842 break;
843 case METRICS_AVERAGE_SOCKETPOWER:
844 *value = metrics->AverageSocketPower << 8;
845 break;
846 case METRICS_TEMPERATURE_EDGE:
847 *value = metrics->AvgTemperature[TEMP_EDGE] *
848 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
849 break;
850 case METRICS_TEMPERATURE_HOTSPOT:
851 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
852 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
853 break;
854 case METRICS_TEMPERATURE_MEM:
855 *value = metrics->AvgTemperature[TEMP_MEM] *
856 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
857 break;
858 case METRICS_TEMPERATURE_VRGFX:
859 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
860 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
861 break;
862 case METRICS_TEMPERATURE_VRSOC:
863 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
864 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
865 break;
866 case METRICS_THROTTLER_STATUS:
867 *value = smu_v13_0_get_throttler_status(metrics);
868 break;
869 case METRICS_CURR_FANSPEED:
870 *value = metrics->AvgFanRpm;
871 break;
872 case METRICS_CURR_FANPWM:
873 *value = metrics->AvgFanPwm;
874 break;
875 case METRICS_VOLTAGE_VDDGFX:
876 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
877 break;
878 case METRICS_PCIE_RATE:
879 *value = metrics->PcieRate;
880 break;
881 case METRICS_PCIE_WIDTH:
882 *value = metrics->PcieWidth;
883 break;
884 default:
885 *value = UINT_MAX;
886 break;
887 }
888
889 return ret;
890 }
891
smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)892 static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
893 enum smu_clk_type clk_type,
894 uint32_t *min,
895 uint32_t *max)
896 {
897 struct smu_13_0_dpm_context *dpm_context =
898 smu->smu_dpm.dpm_context;
899 struct smu_13_0_dpm_table *dpm_table;
900
901 switch (clk_type) {
902 case SMU_MCLK:
903 case SMU_UCLK:
904 /* uclk dpm table */
905 dpm_table = &dpm_context->dpm_tables.uclk_table;
906 break;
907 case SMU_GFXCLK:
908 case SMU_SCLK:
909 /* gfxclk dpm table */
910 dpm_table = &dpm_context->dpm_tables.gfx_table;
911 break;
912 case SMU_SOCCLK:
913 /* socclk dpm table */
914 dpm_table = &dpm_context->dpm_tables.soc_table;
915 break;
916 case SMU_FCLK:
917 /* fclk dpm table */
918 dpm_table = &dpm_context->dpm_tables.fclk_table;
919 break;
920 case SMU_VCLK:
921 case SMU_VCLK1:
922 /* vclk dpm table */
923 dpm_table = &dpm_context->dpm_tables.vclk_table;
924 break;
925 case SMU_DCLK:
926 case SMU_DCLK1:
927 /* dclk dpm table */
928 dpm_table = &dpm_context->dpm_tables.dclk_table;
929 break;
930 default:
931 dev_err(smu->adev->dev, "Unsupported clock type!\n");
932 return -EINVAL;
933 }
934
935 if (min)
936 *min = dpm_table->min;
937 if (max)
938 *max = dpm_table->max;
939
940 return 0;
941 }
942
smu_v13_0_0_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)943 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
944 enum amd_pp_sensors sensor,
945 void *data,
946 uint32_t *size)
947 {
948 struct smu_table_context *table_context = &smu->smu_table;
949 PPTable_t *smc_pptable = table_context->driver_pptable;
950 int ret = 0;
951
952 switch (sensor) {
953 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
954 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
955 *size = 4;
956 break;
957 case AMDGPU_PP_SENSOR_MEM_LOAD:
958 ret = smu_v13_0_0_get_smu_metrics_data(smu,
959 METRICS_AVERAGE_MEMACTIVITY,
960 (uint32_t *)data);
961 *size = 4;
962 break;
963 case AMDGPU_PP_SENSOR_GPU_LOAD:
964 ret = smu_v13_0_0_get_smu_metrics_data(smu,
965 METRICS_AVERAGE_GFXACTIVITY,
966 (uint32_t *)data);
967 *size = 4;
968 break;
969 case AMDGPU_PP_SENSOR_VCN_LOAD:
970 ret = smu_v13_0_0_get_smu_metrics_data(smu,
971 METRICS_AVERAGE_VCNACTIVITY,
972 (uint32_t *)data);
973 *size = 4;
974 break;
975 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
976 ret = smu_v13_0_0_get_smu_metrics_data(smu,
977 METRICS_AVERAGE_SOCKETPOWER,
978 (uint32_t *)data);
979 *size = 4;
980 break;
981 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
982 ret = smu_v13_0_0_get_smu_metrics_data(smu,
983 METRICS_TEMPERATURE_HOTSPOT,
984 (uint32_t *)data);
985 *size = 4;
986 break;
987 case AMDGPU_PP_SENSOR_EDGE_TEMP:
988 ret = smu_v13_0_0_get_smu_metrics_data(smu,
989 METRICS_TEMPERATURE_EDGE,
990 (uint32_t *)data);
991 *size = 4;
992 break;
993 case AMDGPU_PP_SENSOR_MEM_TEMP:
994 ret = smu_v13_0_0_get_smu_metrics_data(smu,
995 METRICS_TEMPERATURE_MEM,
996 (uint32_t *)data);
997 *size = 4;
998 break;
999 case AMDGPU_PP_SENSOR_GFX_MCLK:
1000 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1001 METRICS_CURR_UCLK,
1002 (uint32_t *)data);
1003 *(uint32_t *)data *= 100;
1004 *size = 4;
1005 break;
1006 case AMDGPU_PP_SENSOR_GFX_SCLK:
1007 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1008 METRICS_AVERAGE_GFXCLK,
1009 (uint32_t *)data);
1010 *(uint32_t *)data *= 100;
1011 *size = 4;
1012 break;
1013 case AMDGPU_PP_SENSOR_VDDGFX:
1014 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1015 METRICS_VOLTAGE_VDDGFX,
1016 (uint32_t *)data);
1017 *size = 4;
1018 break;
1019 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1020 default:
1021 ret = -EOPNOTSUPP;
1022 break;
1023 }
1024
1025 return ret;
1026 }
1027
smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1028 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
1029 enum smu_clk_type clk_type,
1030 uint32_t *value)
1031 {
1032 MetricsMember_t member_type;
1033 int clk_id = 0;
1034
1035 clk_id = smu_cmn_to_asic_specific_index(smu,
1036 CMN2ASIC_MAPPING_CLK,
1037 clk_type);
1038 if (clk_id < 0)
1039 return -EINVAL;
1040
1041 switch (clk_id) {
1042 case PPCLK_GFXCLK:
1043 member_type = METRICS_AVERAGE_GFXCLK;
1044 break;
1045 case PPCLK_UCLK:
1046 member_type = METRICS_CURR_UCLK;
1047 break;
1048 case PPCLK_FCLK:
1049 member_type = METRICS_CURR_FCLK;
1050 break;
1051 case PPCLK_SOCCLK:
1052 member_type = METRICS_CURR_SOCCLK;
1053 break;
1054 case PPCLK_VCLK_0:
1055 member_type = METRICS_AVERAGE_VCLK;
1056 break;
1057 case PPCLK_DCLK_0:
1058 member_type = METRICS_AVERAGE_DCLK;
1059 break;
1060 case PPCLK_VCLK_1:
1061 member_type = METRICS_AVERAGE_VCLK1;
1062 break;
1063 case PPCLK_DCLK_1:
1064 member_type = METRICS_AVERAGE_DCLK1;
1065 break;
1066 case PPCLK_DCFCLK:
1067 member_type = METRICS_CURR_DCEFCLK;
1068 break;
1069 default:
1070 return -EINVAL;
1071 }
1072
1073 return smu_v13_0_0_get_smu_metrics_data(smu,
1074 member_type,
1075 value);
1076 }
1077
smu_v13_0_0_is_od_feature_supported(struct smu_context * smu,int od_feature_bit)1078 static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu,
1079 int od_feature_bit)
1080 {
1081 PPTable_t *pptable = smu->smu_table.driver_pptable;
1082 const OverDriveLimits_t * const overdrive_upperlimits =
1083 &pptable->SkuTable.OverDriveLimitsBasicMax;
1084
1085 return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit);
1086 }
1087
smu_v13_0_0_get_od_setting_limits(struct smu_context * smu,int od_feature_bit,int32_t * min,int32_t * max)1088 static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu,
1089 int od_feature_bit,
1090 int32_t *min,
1091 int32_t *max)
1092 {
1093 PPTable_t *pptable = smu->smu_table.driver_pptable;
1094 const OverDriveLimits_t * const overdrive_upperlimits =
1095 &pptable->SkuTable.OverDriveLimitsBasicMax;
1096 const OverDriveLimits_t * const overdrive_lowerlimits =
1097 &pptable->SkuTable.OverDriveLimitsMin;
1098 int32_t od_min_setting, od_max_setting;
1099
1100 switch (od_feature_bit) {
1101 case PP_OD_FEATURE_GFXCLK_FMIN:
1102 od_min_setting = overdrive_lowerlimits->GfxclkFmin;
1103 od_max_setting = overdrive_upperlimits->GfxclkFmin;
1104 break;
1105 case PP_OD_FEATURE_GFXCLK_FMAX:
1106 od_min_setting = overdrive_lowerlimits->GfxclkFmax;
1107 od_max_setting = overdrive_upperlimits->GfxclkFmax;
1108 break;
1109 case PP_OD_FEATURE_UCLK_FMIN:
1110 od_min_setting = overdrive_lowerlimits->UclkFmin;
1111 od_max_setting = overdrive_upperlimits->UclkFmin;
1112 break;
1113 case PP_OD_FEATURE_UCLK_FMAX:
1114 od_min_setting = overdrive_lowerlimits->UclkFmax;
1115 od_max_setting = overdrive_upperlimits->UclkFmax;
1116 break;
1117 case PP_OD_FEATURE_GFX_VF_CURVE:
1118 od_min_setting = overdrive_lowerlimits->VoltageOffsetPerZoneBoundary;
1119 od_max_setting = overdrive_upperlimits->VoltageOffsetPerZoneBoundary;
1120 break;
1121 case PP_OD_FEATURE_FAN_CURVE_TEMP:
1122 od_min_setting = overdrive_lowerlimits->FanLinearTempPoints;
1123 od_max_setting = overdrive_upperlimits->FanLinearTempPoints;
1124 break;
1125 case PP_OD_FEATURE_FAN_CURVE_PWM:
1126 od_min_setting = overdrive_lowerlimits->FanLinearPwmPoints;
1127 od_max_setting = overdrive_upperlimits->FanLinearPwmPoints;
1128 break;
1129 case PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT:
1130 od_min_setting = overdrive_lowerlimits->AcousticLimitRpmThreshold;
1131 od_max_setting = overdrive_upperlimits->AcousticLimitRpmThreshold;
1132 break;
1133 case PP_OD_FEATURE_FAN_ACOUSTIC_TARGET:
1134 od_min_setting = overdrive_lowerlimits->AcousticTargetRpmThreshold;
1135 od_max_setting = overdrive_upperlimits->AcousticTargetRpmThreshold;
1136 break;
1137 case PP_OD_FEATURE_FAN_TARGET_TEMPERATURE:
1138 od_min_setting = overdrive_lowerlimits->FanTargetTemperature;
1139 od_max_setting = overdrive_upperlimits->FanTargetTemperature;
1140 break;
1141 case PP_OD_FEATURE_FAN_MINIMUM_PWM:
1142 od_min_setting = overdrive_lowerlimits->FanMinimumPwm;
1143 od_max_setting = overdrive_upperlimits->FanMinimumPwm;
1144 break;
1145 case PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE:
1146 od_min_setting = overdrive_lowerlimits->FanZeroRpmEnable;
1147 od_max_setting = overdrive_upperlimits->FanZeroRpmEnable;
1148 break;
1149 case PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP:
1150 od_min_setting = overdrive_lowerlimits->FanZeroRpmStopTemp;
1151 od_max_setting = overdrive_upperlimits->FanZeroRpmStopTemp;
1152 break;
1153 default:
1154 od_min_setting = od_max_setting = INT_MAX;
1155 break;
1156 }
1157
1158 if (min)
1159 *min = od_min_setting;
1160 if (max)
1161 *max = od_max_setting;
1162 }
1163
smu_v13_0_0_dump_od_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1164 static void smu_v13_0_0_dump_od_table(struct smu_context *smu,
1165 OverDriveTableExternal_t *od_table)
1166 {
1167 struct amdgpu_device *adev = smu->adev;
1168
1169 dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin,
1170 od_table->OverDriveTable.GfxclkFmax);
1171 dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin,
1172 od_table->OverDriveTable.UclkFmax);
1173 }
1174
smu_v13_0_0_get_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1175 static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu,
1176 OverDriveTableExternal_t *od_table)
1177 {
1178 int ret = 0;
1179
1180 ret = smu_cmn_update_table(smu,
1181 SMU_TABLE_OVERDRIVE,
1182 0,
1183 (void *)od_table,
1184 false);
1185 if (ret)
1186 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1187
1188 return ret;
1189 }
1190
smu_v13_0_0_upload_overdrive_table(struct smu_context * smu,OverDriveTableExternal_t * od_table)1191 static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu,
1192 OverDriveTableExternal_t *od_table)
1193 {
1194 int ret = 0;
1195
1196 ret = smu_cmn_update_table(smu,
1197 SMU_TABLE_OVERDRIVE,
1198 0,
1199 (void *)od_table,
1200 true);
1201 if (ret)
1202 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
1203
1204 return ret;
1205 }
1206
smu_v13_0_0_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1207 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
1208 enum smu_clk_type clk_type,
1209 char *buf)
1210 {
1211 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1212 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1213 OverDriveTableExternal_t *od_table =
1214 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
1215 struct smu_13_0_dpm_table *single_dpm_table;
1216 struct smu_13_0_pcie_table *pcie_table;
1217 uint32_t gen_speed, lane_width;
1218 int i, curr_freq, size = 0;
1219 int32_t min_value, max_value;
1220 int ret = 0;
1221
1222 smu_cmn_get_sysfs_buf(&buf, &size);
1223
1224 if (amdgpu_ras_intr_triggered()) {
1225 size += sysfs_emit_at(buf, size, "unavailable\n");
1226 return size;
1227 }
1228
1229 switch (clk_type) {
1230 case SMU_SCLK:
1231 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1232 break;
1233 case SMU_MCLK:
1234 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1235 break;
1236 case SMU_SOCCLK:
1237 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1238 break;
1239 case SMU_FCLK:
1240 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1241 break;
1242 case SMU_VCLK:
1243 case SMU_VCLK1:
1244 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1245 break;
1246 case SMU_DCLK:
1247 case SMU_DCLK1:
1248 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1249 break;
1250 case SMU_DCEFCLK:
1251 single_dpm_table = &(dpm_context->dpm_tables.dcef_table);
1252 break;
1253 default:
1254 break;
1255 }
1256
1257 switch (clk_type) {
1258 case SMU_SCLK:
1259 case SMU_MCLK:
1260 case SMU_SOCCLK:
1261 case SMU_FCLK:
1262 case SMU_VCLK:
1263 case SMU_VCLK1:
1264 case SMU_DCLK:
1265 case SMU_DCLK1:
1266 case SMU_DCEFCLK:
1267 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1268 if (ret) {
1269 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1270 return ret;
1271 }
1272
1273 if (single_dpm_table->is_fine_grained) {
1274 /*
1275 * For fine grained dpms, there are only two dpm levels:
1276 * - level 0 -> min clock freq
1277 * - level 1 -> max clock freq
1278 * And the current clock frequency can be any value between them.
1279 * So, if the current clock frequency is not at level 0 or level 1,
1280 * we will fake it as three dpm levels:
1281 * - level 0 -> min clock freq
1282 * - level 1 -> current actual clock freq
1283 * - level 2 -> max clock freq
1284 */
1285 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1286 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1287 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1288 single_dpm_table->dpm_levels[0].value);
1289 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1290 curr_freq);
1291 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1292 single_dpm_table->dpm_levels[1].value);
1293 } else {
1294 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1295 single_dpm_table->dpm_levels[0].value,
1296 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1297 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1298 single_dpm_table->dpm_levels[1].value,
1299 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1300 }
1301 } else {
1302 for (i = 0; i < single_dpm_table->count; i++)
1303 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1304 i, single_dpm_table->dpm_levels[i].value,
1305 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1306 }
1307 break;
1308 case SMU_PCIE:
1309 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1310 METRICS_PCIE_RATE,
1311 &gen_speed);
1312 if (ret)
1313 return ret;
1314
1315 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1316 METRICS_PCIE_WIDTH,
1317 &lane_width);
1318 if (ret)
1319 return ret;
1320
1321 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1322 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1323 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1324 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1325 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1326 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1327 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1328 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1329 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1330 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1331 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1332 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1333 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1334 pcie_table->clk_freq[i],
1335 (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
1336 (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
1337 "*" : "");
1338 break;
1339
1340 case SMU_OD_SCLK:
1341 if (!smu_v13_0_0_is_od_feature_supported(smu,
1342 PP_OD_FEATURE_GFXCLK_BIT))
1343 break;
1344
1345 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1346 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1347 od_table->OverDriveTable.GfxclkFmin,
1348 od_table->OverDriveTable.GfxclkFmax);
1349 break;
1350
1351 case SMU_OD_MCLK:
1352 if (!smu_v13_0_0_is_od_feature_supported(smu,
1353 PP_OD_FEATURE_UCLK_BIT))
1354 break;
1355
1356 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1357 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n",
1358 od_table->OverDriveTable.UclkFmin,
1359 od_table->OverDriveTable.UclkFmax);
1360 break;
1361
1362 case SMU_OD_VDDGFX_OFFSET:
1363 if (!smu_v13_0_0_is_od_feature_supported(smu,
1364 PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1365 break;
1366
1367 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1368 size += sysfs_emit_at(buf, size, "%dmV\n",
1369 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[0]);
1370 break;
1371
1372 case SMU_OD_FAN_CURVE:
1373 if (!smu_v13_0_0_is_od_feature_supported(smu,
1374 PP_OD_FEATURE_FAN_CURVE_BIT))
1375 break;
1376
1377 size += sysfs_emit_at(buf, size, "OD_FAN_CURVE:\n");
1378 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++)
1379 size += sysfs_emit_at(buf, size, "%d: %dC %d%%\n",
1380 i,
1381 (int)od_table->OverDriveTable.FanLinearTempPoints[i],
1382 (int)od_table->OverDriveTable.FanLinearPwmPoints[i]);
1383
1384 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1385 smu_v13_0_0_get_od_setting_limits(smu,
1386 PP_OD_FEATURE_FAN_CURVE_TEMP,
1387 &min_value,
1388 &max_value);
1389 size += sysfs_emit_at(buf, size, "FAN_CURVE(hotspot temp): %uC %uC\n",
1390 min_value, max_value);
1391
1392 smu_v13_0_0_get_od_setting_limits(smu,
1393 PP_OD_FEATURE_FAN_CURVE_PWM,
1394 &min_value,
1395 &max_value);
1396 size += sysfs_emit_at(buf, size, "FAN_CURVE(fan speed): %u%% %u%%\n",
1397 min_value, max_value);
1398
1399 break;
1400
1401 case SMU_OD_ACOUSTIC_LIMIT:
1402 if (!smu_v13_0_0_is_od_feature_supported(smu,
1403 PP_OD_FEATURE_FAN_CURVE_BIT))
1404 break;
1405
1406 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_LIMIT:\n");
1407 size += sysfs_emit_at(buf, size, "%d\n",
1408 (int)od_table->OverDriveTable.AcousticLimitRpmThreshold);
1409
1410 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1411 smu_v13_0_0_get_od_setting_limits(smu,
1412 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1413 &min_value,
1414 &max_value);
1415 size += sysfs_emit_at(buf, size, "ACOUSTIC_LIMIT: %u %u\n",
1416 min_value, max_value);
1417 break;
1418
1419 case SMU_OD_ACOUSTIC_TARGET:
1420 if (!smu_v13_0_0_is_od_feature_supported(smu,
1421 PP_OD_FEATURE_FAN_CURVE_BIT))
1422 break;
1423
1424 size += sysfs_emit_at(buf, size, "OD_ACOUSTIC_TARGET:\n");
1425 size += sysfs_emit_at(buf, size, "%d\n",
1426 (int)od_table->OverDriveTable.AcousticTargetRpmThreshold);
1427
1428 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1429 smu_v13_0_0_get_od_setting_limits(smu,
1430 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1431 &min_value,
1432 &max_value);
1433 size += sysfs_emit_at(buf, size, "ACOUSTIC_TARGET: %u %u\n",
1434 min_value, max_value);
1435 break;
1436
1437 case SMU_OD_FAN_TARGET_TEMPERATURE:
1438 if (!smu_v13_0_0_is_od_feature_supported(smu,
1439 PP_OD_FEATURE_FAN_CURVE_BIT))
1440 break;
1441
1442 size += sysfs_emit_at(buf, size, "FAN_TARGET_TEMPERATURE:\n");
1443 size += sysfs_emit_at(buf, size, "%d\n",
1444 (int)od_table->OverDriveTable.FanTargetTemperature);
1445
1446 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1447 smu_v13_0_0_get_od_setting_limits(smu,
1448 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1449 &min_value,
1450 &max_value);
1451 size += sysfs_emit_at(buf, size, "TARGET_TEMPERATURE: %u %u\n",
1452 min_value, max_value);
1453 break;
1454
1455 case SMU_OD_FAN_MINIMUM_PWM:
1456 if (!smu_v13_0_0_is_od_feature_supported(smu,
1457 PP_OD_FEATURE_FAN_CURVE_BIT))
1458 break;
1459
1460 size += sysfs_emit_at(buf, size, "FAN_MINIMUM_PWM:\n");
1461 size += sysfs_emit_at(buf, size, "%d\n",
1462 (int)od_table->OverDriveTable.FanMinimumPwm);
1463
1464 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1465 smu_v13_0_0_get_od_setting_limits(smu,
1466 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1467 &min_value,
1468 &max_value);
1469 size += sysfs_emit_at(buf, size, "MINIMUM_PWM: %u %u\n",
1470 min_value, max_value);
1471 break;
1472
1473 case SMU_OD_FAN_ZERO_RPM_ENABLE:
1474 if (!smu_v13_0_0_is_od_feature_supported(smu,
1475 PP_OD_FEATURE_ZERO_FAN_BIT))
1476 break;
1477
1478 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_ENABLE:\n");
1479 size += sysfs_emit_at(buf, size, "%d\n",
1480 (int)od_table->OverDriveTable.FanZeroRpmEnable);
1481
1482 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1483 smu_v13_0_0_get_od_setting_limits(smu,
1484 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1485 &min_value,
1486 &max_value);
1487 size += sysfs_emit_at(buf, size, "ZERO_RPM_ENABLE: %u %u\n",
1488 min_value, max_value);
1489 break;
1490
1491 case SMU_OD_FAN_ZERO_RPM_STOP_TEMP:
1492 if (!smu_v13_0_0_is_od_feature_supported(smu,
1493 PP_OD_FEATURE_ZERO_FAN_BIT))
1494 break;
1495
1496 size += sysfs_emit_at(buf, size, "FAN_ZERO_RPM_STOP_TEMPERATURE:\n");
1497 size += sysfs_emit_at(buf, size, "%d\n",
1498 (int)od_table->OverDriveTable.FanZeroRpmStopTemp);
1499
1500 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1501 smu_v13_0_0_get_od_setting_limits(smu,
1502 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1503 &min_value,
1504 &max_value);
1505 size += sysfs_emit_at(buf, size, "ZERO_RPM_STOP_TEMPERATURE: %u %u\n",
1506 min_value, max_value);
1507 break;
1508
1509 case SMU_OD_RANGE:
1510 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&
1511 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&
1512 !smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT))
1513 break;
1514
1515 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1516
1517 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1518 smu_v13_0_0_get_od_setting_limits(smu,
1519 PP_OD_FEATURE_GFXCLK_FMIN,
1520 &min_value,
1521 NULL);
1522 smu_v13_0_0_get_od_setting_limits(smu,
1523 PP_OD_FEATURE_GFXCLK_FMAX,
1524 NULL,
1525 &max_value);
1526 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1527 min_value, max_value);
1528 }
1529
1530 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1531 smu_v13_0_0_get_od_setting_limits(smu,
1532 PP_OD_FEATURE_UCLK_FMIN,
1533 &min_value,
1534 NULL);
1535 smu_v13_0_0_get_od_setting_limits(smu,
1536 PP_OD_FEATURE_UCLK_FMAX,
1537 NULL,
1538 &max_value);
1539 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1540 min_value, max_value);
1541 }
1542
1543 if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1544 smu_v13_0_0_get_od_setting_limits(smu,
1545 PP_OD_FEATURE_GFX_VF_CURVE,
1546 &min_value,
1547 &max_value);
1548 size += sysfs_emit_at(buf, size, "VDDGFX_OFFSET: %7dmv %10dmv\n",
1549 min_value, max_value);
1550 }
1551 break;
1552
1553 default:
1554 break;
1555 }
1556
1557 return size;
1558 }
1559
1560
smu_v13_0_0_od_restore_table_single(struct smu_context * smu,long input)1561 static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input)
1562 {
1563 struct smu_table_context *table_context = &smu->smu_table;
1564 OverDriveTableExternal_t *boot_overdrive_table =
1565 (OverDriveTableExternal_t *)table_context->boot_overdrive_table;
1566 OverDriveTableExternal_t *od_table =
1567 (OverDriveTableExternal_t *)table_context->overdrive_table;
1568 struct amdgpu_device *adev = smu->adev;
1569 int i;
1570
1571 switch (input) {
1572 case PP_OD_EDIT_FAN_CURVE:
1573 for (i = 0; i < NUM_OD_FAN_MAX_POINTS; i++) {
1574 od_table->OverDriveTable.FanLinearTempPoints[i] =
1575 boot_overdrive_table->OverDriveTable.FanLinearTempPoints[i];
1576 od_table->OverDriveTable.FanLinearPwmPoints[i] =
1577 boot_overdrive_table->OverDriveTable.FanLinearPwmPoints[i];
1578 }
1579 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1580 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1581 break;
1582 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1583 od_table->OverDriveTable.AcousticLimitRpmThreshold =
1584 boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;
1585 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1586 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1587 break;
1588 case PP_OD_EDIT_ACOUSTIC_TARGET:
1589 od_table->OverDriveTable.AcousticTargetRpmThreshold =
1590 boot_overdrive_table->OverDriveTable.AcousticTargetRpmThreshold;
1591 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1592 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1593 break;
1594 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1595 od_table->OverDriveTable.FanTargetTemperature =
1596 boot_overdrive_table->OverDriveTable.FanTargetTemperature;
1597 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1598 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1599 break;
1600 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1601 od_table->OverDriveTable.FanMinimumPwm =
1602 boot_overdrive_table->OverDriveTable.FanMinimumPwm;
1603 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1604 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1605 break;
1606 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1607 od_table->OverDriveTable.FanZeroRpmEnable =
1608 boot_overdrive_table->OverDriveTable.FanZeroRpmEnable;
1609 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1610 break;
1611 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1612 od_table->OverDriveTable.FanZeroRpmStopTemp =
1613 boot_overdrive_table->OverDriveTable.FanZeroRpmStopTemp;
1614 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1615 break;
1616 default:
1617 dev_info(adev->dev, "Invalid table index: %ld\n", input);
1618 return -EINVAL;
1619 }
1620
1621 return 0;
1622 }
1623
smu_v13_0_0_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1624 static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu,
1625 enum PP_OD_DPM_TABLE_COMMAND type,
1626 long input[],
1627 uint32_t size)
1628 {
1629 struct smu_table_context *table_context = &smu->smu_table;
1630 OverDriveTableExternal_t *od_table =
1631 (OverDriveTableExternal_t *)table_context->overdrive_table;
1632 struct amdgpu_device *adev = smu->adev;
1633 uint32_t offset_of_voltageoffset;
1634 int32_t minimum, maximum;
1635 uint32_t feature_ctrlmask;
1636 int i, ret = 0;
1637
1638 switch (type) {
1639 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1640 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) {
1641 dev_warn(adev->dev, "GFXCLK_LIMITS setting not supported!\n");
1642 return -ENOTSUPP;
1643 }
1644
1645 for (i = 0; i < size; i += 2) {
1646 if (i + 2 > size) {
1647 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1648 return -EINVAL;
1649 }
1650
1651 switch (input[i]) {
1652 case 0:
1653 smu_v13_0_0_get_od_setting_limits(smu,
1654 PP_OD_FEATURE_GFXCLK_FMIN,
1655 &minimum,
1656 &maximum);
1657 if (input[i + 1] < minimum ||
1658 input[i + 1] > maximum) {
1659 dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n",
1660 input[i + 1], minimum, maximum);
1661 return -EINVAL;
1662 }
1663
1664 od_table->OverDriveTable.GfxclkFmin = input[i + 1];
1665 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1666 break;
1667
1668 case 1:
1669 smu_v13_0_0_get_od_setting_limits(smu,
1670 PP_OD_FEATURE_GFXCLK_FMAX,
1671 &minimum,
1672 &maximum);
1673 if (input[i + 1] < minimum ||
1674 input[i + 1] > maximum) {
1675 dev_info(adev->dev, "GfxclkFmax (%ld) must be within [%u, %u]!\n",
1676 input[i + 1], minimum, maximum);
1677 return -EINVAL;
1678 }
1679
1680 od_table->OverDriveTable.GfxclkFmax = input[i + 1];
1681 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT;
1682 break;
1683
1684 default:
1685 dev_info(adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
1686 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1687 return -EINVAL;
1688 }
1689 }
1690
1691 if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) {
1692 dev_err(adev->dev,
1693 "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n",
1694 (uint32_t)od_table->OverDriveTable.GfxclkFmin,
1695 (uint32_t)od_table->OverDriveTable.GfxclkFmax);
1696 return -EINVAL;
1697 }
1698 break;
1699
1700 case PP_OD_EDIT_MCLK_VDDC_TABLE:
1701 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT)) {
1702 dev_warn(adev->dev, "UCLK_LIMITS setting not supported!\n");
1703 return -ENOTSUPP;
1704 }
1705
1706 for (i = 0; i < size; i += 2) {
1707 if (i + 2 > size) {
1708 dev_info(adev->dev, "invalid number of input parameters %d\n", size);
1709 return -EINVAL;
1710 }
1711
1712 switch (input[i]) {
1713 case 0:
1714 smu_v13_0_0_get_od_setting_limits(smu,
1715 PP_OD_FEATURE_UCLK_FMIN,
1716 &minimum,
1717 &maximum);
1718 if (input[i + 1] < minimum ||
1719 input[i + 1] > maximum) {
1720 dev_info(adev->dev, "UclkFmin (%ld) must be within [%u, %u]!\n",
1721 input[i + 1], minimum, maximum);
1722 return -EINVAL;
1723 }
1724
1725 od_table->OverDriveTable.UclkFmin = input[i + 1];
1726 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1727 break;
1728
1729 case 1:
1730 smu_v13_0_0_get_od_setting_limits(smu,
1731 PP_OD_FEATURE_UCLK_FMAX,
1732 &minimum,
1733 &maximum);
1734 if (input[i + 1] < minimum ||
1735 input[i + 1] > maximum) {
1736 dev_info(adev->dev, "UclkFmax (%ld) must be within [%u, %u]!\n",
1737 input[i + 1], minimum, maximum);
1738 return -EINVAL;
1739 }
1740
1741 od_table->OverDriveTable.UclkFmax = input[i + 1];
1742 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_UCLK_BIT;
1743 break;
1744
1745 default:
1746 dev_info(adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
1747 dev_info(adev->dev, "Supported indices: [0:min,1:max]\n");
1748 return -EINVAL;
1749 }
1750 }
1751
1752 if (od_table->OverDriveTable.UclkFmin > od_table->OverDriveTable.UclkFmax) {
1753 dev_err(adev->dev,
1754 "Invalid setting: UclkFmin(%u) is bigger than UclkFmax(%u)\n",
1755 (uint32_t)od_table->OverDriveTable.UclkFmin,
1756 (uint32_t)od_table->OverDriveTable.UclkFmax);
1757 return -EINVAL;
1758 }
1759 break;
1760
1761 case PP_OD_EDIT_VDDGFX_OFFSET:
1762 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFX_VF_CURVE_BIT)) {
1763 dev_warn(adev->dev, "Gfx offset setting not supported!\n");
1764 return -ENOTSUPP;
1765 }
1766
1767 smu_v13_0_0_get_od_setting_limits(smu,
1768 PP_OD_FEATURE_GFX_VF_CURVE,
1769 &minimum,
1770 &maximum);
1771 if (input[0] < minimum ||
1772 input[0] > maximum) {
1773 dev_info(adev->dev, "Voltage offset (%ld) must be within [%d, %d]!\n",
1774 input[0], minimum, maximum);
1775 return -EINVAL;
1776 }
1777
1778 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
1779 od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] = input[0];
1780 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT);
1781 break;
1782
1783 case PP_OD_EDIT_FAN_CURVE:
1784 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1785 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1786 return -ENOTSUPP;
1787 }
1788
1789 if (input[0] >= NUM_OD_FAN_MAX_POINTS - 1 ||
1790 input[0] < 0)
1791 return -EINVAL;
1792
1793 smu_v13_0_0_get_od_setting_limits(smu,
1794 PP_OD_FEATURE_FAN_CURVE_TEMP,
1795 &minimum,
1796 &maximum);
1797 if (input[1] < minimum ||
1798 input[1] > maximum) {
1799 dev_info(adev->dev, "Fan curve temp setting(%ld) must be within [%d, %d]!\n",
1800 input[1], minimum, maximum);
1801 return -EINVAL;
1802 }
1803
1804 smu_v13_0_0_get_od_setting_limits(smu,
1805 PP_OD_FEATURE_FAN_CURVE_PWM,
1806 &minimum,
1807 &maximum);
1808 if (input[2] < minimum ||
1809 input[2] > maximum) {
1810 dev_info(adev->dev, "Fan curve pwm setting(%ld) must be within [%d, %d]!\n",
1811 input[2], minimum, maximum);
1812 return -EINVAL;
1813 }
1814
1815 od_table->OverDriveTable.FanLinearTempPoints[input[0]] = input[1];
1816 od_table->OverDriveTable.FanLinearPwmPoints[input[0]] = input[2];
1817 od_table->OverDriveTable.FanMode = FAN_MODE_MANUAL_LINEAR;
1818 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1819 break;
1820
1821 case PP_OD_EDIT_ACOUSTIC_LIMIT:
1822 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1823 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1824 return -ENOTSUPP;
1825 }
1826
1827 smu_v13_0_0_get_od_setting_limits(smu,
1828 PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT,
1829 &minimum,
1830 &maximum);
1831 if (input[0] < minimum ||
1832 input[0] > maximum) {
1833 dev_info(adev->dev, "acoustic limit threshold setting(%ld) must be within [%d, %d]!\n",
1834 input[0], minimum, maximum);
1835 return -EINVAL;
1836 }
1837
1838 od_table->OverDriveTable.AcousticLimitRpmThreshold = input[0];
1839 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1840 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1841 break;
1842
1843 case PP_OD_EDIT_ACOUSTIC_TARGET:
1844 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1845 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1846 return -ENOTSUPP;
1847 }
1848
1849 smu_v13_0_0_get_od_setting_limits(smu,
1850 PP_OD_FEATURE_FAN_ACOUSTIC_TARGET,
1851 &minimum,
1852 &maximum);
1853 if (input[0] < minimum ||
1854 input[0] > maximum) {
1855 dev_info(adev->dev, "acoustic target threshold setting(%ld) must be within [%d, %d]!\n",
1856 input[0], minimum, maximum);
1857 return -EINVAL;
1858 }
1859
1860 od_table->OverDriveTable.AcousticTargetRpmThreshold = input[0];
1861 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1862 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1863 break;
1864
1865 case PP_OD_EDIT_FAN_TARGET_TEMPERATURE:
1866 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1867 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1868 return -ENOTSUPP;
1869 }
1870
1871 smu_v13_0_0_get_od_setting_limits(smu,
1872 PP_OD_FEATURE_FAN_TARGET_TEMPERATURE,
1873 &minimum,
1874 &maximum);
1875 if (input[0] < minimum ||
1876 input[0] > maximum) {
1877 dev_info(adev->dev, "fan target temperature setting(%ld) must be within [%d, %d]!\n",
1878 input[0], minimum, maximum);
1879 return -EINVAL;
1880 }
1881
1882 od_table->OverDriveTable.FanTargetTemperature = input[0];
1883 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1884 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1885 break;
1886
1887 case PP_OD_EDIT_FAN_MINIMUM_PWM:
1888 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_FAN_CURVE_BIT)) {
1889 dev_warn(adev->dev, "Fan curve setting not supported!\n");
1890 return -ENOTSUPP;
1891 }
1892
1893 smu_v13_0_0_get_od_setting_limits(smu,
1894 PP_OD_FEATURE_FAN_MINIMUM_PWM,
1895 &minimum,
1896 &maximum);
1897 if (input[0] < minimum ||
1898 input[0] > maximum) {
1899 dev_info(adev->dev, "fan minimum pwm setting(%ld) must be within [%d, %d]!\n",
1900 input[0], minimum, maximum);
1901 return -EINVAL;
1902 }
1903
1904 od_table->OverDriveTable.FanMinimumPwm = input[0];
1905 od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;
1906 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
1907 break;
1908
1909 case PP_OD_EDIT_FAN_ZERO_RPM_ENABLE:
1910 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1911 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1912 return -ENOTSUPP;
1913 }
1914
1915 smu_v13_0_0_get_od_setting_limits(smu,
1916 PP_OD_FEATURE_FAN_ZERO_RPM_ENABLE,
1917 &minimum,
1918 &maximum);
1919 if (input[0] < minimum ||
1920 input[0] > maximum) {
1921 dev_info(adev->dev, "zero RPM enable setting(%ld) must be within [%d, %d]!\n",
1922 input[0], minimum, maximum);
1923 return -EINVAL;
1924 }
1925
1926 od_table->OverDriveTable.FanZeroRpmEnable = input[0];
1927 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1928 break;
1929
1930 case PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP:
1931 if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_ZERO_FAN_BIT)) {
1932 dev_warn(adev->dev, "Zero RPM setting not supported!\n");
1933 return -ENOTSUPP;
1934 }
1935
1936 smu_v13_0_0_get_od_setting_limits(smu,
1937 PP_OD_FEATURE_FAN_ZERO_RPM_STOP_TEMP,
1938 &minimum,
1939 &maximum);
1940 if (input[0] < minimum ||
1941 input[0] > maximum) {
1942 dev_info(adev->dev, "zero RPM stop temperature setting(%ld) must be within [%d, %d]!\n",
1943 input[0], minimum, maximum);
1944 return -EINVAL;
1945 }
1946
1947 od_table->OverDriveTable.FanZeroRpmStopTemp = input[0];
1948 od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_ZERO_FAN_BIT);
1949 break;
1950
1951 case PP_OD_RESTORE_DEFAULT_TABLE:
1952 if (size == 1) {
1953 ret = smu_v13_0_0_od_restore_table_single(smu, input[0]);
1954 if (ret)
1955 return ret;
1956 } else {
1957 feature_ctrlmask = od_table->OverDriveTable.FeatureCtrlMask;
1958 memcpy(od_table,
1959 table_context->boot_overdrive_table,
1960 sizeof(OverDriveTableExternal_t));
1961 od_table->OverDriveTable.FeatureCtrlMask = feature_ctrlmask;
1962 }
1963 fallthrough;
1964 case PP_OD_COMMIT_DPM_TABLE:
1965 /*
1966 * The member below instructs PMFW the settings focused in
1967 * this single operation.
1968 * `uint32_t FeatureCtrlMask;`
1969 * It does not contain actual informations about user's custom
1970 * settings. Thus we do not cache it.
1971 */
1972 offset_of_voltageoffset = offsetof(OverDriveTable_t, VoltageOffsetPerZoneBoundary);
1973 if (memcmp((u8 *)od_table + offset_of_voltageoffset,
1974 table_context->user_overdrive_table + offset_of_voltageoffset,
1975 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset)) {
1976 smu_v13_0_0_dump_od_table(smu, od_table);
1977
1978 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
1979 if (ret) {
1980 dev_err(adev->dev, "Failed to upload overdrive table!\n");
1981 return ret;
1982 }
1983
1984 od_table->OverDriveTable.FeatureCtrlMask = 0;
1985 memcpy(table_context->user_overdrive_table + offset_of_voltageoffset,
1986 (u8 *)od_table + offset_of_voltageoffset,
1987 sizeof(OverDriveTableExternal_t) - offset_of_voltageoffset);
1988
1989 if (!memcmp(table_context->user_overdrive_table,
1990 table_context->boot_overdrive_table,
1991 sizeof(OverDriveTableExternal_t)))
1992 smu->user_dpm_profile.user_od = false;
1993 else
1994 smu->user_dpm_profile.user_od = true;
1995 }
1996 break;
1997
1998 default:
1999 return -ENOSYS;
2000 }
2001
2002 return ret;
2003 }
2004
smu_v13_0_0_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)2005 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
2006 enum smu_clk_type clk_type,
2007 uint32_t mask)
2008 {
2009 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
2010 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2011 struct smu_13_0_dpm_table *single_dpm_table;
2012 uint32_t soft_min_level, soft_max_level;
2013 uint32_t min_freq, max_freq;
2014 int ret = 0;
2015
2016 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2017 soft_max_level = mask ? (fls(mask) - 1) : 0;
2018
2019 switch (clk_type) {
2020 case SMU_GFXCLK:
2021 case SMU_SCLK:
2022 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
2023 break;
2024 case SMU_MCLK:
2025 case SMU_UCLK:
2026 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
2027 break;
2028 case SMU_SOCCLK:
2029 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
2030 break;
2031 case SMU_FCLK:
2032 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
2033 break;
2034 case SMU_VCLK:
2035 case SMU_VCLK1:
2036 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
2037 break;
2038 case SMU_DCLK:
2039 case SMU_DCLK1:
2040 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
2041 break;
2042 default:
2043 break;
2044 }
2045
2046 switch (clk_type) {
2047 case SMU_GFXCLK:
2048 case SMU_SCLK:
2049 case SMU_MCLK:
2050 case SMU_UCLK:
2051 case SMU_SOCCLK:
2052 case SMU_FCLK:
2053 case SMU_VCLK:
2054 case SMU_VCLK1:
2055 case SMU_DCLK:
2056 case SMU_DCLK1:
2057 if (single_dpm_table->is_fine_grained) {
2058 /* There is only 2 levels for fine grained DPM */
2059 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
2060 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
2061 } else {
2062 if ((soft_max_level >= single_dpm_table->count) ||
2063 (soft_min_level >= single_dpm_table->count))
2064 return -EINVAL;
2065 }
2066
2067 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
2068 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
2069
2070 ret = smu_v13_0_set_soft_freq_limited_range(smu,
2071 clk_type,
2072 min_freq,
2073 max_freq,
2074 false);
2075 break;
2076 case SMU_DCEFCLK:
2077 case SMU_PCIE:
2078 default:
2079 break;
2080 }
2081
2082 return ret;
2083 }
2084
2085 static const struct smu_temperature_range smu13_thermal_policy[] = {
2086 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
2087 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
2088 };
2089
smu_v13_0_0_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2090 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
2091 struct smu_temperature_range *range)
2092 {
2093 struct smu_table_context *table_context = &smu->smu_table;
2094 struct smu_13_0_0_powerplay_table *powerplay_table =
2095 table_context->power_play_table;
2096 PPTable_t *pptable = smu->smu_table.driver_pptable;
2097
2098 if (amdgpu_sriov_vf(smu->adev))
2099 return 0;
2100
2101 if (!range)
2102 return -EINVAL;
2103
2104 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
2105
2106 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
2107 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2108 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
2109 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2110 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
2111 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2112 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
2113 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2114 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
2115 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2116 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
2117 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2118 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2119 range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
2120
2121 return 0;
2122 }
2123
smu_v13_0_0_get_gpu_metrics(struct smu_context * smu,void ** table)2124 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
2125 void **table)
2126 {
2127 struct smu_table_context *smu_table = &smu->smu_table;
2128 struct gpu_metrics_v1_3 *gpu_metrics =
2129 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2130 SmuMetricsExternal_t metrics_ext;
2131 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
2132 int ret = 0;
2133
2134 ret = smu_cmn_get_metrics_table(smu,
2135 &metrics_ext,
2136 true);
2137 if (ret)
2138 return ret;
2139
2140 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2141
2142 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
2143 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
2144 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
2145 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
2146 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
2147 gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
2148 metrics->AvgTemperature[TEMP_VR_MEM1]);
2149
2150 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
2151 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
2152 gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
2153 metrics->Vcn1ActivityPercentage);
2154
2155 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
2156 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
2157
2158 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2159 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
2160 else
2161 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
2162
2163 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
2164 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
2165 else
2166 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
2167
2168 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
2169 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
2170 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
2171 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
2172
2173 gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
2174 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
2175 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
2176 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
2177 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
2178 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
2179 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
2180
2181 gpu_metrics->throttle_status =
2182 smu_v13_0_get_throttler_status(metrics);
2183 gpu_metrics->indep_throttle_status =
2184 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
2185 smu_v13_0_0_throttler_map);
2186
2187 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
2188
2189 gpu_metrics->pcie_link_width = metrics->PcieWidth;
2190 if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
2191 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
2192 else
2193 gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
2194
2195 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2196
2197 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
2198 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
2199 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
2200
2201 *table = (void *)gpu_metrics;
2202
2203 return sizeof(struct gpu_metrics_v1_3);
2204 }
2205
smu_v13_0_0_set_supported_od_feature_mask(struct smu_context * smu)2206 static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu)
2207 {
2208 struct amdgpu_device *adev = smu->adev;
2209
2210 if (smu_v13_0_0_is_od_feature_supported(smu,
2211 PP_OD_FEATURE_FAN_CURVE_BIT))
2212 adev->pm.od_feature_mask |= OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE |
2213 OD_OPS_SUPPORT_FAN_CURVE_SET |
2214 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE |
2215 OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET |
2216 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE |
2217 OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET |
2218 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |
2219 OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |
2220 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |
2221 OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET |
2222 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_RETRIEVE |
2223 OD_OPS_SUPPORT_FAN_ZERO_RPM_ENABLE_SET |
2224 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_RETRIEVE |
2225 OD_OPS_SUPPORT_FAN_ZERO_RPM_STOP_TEMP_SET;
2226 }
2227
smu_v13_0_0_set_default_od_settings(struct smu_context * smu)2228 static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu)
2229 {
2230 OverDriveTableExternal_t *od_table =
2231 (OverDriveTableExternal_t *)smu->smu_table.overdrive_table;
2232 OverDriveTableExternal_t *boot_od_table =
2233 (OverDriveTableExternal_t *)smu->smu_table.boot_overdrive_table;
2234 OverDriveTableExternal_t *user_od_table =
2235 (OverDriveTableExternal_t *)smu->smu_table.user_overdrive_table;
2236 OverDriveTableExternal_t user_od_table_bak;
2237 int ret = 0;
2238 int i;
2239
2240 ret = smu_v13_0_0_get_overdrive_table(smu, boot_od_table);
2241 if (ret)
2242 return ret;
2243
2244 smu_v13_0_0_dump_od_table(smu, boot_od_table);
2245
2246 memcpy(od_table,
2247 boot_od_table,
2248 sizeof(OverDriveTableExternal_t));
2249
2250 /*
2251 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2252 * but we have to preserve user defined values in "user_od_table".
2253 */
2254 if (!smu->adev->in_suspend) {
2255 memcpy(user_od_table,
2256 boot_od_table,
2257 sizeof(OverDriveTableExternal_t));
2258 smu->user_dpm_profile.user_od = false;
2259 } else if (smu->user_dpm_profile.user_od) {
2260 memcpy(&user_od_table_bak,
2261 user_od_table,
2262 sizeof(OverDriveTableExternal_t));
2263 memcpy(user_od_table,
2264 boot_od_table,
2265 sizeof(OverDriveTableExternal_t));
2266 user_od_table->OverDriveTable.GfxclkFmin =
2267 user_od_table_bak.OverDriveTable.GfxclkFmin;
2268 user_od_table->OverDriveTable.GfxclkFmax =
2269 user_od_table_bak.OverDriveTable.GfxclkFmax;
2270 user_od_table->OverDriveTable.UclkFmin =
2271 user_od_table_bak.OverDriveTable.UclkFmin;
2272 user_od_table->OverDriveTable.UclkFmax =
2273 user_od_table_bak.OverDriveTable.UclkFmax;
2274 for (i = 0; i < PP_NUM_OD_VF_CURVE_POINTS; i++)
2275 user_od_table->OverDriveTable.VoltageOffsetPerZoneBoundary[i] =
2276 user_od_table_bak.OverDriveTable.VoltageOffsetPerZoneBoundary[i];
2277 for (i = 0; i < NUM_OD_FAN_MAX_POINTS - 1; i++) {
2278 user_od_table->OverDriveTable.FanLinearTempPoints[i] =
2279 user_od_table_bak.OverDriveTable.FanLinearTempPoints[i];
2280 user_od_table->OverDriveTable.FanLinearPwmPoints[i] =
2281 user_od_table_bak.OverDriveTable.FanLinearPwmPoints[i];
2282 }
2283 user_od_table->OverDriveTable.AcousticLimitRpmThreshold =
2284 user_od_table_bak.OverDriveTable.AcousticLimitRpmThreshold;
2285 user_od_table->OverDriveTable.AcousticTargetRpmThreshold =
2286 user_od_table_bak.OverDriveTable.AcousticTargetRpmThreshold;
2287 user_od_table->OverDriveTable.FanTargetTemperature =
2288 user_od_table_bak.OverDriveTable.FanTargetTemperature;
2289 user_od_table->OverDriveTable.FanMinimumPwm =
2290 user_od_table_bak.OverDriveTable.FanMinimumPwm;
2291 user_od_table->OverDriveTable.FanZeroRpmEnable =
2292 user_od_table_bak.OverDriveTable.FanZeroRpmEnable;
2293 user_od_table->OverDriveTable.FanZeroRpmStopTemp =
2294 user_od_table_bak.OverDriveTable.FanZeroRpmStopTemp;
2295 }
2296
2297 smu_v13_0_0_set_supported_od_feature_mask(smu);
2298
2299 return 0;
2300 }
2301
smu_v13_0_0_restore_user_od_settings(struct smu_context * smu)2302 static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu)
2303 {
2304 struct smu_table_context *table_context = &smu->smu_table;
2305 OverDriveTableExternal_t *od_table = table_context->overdrive_table;
2306 OverDriveTableExternal_t *user_od_table = table_context->user_overdrive_table;
2307 int res;
2308
2309 user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) |
2310 BIT(PP_OD_FEATURE_UCLK_BIT) |
2311 BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) |
2312 BIT(PP_OD_FEATURE_FAN_CURVE_BIT);
2313 res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table);
2314 user_od_table->OverDriveTable.FeatureCtrlMask = 0;
2315 if (res == 0)
2316 memcpy(od_table, user_od_table, sizeof(OverDriveTableExternal_t));
2317
2318 return res;
2319 }
2320
smu_v13_0_0_populate_umd_state_clk(struct smu_context * smu)2321 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
2322 {
2323 struct smu_13_0_dpm_context *dpm_context =
2324 smu->smu_dpm.dpm_context;
2325 struct smu_13_0_dpm_table *gfx_table =
2326 &dpm_context->dpm_tables.gfx_table;
2327 struct smu_13_0_dpm_table *mem_table =
2328 &dpm_context->dpm_tables.uclk_table;
2329 struct smu_13_0_dpm_table *soc_table =
2330 &dpm_context->dpm_tables.soc_table;
2331 struct smu_13_0_dpm_table *vclk_table =
2332 &dpm_context->dpm_tables.vclk_table;
2333 struct smu_13_0_dpm_table *dclk_table =
2334 &dpm_context->dpm_tables.dclk_table;
2335 struct smu_13_0_dpm_table *fclk_table =
2336 &dpm_context->dpm_tables.fclk_table;
2337 struct smu_umd_pstate_table *pstate_table =
2338 &smu->pstate_table;
2339 struct smu_table_context *table_context = &smu->smu_table;
2340 PPTable_t *pptable = table_context->driver_pptable;
2341 DriverReportedClocks_t driver_clocks =
2342 pptable->SkuTable.DriverReportedClocks;
2343
2344 pstate_table->gfxclk_pstate.min = gfx_table->min;
2345 if (driver_clocks.GameClockAc &&
2346 (driver_clocks.GameClockAc < gfx_table->max))
2347 pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
2348 else
2349 pstate_table->gfxclk_pstate.peak = gfx_table->max;
2350
2351 pstate_table->uclk_pstate.min = mem_table->min;
2352 pstate_table->uclk_pstate.peak = mem_table->max;
2353
2354 pstate_table->socclk_pstate.min = soc_table->min;
2355 pstate_table->socclk_pstate.peak = soc_table->max;
2356
2357 pstate_table->vclk_pstate.min = vclk_table->min;
2358 pstate_table->vclk_pstate.peak = vclk_table->max;
2359
2360 pstate_table->dclk_pstate.min = dclk_table->min;
2361 pstate_table->dclk_pstate.peak = dclk_table->max;
2362
2363 pstate_table->fclk_pstate.min = fclk_table->min;
2364 pstate_table->fclk_pstate.peak = fclk_table->max;
2365
2366 if (driver_clocks.BaseClockAc &&
2367 driver_clocks.BaseClockAc < gfx_table->max)
2368 pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc;
2369 else
2370 pstate_table->gfxclk_pstate.standard = gfx_table->max;
2371 pstate_table->uclk_pstate.standard = mem_table->max;
2372 pstate_table->socclk_pstate.standard = soc_table->min;
2373 pstate_table->vclk_pstate.standard = vclk_table->min;
2374 pstate_table->dclk_pstate.standard = dclk_table->min;
2375 pstate_table->fclk_pstate.standard = fclk_table->min;
2376
2377 return 0;
2378 }
2379
smu_v13_0_0_get_unique_id(struct smu_context * smu)2380 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
2381 {
2382 struct smu_table_context *smu_table = &smu->smu_table;
2383 SmuMetrics_t *metrics =
2384 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
2385 struct amdgpu_device *adev = smu->adev;
2386 uint32_t upper32 = 0, lower32 = 0;
2387 int ret;
2388
2389 ret = smu_cmn_get_metrics_table(smu, NULL, false);
2390 if (ret)
2391 goto out;
2392
2393 upper32 = metrics->PublicSerialNumberUpper;
2394 lower32 = metrics->PublicSerialNumberLower;
2395
2396 out:
2397 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2398 }
2399
smu_v13_0_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)2400 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
2401 uint32_t *speed)
2402 {
2403 int ret;
2404
2405 if (!speed)
2406 return -EINVAL;
2407
2408 ret = smu_v13_0_0_get_smu_metrics_data(smu,
2409 METRICS_CURR_FANPWM,
2410 speed);
2411 if (ret) {
2412 dev_err(smu->adev->dev, "Failed to get fan speed(PWM)!");
2413 return ret;
2414 }
2415
2416 /* Convert the PMFW output which is in percent to pwm(255) based */
2417 *speed = min(*speed * 255 / 100, (uint32_t)255);
2418
2419 return 0;
2420 }
2421
smu_v13_0_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)2422 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
2423 uint32_t *speed)
2424 {
2425 if (!speed)
2426 return -EINVAL;
2427
2428 return smu_v13_0_0_get_smu_metrics_data(smu,
2429 METRICS_CURR_FANSPEED,
2430 speed);
2431 }
2432
smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context * smu)2433 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
2434 {
2435 struct smu_table_context *table_context = &smu->smu_table;
2436 PPTable_t *pptable = table_context->driver_pptable;
2437 SkuTable_t *skutable = &pptable->SkuTable;
2438
2439 /*
2440 * Skip the MGpuFanBoost setting for those ASICs
2441 * which do not support it
2442 */
2443 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
2444 return 0;
2445
2446 return smu_cmn_send_smc_msg_with_param(smu,
2447 SMU_MSG_SetMGpuFanBoostLimitRpm,
2448 0,
2449 NULL);
2450 }
2451
smu_v13_0_0_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2452 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
2453 uint32_t *current_power_limit,
2454 uint32_t *default_power_limit,
2455 uint32_t *max_power_limit,
2456 uint32_t *min_power_limit)
2457 {
2458 struct smu_table_context *table_context = &smu->smu_table;
2459 struct smu_13_0_0_powerplay_table *powerplay_table =
2460 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
2461 PPTable_t *pptable = table_context->driver_pptable;
2462 SkuTable_t *skutable = &pptable->SkuTable;
2463 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2464 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
2465
2466 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
2467 power_limit = smu->adev->pm.ac_power ?
2468 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
2469 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
2470
2471 if (current_power_limit)
2472 *current_power_limit = power_limit;
2473 if (default_power_limit)
2474 *default_power_limit = power_limit;
2475
2476 if (powerplay_table) {
2477 if (smu->od_enabled &&
2478 smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2479 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2480 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2481 } else if (smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
2482 od_percent_upper = 0;
2483 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
2484 }
2485 }
2486
2487 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2488 od_percent_upper, od_percent_lower, power_limit);
2489
2490 if (max_power_limit) {
2491 *max_power_limit = msg_limit * (100 + od_percent_upper);
2492 *max_power_limit /= 100;
2493 }
2494
2495 if (min_power_limit) {
2496 *min_power_limit = power_limit * (100 - od_percent_lower);
2497 *min_power_limit /= 100;
2498 }
2499
2500 return 0;
2501 }
2502
smu_v13_0_0_get_power_profile_mode(struct smu_context * smu,char * buf)2503 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
2504 char *buf)
2505 {
2506 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2507 DpmActivityMonitorCoeffInt_t *activity_monitor =
2508 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2509 static const char *title[] = {
2510 "PROFILE_INDEX(NAME)",
2511 "CLOCK_TYPE(NAME)",
2512 "FPS",
2513 "MinActiveFreqType",
2514 "MinActiveFreq",
2515 "BoosterFreqType",
2516 "BoosterFreq",
2517 "PD_Data_limit_c",
2518 "PD_Data_error_coeff",
2519 "PD_Data_error_rate_coeff"};
2520 int16_t workload_type = 0;
2521 uint32_t i, size = 0;
2522 int result = 0;
2523
2524 if (!buf)
2525 return -EINVAL;
2526
2527 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
2528 title[0], title[1], title[2], title[3], title[4], title[5],
2529 title[6], title[7], title[8], title[9]);
2530
2531 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
2532 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2533 workload_type = smu_cmn_to_asic_specific_index(smu,
2534 CMN2ASIC_MAPPING_WORKLOAD,
2535 i);
2536 if (workload_type == -ENOTSUPP)
2537 continue;
2538 else if (workload_type < 0)
2539 return -EINVAL;
2540
2541 result = smu_cmn_update_table(smu,
2542 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2543 workload_type,
2544 (void *)(&activity_monitor_external),
2545 false);
2546 if (result) {
2547 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2548 return result;
2549 }
2550
2551 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
2552 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
2553
2554 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2555 " ",
2556 0,
2557 "GFXCLK",
2558 activity_monitor->Gfx_FPS,
2559 activity_monitor->Gfx_MinActiveFreqType,
2560 activity_monitor->Gfx_MinActiveFreq,
2561 activity_monitor->Gfx_BoosterFreqType,
2562 activity_monitor->Gfx_BoosterFreq,
2563 activity_monitor->Gfx_PD_Data_limit_c,
2564 activity_monitor->Gfx_PD_Data_error_coeff,
2565 activity_monitor->Gfx_PD_Data_error_rate_coeff);
2566
2567 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
2568 " ",
2569 1,
2570 "FCLK",
2571 activity_monitor->Fclk_FPS,
2572 activity_monitor->Fclk_MinActiveFreqType,
2573 activity_monitor->Fclk_MinActiveFreq,
2574 activity_monitor->Fclk_BoosterFreqType,
2575 activity_monitor->Fclk_BoosterFreq,
2576 activity_monitor->Fclk_PD_Data_limit_c,
2577 activity_monitor->Fclk_PD_Data_error_coeff,
2578 activity_monitor->Fclk_PD_Data_error_rate_coeff);
2579 }
2580
2581 return size;
2582 }
2583
2584 #define SMU_13_0_0_CUSTOM_PARAMS_COUNT 9
2585 #define SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT 2
2586 #define SMU_13_0_0_CUSTOM_PARAMS_SIZE (SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT * SMU_13_0_0_CUSTOM_PARAMS_COUNT * sizeof(long))
2587
smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context * smu,long * input)2588 static int smu_v13_0_0_set_power_profile_mode_coeff(struct smu_context *smu,
2589 long *input)
2590 {
2591 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
2592 DpmActivityMonitorCoeffInt_t *activity_monitor =
2593 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
2594 int ret, idx;
2595
2596 ret = smu_cmn_update_table(smu,
2597 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2598 WORKLOAD_PPLIB_CUSTOM_BIT,
2599 (void *)(&activity_monitor_external),
2600 false);
2601 if (ret) {
2602 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2603 return ret;
2604 }
2605
2606 idx = 0 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2607 if (input[idx]) {
2608 /* Gfxclk */
2609 activity_monitor->Gfx_FPS = input[idx + 1];
2610 activity_monitor->Gfx_MinActiveFreqType = input[idx + 2];
2611 activity_monitor->Gfx_MinActiveFreq = input[idx + 3];
2612 activity_monitor->Gfx_BoosterFreqType = input[idx + 4];
2613 activity_monitor->Gfx_BoosterFreq = input[idx + 5];
2614 activity_monitor->Gfx_PD_Data_limit_c = input[idx + 6];
2615 activity_monitor->Gfx_PD_Data_error_coeff = input[idx + 7];
2616 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[idx + 8];
2617 }
2618 idx = 1 * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2619 if (input[idx]) {
2620 /* Fclk */
2621 activity_monitor->Fclk_FPS = input[idx + 1];
2622 activity_monitor->Fclk_MinActiveFreqType = input[idx + 2];
2623 activity_monitor->Fclk_MinActiveFreq = input[idx + 3];
2624 activity_monitor->Fclk_BoosterFreqType = input[idx + 4];
2625 activity_monitor->Fclk_BoosterFreq = input[idx + 5];
2626 activity_monitor->Fclk_PD_Data_limit_c = input[idx + 6];
2627 activity_monitor->Fclk_PD_Data_error_coeff = input[idx + 7];
2628 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[idx + 8];
2629 }
2630
2631 ret = smu_cmn_update_table(smu,
2632 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
2633 WORKLOAD_PPLIB_CUSTOM_BIT,
2634 (void *)(&activity_monitor_external),
2635 true);
2636 if (ret) {
2637 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2638 return ret;
2639 }
2640
2641 return ret;
2642 }
2643
smu_v13_0_0_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)2644 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
2645 u32 workload_mask,
2646 long *custom_params,
2647 u32 custom_params_max_idx)
2648 {
2649 u32 backend_workload_mask = 0;
2650 int workload_type, ret, idx = -1, i;
2651
2652 smu_cmn_get_backend_workload_mask(smu, workload_mask,
2653 &backend_workload_mask);
2654
2655 /* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
2656 if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) &&
2657 ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2658 ((smu->adev->pm.fw_version == 0x004e6601) ||
2659 (smu->adev->pm.fw_version >= 0x004e7300))) ||
2660 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2661 smu->adev->pm.fw_version >= 0x00504500))) {
2662 workload_type = smu_cmn_to_asic_specific_index(smu,
2663 CMN2ASIC_MAPPING_WORKLOAD,
2664 PP_SMC_POWER_PROFILE_POWERSAVING);
2665 if (workload_type >= 0)
2666 backend_workload_mask |= 1 << workload_type;
2667 }
2668
2669 if (workload_mask & (1 << PP_SMC_POWER_PROFILE_CUSTOM)) {
2670 if (!smu->custom_profile_params) {
2671 smu->custom_profile_params =
2672 kzalloc(SMU_13_0_0_CUSTOM_PARAMS_SIZE, GFP_KERNEL);
2673 if (!smu->custom_profile_params)
2674 return -ENOMEM;
2675 }
2676 if (custom_params && custom_params_max_idx) {
2677 if (custom_params_max_idx != SMU_13_0_0_CUSTOM_PARAMS_COUNT)
2678 return -EINVAL;
2679 if (custom_params[0] >= SMU_13_0_0_CUSTOM_PARAMS_CLOCK_COUNT)
2680 return -EINVAL;
2681 idx = custom_params[0] * SMU_13_0_0_CUSTOM_PARAMS_COUNT;
2682 smu->custom_profile_params[idx] = 1;
2683 for (i = 1; i < custom_params_max_idx; i++)
2684 smu->custom_profile_params[idx + i] = custom_params[i];
2685 }
2686 ret = smu_v13_0_0_set_power_profile_mode_coeff(smu,
2687 smu->custom_profile_params);
2688 if (ret) {
2689 if (idx != -1)
2690 smu->custom_profile_params[idx] = 0;
2691 return ret;
2692 }
2693 } else if (smu->custom_profile_params) {
2694 memset(smu->custom_profile_params, 0, SMU_13_0_0_CUSTOM_PARAMS_SIZE);
2695 }
2696
2697 ret = smu_cmn_send_smc_msg_with_param(smu,
2698 SMU_MSG_SetWorkloadMask,
2699 backend_workload_mask,
2700 NULL);
2701 if (ret) {
2702 dev_err(smu->adev->dev, "Failed to set workload mask 0x%08x\n",
2703 workload_mask);
2704 if (idx != -1)
2705 smu->custom_profile_params[idx] = 0;
2706 return ret;
2707 }
2708
2709 return ret;
2710 }
2711
smu_v13_0_0_is_mode1_reset_supported(struct smu_context * smu)2712 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
2713 {
2714 struct amdgpu_device *adev = smu->adev;
2715 u32 smu_version;
2716 int ret;
2717
2718 /* SRIOV does not support SMU mode1 reset */
2719 if (amdgpu_sriov_vf(adev))
2720 return false;
2721
2722 /* PMFW support is available since 78.41 */
2723 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2724 if (ret)
2725 return false;
2726
2727 if (smu_version < 0x004e2900)
2728 return false;
2729
2730 return true;
2731 }
2732
smu_v13_0_0_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2733 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
2734 struct i2c_msg *msg, int num_msgs)
2735 {
2736 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2737 struct amdgpu_device *adev = smu_i2c->adev;
2738 struct smu_context *smu = adev->powerplay.pp_handle;
2739 struct smu_table_context *smu_table = &smu->smu_table;
2740 struct smu_table *table = &smu_table->driver_table;
2741 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2742 int i, j, r, c;
2743 u16 dir;
2744
2745 if (!adev->pm.dpm_enabled)
2746 return -EBUSY;
2747
2748 req = kzalloc(sizeof(*req), GFP_KERNEL);
2749 if (!req)
2750 return -ENOMEM;
2751
2752 req->I2CcontrollerPort = smu_i2c->port;
2753 req->I2CSpeed = I2C_SPEED_FAST_400K;
2754 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2755 dir = msg[0].flags & I2C_M_RD;
2756
2757 for (c = i = 0; i < num_msgs; i++) {
2758 for (j = 0; j < msg[i].len; j++, c++) {
2759 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2760
2761 if (!(msg[i].flags & I2C_M_RD)) {
2762 /* write */
2763 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2764 cmd->ReadWriteData = msg[i].buf[j];
2765 }
2766
2767 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2768 /* The direction changes.
2769 */
2770 dir = msg[i].flags & I2C_M_RD;
2771 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2772 }
2773
2774 req->NumCmds++;
2775
2776 /*
2777 * Insert STOP if we are at the last byte of either last
2778 * message for the transaction or the client explicitly
2779 * requires a STOP at this particular message.
2780 */
2781 if ((j == msg[i].len - 1) &&
2782 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2783 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2784 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2785 }
2786 }
2787 }
2788 mutex_lock(&adev->pm.mutex);
2789 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2790 if (r)
2791 goto fail;
2792
2793 for (c = i = 0; i < num_msgs; i++) {
2794 if (!(msg[i].flags & I2C_M_RD)) {
2795 c += msg[i].len;
2796 continue;
2797 }
2798 for (j = 0; j < msg[i].len; j++, c++) {
2799 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2800
2801 msg[i].buf[j] = cmd->ReadWriteData;
2802 }
2803 }
2804 r = num_msgs;
2805 fail:
2806 mutex_unlock(&adev->pm.mutex);
2807 kfree(req);
2808 return r;
2809 }
2810
smu_v13_0_0_i2c_func(struct i2c_adapter * adap)2811 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
2812 {
2813 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2814 }
2815
2816 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
2817 .master_xfer = smu_v13_0_0_i2c_xfer,
2818 .functionality = smu_v13_0_0_i2c_func,
2819 };
2820
2821 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
2822 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2823 .max_read_len = MAX_SW_I2C_COMMANDS,
2824 .max_write_len = MAX_SW_I2C_COMMANDS,
2825 .max_comb_1st_msg_len = 2,
2826 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2827 };
2828
smu_v13_0_0_i2c_control_init(struct smu_context * smu)2829 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
2830 {
2831 struct amdgpu_device *adev = smu->adev;
2832 int res, i;
2833
2834 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2835 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2836 struct i2c_adapter *control = &smu_i2c->adapter;
2837
2838 smu_i2c->adev = adev;
2839 smu_i2c->port = i;
2840 mutex_init(&smu_i2c->mutex);
2841 control->owner = THIS_MODULE;
2842 control->dev.parent = &adev->pdev->dev;
2843 control->algo = &smu_v13_0_0_i2c_algo;
2844 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2845 control->quirks = &smu_v13_0_0_i2c_control_quirks;
2846 i2c_set_adapdata(control, smu_i2c);
2847
2848 res = i2c_add_adapter(control);
2849 if (res) {
2850 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2851 goto Out_err;
2852 }
2853 }
2854
2855 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
2856 /* XXX ideally this would be something in a vbios data table */
2857 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
2858 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2859
2860 return 0;
2861 Out_err:
2862 for ( ; i >= 0; i--) {
2863 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2864 struct i2c_adapter *control = &smu_i2c->adapter;
2865
2866 i2c_del_adapter(control);
2867 }
2868 return res;
2869 }
2870
smu_v13_0_0_i2c_control_fini(struct smu_context * smu)2871 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
2872 {
2873 struct amdgpu_device *adev = smu->adev;
2874 int i;
2875
2876 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2877 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2878 struct i2c_adapter *control = &smu_i2c->adapter;
2879
2880 i2c_del_adapter(control);
2881 }
2882 adev->pm.ras_eeprom_i2c_bus = NULL;
2883 adev->pm.fru_eeprom_i2c_bus = NULL;
2884 }
2885
smu_v13_0_0_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)2886 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
2887 enum pp_mp1_state mp1_state)
2888 {
2889 int ret;
2890
2891 switch (mp1_state) {
2892 case PP_MP1_STATE_UNLOAD:
2893 ret = smu_cmn_send_smc_msg_with_param(smu,
2894 SMU_MSG_PrepareMp1ForUnload,
2895 0x55, NULL);
2896
2897 if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT)
2898 ret = smu_v13_0_disable_pmfw_state(smu);
2899
2900 break;
2901 default:
2902 /* Ignore others */
2903 ret = 0;
2904 }
2905
2906 return ret;
2907 }
2908
smu_v13_0_0_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)2909 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
2910 enum pp_df_cstate state)
2911 {
2912 return smu_cmn_send_smc_msg_with_param(smu,
2913 SMU_MSG_DFCstateControl,
2914 state,
2915 NULL);
2916 }
2917
smu_v13_0_0_set_mode1_reset_param(struct smu_context * smu,uint32_t supported_version,uint32_t * param)2918 static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu,
2919 uint32_t supported_version,
2920 uint32_t *param)
2921 {
2922 struct amdgpu_device *adev = smu->adev;
2923
2924 if ((smu->smc_fw_version >= supported_version) &&
2925 amdgpu_ras_get_fed_status(adev))
2926 /* Set RAS fatal error reset flag */
2927 *param = 1 << 16;
2928 else
2929 *param = 0;
2930 }
2931
smu_v13_0_0_mode1_reset(struct smu_context * smu)2932 static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
2933 {
2934 int ret;
2935 uint32_t param;
2936 struct amdgpu_device *adev = smu->adev;
2937
2938 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2939 case IP_VERSION(13, 0, 0):
2940 /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */
2941 smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m);
2942
2943 ret = smu_cmn_send_smc_msg_with_param(smu,
2944 SMU_MSG_Mode1Reset, param, NULL);
2945 break;
2946
2947 case IP_VERSION(13, 0, 10):
2948 /* SMU 13_0_10 PMFW supports RAS fatal error reset from 80.28 */
2949 smu_v13_0_0_set_mode1_reset_param(smu, 0x00501c00, ¶m);
2950
2951 ret = smu_cmn_send_debug_smc_msg_with_param(smu,
2952 DEBUGSMC_MSG_Mode1Reset, param);
2953 break;
2954
2955 default:
2956 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
2957 break;
2958 }
2959
2960 if (!ret)
2961 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
2962
2963 return ret;
2964 }
2965
smu_v13_0_0_mode2_reset(struct smu_context * smu)2966 static int smu_v13_0_0_mode2_reset(struct smu_context *smu)
2967 {
2968 int ret;
2969 struct amdgpu_device *adev = smu->adev;
2970
2971 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2972 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode2Reset, NULL);
2973 else
2974 return -EOPNOTSUPP;
2975
2976 return ret;
2977 }
2978
smu_v13_0_0_enable_gfx_features(struct smu_context * smu)2979 static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu)
2980 {
2981 struct amdgpu_device *adev = smu->adev;
2982
2983 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))
2984 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableAllSmuFeatures,
2985 FEATURE_PWR_GFX, NULL);
2986 else
2987 return -EOPNOTSUPP;
2988 }
2989
smu_v13_0_0_set_smu_mailbox_registers(struct smu_context * smu)2990 static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
2991 {
2992 struct amdgpu_device *adev = smu->adev;
2993
2994 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2995 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2996 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2997
2998 smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
2999 smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
3000 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
3001 }
3002
smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context * smu,uint32_t size)3003 static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
3004 uint32_t size)
3005 {
3006 int ret = 0;
3007
3008 /* message SMU to update the bad page number on SMUBUS */
3009 ret = smu_cmn_send_smc_msg_with_param(smu,
3010 SMU_MSG_SetNumBadMemoryPagesRetired,
3011 size, NULL);
3012 if (ret)
3013 dev_err(smu->adev->dev,
3014 "[%s] failed to message SMU to update bad memory pages number\n",
3015 __func__);
3016
3017 return ret;
3018 }
3019
smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context * smu,uint32_t size)3020 static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu,
3021 uint32_t size)
3022 {
3023 int ret = 0;
3024
3025 /* message SMU to update the bad channel info on SMUBUS */
3026 ret = smu_cmn_send_smc_msg_with_param(smu,
3027 SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel,
3028 size, NULL);
3029 if (ret)
3030 dev_err(smu->adev->dev,
3031 "[%s] failed to message SMU to update bad memory pages channel info\n",
3032 __func__);
3033
3034 return ret;
3035 }
3036
smu_v13_0_0_check_ecc_table_support(struct smu_context * smu)3037 static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu)
3038 {
3039 struct amdgpu_device *adev = smu->adev;
3040 int ret = 0;
3041
3042 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) &&
3043 (smu->smc_fw_version >= SUPPORT_ECCTABLE_SMU_13_0_10_VERSION))
3044 return ret;
3045 else
3046 return -EOPNOTSUPP;
3047 }
3048
smu_v13_0_0_get_ecc_info(struct smu_context * smu,void * table)3049 static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu,
3050 void *table)
3051 {
3052 struct smu_table_context *smu_table = &smu->smu_table;
3053 struct amdgpu_device *adev = smu->adev;
3054 EccInfoTable_t *ecc_table = NULL;
3055 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
3056 int i, ret = 0;
3057 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
3058
3059 ret = smu_v13_0_0_check_ecc_table_support(smu);
3060 if (ret)
3061 return ret;
3062
3063 ret = smu_cmn_update_table(smu,
3064 SMU_TABLE_ECCINFO,
3065 0,
3066 smu_table->ecc_table,
3067 false);
3068 if (ret) {
3069 dev_info(adev->dev, "Failed to export SMU ecc table!\n");
3070 return ret;
3071 }
3072
3073 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
3074
3075 for (i = 0; i < ARRAY_SIZE(ecc_table->EccInfo); i++) {
3076 ecc_info_per_channel = &(eccinfo->ecc[i]);
3077 ecc_info_per_channel->ce_count_lo_chip =
3078 ecc_table->EccInfo[i].ce_count_lo_chip;
3079 ecc_info_per_channel->ce_count_hi_chip =
3080 ecc_table->EccInfo[i].ce_count_hi_chip;
3081 ecc_info_per_channel->mca_umc_status =
3082 ecc_table->EccInfo[i].mca_umc_status;
3083 ecc_info_per_channel->mca_umc_addr =
3084 ecc_table->EccInfo[i].mca_umc_addr;
3085 }
3086
3087 return ret;
3088 }
3089
smu_v13_0_0_wbrf_support_check(struct smu_context * smu)3090 static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu)
3091 {
3092 struct amdgpu_device *adev = smu->adev;
3093
3094 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3095 case IP_VERSION(13, 0, 0):
3096 return smu->smc_fw_version >= 0x004e6300;
3097 case IP_VERSION(13, 0, 10):
3098 return smu->smc_fw_version >= 0x00503300;
3099 default:
3100 return false;
3101 }
3102 }
3103
smu_v13_0_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)3104 static int smu_v13_0_0_set_power_limit(struct smu_context *smu,
3105 enum smu_ppt_limit_type limit_type,
3106 uint32_t limit)
3107 {
3108 PPTable_t *pptable = smu->smu_table.driver_pptable;
3109 SkuTable_t *skutable = &pptable->SkuTable;
3110 uint32_t msg_limit = skutable->MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
3111 struct smu_table_context *table_context = &smu->smu_table;
3112 OverDriveTableExternal_t *od_table =
3113 (OverDriveTableExternal_t *)table_context->overdrive_table;
3114 int ret = 0;
3115
3116 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
3117 return -EINVAL;
3118
3119 if (limit <= msg_limit) {
3120 if (smu->current_power_limit > msg_limit) {
3121 od_table->OverDriveTable.Ppt = 0;
3122 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3123
3124 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3125 if (ret) {
3126 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3127 return ret;
3128 }
3129 }
3130 return smu_v13_0_set_power_limit(smu, limit_type, limit);
3131 } else if (smu->od_enabled) {
3132 ret = smu_v13_0_set_power_limit(smu, limit_type, msg_limit);
3133 if (ret)
3134 return ret;
3135
3136 od_table->OverDriveTable.Ppt = (limit * 100) / msg_limit - 100;
3137 od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_PPT_BIT;
3138
3139 ret = smu_v13_0_0_upload_overdrive_table(smu, od_table);
3140 if (ret) {
3141 dev_err(smu->adev->dev, "Failed to upload overdrive table!\n");
3142 return ret;
3143 }
3144
3145 smu->current_power_limit = limit;
3146 } else {
3147 return -EINVAL;
3148 }
3149
3150 return 0;
3151 }
3152
3153 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
3154 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
3155 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
3156 .i2c_init = smu_v13_0_0_i2c_control_init,
3157 .i2c_fini = smu_v13_0_0_i2c_control_fini,
3158 .is_dpm_running = smu_v13_0_0_is_dpm_running,
3159 .init_microcode = smu_v13_0_init_microcode,
3160 .load_microcode = smu_v13_0_load_microcode,
3161 .fini_microcode = smu_v13_0_fini_microcode,
3162 .init_smc_tables = smu_v13_0_0_init_smc_tables,
3163 .fini_smc_tables = smu_v13_0_fini_smc_tables,
3164 .init_power = smu_v13_0_init_power,
3165 .fini_power = smu_v13_0_fini_power,
3166 .check_fw_status = smu_v13_0_check_fw_status,
3167 .setup_pptable = smu_v13_0_0_setup_pptable,
3168 .check_fw_version = smu_v13_0_check_fw_version,
3169 .write_pptable = smu_cmn_write_pptable,
3170 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3171 .system_features_control = smu_v13_0_0_system_features_control,
3172 .set_allowed_mask = smu_v13_0_set_allowed_mask,
3173 .get_enabled_mask = smu_cmn_get_enabled_mask,
3174 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
3175 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
3176 .get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
3177 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
3178 .read_sensor = smu_v13_0_0_read_sensor,
3179 .feature_is_enabled = smu_cmn_feature_is_enabled,
3180 .print_clk_levels = smu_v13_0_0_print_clk_levels,
3181 .force_clk_levels = smu_v13_0_0_force_clk_levels,
3182 .update_pcie_parameters = smu_v13_0_update_pcie_parameters,
3183 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
3184 .register_irq_handler = smu_v13_0_register_irq_handler,
3185 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3186 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3187 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3188 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
3189 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
3190 .set_default_od_settings = smu_v13_0_0_set_default_od_settings,
3191 .restore_user_od_settings = smu_v13_0_0_restore_user_od_settings,
3192 .od_edit_dpm_table = smu_v13_0_0_od_edit_dpm_table,
3193 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
3194 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
3195 .set_performance_level = smu_v13_0_set_performance_level,
3196 .gfx_off_control = smu_v13_0_gfx_off_control,
3197 .get_unique_id = smu_v13_0_0_get_unique_id,
3198 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
3199 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
3200 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
3201 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
3202 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
3203 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
3204 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
3205 .get_power_limit = smu_v13_0_0_get_power_limit,
3206 .set_power_limit = smu_v13_0_0_set_power_limit,
3207 .set_power_source = smu_v13_0_set_power_source,
3208 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
3209 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
3210 .run_btc = smu_v13_0_run_btc,
3211 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3212 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3213 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3214 .deep_sleep_control = smu_v13_0_deep_sleep_control,
3215 .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
3216 .get_bamaco_support = smu_v13_0_get_bamaco_support,
3217 .baco_enter = smu_v13_0_baco_enter,
3218 .baco_exit = smu_v13_0_baco_exit,
3219 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
3220 .mode1_reset = smu_v13_0_0_mode1_reset,
3221 .mode2_reset = smu_v13_0_0_mode2_reset,
3222 .enable_gfx_features = smu_v13_0_0_enable_gfx_features,
3223 .set_mp1_state = smu_v13_0_0_set_mp1_state,
3224 .set_df_cstate = smu_v13_0_0_set_df_cstate,
3225 .send_hbm_bad_pages_num = smu_v13_0_0_smu_send_bad_mem_page_num,
3226 .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag,
3227 .gpo_control = smu_v13_0_gpo_control,
3228 .get_ecc_info = smu_v13_0_0_get_ecc_info,
3229 .notify_display_change = smu_v13_0_notify_display_change,
3230 .is_asic_wbrf_supported = smu_v13_0_0_wbrf_support_check,
3231 .enable_uclk_shadow = smu_v13_0_enable_uclk_shadow,
3232 .set_wbrf_exclusion_ranges = smu_v13_0_set_wbrf_exclusion_ranges,
3233 .interrupt_work = smu_v13_0_interrupt_work,
3234 };
3235
smu_v13_0_0_set_ppt_funcs(struct smu_context * smu)3236 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
3237 {
3238 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
3239 smu->message_map = smu_v13_0_0_message_map;
3240 smu->clock_map = smu_v13_0_0_clk_map;
3241 smu->feature_map = smu_v13_0_0_feature_mask_map;
3242 smu->table_map = smu_v13_0_0_table_map;
3243 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
3244 smu->workload_map = smu_v13_0_0_workload_map;
3245 smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;
3246 smu_v13_0_0_set_smu_mailbox_registers(smu);
3247
3248 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3249 IP_VERSION(13, 0, 10) &&
3250 !amdgpu_device_has_display_hardware(smu->adev))
3251 smu->adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3252 }
3253