1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SMU_V13_0_H__
24 #define __SMU_V13_0_H__
25 
26 #include "amdgpu_smu.h"
27 
28 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
29 
30 /* MP Apertures */
31 #define MP0_Public			0x03800000
32 #define MP0_SRAM			0x03900000
33 #define MP1_Public			0x03b00000
34 #define MP1_SRAM			0x03c00004
35 
36 /* address block */
37 #define smnMP1_FIRMWARE_FLAGS		0x3010024
38 #define smnMP1_V13_0_4_FIRMWARE_FLAGS	0x3010028
39 #define smnMP0_FW_INTF			0x30101c0
40 #define smnMP1_PUB_CTRL			0x3010b14
41 
42 #define TEMP_RANGE_MIN			(0)
43 #define TEMP_RANGE_MAX			(80 * 1000)
44 
45 #define SMU13_TOOL_SIZE			0x19000
46 
47 #define MAX_DPM_LEVELS 16
48 #define MAX_PCIE_CONF 3
49 
50 #define CTF_OFFSET_EDGE			5
51 #define CTF_OFFSET_HOTSPOT		5
52 #define CTF_OFFSET_MEM			5
53 
54 #define SMU_13_VCLK_SHIFT		16
55 
56 #define SMUQ10_TO_UINT(x) ((x) >> 10)
57 #define SMUQ10_FRAC(x) ((x) & 0x3ff)
58 #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
59 
60 extern const int pmfw_decoded_link_speed[5];
61 extern const int pmfw_decoded_link_width[7];
62 
63 #define DECODE_GEN_SPEED(gen_speed_idx)		(pmfw_decoded_link_speed[gen_speed_idx])
64 #define DECODE_LANE_WIDTH(lane_width_idx)	(pmfw_decoded_link_width[lane_width_idx])
65 
66 struct smu_13_0_max_sustainable_clocks {
67 	uint32_t display_clock;
68 	uint32_t phy_clock;
69 	uint32_t pixel_clock;
70 	uint32_t uclock;
71 	uint32_t dcef_clock;
72 	uint32_t soc_clock;
73 };
74 
75 struct smu_13_0_dpm_clk_level {
76 	bool				enabled;
77 	uint32_t			value;
78 };
79 
80 struct smu_13_0_dpm_table {
81 	uint32_t			min;        /* MHz */
82 	uint32_t			max;        /* MHz */
83 	uint32_t			count;
84 	bool				is_fine_grained;
85 	struct smu_13_0_dpm_clk_level	dpm_levels[MAX_DPM_LEVELS];
86 };
87 
88 struct smu_13_0_pcie_table {
89 	uint8_t  pcie_gen[MAX_PCIE_CONF];
90 	uint8_t  pcie_lane[MAX_PCIE_CONF];
91 	uint16_t clk_freq[MAX_PCIE_CONF];
92 	uint32_t num_of_link_levels;
93 };
94 
95 struct smu_13_0_dpm_tables {
96 	struct smu_13_0_dpm_table        soc_table;
97 	struct smu_13_0_dpm_table        gfx_table;
98 	struct smu_13_0_dpm_table        uclk_table;
99 	struct smu_13_0_dpm_table        eclk_table;
100 	struct smu_13_0_dpm_table        vclk_table;
101 	struct smu_13_0_dpm_table        dclk_table;
102 	struct smu_13_0_dpm_table        dcef_table;
103 	struct smu_13_0_dpm_table        pixel_table;
104 	struct smu_13_0_dpm_table        display_table;
105 	struct smu_13_0_dpm_table        phy_table;
106 	struct smu_13_0_dpm_table        fclk_table;
107 	struct smu_13_0_pcie_table       pcie_table;
108 };
109 
110 struct smu_13_0_dpm_context {
111 	struct smu_13_0_dpm_tables  dpm_tables;
112 	uint32_t                    workload_policy_mask;
113 	uint32_t                    dcef_min_ds_clk;
114 	uint64_t                    caps;
115 };
116 
117 enum smu_13_0_power_state {
118 	SMU_13_0_POWER_STATE__D0 = 0,
119 	SMU_13_0_POWER_STATE__D1,
120 	SMU_13_0_POWER_STATE__D3, /* Sleep*/
121 	SMU_13_0_POWER_STATE__D4, /* Hibernate*/
122 	SMU_13_0_POWER_STATE__D5, /* Power off*/
123 };
124 
125 struct smu_13_0_power_context {
126 	uint32_t	power_source;
127 	uint8_t		in_power_limit_boost_mode;
128 	enum smu_13_0_power_state power_state;
129 	atomic_t	throttle_status;
130 };
131 
132 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
133 
134 int smu_v13_0_init_microcode(struct smu_context *smu);
135 
136 void smu_v13_0_fini_microcode(struct smu_context *smu);
137 
138 int smu_v13_0_load_microcode(struct smu_context *smu);
139 
140 int smu_v13_0_init_smc_tables(struct smu_context *smu);
141 
142 int smu_v13_0_fini_smc_tables(struct smu_context *smu);
143 
144 int smu_v13_0_init_power(struct smu_context *smu);
145 
146 int smu_v13_0_fini_power(struct smu_context *smu);
147 
148 int smu_v13_0_check_fw_status(struct smu_context *smu);
149 
150 int smu_v13_0_setup_pptable(struct smu_context *smu);
151 
152 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
153 
154 int smu_v13_0_check_fw_version(struct smu_context *smu);
155 
156 int smu_v13_0_set_driver_table_location(struct smu_context *smu);
157 
158 int smu_v13_0_set_tool_table_location(struct smu_context *smu);
159 
160 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
161 
162 int smu_v13_0_system_features_control(struct smu_context *smu,
163 				      bool en);
164 
165 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
166 
167 int smu_v13_0_set_allowed_mask(struct smu_context *smu);
168 
169 int smu_v13_0_notify_display_change(struct smu_context *smu);
170 
171 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
172 				      uint32_t *power_limit);
173 
174 int smu_v13_0_set_power_limit(struct smu_context *smu,
175 			      enum smu_ppt_limit_type limit_type,
176 			      uint32_t limit);
177 
178 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
179 
180 int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
181 
182 int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
183 
184 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
185 
186 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
187 
188 int
189 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
190 					struct pp_display_clock_request
191 					*clock_req);
192 
193 uint32_t
194 smu_v13_0_get_fan_control_mode(struct smu_context *smu);
195 
196 int
197 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
198 			       uint32_t mode);
199 
200 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
201 				uint32_t speed);
202 
203 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
204 				uint32_t speed);
205 
206 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
207 			      uint32_t pstate);
208 
209 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
210 
211 int smu_v13_0_register_irq_handler(struct smu_context *smu);
212 
213 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
214 
215 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
216 					       struct pp_smu_nv_clock_table *max_clocks);
217 
218 int smu_v13_0_get_bamaco_support(struct smu_context *smu);
219 
220 int smu_v13_0_baco_enter(struct smu_context *smu);
221 int smu_v13_0_baco_exit(struct smu_context *smu);
222 
223 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
224 				    uint32_t *min, uint32_t *max);
225 
226 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
227 					  uint32_t min, uint32_t max, bool automatic);
228 
229 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
230 					  enum smu_clk_type clk_type,
231 					  uint32_t min,
232 					  uint32_t max);
233 
234 int smu_v13_0_set_performance_level(struct smu_context *smu,
235 				    enum amd_dpm_forced_level level);
236 
237 int smu_v13_0_set_power_source(struct smu_context *smu,
238 			       enum smu_power_src_type power_src);
239 
240 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
241 				   enum smu_clk_type clk_type,
242 				   struct smu_13_0_dpm_table *single_dpm_table);
243 
244 int smu_v13_0_get_dpm_freq_by_index(struct smu_context *smu,
245 				    enum smu_clk_type clk_type, uint16_t level,
246 				    uint32_t *value);
247 
248 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
249 
250 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
251 
252 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
253 
254 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
255 
256 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
257 			      bool enablement);
258 
259 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
260 			     uint64_t event_arg);
261 
262 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
263 			      bool enable,
264 			      int inst);
265 
266 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
267 			      bool enable);
268 
269 int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
270 
271 int smu_v13_0_run_btc(struct smu_context *smu);
272 
273 int smu_v13_0_gpo_control(struct smu_context *smu,
274 			  bool enablement);
275 
276 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
277 				 bool enablement);
278 
279 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
280 
281 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
282 				enum PP_OD_DPM_TABLE_COMMAND type,
283 				long input[],
284 				uint32_t size);
285 
286 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
287 
288 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
289 
290 int smu_v13_0_mode1_reset(struct smu_context *smu);
291 
292 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
293 					void **table,
294 					uint32_t *size,
295 					uint32_t pptable_id);
296 
297 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
298 				     uint8_t pcie_gen_cap,
299 				     uint8_t pcie_width_cap);
300 
301 int smu_v13_0_disable_pmfw_state(struct smu_context *smu);
302 
303 int smu_v13_0_enable_uclk_shadow(struct smu_context *smu, bool enable);
304 
305 int smu_v13_0_set_wbrf_exclusion_ranges(struct smu_context *smu,
306 						 struct freq_band_range *exclusion_ranges);
307 
308 int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
309 				     enum smu_clk_type clk_type,
310 				     uint32_t *value);
311 
312 void smu_v13_0_interrupt_work(struct smu_context *smu);
313 bool smu_v13_0_12_is_dpm_running(struct smu_context *smu);
314 int smu_v13_0_12_get_max_metrics_size(void);
315 int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu);
316 int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu,
317 				      MetricsMember_t member,
318 				      uint32_t *value);
319 ssize_t smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table);
320 extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[];
321 extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[];
322 #endif
323 #endif
324