1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __MES_API_DEF_H__
25 #define __MES_API_DEF_H__
26 
27 #pragma pack(push, 8)
28 
29 #define MES_API_VERSION 0x14
30 
31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */
32 #define  AMDGPU_MES_LOG_BUFFER_SIZE  0xC000
33 
34 /* Driver submits one API(cmd) as a single Frame and this command size is same for all API
35  * to ease the debugging and parsing of ring buffer.
36  */
37 enum {API_FRAME_SIZE_IN_DWORDS = 64};
38 
39 /* To avoid command in scheduler context to be overwritten whenenver mutilple interrupts come in,
40  * this creates another queue
41  */
42 enum {API_NUMBER_OF_COMMAND_MAX   = 32};
43 
44 enum MES_API_TYPE {
45 	MES_API_TYPE_SCHEDULER = 1,
46 	MES_API_TYPE_MAX
47 };
48 
49 enum MES_SCH_API_OPCODE {
50 	MES_SCH_API_SET_HW_RSRC			= 0,
51 	MES_SCH_API_SET_SCHEDULING_CONFIG	= 1, /* agreegated db, quantums, etc */
52 	MES_SCH_API_ADD_QUEUE			= 2,
53 	MES_SCH_API_REMOVE_QUEUE		= 3,
54 	MES_SCH_API_PERFORM_YIELD		= 4,
55 	MES_SCH_API_SET_GANG_PRIORITY_LEVEL	= 5, /* For windows GANG = Context */
56 	MES_SCH_API_SUSPEND			= 6,
57 	MES_SCH_API_RESUME			= 7,
58 	MES_SCH_API_RESET			= 8,
59 	MES_SCH_API_SET_LOG_BUFFER		= 9,
60 	MES_SCH_API_CHANGE_GANG_PRORITY		= 10,
61 	MES_SCH_API_QUERY_SCHEDULER_STATUS	= 11,
62 	MES_SCH_API_SET_DEBUG_VMID		= 13,
63 	MES_SCH_API_MISC			= 14,
64 	MES_SCH_API_UPDATE_ROOT_PAGE_TABLE	= 15,
65 	MES_SCH_API_AMD_LOG			= 16,
66 	MES_SCH_API_SET_SE_MODE			= 17,
67 	MES_SCH_API_SET_GANG_SUBMIT		= 18,
68 	MES_SCH_API_SET_HW_RSRC_1               = 19,
69 
70 	MES_SCH_API_MAX = 0xFF
71 };
72 
73 union MES_API_HEADER {
74 	struct {
75 		uint32_t type	  : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
76 		uint32_t opcode   : 8;
77 		uint32_t dwsize   : 8; /* including header */
78 		uint32_t reserved : 12;
79 	};
80 
81 	uint32_t u32All;
82 };
83 
84 enum MES_AMD_PRIORITY_LEVEL {
85 	AMD_PRIORITY_LEVEL_LOW		= 0,
86 	AMD_PRIORITY_LEVEL_NORMAL	= 1,
87 	AMD_PRIORITY_LEVEL_MEDIUM	= 2,
88 	AMD_PRIORITY_LEVEL_HIGH		= 3,
89 	AMD_PRIORITY_LEVEL_REALTIME	= 4,
90 
91 	AMD_PRIORITY_NUM_LEVELS
92 };
93 
94 enum MES_QUEUE_TYPE {
95 	MES_QUEUE_TYPE_GFX,
96 	MES_QUEUE_TYPE_COMPUTE,
97 	MES_QUEUE_TYPE_SDMA,
98 
99 	MES_QUEUE_TYPE_MAX,
100 	MES_QUEUE_TYPE_SCHQ = MES_QUEUE_TYPE_MAX,
101 };
102 
103 struct MES_API_STATUS {
104 	uint64_t api_completion_fence_addr;
105 	uint64_t api_completion_fence_value;
106 };
107 
108 /*
109  * MES will set api_completion_fence_value in api_completion_fence_addr
110  * when it can successflly process the API. MES will also trigger
111  * following interrupt when it finish process the API no matter success
112  * or failed.
113  *     Interrupt source id 181 (EOP) with context ID (DW 6 in the int
114  *     cookie) set to 0xb1 and context type set to 8. Driver side need
115  *     to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to
116  *     catch this interrupt.
117  *     Driver side also need to set enable_mes_fence_int = 1 in
118  *     set_HW_resource package to enable this fence interrupt.
119  * when the API process failed.
120  *     lowre 32 bits set to 0.
121  *     higher 32 bits set as follows (bit shift within high 32)
122  *         bit 0  -  7    API specific error code.
123  *         bit 8  - 15    API OPCODE.
124  *         bit 16 - 23    MISC OPCODE if any
125  *         bit 24 - 30    ERROR category (API_ERROR_XXX)
126  *         bit 31         Set to 1 to indicate error status
127  *
128  */
129 enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };
130 enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };
131 enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };
132 enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 };
133 
134 enum MES_ERROR_CATEGORY_CODE_12 {
135 	MES_ERROR_API                = 1,
136 	MES_ERROR_SCHEDULING         = 2,
137 	MES_ERROR_UNKNOWN            = 3,
138 };
139 
140 #define MES_ERR_CODE(api_err, opcode, misc_op, category) \
141 			((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \
142 			misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \
143 			category << MES_ERROR_CATEGORY_SHIFT_12 | \
144 			1 << MES_API_STATUS_ERROR_SHIFT_12) << 32)
145 
146 enum { MAX_COMPUTE_PIPES = 8 };
147 enum { MAX_GFX_PIPES	 = 2 };
148 enum { MAX_SDMA_PIPES	 = 2 };
149 
150 enum { MAX_COMPUTE_HQD_PER_PIPE		= 8 };
151 enum { MAX_GFX_HQD_PER_PIPE		= 8 };
152 enum { MAX_SDMA_HQD_PER_PIPE		= 10 };
153 enum { MAX_SDMA_HQD_PER_PIPE_11_0	= 8 };
154 
155 
156 enum { MAX_QUEUES_IN_A_GANG = 8 };
157 
158 enum VM_HUB_TYPE {
159 	VM_HUB_TYPE_GC = 0,
160 	VM_HUB_TYPE_MM = 1,
161 
162 	VM_HUB_TYPE_MAX,
163 };
164 
165 enum { VMID_INVALID = 0xffff };
166 
167 enum { MAX_VMID_GCHUB = 16 };
168 enum { MAX_VMID_MMHUB = 16 };
169 
170 enum SET_DEBUG_VMID_OPERATIONS {
171 	DEBUG_VMID_OP_PROGRAM	= 0,
172 	DEBUG_VMID_OP_ALLOCATE	= 1,
173 	DEBUG_VMID_OP_RELEASE	= 2,
174 	DEBUG_VMID_OP_VM_SETUP	= 3 // used to set up the debug vmid page table in the kernel queue case (mode 1)
175 };
176 
177 enum MES_MS_LOG_CONTEXT_STATE {
178 	MES_LOG_CONTEXT_STATE_IDLE		= 0,
179 	MES_LOG_CONTEXT_STATE_RUNNING		= 1,
180 	MES_LOG_CONTEXT_STATE_READY		= 2,
181 	MES_LOG_CONTEXT_STATE_READY_STANDBY	= 3,
182 	MES_LOG_CONTEXT_STATE_INVALID		= 0xF,
183 };
184 
185 enum MES_MS_LOG_OPERATION {
186 	MES_LOG_OPERATION_CONTEXT_STATE_CHANGE		= 0,
187 	MES_LOG_OPERATION_QUEUE_NEW_WORK		= 1,
188 	MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT	= 2,
189 	MES_LOG_OPERATION_QUEUE_NO_MORE_WORK		= 3,
190 	MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT	= 4,
191 	MES_LOG_OPERATION_QUEUE_INVALID			= 0xF,
192 };
193 
194 struct MES_LOG_CONTEXT_STATE_CHANGE {
195 	uint64_t			h_context;
196 	enum MES_MS_LOG_CONTEXT_STATE	new_context_state;
197 };
198 
199 struct MES_LOG_QUEUE_NEW_WORK {
200 	uint64_t	h_queue;
201 	uint64_t	reserved;
202 };
203 
204 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
205 	uint64_t	h_queue;
206 	uint64_t	h_sync_object;
207 };
208 
209 struct MES_LOG_QUEUE_NO_MORE_WORK {
210 	uint64_t	h_queue;
211 	uint64_t	reserved;
212 };
213 
214 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
215 	uint64_t	h_queue;
216 	uint64_t	h_sync_object;
217 };
218 
219 struct MES_LOG_ENTRY_HEADER {
220 	uint32_t first_free_entry_index;
221 	uint32_t wraparound_count;
222 	uint64_t number_of_entries;
223 	uint64_t reserved[2];
224 };
225 
226 struct MES_LOG_ENTRY_DATA {
227 	uint64_t gpu_time_stamp;
228 	uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
229 	uint32_t reserved_operation_type_bits;
230 	union {
231 		struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
232 		struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
233 		struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
234 		struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
235 		struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
236 		uint64_t all[2];
237 	};
238 };
239 
240 struct MES_LOG_BUFFER {
241 	struct MES_LOG_ENTRY_HEADER header;
242 	struct MES_LOG_ENTRY_DATA	entries[];
243 };
244 
245 enum MES_SWIP_TO_HWIP_DEF {
246 	MES_MAX_HWIP_SEGMENT = 8,
247 };
248 
249 union MESAPI_SET_HW_RESOURCES {
250 	struct {
251 		union MES_API_HEADER	header;
252 		uint32_t		vmid_mask_mmhub;
253 		uint32_t		vmid_mask_gfxhub;
254 		uint32_t		gds_size;
255 		uint32_t		paging_vmid;
256 		uint32_t		compute_hqd_mask[MAX_COMPUTE_PIPES];
257 		uint32_t		gfx_hqd_mask[MAX_GFX_PIPES];
258 		uint32_t		sdma_hqd_mask[MAX_SDMA_PIPES];
259 		uint32_t		aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
260 		uint64_t		g_sch_ctx_gpu_mc_ptr;
261 		uint64_t		query_status_fence_gpu_mc_ptr;
262 		uint32_t		gc_base[MES_MAX_HWIP_SEGMENT];
263 		uint32_t		mmhub_base[MES_MAX_HWIP_SEGMENT];
264 		uint32_t		osssys_base[MES_MAX_HWIP_SEGMENT];
265 		struct MES_API_STATUS	api_status;
266 		union {
267 			struct {
268 				uint32_t disable_reset : 1;
269 				uint32_t use_different_vmid_compute : 1;
270 				uint32_t disable_mes_log   : 1;
271 				uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
272 				uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
273 				uint32_t second_gfx_pipe_enabled : 1;
274 				uint32_t enable_level_process_quantum_check : 1;
275 				uint32_t legacy_sch_mode : 1;
276 				uint32_t disable_add_queue_wptr_mc_addr : 1;
277 				uint32_t enable_mes_event_int_logging : 1;
278 				uint32_t enable_reg_active_poll : 1;
279 				uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
280 				uint32_t send_write_data : 1;
281 				uint32_t os_tdr_timeout_override : 1;
282 				uint32_t use_rs64mem_for_proc_gang_ctx : 1;
283 				uint32_t halt_on_misaligned_access : 1;
284 				uint32_t use_add_queue_unmap_flag_addr : 1;
285 				uint32_t enable_mes_sch_stb_log : 1;
286 				uint32_t limit_single_process : 1;
287 				uint32_t unmapped_doorbell_handling: 2;
288 				uint32_t enable_mes_fence_int: 1;
289 				uint32_t reserved : 10;
290 			};
291 			uint32_t uint32_all;
292 		};
293 	uint32_t	oversubscription_timer;
294 	uint64_t	doorbell_info;
295 	uint64_t	event_intr_history_gpu_mc_ptr;
296 	uint64_t	timestamp;
297 	uint32_t	os_tdr_timeout_in_sec;
298 	};
299 
300 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
301 };
302 
303 union MESAPI_SET_HW_RESOURCES_1 {
304 	struct {
305 		union MES_API_HEADER                header;
306 		struct MES_API_STATUS               api_status;
307 		uint64_t                            timestamp;
308 		union {
309 			struct {
310 				uint32_t enable_mes_debug_ctx : 1;
311 				uint32_t reserved : 31;
312 			};
313 			uint32_t uint32_all;
314 		};
315 		uint64_t                            mes_debug_ctx_mc_addr;
316 		uint32_t                            mes_debug_ctx_size;
317 		/* unit is 100ms */
318 		uint32_t                            mes_kiq_unmap_timeout;
319 		uint64_t                            reserved1;
320 		uint64_t                            cleaner_shader_fence_mc_addr;
321 	};
322 
323 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
324 };
325 
326 union MESAPI__ADD_QUEUE {
327 	struct {
328 		union MES_API_HEADER	header;
329 		uint32_t		process_id;
330 		uint64_t		page_table_base_addr;
331 		uint64_t		process_va_start;
332 		uint64_t		process_va_end;
333 		uint64_t		process_quantum;
334 		uint64_t		process_context_addr;
335 		uint64_t		gang_quantum;
336 		uint64_t		gang_context_addr;
337 		uint32_t		inprocess_gang_priority;
338 		enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
339 		uint32_t		doorbell_offset;
340 		uint64_t		mqd_addr;
341 		/* From MES_API_VERSION 2, mc addr is expected for wptr_addr */
342 		uint64_t		wptr_addr;
343 		uint64_t		h_context;
344 		uint64_t		h_queue;
345 		enum MES_QUEUE_TYPE	queue_type;
346 		uint32_t		gds_base;
347 		union {
348 			/* backwards compatibility with Linux, remove union once they use kfd_queue_size */
349 			uint32_t	gds_size;
350 			uint32_t	kfd_queue_size;
351 		};
352 		uint32_t		gws_base;
353 		uint32_t		gws_size;
354 		uint32_t		oa_mask;
355 		uint64_t		trap_handler_addr;
356 		uint32_t		vm_context_cntl;
357 
358 		struct {
359 			uint32_t paging	 : 1;
360 			uint32_t debug_vmid  : 4;
361 			uint32_t program_gds : 1;
362 			uint32_t is_gang_suspended : 1;
363 			uint32_t is_tmz_queue : 1;
364 			uint32_t map_kiq_utility_queue : 1;
365 			uint32_t is_kfd_process : 1;
366 			uint32_t trap_en : 1;
367 			uint32_t is_aql_queue : 1;
368 			uint32_t skip_process_ctx_clear : 1;
369 			uint32_t map_legacy_kq : 1;
370 			uint32_t exclusively_scheduled : 1;
371 			uint32_t is_long_running : 1;
372 			uint32_t is_dwm_queue : 1;
373 			uint32_t reserved	 : 15;
374 		};
375 		struct MES_API_STATUS	api_status;
376 		uint64_t		tma_addr;
377 		uint32_t		sch_id;
378 		uint64_t		timestamp;
379 		uint32_t		process_context_array_index;
380 		uint32_t		gang_context_array_index;
381 		uint32_t		pipe_id;	//used for mapping legacy kernel queue
382 		uint32_t		queue_id;
383 		uint32_t		alignment_mode_setting;
384 	};
385 
386 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
387 };
388 
389 union MESAPI__REMOVE_QUEUE {
390 	struct {
391 		union MES_API_HEADER	header;
392 		uint32_t		doorbell_offset;
393 		uint64_t		gang_context_addr;
394 
395 		struct {
396 			uint32_t reserved01		  : 1;
397 			uint32_t unmap_kiq_utility_queue  : 1;
398 			uint32_t preempt_legacy_gfx_queue : 1;
399 			uint32_t unmap_legacy_queue	  : 1;
400 			uint32_t reserved		  : 28;
401 		};
402 		struct MES_API_STATUS		api_status;
403 
404 		uint32_t			pipe_id;
405 		uint32_t			queue_id;
406 
407 		uint64_t			tf_addr;
408 		uint32_t			tf_data;
409 
410 		enum MES_QUEUE_TYPE		queue_type;
411 		uint64_t			timestamp;
412 		uint32_t			gang_context_array_index;
413 	};
414 
415 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
416 };
417 
418 union MESAPI__SET_SCHEDULING_CONFIG {
419 	struct {
420 		union MES_API_HEADER	header;
421 		/* Grace period when preempting another priority band for this priority band.
422 		 * The value for idle priority band is ignored, as it never preempts other bands.
423 		 */
424 		uint64_t		grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
425 
426 		/* Default quantum for scheduling across processes within a priority band. */
427 		uint64_t		process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
428 
429 		/* Default grace period for processes that preempt each other within a priority band.*/
430 		uint64_t		process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
431 
432 		/* For normal level this field specifies the target GPU percentage in situations when it's starved by the high level.
433 		 * Valid values are between 0 and 50, with the default being 10.
434 		 */
435 		uint32_t		normal_yield_percent;
436 
437 		struct MES_API_STATUS	api_status;
438 		uint64_t		timestamp;
439 	};
440 
441 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
442 };
443 
444 union MESAPI__PERFORM_YIELD {
445 	struct {
446 		union MES_API_HEADER	header;
447 		uint32_t		dummy;
448 		struct MES_API_STATUS	api_status;
449 		uint64_t		timestamp;
450 	};
451 
452 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
453 };
454 
455 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
456 	struct {
457 		union MES_API_HEADER		header;
458 		uint32_t			inprocess_gang_priority;
459 		enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
460 		uint64_t			gang_quantum;
461 		uint64_t			gang_context_addr;
462 		struct MES_API_STATUS		api_status;
463 		uint32_t			doorbell_offset;
464 		uint64_t			timestamp;
465 		uint32_t			gang_context_array_index;
466 		struct {
467 			uint32_t		queue_quantum_scale	: 2;
468 			uint32_t		queue_quantum_duration	: 8;
469 			uint32_t		apply_quantum_all_processes : 1;
470 			uint32_t		reserved		: 21;
471 		};
472 	};
473 
474 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
475 };
476 
477 union MESAPI__SUSPEND {
478 	struct {
479 		union MES_API_HEADER	header;
480 		/* false - suspend all gangs; true - specific gang */
481 		struct {
482 			uint32_t	suspend_all_gangs : 1;
483 			uint32_t	reserved : 31;
484 		};
485 		/* gang_context_addr is valid only if suspend_all = false */
486 
487 		uint64_t		gang_context_addr;
488 
489 		uint64_t		suspend_fence_addr;
490 		uint32_t		suspend_fence_value;
491 
492 		struct MES_API_STATUS	api_status;
493 
494 		union {
495 			uint32_t return_value; // to be removed
496 			uint32_t sch_id;       //keep the old return_value temporarily for compatibility
497 		};
498 		uint32_t		doorbell_offset;
499 		uint64_t		timestamp;
500 		enum MES_QUEUE_TYPE	legacy_uq_type;
501 		enum MES_AMD_PRIORITY_LEVEL legacy_uq_priority_level;
502 		uint32_t		gang_context_array_index;
503 	};
504 
505 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
506 };
507 
508 union MESAPI__RESUME {
509 	struct {
510 		union MES_API_HEADER	header;
511 		/* false - resume all gangs; true - specified gang */
512 		struct {
513 			uint32_t	resume_all_gangs : 1;
514 			uint32_t	reserved : 31;
515 		};
516 		/* valid only if resume_all_gangs = false */
517 		uint64_t		gang_context_addr;
518 
519 		struct MES_API_STATUS	api_status;
520 		uint32_t		doorbell_offset;
521 		uint64_t		timestamp;
522 		uint32_t		gang_context_array_index;
523 	};
524 
525 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
526 };
527 
528 union MESAPI__RESET {
529 	struct {
530 		union MES_API_HEADER		header;
531 
532 		struct {
533 			/* Only reset the queue given by doorbell_offset (not entire gang) */
534 			uint32_t		reset_queue_only : 1;
535 			/* Hang detection first then reset any queues that are hung */
536 			uint32_t		hang_detect_then_reset : 1;
537 			/* Only do hang detection (no reset) */
538 			uint32_t		hang_detect_only : 1;
539 			/* Reset HP and LP kernel queues not managed by MES */
540 			uint32_t		reset_legacy_gfx : 1;
541 			/* Fallback to use conneceted queue index when CP_CNTX_STAT method fails (gfx pipe 0) */
542 			uint32_t		use_connected_queue_index : 1;
543 			/* For gfx pipe 1 */
544 			uint32_t		use_connected_queue_index_p1 : 1;
545 			uint32_t		reserved : 26;
546 		};
547 
548 		uint64_t			gang_context_addr;
549 
550 		/* valid only if reset_queue_only = true */
551 		uint32_t			doorbell_offset;
552 
553 		/* valid only if hang_detect_then_reset = true */
554 		uint64_t			doorbell_offset_addr;
555 		enum MES_QUEUE_TYPE		queue_type;
556 
557 		/* valid only if reset_legacy_gfx = true */
558 		uint32_t			pipe_id_lp;
559 		uint32_t			queue_id_lp;
560 		uint32_t			vmid_id_lp;
561 		uint64_t			mqd_mc_addr_lp;
562 		uint32_t			doorbell_offset_lp;
563 		uint64_t			wptr_addr_lp;
564 
565 		uint32_t			pipe_id_hp;
566 		uint32_t			queue_id_hp;
567 		uint32_t			vmid_id_hp;
568 		uint64_t			mqd_mc_addr_hp;
569 		uint32_t			doorbell_offset_hp;
570 		uint64_t			wptr_addr_hp;
571 
572 		struct MES_API_STATUS		api_status;
573 		uint32_t			active_vmids;
574 		uint64_t			timestamp;
575 
576 		uint32_t			gang_context_array_index;
577 
578 		uint32_t			connected_queue_index;
579 		uint32_t			connected_queue_index_p1;
580 	};
581 
582 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
583 };
584 
585 union MESAPI__SET_LOGGING_BUFFER {
586 	struct {
587 		union MES_API_HEADER		header;
588 		/* There are separate log buffers for each queue type */
589 		enum MES_QUEUE_TYPE		log_type;
590 		/* Log buffer GPU Address */
591 		uint64_t			logging_buffer_addr;
592 		/* number of entries in the log buffer */
593 		uint32_t			number_of_entries;
594 		/* Entry index at which CPU interrupt needs to be signalled */
595 		uint32_t			interrupt_entry;
596 
597 		struct MES_API_STATUS		api_status;
598 		uint64_t			timestamp;
599 		uint32_t			vmid;
600 	};
601 
602 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
603 };
604 
605 enum MES_API_QUERY_MES_OPCODE {
606 	MES_API_QUERY_MES__GET_CTX_ARRAY_SIZE,
607 	MES_API_QUERY_MES__CHECK_HEALTHY,
608 	MES_API_QUERY_MES__MAX,
609 };
610 
611 enum { QUERY_MES_MAX_SIZE_IN_DWORDS = 20 };
612 
613 struct MES_API_QUERY_MES__CTX_ARRAY_SIZE {
614 	uint64_t	proc_ctx_array_size_addr;
615 	uint64_t	gang_ctx_array_size_addr;
616 };
617 
618 struct MES_API_QUERY_MES__HEALTHY_CHECK {
619 	uint64_t	healthy_addr;
620 };
621 
622 union MESAPI__QUERY_MES_STATUS {
623 	struct {
624 		union MES_API_HEADER		header;
625 		enum MES_API_QUERY_MES_OPCODE	subopcode;
626 		struct MES_API_STATUS		api_status;
627 		uint64_t			timestamp;
628 		union {
629 			struct MES_API_QUERY_MES__CTX_ARRAY_SIZE	ctx_array_size;
630 			struct MES_API_QUERY_MES__HEALTHY_CHECK	healthy_check;
631 			uint32_t data[QUERY_MES_MAX_SIZE_IN_DWORDS];
632 		};
633 	};
634 
635 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
636 };
637 
638 union MESAPI__SET_DEBUG_VMID {
639 	struct {
640 		union MES_API_HEADER	header;
641 		struct MES_API_STATUS	api_status;
642 		union {
643 			struct {
644 			uint32_t use_gds   : 1;
645 			uint32_t operation : 2;
646 			uint32_t reserved  : 29;
647 			} flags;
648 			uint32_t u32All;
649 		};
650 		uint32_t		reserved;
651 		uint32_t		debug_vmid;
652 		uint64_t		process_context_addr;
653 		uint64_t		page_table_base_addr;
654 		uint64_t		process_va_start;
655 		uint64_t		process_va_end;
656 		uint32_t		gds_base;
657 		uint32_t		gds_size;
658 		uint32_t		gws_base;
659 		uint32_t		gws_size;
660 		uint32_t		oa_mask;
661 
662 		uint64_t		output_addr; // output addr of the acquired vmid value
663 
664 		uint64_t		timestamp;
665 
666 		uint32_t		process_vm_cntl;
667 		enum MES_QUEUE_TYPE	queue_type;
668 
669 		uint32_t		process_context_array_index;
670 
671 		uint32_t		alignment_mode_setting;
672 	};
673 
674 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
675 };
676 
677 enum MESAPI_MISC_OPCODE {
678 	MESAPI_MISC__WRITE_REG,
679 	MESAPI_MISC__INV_GART,
680 	MESAPI_MISC__QUERY_STATUS,
681 	MESAPI_MISC__READ_REG,
682 	MESAPI_MISC__WAIT_REG_MEM,
683 	MESAPI_MISC__SET_SHADER_DEBUGGER,
684 	MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
685 	MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
686 	MESAPI_MISC__QUERY_HUNG_ENGINE_ID,
687 	MESAPI_MISC__CHANGE_CONFIG,
688 	MESAPI_MISC__LAUNCH_CLEANER_SHADER,
689 	MESAPI_MISC__SETUP_MES_DBGEXT,
690 
691 	MESAPI_MISC__MAX,
692 };
693 
694 enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20};
695 
696 struct WRITE_REG {
697 	uint32_t	reg_offset;
698 	uint32_t	reg_value;
699 };
700 
701 struct READ_REG {
702 	uint32_t reg_offset;
703 	uint64_t buffer_addr;
704 	union {
705 		struct {
706 			uint32_t read64Bits : 1;
707 			uint32_t reserved : 31;
708 		} bits;
709 		uint32_t all;
710 	} option;
711 };
712 
713 struct INV_GART {
714 	uint64_t	inv_range_va_start;
715 	uint64_t	inv_range_size;
716 };
717 
718 struct QUERY_STATUS {
719 	uint32_t context_id;
720 };
721 
722 enum WRM_OPERATION {
723 	WRM_OPERATION__WAIT_REG_MEM,
724 	WRM_OPERATION__WR_WAIT_WR_REG,
725 
726 	WRM_OPERATION__MAX,
727 };
728 
729 struct WAIT_REG_MEM {
730 	enum WRM_OPERATION op;
731 	/* only function = equal_to_the_reference_value and mem_space = register_space supported for now */
732 	uint32_t reference;
733 	uint32_t mask;
734 	uint32_t reg_offset1;
735 	uint32_t reg_offset2;
736 };
737 
738 struct SET_SHADER_DEBUGGER {
739 	uint64_t process_context_addr;
740 	union {
741 		struct {
742 			uint32_t single_memop : 1; // SQ_DEBUG.single_memop
743 			uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op
744 			uint32_t reserved : 30;
745 		};
746 		uint32_t u32all;
747 	} flags;
748 	uint32_t spi_gdbg_per_vmid_cntl;
749 	uint32_t tcp_watch_cntl[4]; // TCP_WATCHx_CNTL
750 	uint32_t trap_en;
751 };
752 
753 struct SET_GANG_SUBMIT {
754 	uint64_t gang_context_addr;
755 	uint64_t slave_gang_context_addr;
756 	uint32_t gang_context_array_index;
757 	uint32_t slave_gang_context_array_index;
758 };
759 
760 enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
761 	MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
762 	MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
763 	MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG    = 2,
764 
765 	MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
766 };
767 
768 struct CHANGE_CONFIG {
769 	enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
770 	union {
771 		struct  {
772 			uint32_t limit_single_process : 1;
773 			uint32_t enable_hws_logging_buffer : 1;
774 			uint32_t reserved : 30;
775 		} bits;
776 		uint32_t all;
777 	} option;
778 
779 	struct {
780 		uint32_t tdr_level;
781 		uint32_t tdr_delay;
782 	} tdr_config;
783 };
784 
785 union MESAPI__MISC {
786 	struct {
787 		union MES_API_HEADER	header;
788 		enum MESAPI_MISC_OPCODE opcode;
789 		struct MES_API_STATUS	api_status;
790 		union {
791 			struct WRITE_REG write_reg;
792 			struct INV_GART inv_gart;
793 			struct QUERY_STATUS query_status;
794 			struct READ_REG read_reg;
795 			struct WAIT_REG_MEM wait_reg_mem;
796 			struct SET_SHADER_DEBUGGER set_shader_debugger;
797 			enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
798 			struct CHANGE_CONFIG change_config;
799 			uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
800 		};
801 		uint64_t		timestamp;
802 		uint32_t		doorbell_offset;
803 		uint32_t		os_fence;
804 	};
805 
806 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
807 };
808 
809 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
810 	struct {
811 		union MES_API_HEADER		header;
812 		uint64_t			page_table_base_addr;
813 		uint64_t			process_context_addr;
814 		struct MES_API_STATUS		api_status;
815 		uint64_t			timestamp;
816 		uint32_t			process_context_array_index;
817 	};
818 
819 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
820 };
821 
822 union MESAPI_AMD_LOG {
823 	struct {
824 		union MES_API_HEADER		header;
825 		uint64_t			p_buffer_memory;
826 		uint64_t			p_buffer_size_used;
827 		struct MES_API_STATUS		api_status;
828 		uint64_t			timestamp;
829 	};
830 
831 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
832 };
833 
834 enum MES_SE_MODE {
835 	MES_SE_MODE_INVALID	= 0,
836 	MES_SE_MODE_SINGLE_SE	= 1,
837 	MES_SE_MODE_DUAL_SE	= 2,
838 	MES_SE_MODE_LOWER_POWER	= 3,
839 };
840 
841 union MESAPI__SET_SE_MODE {
842 	struct {
843 		union MES_API_HEADER header;
844 		/* the new SE mode to apply*/
845 		enum MES_SE_MODE new_se_mode;
846 		/* the fence to make sure the ItCpgCtxtSync packet is completed */
847 		uint64_t cpg_ctxt_sync_fence_addr;
848 		uint32_t cpg_ctxt_sync_fence_value;
849 		/* log_seq_time - Scheduler logs the switch seq start/end ts in the IH cookies */
850 		union {
851 			struct {
852 				uint32_t log_seq_time : 1;
853 				uint32_t reserved : 31;
854 			};
855 			uint32_t uint32_all;
856 		};
857 		struct MES_API_STATUS api_status;
858 	};
859 
860 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
861 };
862 
863 union MESAPI__SET_GANG_SUBMIT {
864 	struct {
865 		union MES_API_HEADER	header;
866 		struct MES_API_STATUS	api_status;
867 		struct SET_GANG_SUBMIT	set_gang_submit;
868 	};
869 
870 	uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
871 };
872 
873 #pragma pack(pop)
874 
875 #endif
876