1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 OD_FAN_ZERO_RPM_ENABLE, 123 OD_FAN_ZERO_RPM_STOP_TEMP, 124 }; 125 126 enum amd_pp_sensors { 127 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 128 AMDGPU_PP_SENSOR_CPU_CLK, 129 AMDGPU_PP_SENSOR_VDDNB, 130 AMDGPU_PP_SENSOR_VDDGFX, 131 AMDGPU_PP_SENSOR_UVD_VCLK, 132 AMDGPU_PP_SENSOR_UVD_DCLK, 133 AMDGPU_PP_SENSOR_VCE_ECCLK, 134 AMDGPU_PP_SENSOR_GPU_LOAD, 135 AMDGPU_PP_SENSOR_MEM_LOAD, 136 AMDGPU_PP_SENSOR_GFX_MCLK, 137 AMDGPU_PP_SENSOR_GPU_TEMP, 138 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 139 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 140 AMDGPU_PP_SENSOR_MEM_TEMP, 141 AMDGPU_PP_SENSOR_VCE_POWER, 142 AMDGPU_PP_SENSOR_UVD_POWER, 143 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 144 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 145 AMDGPU_PP_SENSOR_SS_APU_SHARE, 146 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 147 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 148 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 149 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 150 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 151 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 152 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 153 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 154 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 155 AMDGPU_PP_SENSOR_VCN_LOAD, 156 }; 157 158 enum amd_pp_task { 159 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 160 AMD_PP_TASK_ENABLE_USER_STATE, 161 AMD_PP_TASK_READJUST_POWER_STATE, 162 AMD_PP_TASK_COMPLETE_INIT, 163 AMD_PP_TASK_MAX 164 }; 165 166 enum PP_SMC_POWER_PROFILE { 167 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 168 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 169 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 170 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 171 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 172 PP_SMC_POWER_PROFILE_VR = 0x4, 173 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 174 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 175 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 176 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 177 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 178 PP_SMC_POWER_PROFILE_COUNT, 179 }; 180 181 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 182 183 184 185 enum { 186 PP_GROUP_UNKNOWN = 0, 187 PP_GROUP_GFX = 1, 188 PP_GROUP_SYS, 189 PP_GROUP_MAX 190 }; 191 192 enum PP_OD_DPM_TABLE_COMMAND { 193 PP_OD_EDIT_SCLK_VDDC_TABLE, 194 PP_OD_EDIT_MCLK_VDDC_TABLE, 195 PP_OD_EDIT_CCLK_VDDC_TABLE, 196 PP_OD_EDIT_VDDC_CURVE, 197 PP_OD_RESTORE_DEFAULT_TABLE, 198 PP_OD_COMMIT_DPM_TABLE, 199 PP_OD_EDIT_VDDGFX_OFFSET, 200 PP_OD_EDIT_FAN_CURVE, 201 PP_OD_EDIT_ACOUSTIC_LIMIT, 202 PP_OD_EDIT_ACOUSTIC_TARGET, 203 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 204 PP_OD_EDIT_FAN_MINIMUM_PWM, 205 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 206 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 207 }; 208 209 struct pp_states_info { 210 uint32_t nums; 211 uint32_t states[16]; 212 }; 213 214 enum PP_HWMON_TEMP { 215 PP_TEMP_EDGE = 0, 216 PP_TEMP_JUNCTION, 217 PP_TEMP_MEM, 218 PP_TEMP_MAX 219 }; 220 221 enum pp_mp1_state { 222 PP_MP1_STATE_NONE, 223 PP_MP1_STATE_SHUTDOWN, 224 PP_MP1_STATE_UNLOAD, 225 PP_MP1_STATE_RESET, 226 PP_MP1_STATE_FLR, 227 }; 228 229 enum pp_df_cstate { 230 DF_CSTATE_DISALLOW = 0, 231 DF_CSTATE_ALLOW, 232 }; 233 234 /** 235 * DOC: amdgpu_pp_power 236 * 237 * APU power is managed to system-level requirements through the PPT 238 * (package power tracking) feature. PPT is intended to limit power to the 239 * requirements of the power source and could be dynamically updated to 240 * maximize APU performance within the system power budget. 241 * 242 * Two types of power measurement can be requested, where supported, with 243 * :c:type:`enum pp_power_type <pp_power_type>`. 244 */ 245 246 /** 247 * enum pp_power_limit_level - Used to query the power limits 248 * 249 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 250 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 251 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 252 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 253 */ 254 enum pp_power_limit_level { 255 PP_PWR_LIMIT_MIN = -1, 256 PP_PWR_LIMIT_CURRENT, 257 PP_PWR_LIMIT_DEFAULT, 258 PP_PWR_LIMIT_MAX, 259 }; 260 261 /** 262 * enum pp_power_type - Used to specify the type of the requested power 263 * 264 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 265 * moving average of APU power (default ~5000 ms). 266 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 267 * where supported. 268 */ 269 enum pp_power_type { 270 PP_PWR_TYPE_SUSTAINED, 271 PP_PWR_TYPE_FAST, 272 }; 273 274 enum pp_xgmi_plpd_mode { 275 XGMI_PLPD_NONE = -1, 276 XGMI_PLPD_DISALLOW, 277 XGMI_PLPD_DEFAULT, 278 XGMI_PLPD_OPTIMIZED, 279 XGMI_PLPD_COUNT, 280 }; 281 282 enum pp_pm_policy { 283 PP_PM_POLICY_NONE = -1, 284 PP_PM_POLICY_SOC_PSTATE = 0, 285 PP_PM_POLICY_XGMI_PLPD, 286 PP_PM_POLICY_NUM, 287 }; 288 289 enum pp_policy_soc_pstate { 290 SOC_PSTATE_DEFAULT = 0, 291 SOC_PSTATE_0, 292 SOC_PSTATE_1, 293 SOC_PSTATE_2, 294 SOC_PSTAT_COUNT, 295 }; 296 297 #define PP_POLICY_MAX_LEVELS 5 298 299 #define PP_GROUP_MASK 0xF0000000 300 #define PP_GROUP_SHIFT 28 301 302 #define PP_BLOCK_MASK 0x0FFFFF00 303 #define PP_BLOCK_SHIFT 8 304 305 #define PP_BLOCK_GFX_CG 0x01 306 #define PP_BLOCK_GFX_MG 0x02 307 #define PP_BLOCK_GFX_3D 0x04 308 #define PP_BLOCK_GFX_RLC 0x08 309 #define PP_BLOCK_GFX_CP 0x10 310 #define PP_BLOCK_SYS_BIF 0x01 311 #define PP_BLOCK_SYS_MC 0x02 312 #define PP_BLOCK_SYS_ROM 0x04 313 #define PP_BLOCK_SYS_DRM 0x08 314 #define PP_BLOCK_SYS_HDP 0x10 315 #define PP_BLOCK_SYS_SDMA 0x20 316 317 #define PP_STATE_MASK 0x0000000F 318 #define PP_STATE_SHIFT 0 319 #define PP_STATE_SUPPORT_MASK 0x000000F0 320 #define PP_STATE_SUPPORT_SHIFT 0 321 322 #define PP_STATE_CG 0x01 323 #define PP_STATE_LS 0x02 324 #define PP_STATE_DS 0x04 325 #define PP_STATE_SD 0x08 326 #define PP_STATE_SUPPORT_CG 0x10 327 #define PP_STATE_SUPPORT_LS 0x20 328 #define PP_STATE_SUPPORT_DS 0x40 329 #define PP_STATE_SUPPORT_SD 0x80 330 331 #define PP_CG_MSG_ID(group, block, support, state) \ 332 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 333 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 334 335 #define XGMI_MODE_PSTATE_D3 0 336 #define XGMI_MODE_PSTATE_D0 1 337 338 #define NUM_HBM_INSTANCES 4 339 #define NUM_XGMI_LINKS 8 340 #define MAX_GFX_CLKS 8 341 #define MAX_CLKS 4 342 #define NUM_VCN 4 343 #define NUM_JPEG_ENG 32 344 #define NUM_JPEG_ENG_V1 40 345 #define MAX_XCC 8 346 #define NUM_XCP 8 347 struct seq_file; 348 enum amd_pp_clock_type; 349 struct amd_pp_simple_clock_info; 350 struct amd_pp_display_configuration; 351 struct amd_pp_clock_info; 352 struct pp_display_clock_request; 353 struct pp_clock_levels_with_voltage; 354 struct pp_clock_levels_with_latency; 355 struct amd_pp_clocks; 356 struct pp_smu_wm_range_sets; 357 struct pp_smu_nv_clock_table; 358 struct dpm_clocks; 359 360 struct amdgpu_xcp_metrics { 361 /* Utilization Instantaneous (%) */ 362 uint32_t gfx_busy_inst[MAX_XCC]; 363 uint16_t jpeg_busy[NUM_JPEG_ENG]; 364 uint16_t vcn_busy[NUM_VCN]; 365 /* Utilization Accumulated (%) */ 366 uint64_t gfx_busy_acc[MAX_XCC]; 367 }; 368 369 struct amdgpu_xcp_metrics_v1_1 { 370 /* Utilization Instantaneous (%) */ 371 uint32_t gfx_busy_inst[MAX_XCC]; 372 uint16_t jpeg_busy[NUM_JPEG_ENG]; 373 uint16_t vcn_busy[NUM_VCN]; 374 /* Utilization Accumulated (%) */ 375 uint64_t gfx_busy_acc[MAX_XCC]; 376 /* Total App Clock Counter Accumulated */ 377 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 378 }; 379 380 struct amdgpu_xcp_metrics_v1_2 { 381 /* Utilization Instantaneous (%) */ 382 uint32_t gfx_busy_inst[MAX_XCC]; 383 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 384 uint16_t vcn_busy[NUM_VCN]; 385 /* Utilization Accumulated (%) */ 386 uint64_t gfx_busy_acc[MAX_XCC]; 387 /* Total App Clock Counter Accumulated */ 388 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 389 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 390 uint64_t gfx_low_utilization_acc[MAX_XCC]; 391 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 392 }; 393 394 struct amd_pm_funcs { 395 /* export for dpm on ci and si */ 396 int (*pre_set_power_state)(void *handle); 397 int (*set_power_state)(void *handle); 398 void (*post_set_power_state)(void *handle); 399 void (*display_configuration_changed)(void *handle); 400 void (*print_power_state)(void *handle, void *ps); 401 bool (*vblank_too_short)(void *handle); 402 void (*enable_bapm)(void *handle, bool enable); 403 int (*check_state_equal)(void *handle, 404 void *cps, 405 void *rps, 406 bool *equal); 407 /* export for sysfs */ 408 int (*set_fan_control_mode)(void *handle, u32 mode); 409 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 410 int (*set_fan_speed_pwm)(void *handle, u32 speed); 411 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 412 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 413 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 414 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 415 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 416 int (*get_sclk_od)(void *handle); 417 int (*set_sclk_od)(void *handle, uint32_t value); 418 int (*get_mclk_od)(void *handle); 419 int (*set_mclk_od)(void *handle, uint32_t value); 420 int (*read_sensor)(void *handle, int idx, void *value, int *size); 421 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 422 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 423 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 424 enum amd_pm_state_type (*get_current_power_state)(void *handle); 425 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 426 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 427 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 428 int (*get_pp_table)(void *handle, char **table); 429 int (*set_pp_table)(void *handle, const char *buf, size_t size); 430 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 431 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 432 int (*pause_power_profile)(void *handle, bool pause); 433 /* export to amdgpu */ 434 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 435 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 436 enum amd_pm_state_type *user_state); 437 int (*load_firmware)(void *handle); 438 int (*wait_for_fw_loading_complete)(void *handle); 439 int (*set_powergating_by_smu)(void *handle, 440 uint32_t block_type, 441 bool gate, 442 int inst); 443 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 444 int (*set_power_limit)(void *handle, uint32_t n); 445 int (*get_power_limit)(void *handle, uint32_t *limit, 446 enum pp_power_limit_level pp_limit_level, 447 enum pp_power_type power_type); 448 int (*get_power_profile_mode)(void *handle, char *buf); 449 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 450 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 451 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 452 long *input, uint32_t size); 453 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 454 int (*smu_i2c_bus_access)(void *handle, bool acquire); 455 int (*gfx_state_change_set)(void *handle, uint32_t state); 456 /* export to DC */ 457 u32 (*get_sclk)(void *handle, bool low); 458 u32 (*get_mclk)(void *handle, bool low); 459 int (*display_configuration_change)(void *handle, 460 const struct amd_pp_display_configuration *input); 461 int (*get_display_power_level)(void *handle, 462 struct amd_pp_simple_clock_info *output); 463 int (*get_current_clocks)(void *handle, 464 struct amd_pp_clock_info *clocks); 465 int (*get_clock_by_type)(void *handle, 466 enum amd_pp_clock_type type, 467 struct amd_pp_clocks *clocks); 468 int (*get_clock_by_type_with_latency)(void *handle, 469 enum amd_pp_clock_type type, 470 struct pp_clock_levels_with_latency *clocks); 471 int (*get_clock_by_type_with_voltage)(void *handle, 472 enum amd_pp_clock_type type, 473 struct pp_clock_levels_with_voltage *clocks); 474 int (*set_watermarks_for_clocks_ranges)(void *handle, 475 void *clock_ranges); 476 int (*display_clock_voltage_request)(void *handle, 477 struct pp_display_clock_request *clock); 478 int (*get_display_mode_validation_clocks)(void *handle, 479 struct amd_pp_simple_clock_info *clocks); 480 int (*notify_smu_enable_pwe)(void *handle); 481 int (*enable_mgpu_fan_boost)(void *handle); 482 int (*set_active_display_count)(void *handle, uint32_t count); 483 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 484 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 485 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 486 int (*get_asic_baco_capability)(void *handle); 487 int (*get_asic_baco_state)(void *handle, int *state); 488 int (*set_asic_baco_state)(void *handle, int state); 489 int (*get_ppfeature_status)(void *handle, char *buf); 490 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 491 int (*asic_reset_mode_2)(void *handle); 492 int (*asic_reset_enable_gfx_features)(void *handle); 493 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 494 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 495 ssize_t (*get_gpu_metrics)(void *handle, void **table); 496 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 497 int (*set_watermarks_for_clock_ranges)(void *handle, 498 struct pp_smu_wm_range_sets *ranges); 499 int (*display_disable_memory_clock_switch)(void *handle, 500 bool disable_memory_clock_switch); 501 int (*get_max_sustainable_clocks_by_dc)(void *handle, 502 struct pp_smu_nv_clock_table *max_clocks); 503 int (*get_uclk_dpm_states)(void *handle, 504 unsigned int *clock_values_in_khz, 505 unsigned int *num_states); 506 int (*get_dpm_clock_table)(void *handle, 507 struct dpm_clocks *clock_table); 508 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 509 void (*pm_compute_clocks)(void *handle); 510 int (*notify_rlc_state)(void *handle, bool en); 511 }; 512 513 struct metrics_table_header { 514 uint16_t structure_size; 515 uint8_t format_revision; 516 uint8_t content_revision; 517 }; 518 519 /* 520 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 521 * Use gpu_metrics_v1_1 or later instead. 522 */ 523 struct gpu_metrics_v1_0 { 524 struct metrics_table_header common_header; 525 526 /* Driver attached timestamp (in ns) */ 527 uint64_t system_clock_counter; 528 529 /* Temperature */ 530 uint16_t temperature_edge; 531 uint16_t temperature_hotspot; 532 uint16_t temperature_mem; 533 uint16_t temperature_vrgfx; 534 uint16_t temperature_vrsoc; 535 uint16_t temperature_vrmem; 536 537 /* Utilization */ 538 uint16_t average_gfx_activity; 539 uint16_t average_umc_activity; // memory controller 540 uint16_t average_mm_activity; // UVD or VCN 541 542 /* Power/Energy */ 543 uint16_t average_socket_power; 544 uint32_t energy_accumulator; 545 546 /* Average clocks */ 547 uint16_t average_gfxclk_frequency; 548 uint16_t average_socclk_frequency; 549 uint16_t average_uclk_frequency; 550 uint16_t average_vclk0_frequency; 551 uint16_t average_dclk0_frequency; 552 uint16_t average_vclk1_frequency; 553 uint16_t average_dclk1_frequency; 554 555 /* Current clocks */ 556 uint16_t current_gfxclk; 557 uint16_t current_socclk; 558 uint16_t current_uclk; 559 uint16_t current_vclk0; 560 uint16_t current_dclk0; 561 uint16_t current_vclk1; 562 uint16_t current_dclk1; 563 564 /* Throttle status */ 565 uint32_t throttle_status; 566 567 /* Fans */ 568 uint16_t current_fan_speed; 569 570 /* Link width/speed */ 571 uint8_t pcie_link_width; 572 uint8_t pcie_link_speed; // in 0.1 GT/s 573 }; 574 575 struct gpu_metrics_v1_1 { 576 struct metrics_table_header common_header; 577 578 /* Temperature */ 579 uint16_t temperature_edge; 580 uint16_t temperature_hotspot; 581 uint16_t temperature_mem; 582 uint16_t temperature_vrgfx; 583 uint16_t temperature_vrsoc; 584 uint16_t temperature_vrmem; 585 586 /* Utilization */ 587 uint16_t average_gfx_activity; 588 uint16_t average_umc_activity; // memory controller 589 uint16_t average_mm_activity; // UVD or VCN 590 591 /* Power/Energy */ 592 uint16_t average_socket_power; 593 uint64_t energy_accumulator; 594 595 /* Driver attached timestamp (in ns) */ 596 uint64_t system_clock_counter; 597 598 /* Average clocks */ 599 uint16_t average_gfxclk_frequency; 600 uint16_t average_socclk_frequency; 601 uint16_t average_uclk_frequency; 602 uint16_t average_vclk0_frequency; 603 uint16_t average_dclk0_frequency; 604 uint16_t average_vclk1_frequency; 605 uint16_t average_dclk1_frequency; 606 607 /* Current clocks */ 608 uint16_t current_gfxclk; 609 uint16_t current_socclk; 610 uint16_t current_uclk; 611 uint16_t current_vclk0; 612 uint16_t current_dclk0; 613 uint16_t current_vclk1; 614 uint16_t current_dclk1; 615 616 /* Throttle status */ 617 uint32_t throttle_status; 618 619 /* Fans */ 620 uint16_t current_fan_speed; 621 622 /* Link width/speed */ 623 uint16_t pcie_link_width; 624 uint16_t pcie_link_speed; // in 0.1 GT/s 625 626 uint16_t padding; 627 628 uint32_t gfx_activity_acc; 629 uint32_t mem_activity_acc; 630 631 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 632 }; 633 634 struct gpu_metrics_v1_2 { 635 struct metrics_table_header common_header; 636 637 /* Temperature */ 638 uint16_t temperature_edge; 639 uint16_t temperature_hotspot; 640 uint16_t temperature_mem; 641 uint16_t temperature_vrgfx; 642 uint16_t temperature_vrsoc; 643 uint16_t temperature_vrmem; 644 645 /* Utilization */ 646 uint16_t average_gfx_activity; 647 uint16_t average_umc_activity; // memory controller 648 uint16_t average_mm_activity; // UVD or VCN 649 650 /* Power/Energy */ 651 uint16_t average_socket_power; 652 uint64_t energy_accumulator; 653 654 /* Driver attached timestamp (in ns) */ 655 uint64_t system_clock_counter; 656 657 /* Average clocks */ 658 uint16_t average_gfxclk_frequency; 659 uint16_t average_socclk_frequency; 660 uint16_t average_uclk_frequency; 661 uint16_t average_vclk0_frequency; 662 uint16_t average_dclk0_frequency; 663 uint16_t average_vclk1_frequency; 664 uint16_t average_dclk1_frequency; 665 666 /* Current clocks */ 667 uint16_t current_gfxclk; 668 uint16_t current_socclk; 669 uint16_t current_uclk; 670 uint16_t current_vclk0; 671 uint16_t current_dclk0; 672 uint16_t current_vclk1; 673 uint16_t current_dclk1; 674 675 /* Throttle status (ASIC dependent) */ 676 uint32_t throttle_status; 677 678 /* Fans */ 679 uint16_t current_fan_speed; 680 681 /* Link width/speed */ 682 uint16_t pcie_link_width; 683 uint16_t pcie_link_speed; // in 0.1 GT/s 684 685 uint16_t padding; 686 687 uint32_t gfx_activity_acc; 688 uint32_t mem_activity_acc; 689 690 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 691 692 /* PMFW attached timestamp (10ns resolution) */ 693 uint64_t firmware_timestamp; 694 }; 695 696 struct gpu_metrics_v1_3 { 697 struct metrics_table_header common_header; 698 699 /* Temperature */ 700 uint16_t temperature_edge; 701 uint16_t temperature_hotspot; 702 uint16_t temperature_mem; 703 uint16_t temperature_vrgfx; 704 uint16_t temperature_vrsoc; 705 uint16_t temperature_vrmem; 706 707 /* Utilization */ 708 uint16_t average_gfx_activity; 709 uint16_t average_umc_activity; // memory controller 710 uint16_t average_mm_activity; // UVD or VCN 711 712 /* Power/Energy */ 713 uint16_t average_socket_power; 714 uint64_t energy_accumulator; 715 716 /* Driver attached timestamp (in ns) */ 717 uint64_t system_clock_counter; 718 719 /* Average clocks */ 720 uint16_t average_gfxclk_frequency; 721 uint16_t average_socclk_frequency; 722 uint16_t average_uclk_frequency; 723 uint16_t average_vclk0_frequency; 724 uint16_t average_dclk0_frequency; 725 uint16_t average_vclk1_frequency; 726 uint16_t average_dclk1_frequency; 727 728 /* Current clocks */ 729 uint16_t current_gfxclk; 730 uint16_t current_socclk; 731 uint16_t current_uclk; 732 uint16_t current_vclk0; 733 uint16_t current_dclk0; 734 uint16_t current_vclk1; 735 uint16_t current_dclk1; 736 737 /* Throttle status */ 738 uint32_t throttle_status; 739 740 /* Fans */ 741 uint16_t current_fan_speed; 742 743 /* Link width/speed */ 744 uint16_t pcie_link_width; 745 uint16_t pcie_link_speed; // in 0.1 GT/s 746 747 uint16_t padding; 748 749 uint32_t gfx_activity_acc; 750 uint32_t mem_activity_acc; 751 752 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 753 754 /* PMFW attached timestamp (10ns resolution) */ 755 uint64_t firmware_timestamp; 756 757 /* Voltage (mV) */ 758 uint16_t voltage_soc; 759 uint16_t voltage_gfx; 760 uint16_t voltage_mem; 761 762 uint16_t padding1; 763 764 /* Throttle status (ASIC independent) */ 765 uint64_t indep_throttle_status; 766 }; 767 768 struct gpu_metrics_v1_4 { 769 struct metrics_table_header common_header; 770 771 /* Temperature (Celsius) */ 772 uint16_t temperature_hotspot; 773 uint16_t temperature_mem; 774 uint16_t temperature_vrsoc; 775 776 /* Power (Watts) */ 777 uint16_t curr_socket_power; 778 779 /* Utilization (%) */ 780 uint16_t average_gfx_activity; 781 uint16_t average_umc_activity; // memory controller 782 uint16_t vcn_activity[NUM_VCN]; 783 784 /* Energy (15.259uJ (2^-16) units) */ 785 uint64_t energy_accumulator; 786 787 /* Driver attached timestamp (in ns) */ 788 uint64_t system_clock_counter; 789 790 /* Throttle status */ 791 uint32_t throttle_status; 792 793 /* Clock Lock Status. Each bit corresponds to clock instance */ 794 uint32_t gfxclk_lock_status; 795 796 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 797 uint16_t pcie_link_width; 798 uint16_t pcie_link_speed; 799 800 /* XGMI bus width and bitrate (in Gbps) */ 801 uint16_t xgmi_link_width; 802 uint16_t xgmi_link_speed; 803 804 /* Utilization Accumulated (%) */ 805 uint32_t gfx_activity_acc; 806 uint32_t mem_activity_acc; 807 808 /*PCIE accumulated bandwidth (GB/sec) */ 809 uint64_t pcie_bandwidth_acc; 810 811 /*PCIE instantaneous bandwidth (GB/sec) */ 812 uint64_t pcie_bandwidth_inst; 813 814 /* PCIE L0 to recovery state transition accumulated count */ 815 uint64_t pcie_l0_to_recov_count_acc; 816 817 /* PCIE replay accumulated count */ 818 uint64_t pcie_replay_count_acc; 819 820 /* PCIE replay rollover accumulated count */ 821 uint64_t pcie_replay_rover_count_acc; 822 823 /* XGMI accumulated data transfer size(KiloBytes) */ 824 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 825 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 826 827 /* PMFW attached timestamp (10ns resolution) */ 828 uint64_t firmware_timestamp; 829 830 /* Current clocks (Mhz) */ 831 uint16_t current_gfxclk[MAX_GFX_CLKS]; 832 uint16_t current_socclk[MAX_CLKS]; 833 uint16_t current_vclk0[MAX_CLKS]; 834 uint16_t current_dclk0[MAX_CLKS]; 835 uint16_t current_uclk; 836 837 uint16_t padding; 838 }; 839 840 struct gpu_metrics_v1_5 { 841 struct metrics_table_header common_header; 842 843 /* Temperature (Celsius) */ 844 uint16_t temperature_hotspot; 845 uint16_t temperature_mem; 846 uint16_t temperature_vrsoc; 847 848 /* Power (Watts) */ 849 uint16_t curr_socket_power; 850 851 /* Utilization (%) */ 852 uint16_t average_gfx_activity; 853 uint16_t average_umc_activity; // memory controller 854 uint16_t vcn_activity[NUM_VCN]; 855 uint16_t jpeg_activity[NUM_JPEG_ENG]; 856 857 /* Energy (15.259uJ (2^-16) units) */ 858 uint64_t energy_accumulator; 859 860 /* Driver attached timestamp (in ns) */ 861 uint64_t system_clock_counter; 862 863 /* Throttle status */ 864 uint32_t throttle_status; 865 866 /* Clock Lock Status. Each bit corresponds to clock instance */ 867 uint32_t gfxclk_lock_status; 868 869 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 870 uint16_t pcie_link_width; 871 uint16_t pcie_link_speed; 872 873 /* XGMI bus width and bitrate (in Gbps) */ 874 uint16_t xgmi_link_width; 875 uint16_t xgmi_link_speed; 876 877 /* Utilization Accumulated (%) */ 878 uint32_t gfx_activity_acc; 879 uint32_t mem_activity_acc; 880 881 /*PCIE accumulated bandwidth (GB/sec) */ 882 uint64_t pcie_bandwidth_acc; 883 884 /*PCIE instantaneous bandwidth (GB/sec) */ 885 uint64_t pcie_bandwidth_inst; 886 887 /* PCIE L0 to recovery state transition accumulated count */ 888 uint64_t pcie_l0_to_recov_count_acc; 889 890 /* PCIE replay accumulated count */ 891 uint64_t pcie_replay_count_acc; 892 893 /* PCIE replay rollover accumulated count */ 894 uint64_t pcie_replay_rover_count_acc; 895 896 /* PCIE NAK sent accumulated count */ 897 uint32_t pcie_nak_sent_count_acc; 898 899 /* PCIE NAK received accumulated count */ 900 uint32_t pcie_nak_rcvd_count_acc; 901 902 /* XGMI accumulated data transfer size(KiloBytes) */ 903 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 904 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 905 906 /* PMFW attached timestamp (10ns resolution) */ 907 uint64_t firmware_timestamp; 908 909 /* Current clocks (Mhz) */ 910 uint16_t current_gfxclk[MAX_GFX_CLKS]; 911 uint16_t current_socclk[MAX_CLKS]; 912 uint16_t current_vclk0[MAX_CLKS]; 913 uint16_t current_dclk0[MAX_CLKS]; 914 uint16_t current_uclk; 915 916 uint16_t padding; 917 }; 918 919 struct gpu_metrics_v1_6 { 920 struct metrics_table_header common_header; 921 922 /* Temperature (Celsius) */ 923 uint16_t temperature_hotspot; 924 uint16_t temperature_mem; 925 uint16_t temperature_vrsoc; 926 927 /* Power (Watts) */ 928 uint16_t curr_socket_power; 929 930 /* Utilization (%) */ 931 uint16_t average_gfx_activity; 932 uint16_t average_umc_activity; // memory controller 933 934 /* Energy (15.259uJ (2^-16) units) */ 935 uint64_t energy_accumulator; 936 937 /* Driver attached timestamp (in ns) */ 938 uint64_t system_clock_counter; 939 940 /* Accumulation cycle counter */ 941 uint32_t accumulation_counter; 942 943 /* Accumulated throttler residencies */ 944 uint32_t prochot_residency_acc; 945 uint32_t ppt_residency_acc; 946 uint32_t socket_thm_residency_acc; 947 uint32_t vr_thm_residency_acc; 948 uint32_t hbm_thm_residency_acc; 949 950 /* Clock Lock Status. Each bit corresponds to clock instance */ 951 uint32_t gfxclk_lock_status; 952 953 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 954 uint16_t pcie_link_width; 955 uint16_t pcie_link_speed; 956 957 /* XGMI bus width and bitrate (in Gbps) */ 958 uint16_t xgmi_link_width; 959 uint16_t xgmi_link_speed; 960 961 /* Utilization Accumulated (%) */ 962 uint32_t gfx_activity_acc; 963 uint32_t mem_activity_acc; 964 965 /*PCIE accumulated bandwidth (GB/sec) */ 966 uint64_t pcie_bandwidth_acc; 967 968 /*PCIE instantaneous bandwidth (GB/sec) */ 969 uint64_t pcie_bandwidth_inst; 970 971 /* PCIE L0 to recovery state transition accumulated count */ 972 uint64_t pcie_l0_to_recov_count_acc; 973 974 /* PCIE replay accumulated count */ 975 uint64_t pcie_replay_count_acc; 976 977 /* PCIE replay rollover accumulated count */ 978 uint64_t pcie_replay_rover_count_acc; 979 980 /* PCIE NAK sent accumulated count */ 981 uint32_t pcie_nak_sent_count_acc; 982 983 /* PCIE NAK received accumulated count */ 984 uint32_t pcie_nak_rcvd_count_acc; 985 986 /* XGMI accumulated data transfer size(KiloBytes) */ 987 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 988 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 989 990 /* PMFW attached timestamp (10ns resolution) */ 991 uint64_t firmware_timestamp; 992 993 /* Current clocks (Mhz) */ 994 uint16_t current_gfxclk[MAX_GFX_CLKS]; 995 uint16_t current_socclk[MAX_CLKS]; 996 uint16_t current_vclk0[MAX_CLKS]; 997 uint16_t current_dclk0[MAX_CLKS]; 998 uint16_t current_uclk; 999 1000 /* Number of current partition */ 1001 uint16_t num_partition; 1002 1003 /* XCP metrics stats */ 1004 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1005 1006 /* PCIE other end recovery counter */ 1007 uint32_t pcie_lc_perf_other_end_recovery; 1008 }; 1009 1010 struct gpu_metrics_v1_7 { 1011 struct metrics_table_header common_header; 1012 1013 /* Temperature (Celsius) */ 1014 uint16_t temperature_hotspot; 1015 uint16_t temperature_mem; 1016 uint16_t temperature_vrsoc; 1017 1018 /* Power (Watts) */ 1019 uint16_t curr_socket_power; 1020 1021 /* Utilization (%) */ 1022 uint16_t average_gfx_activity; 1023 uint16_t average_umc_activity; // memory controller 1024 1025 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1026 uint64_t mem_max_bandwidth; 1027 1028 /* Energy (15.259uJ (2^-16) units) */ 1029 uint64_t energy_accumulator; 1030 1031 /* Driver attached timestamp (in ns) */ 1032 uint64_t system_clock_counter; 1033 1034 /* Accumulation cycle counter */ 1035 uint32_t accumulation_counter; 1036 1037 /* Accumulated throttler residencies */ 1038 uint32_t prochot_residency_acc; 1039 uint32_t ppt_residency_acc; 1040 uint32_t socket_thm_residency_acc; 1041 uint32_t vr_thm_residency_acc; 1042 uint32_t hbm_thm_residency_acc; 1043 1044 /* Clock Lock Status. Each bit corresponds to clock instance */ 1045 uint32_t gfxclk_lock_status; 1046 1047 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1048 uint16_t pcie_link_width; 1049 uint16_t pcie_link_speed; 1050 1051 /* XGMI bus width and bitrate (in Gbps) */ 1052 uint16_t xgmi_link_width; 1053 uint16_t xgmi_link_speed; 1054 1055 /* Utilization Accumulated (%) */ 1056 uint32_t gfx_activity_acc; 1057 uint32_t mem_activity_acc; 1058 1059 /*PCIE accumulated bandwidth (GB/sec) */ 1060 uint64_t pcie_bandwidth_acc; 1061 1062 /*PCIE instantaneous bandwidth (GB/sec) */ 1063 uint64_t pcie_bandwidth_inst; 1064 1065 /* PCIE L0 to recovery state transition accumulated count */ 1066 uint64_t pcie_l0_to_recov_count_acc; 1067 1068 /* PCIE replay accumulated count */ 1069 uint64_t pcie_replay_count_acc; 1070 1071 /* PCIE replay rollover accumulated count */ 1072 uint64_t pcie_replay_rover_count_acc; 1073 1074 /* PCIE NAK sent accumulated count */ 1075 uint32_t pcie_nak_sent_count_acc; 1076 1077 /* PCIE NAK received accumulated count */ 1078 uint32_t pcie_nak_rcvd_count_acc; 1079 1080 /* XGMI accumulated data transfer size(KiloBytes) */ 1081 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1082 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1083 1084 /* XGMI link status(active/inactive) */ 1085 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1086 1087 uint16_t padding; 1088 1089 /* PMFW attached timestamp (10ns resolution) */ 1090 uint64_t firmware_timestamp; 1091 1092 /* Current clocks (Mhz) */ 1093 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1094 uint16_t current_socclk[MAX_CLKS]; 1095 uint16_t current_vclk0[MAX_CLKS]; 1096 uint16_t current_dclk0[MAX_CLKS]; 1097 uint16_t current_uclk; 1098 1099 /* Number of current partition */ 1100 uint16_t num_partition; 1101 1102 /* XCP metrics stats */ 1103 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1104 1105 /* PCIE other end recovery counter */ 1106 uint32_t pcie_lc_perf_other_end_recovery; 1107 }; 1108 1109 struct gpu_metrics_v1_8 { 1110 struct metrics_table_header common_header; 1111 1112 /* Temperature (Celsius) */ 1113 uint16_t temperature_hotspot; 1114 uint16_t temperature_mem; 1115 uint16_t temperature_vrsoc; 1116 1117 /* Power (Watts) */ 1118 uint16_t curr_socket_power; 1119 1120 /* Utilization (%) */ 1121 uint16_t average_gfx_activity; 1122 uint16_t average_umc_activity; // memory controller 1123 1124 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1125 uint64_t mem_max_bandwidth; 1126 1127 /* Energy (15.259uJ (2^-16) units) */ 1128 uint64_t energy_accumulator; 1129 1130 /* Driver attached timestamp (in ns) */ 1131 uint64_t system_clock_counter; 1132 1133 /* Accumulation cycle counter */ 1134 uint32_t accumulation_counter; 1135 1136 /* Accumulated throttler residencies */ 1137 uint32_t prochot_residency_acc; 1138 uint32_t ppt_residency_acc; 1139 uint32_t socket_thm_residency_acc; 1140 uint32_t vr_thm_residency_acc; 1141 uint32_t hbm_thm_residency_acc; 1142 1143 /* Clock Lock Status. Each bit corresponds to clock instance */ 1144 uint32_t gfxclk_lock_status; 1145 1146 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1147 uint16_t pcie_link_width; 1148 uint16_t pcie_link_speed; 1149 1150 /* XGMI bus width and bitrate (in Gbps) */ 1151 uint16_t xgmi_link_width; 1152 uint16_t xgmi_link_speed; 1153 1154 /* Utilization Accumulated (%) */ 1155 uint32_t gfx_activity_acc; 1156 uint32_t mem_activity_acc; 1157 1158 /*PCIE accumulated bandwidth (GB/sec) */ 1159 uint64_t pcie_bandwidth_acc; 1160 1161 /*PCIE instantaneous bandwidth (GB/sec) */ 1162 uint64_t pcie_bandwidth_inst; 1163 1164 /* PCIE L0 to recovery state transition accumulated count */ 1165 uint64_t pcie_l0_to_recov_count_acc; 1166 1167 /* PCIE replay accumulated count */ 1168 uint64_t pcie_replay_count_acc; 1169 1170 /* PCIE replay rollover accumulated count */ 1171 uint64_t pcie_replay_rover_count_acc; 1172 1173 /* PCIE NAK sent accumulated count */ 1174 uint32_t pcie_nak_sent_count_acc; 1175 1176 /* PCIE NAK received accumulated count */ 1177 uint32_t pcie_nak_rcvd_count_acc; 1178 1179 /* XGMI accumulated data transfer size(KiloBytes) */ 1180 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1181 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1182 1183 /* XGMI link status(active/inactive) */ 1184 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1185 1186 uint16_t padding; 1187 1188 /* PMFW attached timestamp (10ns resolution) */ 1189 uint64_t firmware_timestamp; 1190 1191 /* Current clocks (Mhz) */ 1192 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1193 uint16_t current_socclk[MAX_CLKS]; 1194 uint16_t current_vclk0[MAX_CLKS]; 1195 uint16_t current_dclk0[MAX_CLKS]; 1196 uint16_t current_uclk; 1197 1198 /* Number of current partition */ 1199 uint16_t num_partition; 1200 1201 /* XCP metrics stats */ 1202 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1203 1204 /* PCIE other end recovery counter */ 1205 uint32_t pcie_lc_perf_other_end_recovery; 1206 }; 1207 1208 /* 1209 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1210 * Use gpu_metrics_v2_1 or later instead. 1211 */ 1212 struct gpu_metrics_v2_0 { 1213 struct metrics_table_header common_header; 1214 1215 /* Driver attached timestamp (in ns) */ 1216 uint64_t system_clock_counter; 1217 1218 /* Temperature */ 1219 uint16_t temperature_gfx; // gfx temperature on APUs 1220 uint16_t temperature_soc; // soc temperature on APUs 1221 uint16_t temperature_core[8]; // CPU core temperature on APUs 1222 uint16_t temperature_l3[2]; 1223 1224 /* Utilization */ 1225 uint16_t average_gfx_activity; 1226 uint16_t average_mm_activity; // UVD or VCN 1227 1228 /* Power/Energy */ 1229 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1230 uint16_t average_cpu_power; 1231 uint16_t average_soc_power; 1232 uint16_t average_gfx_power; 1233 uint16_t average_core_power[8]; // CPU core power on APUs 1234 1235 /* Average clocks */ 1236 uint16_t average_gfxclk_frequency; 1237 uint16_t average_socclk_frequency; 1238 uint16_t average_uclk_frequency; 1239 uint16_t average_fclk_frequency; 1240 uint16_t average_vclk_frequency; 1241 uint16_t average_dclk_frequency; 1242 1243 /* Current clocks */ 1244 uint16_t current_gfxclk; 1245 uint16_t current_socclk; 1246 uint16_t current_uclk; 1247 uint16_t current_fclk; 1248 uint16_t current_vclk; 1249 uint16_t current_dclk; 1250 uint16_t current_coreclk[8]; // CPU core clocks 1251 uint16_t current_l3clk[2]; 1252 1253 /* Throttle status */ 1254 uint32_t throttle_status; 1255 1256 /* Fans */ 1257 uint16_t fan_pwm; 1258 1259 uint16_t padding; 1260 }; 1261 1262 struct gpu_metrics_v2_1 { 1263 struct metrics_table_header common_header; 1264 1265 /* Temperature */ 1266 uint16_t temperature_gfx; // gfx temperature on APUs 1267 uint16_t temperature_soc; // soc temperature on APUs 1268 uint16_t temperature_core[8]; // CPU core temperature on APUs 1269 uint16_t temperature_l3[2]; 1270 1271 /* Utilization */ 1272 uint16_t average_gfx_activity; 1273 uint16_t average_mm_activity; // UVD or VCN 1274 1275 /* Driver attached timestamp (in ns) */ 1276 uint64_t system_clock_counter; 1277 1278 /* Power/Energy */ 1279 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1280 uint16_t average_cpu_power; 1281 uint16_t average_soc_power; 1282 uint16_t average_gfx_power; 1283 uint16_t average_core_power[8]; // CPU core power on APUs 1284 1285 /* Average clocks */ 1286 uint16_t average_gfxclk_frequency; 1287 uint16_t average_socclk_frequency; 1288 uint16_t average_uclk_frequency; 1289 uint16_t average_fclk_frequency; 1290 uint16_t average_vclk_frequency; 1291 uint16_t average_dclk_frequency; 1292 1293 /* Current clocks */ 1294 uint16_t current_gfxclk; 1295 uint16_t current_socclk; 1296 uint16_t current_uclk; 1297 uint16_t current_fclk; 1298 uint16_t current_vclk; 1299 uint16_t current_dclk; 1300 uint16_t current_coreclk[8]; // CPU core clocks 1301 uint16_t current_l3clk[2]; 1302 1303 /* Throttle status */ 1304 uint32_t throttle_status; 1305 1306 /* Fans */ 1307 uint16_t fan_pwm; 1308 1309 uint16_t padding[3]; 1310 }; 1311 1312 struct gpu_metrics_v2_2 { 1313 struct metrics_table_header common_header; 1314 1315 /* Temperature */ 1316 uint16_t temperature_gfx; // gfx temperature on APUs 1317 uint16_t temperature_soc; // soc temperature on APUs 1318 uint16_t temperature_core[8]; // CPU core temperature on APUs 1319 uint16_t temperature_l3[2]; 1320 1321 /* Utilization */ 1322 uint16_t average_gfx_activity; 1323 uint16_t average_mm_activity; // UVD or VCN 1324 1325 /* Driver attached timestamp (in ns) */ 1326 uint64_t system_clock_counter; 1327 1328 /* Power/Energy */ 1329 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1330 uint16_t average_cpu_power; 1331 uint16_t average_soc_power; 1332 uint16_t average_gfx_power; 1333 uint16_t average_core_power[8]; // CPU core power on APUs 1334 1335 /* Average clocks */ 1336 uint16_t average_gfxclk_frequency; 1337 uint16_t average_socclk_frequency; 1338 uint16_t average_uclk_frequency; 1339 uint16_t average_fclk_frequency; 1340 uint16_t average_vclk_frequency; 1341 uint16_t average_dclk_frequency; 1342 1343 /* Current clocks */ 1344 uint16_t current_gfxclk; 1345 uint16_t current_socclk; 1346 uint16_t current_uclk; 1347 uint16_t current_fclk; 1348 uint16_t current_vclk; 1349 uint16_t current_dclk; 1350 uint16_t current_coreclk[8]; // CPU core clocks 1351 uint16_t current_l3clk[2]; 1352 1353 /* Throttle status (ASIC dependent) */ 1354 uint32_t throttle_status; 1355 1356 /* Fans */ 1357 uint16_t fan_pwm; 1358 1359 uint16_t padding[3]; 1360 1361 /* Throttle status (ASIC independent) */ 1362 uint64_t indep_throttle_status; 1363 }; 1364 1365 struct gpu_metrics_v2_3 { 1366 struct metrics_table_header common_header; 1367 1368 /* Temperature */ 1369 uint16_t temperature_gfx; // gfx temperature on APUs 1370 uint16_t temperature_soc; // soc temperature on APUs 1371 uint16_t temperature_core[8]; // CPU core temperature on APUs 1372 uint16_t temperature_l3[2]; 1373 1374 /* Utilization */ 1375 uint16_t average_gfx_activity; 1376 uint16_t average_mm_activity; // UVD or VCN 1377 1378 /* Driver attached timestamp (in ns) */ 1379 uint64_t system_clock_counter; 1380 1381 /* Power/Energy */ 1382 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1383 uint16_t average_cpu_power; 1384 uint16_t average_soc_power; 1385 uint16_t average_gfx_power; 1386 uint16_t average_core_power[8]; // CPU core power on APUs 1387 1388 /* Average clocks */ 1389 uint16_t average_gfxclk_frequency; 1390 uint16_t average_socclk_frequency; 1391 uint16_t average_uclk_frequency; 1392 uint16_t average_fclk_frequency; 1393 uint16_t average_vclk_frequency; 1394 uint16_t average_dclk_frequency; 1395 1396 /* Current clocks */ 1397 uint16_t current_gfxclk; 1398 uint16_t current_socclk; 1399 uint16_t current_uclk; 1400 uint16_t current_fclk; 1401 uint16_t current_vclk; 1402 uint16_t current_dclk; 1403 uint16_t current_coreclk[8]; // CPU core clocks 1404 uint16_t current_l3clk[2]; 1405 1406 /* Throttle status (ASIC dependent) */ 1407 uint32_t throttle_status; 1408 1409 /* Fans */ 1410 uint16_t fan_pwm; 1411 1412 uint16_t padding[3]; 1413 1414 /* Throttle status (ASIC independent) */ 1415 uint64_t indep_throttle_status; 1416 1417 /* Average Temperature */ 1418 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1419 uint16_t average_temperature_soc; // average soc temperature on APUs 1420 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1421 uint16_t average_temperature_l3[2]; 1422 }; 1423 1424 struct gpu_metrics_v2_4 { 1425 struct metrics_table_header common_header; 1426 1427 /* Temperature (unit: centi-Celsius) */ 1428 uint16_t temperature_gfx; 1429 uint16_t temperature_soc; 1430 uint16_t temperature_core[8]; 1431 uint16_t temperature_l3[2]; 1432 1433 /* Utilization (unit: centi) */ 1434 uint16_t average_gfx_activity; 1435 uint16_t average_mm_activity; 1436 1437 /* Driver attached timestamp (in ns) */ 1438 uint64_t system_clock_counter; 1439 1440 /* Power/Energy (unit: mW) */ 1441 uint16_t average_socket_power; 1442 uint16_t average_cpu_power; 1443 uint16_t average_soc_power; 1444 uint16_t average_gfx_power; 1445 uint16_t average_core_power[8]; 1446 1447 /* Average clocks (unit: MHz) */ 1448 uint16_t average_gfxclk_frequency; 1449 uint16_t average_socclk_frequency; 1450 uint16_t average_uclk_frequency; 1451 uint16_t average_fclk_frequency; 1452 uint16_t average_vclk_frequency; 1453 uint16_t average_dclk_frequency; 1454 1455 /* Current clocks (unit: MHz) */ 1456 uint16_t current_gfxclk; 1457 uint16_t current_socclk; 1458 uint16_t current_uclk; 1459 uint16_t current_fclk; 1460 uint16_t current_vclk; 1461 uint16_t current_dclk; 1462 uint16_t current_coreclk[8]; 1463 uint16_t current_l3clk[2]; 1464 1465 /* Throttle status (ASIC dependent) */ 1466 uint32_t throttle_status; 1467 1468 /* Fans */ 1469 uint16_t fan_pwm; 1470 1471 uint16_t padding[3]; 1472 1473 /* Throttle status (ASIC independent) */ 1474 uint64_t indep_throttle_status; 1475 1476 /* Average Temperature (unit: centi-Celsius) */ 1477 uint16_t average_temperature_gfx; 1478 uint16_t average_temperature_soc; 1479 uint16_t average_temperature_core[8]; 1480 uint16_t average_temperature_l3[2]; 1481 1482 /* Power/Voltage (unit: mV) */ 1483 uint16_t average_cpu_voltage; 1484 uint16_t average_soc_voltage; 1485 uint16_t average_gfx_voltage; 1486 1487 /* Power/Current (unit: mA) */ 1488 uint16_t average_cpu_current; 1489 uint16_t average_soc_current; 1490 uint16_t average_gfx_current; 1491 }; 1492 1493 struct gpu_metrics_v3_0 { 1494 struct metrics_table_header common_header; 1495 1496 /* Temperature */ 1497 /* gfx temperature on APUs */ 1498 uint16_t temperature_gfx; 1499 /* soc temperature on APUs */ 1500 uint16_t temperature_soc; 1501 /* CPU core temperature on APUs */ 1502 uint16_t temperature_core[16]; 1503 /* skin temperature on APUs */ 1504 uint16_t temperature_skin; 1505 1506 /* Utilization */ 1507 /* time filtered GFX busy % [0-100] */ 1508 uint16_t average_gfx_activity; 1509 /* time filtered VCN busy % [0-100] */ 1510 uint16_t average_vcn_activity; 1511 /* time filtered IPU per-column busy % [0-100] */ 1512 uint16_t average_ipu_activity[8]; 1513 /* time filtered per-core C0 residency % [0-100]*/ 1514 uint16_t average_core_c0_activity[16]; 1515 /* time filtered DRAM read bandwidth [MB/sec] */ 1516 uint16_t average_dram_reads; 1517 /* time filtered DRAM write bandwidth [MB/sec] */ 1518 uint16_t average_dram_writes; 1519 /* time filtered IPU read bandwidth [MB/sec] */ 1520 uint16_t average_ipu_reads; 1521 /* time filtered IPU write bandwidth [MB/sec] */ 1522 uint16_t average_ipu_writes; 1523 1524 /* Driver attached timestamp (in ns) */ 1525 uint64_t system_clock_counter; 1526 1527 /* Power/Energy */ 1528 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1529 uint32_t average_socket_power; 1530 /* time filtered IPU power [mW] */ 1531 uint16_t average_ipu_power; 1532 /* time filtered APU power [mW] */ 1533 uint32_t average_apu_power; 1534 /* time filtered GFX power [mW] */ 1535 uint32_t average_gfx_power; 1536 /* time filtered dGPU power [mW] */ 1537 uint32_t average_dgpu_power; 1538 /* time filtered sum of core power across all cores in the socket [mW] */ 1539 uint32_t average_all_core_power; 1540 /* calculated core power [mW] */ 1541 uint16_t average_core_power[16]; 1542 /* time filtered total system power [mW] */ 1543 uint16_t average_sys_power; 1544 /* maximum IRM defined STAPM power limit [mW] */ 1545 uint16_t stapm_power_limit; 1546 /* time filtered STAPM power limit [mW] */ 1547 uint16_t current_stapm_power_limit; 1548 1549 /* time filtered clocks [MHz] */ 1550 uint16_t average_gfxclk_frequency; 1551 uint16_t average_socclk_frequency; 1552 uint16_t average_vpeclk_frequency; 1553 uint16_t average_ipuclk_frequency; 1554 uint16_t average_fclk_frequency; 1555 uint16_t average_vclk_frequency; 1556 uint16_t average_uclk_frequency; 1557 uint16_t average_mpipu_frequency; 1558 1559 /* Current clocks */ 1560 /* target core frequency [MHz] */ 1561 uint16_t current_coreclk[16]; 1562 /* CCLK frequency limit enforced on classic cores [MHz] */ 1563 uint16_t current_core_maxfreq; 1564 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1565 uint16_t current_gfx_maxfreq; 1566 1567 /* Throttle Residency (ASIC dependent) */ 1568 uint32_t throttle_residency_prochot; 1569 uint32_t throttle_residency_spl; 1570 uint32_t throttle_residency_fppt; 1571 uint32_t throttle_residency_sppt; 1572 uint32_t throttle_residency_thm_core; 1573 uint32_t throttle_residency_thm_gfx; 1574 uint32_t throttle_residency_thm_soc; 1575 1576 /* Metrics table alpha filter time constant [us] */ 1577 uint32_t time_filter_alphavalue; 1578 }; 1579 1580 struct amdgpu_pmmetrics_header { 1581 uint16_t structure_size; 1582 uint16_t pad; 1583 uint32_t mp1_ip_discovery_version; 1584 uint32_t pmfw_version; 1585 uint32_t pmmetrics_version; 1586 }; 1587 1588 struct amdgpu_pm_metrics { 1589 struct amdgpu_pmmetrics_header common_header; 1590 1591 uint8_t data[]; 1592 }; 1593 1594 #endif 1595