1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 /* FILE POLICY AND INTENDED USAGE:
27  * This file implements dp specific link capability retrieval sequence. It is
28  * responsible for retrieving, parsing, overriding, deciding capability obtained
29  * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
30  * usb and all other possible backend capabilities. Other components should
31  * include this header file in order to access link capability. Accessing link
32  * capability by dereferencing dc_link outside dp_link_capability is not a
33  * recommended method as it makes the component dependent on the underlying data
34  * structure used to represent link capability instead of function interfaces.
35  */
36 
37 #include "link_dp_capability.h"
38 #include "link_ddc.h"
39 #include "link_dpcd.h"
40 #include "link_dp_dpia.h"
41 #include "link_dp_phy.h"
42 #include "link_edp_panel_control.h"
43 #include "link_dp_irq_handler.h"
44 #include "link/accessories/link_dp_trace.h"
45 #include "link/link_detection.h"
46 #include "link/link_validation.h"
47 #include "link_dp_training.h"
48 #include "atomfirmware.h"
49 #include "resource.h"
50 #include "link_enc_cfg.h"
51 #include "dc_dmub_srv.h"
52 #include "gpio_service_interface.h"
53 
54 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
55 
56 #define DC_LOGGER \
57 	link->ctx->logger
58 
59 #ifndef MAX
60 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
61 #endif
62 #ifndef MIN
63 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
64 #endif
65 
66 struct dp_lt_fallback_entry {
67 	enum dc_lane_count lane_count;
68 	enum dc_link_rate link_rate;
69 };
70 
71 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
72 		/* This link training fallback array is ordered by
73 		 * link bandwidth from highest to lowest.
74 		 * DP specs makes it a normative policy to always
75 		 * choose the next highest link bandwidth during
76 		 * link training fallback.
77 		 */
78 		{LANE_COUNT_FOUR, LINK_RATE_UHBR20},
79 		{LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
80 		{LANE_COUNT_TWO, LINK_RATE_UHBR20},
81 		{LANE_COUNT_FOUR, LINK_RATE_UHBR10},
82 		{LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
83 		{LANE_COUNT_FOUR, LINK_RATE_HIGH3},
84 		{LANE_COUNT_ONE, LINK_RATE_UHBR20},
85 		{LANE_COUNT_TWO, LINK_RATE_UHBR10},
86 		{LANE_COUNT_FOUR, LINK_RATE_HIGH2},
87 		{LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
88 		{LANE_COUNT_TWO, LINK_RATE_HIGH3},
89 		{LANE_COUNT_ONE, LINK_RATE_UHBR10},
90 		{LANE_COUNT_TWO, LINK_RATE_HIGH2},
91 		{LANE_COUNT_FOUR, LINK_RATE_HIGH},
92 		{LANE_COUNT_ONE, LINK_RATE_HIGH3},
93 		{LANE_COUNT_FOUR, LINK_RATE_LOW},
94 		{LANE_COUNT_ONE, LINK_RATE_HIGH2},
95 		{LANE_COUNT_TWO, LINK_RATE_HIGH},
96 		{LANE_COUNT_TWO, LINK_RATE_LOW},
97 		{LANE_COUNT_ONE, LINK_RATE_HIGH},
98 		{LANE_COUNT_ONE, LINK_RATE_LOW},
99 };
100 
101 static const struct dc_link_settings fail_safe_link_settings = {
102 		.lane_count = LANE_COUNT_ONE,
103 		.link_rate = LINK_RATE_LOW,
104 		.link_spread = LINK_SPREAD_DISABLED,
105 };
106 
is_dp_active_dongle(const struct dc_link * link)107 bool is_dp_active_dongle(const struct dc_link *link)
108 {
109 	return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
110 				(link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
111 }
112 
is_dp_branch_device(const struct dc_link * link)113 bool is_dp_branch_device(const struct dc_link *link)
114 {
115 	return link->dpcd_caps.is_branch_dev;
116 }
117 
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)118 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
119 {
120 	switch (bpc) {
121 	case DOWN_STREAM_MAX_8BPC:
122 		return 8;
123 	case DOWN_STREAM_MAX_10BPC:
124 		return 10;
125 	case DOWN_STREAM_MAX_12BPC:
126 		return 12;
127 	case DOWN_STREAM_MAX_16BPC:
128 		return 16;
129 	default:
130 		break;
131 	}
132 
133 	return -1;
134 }
135 
dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)136 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
137 {
138 	switch (lttpr_repeater_count) {
139 	case 0x80: // 1 lttpr repeater
140 		return 1;
141 	case 0x40: // 2 lttpr repeaters
142 		return 2;
143 	case 0x20: // 3 lttpr repeaters
144 		return 3;
145 	case 0x10: // 4 lttpr repeaters
146 		return 4;
147 	case 0x08: // 5 lttpr repeaters
148 		return 5;
149 	case 0x04: // 6 lttpr repeaters
150 		return 6;
151 	case 0x02: // 7 lttpr repeaters
152 		return 7;
153 	case 0x01: // 8 lttpr repeaters
154 		return 8;
155 	default:
156 		break;
157 	}
158 	return 0; // invalid value
159 }
160 
link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)161 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
162 {
163 	switch (bw) {
164 	case 0b001:
165 		return 9000000;
166 	case 0b010:
167 		return 18000000;
168 	case 0b011:
169 		return 24000000;
170 	case 0b100:
171 		return 32000000;
172 	case 0b101:
173 		return 40000000;
174 	case 0b110:
175 		return 48000000;
176 	}
177 
178 	return 0;
179 }
180 
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)181 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
182 {
183 	enum dc_link_rate link_rate;
184 	// LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
185 	switch (link_rate_in_khz) {
186 	case 1620000:
187 		link_rate = LINK_RATE_LOW;	// Rate_1 (RBR)	- 1.62 Gbps/Lane
188 		break;
189 	case 2160000:
190 		link_rate = LINK_RATE_RATE_2;	// Rate_2	- 2.16 Gbps/Lane
191 		break;
192 	case 2430000:
193 		link_rate = LINK_RATE_RATE_3;	// Rate_3	- 2.43 Gbps/Lane
194 		break;
195 	case 2700000:
196 		link_rate = LINK_RATE_HIGH;	// Rate_4 (HBR)	- 2.70 Gbps/Lane
197 		break;
198 	case 3240000:
199 		link_rate = LINK_RATE_RBR2;	// Rate_5 (RBR2)- 3.24 Gbps/Lane
200 		break;
201 	case 4320000:
202 		link_rate = LINK_RATE_RATE_6;	// Rate_6	- 4.32 Gbps/Lane
203 		break;
204 	case 5400000:
205 		link_rate = LINK_RATE_HIGH2;	// Rate_7 (HBR2)- 5.40 Gbps/Lane
206 		break;
207 	case 6750000:
208 		link_rate = LINK_RATE_RATE_8;	// Rate_8	- 6.75 Gbps/Lane
209 		break;
210 	case 8100000:
211 		link_rate = LINK_RATE_HIGH3;	// Rate_9 (HBR3)- 8.10 Gbps/Lane
212 		break;
213 	case 10000000:
214 		link_rate = LINK_RATE_UHBR10;	// UHBR10 - 10.0 Gbps/Lane
215 		break;
216 	case 13500000:
217 		link_rate = LINK_RATE_UHBR13_5;	// UHBR13.5 - 13.5 Gbps/Lane
218 		break;
219 	case 20000000:
220 		link_rate = LINK_RATE_UHBR20;	// UHBR20 - 20.0 Gbps/Lane
221 		break;
222 
223 	default:
224 		link_rate = LINK_RATE_UNKNOWN;
225 		break;
226 	}
227 	return link_rate;
228 }
229 
intersect_cable_id(union dp_cable_id * a,union dp_cable_id * b)230 static union dp_cable_id intersect_cable_id(
231 		union dp_cable_id *a, union dp_cable_id *b)
232 {
233 	union dp_cable_id out;
234 
235 	out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
236 			b->bits.UHBR10_20_CAPABILITY);
237 	out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
238 			b->bits.UHBR13_5_CAPABILITY);
239 	out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
240 
241 	return out;
242 }
243 
244 /*
245  * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
246  */
intersect_frl_link_bw_support(const uint32_t max_supported_frl_bw_in_kbps,const union hdmi_encoded_link_bw hdmi_encoded_link_bw)247 static uint32_t intersect_frl_link_bw_support(
248 	const uint32_t max_supported_frl_bw_in_kbps,
249 	const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
250 {
251 	uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
252 
253 	/* Skip checking FRL_MODE bit, as certain PCON will clear
254 	 * it despite supporting the link BW indicated in the other bits.
255 	 */
256 	if (hdmi_encoded_link_bw.bits.BW_48Gbps)
257 		supported_bw_in_kbps = 48000000;
258 	else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
259 		supported_bw_in_kbps = 40000000;
260 	else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
261 		supported_bw_in_kbps = 32000000;
262 	else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
263 		supported_bw_in_kbps = 24000000;
264 	else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
265 		supported_bw_in_kbps = 18000000;
266 	else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
267 		supported_bw_in_kbps = 9000000;
268 	else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)
269 		supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */
270 
271 	return supported_bw_in_kbps;
272 }
273 
get_clock_source_id(struct dc_link * link)274 static enum clock_source_id get_clock_source_id(struct dc_link *link)
275 {
276 	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
277 	struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
278 
279 	if (dp_cs != NULL) {
280 		dp_cs_id = dp_cs->id;
281 	} else {
282 		/*
283 		 * dp clock source is not initialized for some reason.
284 		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
285 		 */
286 		ASSERT(dp_cs);
287 	}
288 
289 	return dp_cs_id;
290 }
291 
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)292 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
293 		int length)
294 {
295 	int retry = 0;
296 
297 	if (!link->dpcd_caps.dpcd_rev.raw) {
298 		do {
299 			dpcd_write_rx_power_ctrl(link, true);
300 			core_link_read_dpcd(link, DP_DPCD_REV,
301 							dpcd_data, length);
302 			link->dpcd_caps.dpcd_rev.raw = dpcd_data[
303 				DP_DPCD_REV -
304 				DP_DPCD_REV];
305 		} while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
306 	}
307 
308 	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
309 		switch (link->dpcd_caps.branch_dev_id) {
310 		/* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
311 		 * all internal circuits including AUX communication preventing
312 		 * reading DPCD table and EDID (spec violation).
313 		 * Encoder will skip DP RX power down on disable_output to
314 		 * keep receiver powered all the time.*/
315 		case DP_BRANCH_DEVICE_ID_0010FA:
316 		case DP_BRANCH_DEVICE_ID_0080E1:
317 		case DP_BRANCH_DEVICE_ID_00E04C:
318 			link->wa_flags.dp_keep_receiver_powered = true;
319 			break;
320 
321 		/* TODO: May need work around for other dongles. */
322 		default:
323 			link->wa_flags.dp_keep_receiver_powered = false;
324 			break;
325 		}
326 	} else
327 		link->wa_flags.dp_keep_receiver_powered = false;
328 }
329 
dp_is_fec_supported(const struct dc_link * link)330 bool dp_is_fec_supported(const struct dc_link *link)
331 {
332 	/* TODO - use asic cap instead of link_enc->features
333 	 * we no longer know which link enc to use for this link before commit
334 	 */
335 	struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
336 	struct resource_pool *res_pool = link->dc->res_pool;
337 	struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
338 
339 	if (!link->dc->config.unify_link_enc_assignment)
340 		link_enc = link_enc_cfg_get_link_enc(link);
341 	ASSERT(link_enc);
342 
343 	return (dc_is_dp_signal(link->connector_signal) && link_enc &&
344 			link_enc->features.fec_supported &&
345 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
346 }
347 
dp_should_enable_fec(const struct dc_link * link)348 bool dp_should_enable_fec(const struct dc_link *link)
349 {
350 	bool force_disable = false;
351 
352 	if (link->fec_state == dc_link_fec_enabled)
353 		force_disable = false;
354 	else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
355 			link->local_sink &&
356 			link->local_sink->edid_caps.panel_patch.disable_fec)
357 		force_disable = true;
358 	else if (link->connector_signal == SIGNAL_TYPE_EDP
359 			&& (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
360 			 dsc_support.DSC_SUPPORT == false
361 				|| link->panel_config.dsc.disable_dsc_edp
362 				|| !link->dc->caps.edp_dsc_support))
363 		force_disable = true;
364 
365 	return !force_disable && dp_is_fec_supported(link);
366 }
367 
dp_is_128b_132b_signal(struct pipe_ctx * pipe_ctx)368 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
369 {
370 	/* If this assert is hit then we have a link encoder dynamic management issue */
371 	ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
372 	return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
373 			pipe_ctx->link_res.hpo_dp_link_enc &&
374 			dc_is_dp_signal(pipe_ctx->stream->signal));
375 }
376 
dp_is_lttpr_present(struct dc_link * link)377 bool dp_is_lttpr_present(struct dc_link *link)
378 {
379 	/* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
380 	return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
381 			link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
382 			link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
383 }
384 
385 /* in DP compliance test, DPR-120 may have
386  * a random value in its MAX_LINK_BW dpcd field.
387  * We map it to the maximum supported link rate that
388  * is smaller than MAX_LINK_BW in this case.
389  */
get_link_rate_from_max_link_bw(uint8_t max_link_bw)390 static enum dc_link_rate get_link_rate_from_max_link_bw(
391 		 uint8_t max_link_bw)
392 {
393 	enum dc_link_rate link_rate;
394 
395 	if (max_link_bw >= LINK_RATE_HIGH3) {
396 		link_rate = LINK_RATE_HIGH3;
397 	} else if (max_link_bw < LINK_RATE_HIGH3
398 			&& max_link_bw >= LINK_RATE_HIGH2) {
399 		link_rate = LINK_RATE_HIGH2;
400 	} else if (max_link_bw < LINK_RATE_HIGH2
401 			&& max_link_bw >= LINK_RATE_HIGH) {
402 		link_rate = LINK_RATE_HIGH;
403 	} else if (max_link_bw < LINK_RATE_HIGH
404 			&& max_link_bw >= LINK_RATE_LOW) {
405 		link_rate = LINK_RATE_LOW;
406 	} else {
407 		link_rate = LINK_RATE_UNKNOWN;
408 	}
409 
410 	return link_rate;
411 }
412 
get_lttpr_max_link_rate(struct dc_link * link)413 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
414 {
415 
416 	enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN;
417 
418 	switch (link->dpcd_caps.lttpr_caps.max_link_rate) {
419 	case LINK_RATE_LOW:
420 	case LINK_RATE_HIGH:
421 	case LINK_RATE_HIGH2:
422 	case LINK_RATE_HIGH3:
423 		lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
424 		break;
425 	}
426 
427 	if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
428 		lttpr_max_link_rate = LINK_RATE_UHBR20;
429 	else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
430 		lttpr_max_link_rate = LINK_RATE_UHBR13_5;
431 	else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
432 		lttpr_max_link_rate = LINK_RATE_UHBR10;
433 
434 	return lttpr_max_link_rate;
435 }
436 
get_cable_max_link_rate(struct dc_link * link)437 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
438 {
439 	enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
440 
441 	if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) {
442 		cable_max_link_rate = LINK_RATE_UHBR20;
443 	} else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) {
444 		cable_max_link_rate = LINK_RATE_UHBR13_5;
445 	} else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) {
446 		// allow DP40 cables to do UHBR13.5 for passive or unknown cable type
447 		if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) {
448 			cable_max_link_rate = LINK_RATE_UHBR13_5;
449 		} else {
450 			cable_max_link_rate = LINK_RATE_UHBR10;
451 		}
452 	}
453 
454 	return cable_max_link_rate;
455 }
456 
reached_minimum_lane_count(enum dc_lane_count lane_count)457 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
458 {
459 	return lane_count <= LANE_COUNT_ONE;
460 }
461 
reached_minimum_link_rate(enum dc_link_rate link_rate)462 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
463 {
464 	return link_rate <= LINK_RATE_LOW;
465 }
466 
reduce_lane_count(enum dc_lane_count lane_count)467 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
468 {
469 	switch (lane_count) {
470 	case LANE_COUNT_FOUR:
471 		return LANE_COUNT_TWO;
472 	case LANE_COUNT_TWO:
473 		return LANE_COUNT_ONE;
474 	case LANE_COUNT_ONE:
475 		return LANE_COUNT_UNKNOWN;
476 	default:
477 		return LANE_COUNT_UNKNOWN;
478 	}
479 }
480 
reduce_link_rate(const struct dc_link * link,enum dc_link_rate link_rate)481 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
482 {
483 	// NEEDSWORK: provide some details about why this function never returns some of the
484 	// obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended.
485 	//
486 
487 	switch (link_rate) {
488 	case LINK_RATE_UHBR20:
489 		return LINK_RATE_UHBR13_5;
490 	case LINK_RATE_UHBR13_5:
491 		return LINK_RATE_UHBR10;
492 	case LINK_RATE_UHBR10:
493 		return LINK_RATE_HIGH3;
494 	case LINK_RATE_HIGH3:
495 		if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)
496 			return LINK_RATE_RATE_8;
497 		return LINK_RATE_HIGH2;
498 	case LINK_RATE_RATE_8:
499 		return LINK_RATE_HIGH2;
500 	case LINK_RATE_HIGH2:
501 		return LINK_RATE_HIGH;
502 	case LINK_RATE_RATE_6:
503 	case LINK_RATE_RBR2:
504 		return LINK_RATE_HIGH;
505 	case LINK_RATE_HIGH:
506 		return LINK_RATE_LOW;
507 	case LINK_RATE_RATE_3:
508 	case LINK_RATE_RATE_2:
509 		return LINK_RATE_LOW;
510 	case LINK_RATE_LOW:
511 	default:
512 		return LINK_RATE_UNKNOWN;
513 	}
514 }
515 
increase_lane_count(enum dc_lane_count lane_count)516 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
517 {
518 	switch (lane_count) {
519 	case LANE_COUNT_ONE:
520 		return LANE_COUNT_TWO;
521 	case LANE_COUNT_TWO:
522 		return LANE_COUNT_FOUR;
523 	default:
524 		return LANE_COUNT_UNKNOWN;
525 	}
526 }
527 
increase_link_rate(struct dc_link * link,enum dc_link_rate link_rate)528 static enum dc_link_rate increase_link_rate(struct dc_link *link,
529 		enum dc_link_rate link_rate)
530 {
531 	switch (link_rate) {
532 	case LINK_RATE_LOW:
533 		return LINK_RATE_HIGH;
534 	case LINK_RATE_HIGH:
535 		return LINK_RATE_HIGH2;
536 	case LINK_RATE_HIGH2:
537 		return LINK_RATE_HIGH3;
538 	case LINK_RATE_HIGH3:
539 		return LINK_RATE_UHBR10;
540 	case LINK_RATE_UHBR10:
541 		/* upto DP2.x specs UHBR13.5 is the only link rate that could be
542 		 * not supported by DPRX when higher link rate is supported.
543 		 * so we treat it as a special case for code simplicity. When we
544 		 * have new specs with more link rates like this, we should
545 		 * consider a more generic solution to handle discrete link
546 		 * rate capabilities.
547 		 */
548 		return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
549 				LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
550 	case LINK_RATE_UHBR13_5:
551 		return LINK_RATE_UHBR20;
552 	default:
553 		return LINK_RATE_UNKNOWN;
554 	}
555 }
556 
increase_edp_link_rate(struct dc_link * link,struct dc_link_settings * current_link_setting)557 static void increase_edp_link_rate(struct dc_link *link,
558 		struct dc_link_settings *current_link_setting)
559 {
560 	if (current_link_setting->use_link_rate_set) {
561 		if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
562 			current_link_setting->link_rate_set++;
563 			current_link_setting->link_rate =
564 				link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set];
565 		} else {
566 			current_link_setting->use_link_rate_set = false;
567 			current_link_setting->link_rate = LINK_RATE_UHBR10;
568 		}
569 	} else {
570 		current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate);
571 	}
572 }
573 
decide_fallback_link_setting_max_bw_policy(struct dc_link * link,const struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)574 static bool decide_fallback_link_setting_max_bw_policy(
575 		struct dc_link *link,
576 		const struct dc_link_settings *max,
577 		struct dc_link_settings *cur,
578 		enum link_training_result training_result)
579 {
580 	uint32_t cur_idx = 0, next_idx;
581 	bool found = false;
582 
583 	if (training_result == LINK_TRAINING_ABORT)
584 		return false;
585 
586 	while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
587 		/* find current index */
588 		if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
589 				dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
590 			break;
591 		else
592 			cur_idx++;
593 
594 	next_idx = cur_idx + 1;
595 
596 	while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
597 		/* find next index */
598 		if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
599 				dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
600 			next_idx++;
601 		else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
602 				link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
603 			/* upto DP2.x specs UHBR13.5 is the only link rate that
604 			 * could be not supported by DPRX when higher link rate
605 			 * is supported. so we treat it as a special case for
606 			 * code simplicity. When we have new specs with more
607 			 * link rates like this, we should consider a more
608 			 * generic solution to handle discrete link rate
609 			 * capabilities.
610 			 */
611 			next_idx++;
612 		else
613 			break;
614 
615 	if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
616 		cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
617 		cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
618 		found = true;
619 	}
620 
621 	return found;
622 }
623 
624 /*
625  * function: set link rate and lane count fallback based
626  * on current link setting and last link training result
627  * return value:
628  *			true - link setting could be set
629  *			false - has reached minimum setting
630  *					and no further fallback could be done
631  */
decide_fallback_link_setting(struct dc_link * link,struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)632 bool decide_fallback_link_setting(
633 		struct dc_link *link,
634 		struct dc_link_settings *max,
635 		struct dc_link_settings *cur,
636 		enum link_training_result training_result)
637 {
638 	if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
639 			link->dc->debug.force_dp2_lt_fallback_method)
640 		return decide_fallback_link_setting_max_bw_policy(link, max,
641 				cur, training_result);
642 
643 	switch (training_result) {
644 	case LINK_TRAINING_CR_FAIL_LANE0:
645 	case LINK_TRAINING_CR_FAIL_LANE1:
646 	case LINK_TRAINING_CR_FAIL_LANE23:
647 	case LINK_TRAINING_LQA_FAIL:
648 	{
649 		if (!reached_minimum_link_rate(cur->link_rate)) {
650 			cur->link_rate = reduce_link_rate(link, cur->link_rate);
651 		} else if (!reached_minimum_lane_count(cur->lane_count)) {
652 			cur->link_rate = max->link_rate;
653 			if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
654 				return false;
655 			else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
656 				cur->lane_count = LANE_COUNT_ONE;
657 			else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
658 				cur->lane_count = LANE_COUNT_TWO;
659 			else
660 				cur->lane_count = reduce_lane_count(cur->lane_count);
661 		} else {
662 			return false;
663 		}
664 		break;
665 	}
666 	case LINK_TRAINING_EQ_FAIL_EQ:
667 	case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
668 	{
669 		if (!reached_minimum_lane_count(cur->lane_count)) {
670 			cur->lane_count = reduce_lane_count(cur->lane_count);
671 		} else if (!reached_minimum_link_rate(cur->link_rate)) {
672 			cur->link_rate = reduce_link_rate(link, cur->link_rate);
673 			/* Reduce max link rate to avoid potential infinite loop.
674 			 * Needed so that any subsequent CR_FAIL fallback can't
675 			 * re-set the link rate higher than the link rate from
676 			 * the latest EQ_FAIL fallback.
677 			 */
678 			max->link_rate = cur->link_rate;
679 			cur->lane_count = max->lane_count;
680 		} else {
681 			return false;
682 		}
683 		break;
684 	}
685 	case LINK_TRAINING_EQ_FAIL_CR:
686 	{
687 		if (!reached_minimum_link_rate(cur->link_rate)) {
688 			cur->link_rate = reduce_link_rate(link, cur->link_rate);
689 			/* Reduce max link rate to avoid potential infinite loop.
690 			 * Needed so that any subsequent CR_FAIL fallback can't
691 			 * re-set the link rate higher than the link rate from
692 			 * the latest EQ_FAIL fallback.
693 			 */
694 			max->link_rate = cur->link_rate;
695 			cur->lane_count = max->lane_count;
696 		} else {
697 			return false;
698 		}
699 		break;
700 	}
701 	default:
702 		return false;
703 	}
704 	return true;
705 }
decide_dp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)706 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
707 {
708 	struct dc_link_settings initial_link_setting = {
709 		LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
710 	struct dc_link_settings current_link_setting =
711 			initial_link_setting;
712 	uint32_t link_bw;
713 
714 	if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
715 		return false;
716 
717 	/* search for the minimum link setting that:
718 	 * 1. is supported according to the link training result
719 	 * 2. could support the b/w requested by the timing
720 	 */
721 	while (current_link_setting.link_rate <=
722 			link->verified_link_cap.link_rate) {
723 		link_bw = dp_link_bandwidth_kbps(
724 				link,
725 				&current_link_setting);
726 		if (req_bw <= link_bw) {
727 			*link_setting = current_link_setting;
728 			return true;
729 		}
730 
731 		if (current_link_setting.lane_count <
732 				link->verified_link_cap.lane_count) {
733 			current_link_setting.lane_count =
734 					increase_lane_count(
735 							current_link_setting.lane_count);
736 		} else {
737 			current_link_setting.link_rate =
738 					increase_link_rate(link,
739 							current_link_setting.link_rate);
740 			current_link_setting.lane_count =
741 					initial_link_setting.lane_count;
742 		}
743 	}
744 
745 	return false;
746 }
747 
edp_decide_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)748 bool edp_decide_link_settings(struct dc_link *link,
749 		struct dc_link_settings *link_setting, uint32_t req_bw)
750 {
751 	struct dc_link_settings initial_link_setting;
752 	struct dc_link_settings current_link_setting;
753 	uint32_t link_bw;
754 
755 	/*
756 	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
757 	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
758 	 */
759 	if (!edp_is_ilr_optimization_enabled(link)) {
760 		*link_setting = link->verified_link_cap;
761 		return true;
762 	}
763 
764 	memset(&initial_link_setting, 0, sizeof(initial_link_setting));
765 	initial_link_setting.lane_count = LANE_COUNT_ONE;
766 	initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
767 	initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
768 	initial_link_setting.use_link_rate_set = true;
769 	initial_link_setting.link_rate_set = 0;
770 	current_link_setting = initial_link_setting;
771 
772 	/* search for the minimum link setting that:
773 	 * 1. is supported according to the link training result
774 	 * 2. could support the b/w requested by the timing
775 	 */
776 	while (current_link_setting.link_rate <=
777 			link->verified_link_cap.link_rate) {
778 		link_bw = dp_link_bandwidth_kbps(
779 				link,
780 				&current_link_setting);
781 		if (req_bw <= link_bw) {
782 			*link_setting = current_link_setting;
783 			return true;
784 		}
785 
786 		if (current_link_setting.lane_count <
787 				link->verified_link_cap.lane_count) {
788 			current_link_setting.lane_count =
789 					increase_lane_count(
790 							current_link_setting.lane_count);
791 		} else {
792 			increase_edp_link_rate(link, &current_link_setting);
793 		}
794 	}
795 	return false;
796 }
797 
decide_edp_link_settings_with_dsc(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw,enum dc_link_rate max_link_rate)798 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
799 		struct dc_link_settings *link_setting,
800 		uint32_t req_bw,
801 		enum dc_link_rate max_link_rate)
802 {
803 	struct dc_link_settings initial_link_setting;
804 	struct dc_link_settings current_link_setting;
805 	uint32_t link_bw;
806 
807 	unsigned int policy = 0;
808 
809 	policy = link->panel_config.dsc.force_dsc_edp_policy;
810 	if (max_link_rate == LINK_RATE_UNKNOWN)
811 		max_link_rate = link->verified_link_cap.link_rate;
812 	/*
813 	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
814 	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
815 	 */
816 	if (!edp_is_ilr_optimization_enabled(link)) {
817 		/* for DSC enabled case, we search for minimum lane count */
818 		memset(&initial_link_setting, 0, sizeof(initial_link_setting));
819 		initial_link_setting.lane_count = LANE_COUNT_ONE;
820 		initial_link_setting.link_rate = LINK_RATE_LOW;
821 		initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
822 		initial_link_setting.use_link_rate_set = false;
823 		initial_link_setting.link_rate_set = 0;
824 		current_link_setting = initial_link_setting;
825 		if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
826 			return false;
827 
828 		/* search for the minimum link setting that:
829 		 * 1. is supported according to the link training result
830 		 * 2. could support the b/w requested by the timing
831 		 */
832 		while (current_link_setting.link_rate <=
833 				max_link_rate) {
834 			link_bw = dp_link_bandwidth_kbps(
835 					link,
836 					&current_link_setting);
837 			if (req_bw <= link_bw) {
838 				*link_setting = current_link_setting;
839 				return true;
840 			}
841 			if (policy) {
842 				/* minimize lane */
843 				if (current_link_setting.link_rate < max_link_rate) {
844 					increase_edp_link_rate(link, &current_link_setting);
845 				} else {
846 					if (current_link_setting.lane_count <
847 									link->verified_link_cap.lane_count) {
848 						current_link_setting.lane_count =
849 								increase_lane_count(
850 										current_link_setting.lane_count);
851 						current_link_setting.link_rate = initial_link_setting.link_rate;
852 					} else
853 						break;
854 				}
855 			} else {
856 				/* minimize link rate */
857 				if (current_link_setting.lane_count <
858 						link->verified_link_cap.lane_count) {
859 					current_link_setting.lane_count =
860 							increase_lane_count(
861 									current_link_setting.lane_count);
862 				} else {
863 					increase_edp_link_rate(link, &current_link_setting);
864 					current_link_setting.lane_count =
865 							initial_link_setting.lane_count;
866 				}
867 			}
868 		}
869 		return false;
870 	}
871 
872 	/* if optimize edp link is supported */
873 	memset(&initial_link_setting, 0, sizeof(initial_link_setting));
874 	initial_link_setting.lane_count = LANE_COUNT_ONE;
875 	initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
876 	initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
877 	initial_link_setting.use_link_rate_set = true;
878 	initial_link_setting.link_rate_set = 0;
879 	current_link_setting = initial_link_setting;
880 
881 	/* search for the minimum link setting that:
882 	 * 1. is supported according to the link training result
883 	 * 2. could support the b/w requested by the timing
884 	 */
885 	while (current_link_setting.link_rate <=
886 			max_link_rate) {
887 		link_bw = dp_link_bandwidth_kbps(
888 				link,
889 				&current_link_setting);
890 		if (req_bw <= link_bw) {
891 			*link_setting = current_link_setting;
892 			return true;
893 		}
894 		if (policy) {
895 			/* minimize lane */
896 			if (current_link_setting.link_rate < max_link_rate) {
897 				increase_edp_link_rate(link, &current_link_setting);
898 			} else {
899 				if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
900 					current_link_setting.lane_count =
901 							increase_lane_count(
902 									current_link_setting.lane_count);
903 					current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
904 					current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set;
905 					current_link_setting.link_rate =
906 						link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
907 				} else
908 					break;
909 			}
910 		} else {
911 			/* minimize link rate */
912 			if (current_link_setting.lane_count <
913 					link->verified_link_cap.lane_count) {
914 				current_link_setting.lane_count =
915 						increase_lane_count(
916 								current_link_setting.lane_count);
917 			} else {
918 				increase_edp_link_rate(link, &current_link_setting);
919 				if (current_link_setting.link_rate == LINK_RATE_UNKNOWN)
920 					break;
921 			}
922 		}
923 	}
924 	return false;
925 }
926 
decide_mst_link_settings(const struct dc_link * link,struct dc_link_settings * link_setting)927 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
928 {
929 	*link_setting = link->verified_link_cap;
930 	return true;
931 }
932 
link_decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)933 bool link_decide_link_settings(struct dc_stream_state *stream,
934 	struct dc_link_settings *link_setting)
935 {
936 	struct dc_link *link = stream->link;
937 	uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
938 
939 	memset(link_setting, 0, sizeof(*link_setting));
940 
941 	if (dc_is_dp_signal(stream->signal)  &&
942 			link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
943 			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
944 		/* if preferred is specified through AMDDP, use it, if it's enough
945 		 * to drive the mode
946 		 */
947 		*link_setting = link->preferred_link_setting;
948 	} else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
949 		/* MST doesn't perform link training for now
950 		 * TODO: add MST specific link training routine
951 		 */
952 		decide_mst_link_settings(link, link_setting);
953 	} else if (stream->signal == SIGNAL_TYPE_VIRTUAL) {
954 		link_setting->lane_count = LANE_COUNT_FOUR;
955 		link_setting->link_rate = LINK_RATE_HIGH3;
956 	} else if (link->connector_signal == SIGNAL_TYPE_EDP) {
957 		/* enable edp link optimization for DSC eDP case */
958 		if (stream->timing.flags.DSC) {
959 			enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
960 
961 			if (link->panel_config.dsc.force_dsc_edp_policy) {
962 				/* calculate link max link rate cap*/
963 				struct dc_link_settings tmp_link_setting;
964 				struct dc_crtc_timing tmp_timing = stream->timing;
965 				uint32_t orig_req_bw;
966 
967 				tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
968 				tmp_timing.flags.DSC = 0;
969 				orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
970 						dc_link_get_highest_encoding_format(link));
971 				edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
972 				max_link_rate = tmp_link_setting.link_rate;
973 			}
974 			decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
975 		} else {
976 			edp_decide_link_settings(link, link_setting, req_bw);
977 		}
978 	} else {
979 		decide_dp_link_settings(link, link_setting, req_bw);
980 	}
981 
982 	return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
983 			link_setting->link_rate != LINK_RATE_UNKNOWN;
984 }
985 
link_dp_get_encoding_format(const struct dc_link_settings * link_settings)986 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
987 {
988 	if ((link_settings->link_rate >= LINK_RATE_LOW) &&
989 			(link_settings->link_rate <= LINK_RATE_HIGH3))
990 		return DP_8b_10b_ENCODING;
991 	else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
992 			(link_settings->link_rate <= LINK_RATE_UHBR20))
993 		return DP_128b_132b_ENCODING;
994 	return DP_UNKNOWN_ENCODING;
995 }
996 
mst_decide_link_encoding_format(const struct dc_link * link)997 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
998 {
999 	struct dc_link_settings link_settings = {0};
1000 
1001 	if (!dc_is_dp_signal(link->connector_signal))
1002 		return DP_UNKNOWN_ENCODING;
1003 
1004 	if (link->preferred_link_setting.lane_count !=
1005 			LANE_COUNT_UNKNOWN &&
1006 			link->preferred_link_setting.link_rate !=
1007 					LINK_RATE_UNKNOWN) {
1008 		link_settings = link->preferred_link_setting;
1009 	} else {
1010 		decide_mst_link_settings(link, &link_settings);
1011 	}
1012 
1013 	return link_dp_get_encoding_format(&link_settings);
1014 }
1015 
read_dp_device_vendor_id(struct dc_link * link)1016 static void read_dp_device_vendor_id(struct dc_link *link)
1017 {
1018 	struct dp_device_vendor_id dp_id = {0};
1019 
1020 	/* read IEEE branch device id */
1021 	core_link_read_dpcd(
1022 		link,
1023 		DP_BRANCH_OUI,
1024 		(uint8_t *)&dp_id,
1025 		sizeof(dp_id));
1026 
1027 	link->dpcd_caps.branch_dev_id =
1028 		(dp_id.ieee_oui[0] << 16) +
1029 		(dp_id.ieee_oui[1] << 8) +
1030 		dp_id.ieee_oui[2];
1031 
1032 	memmove(
1033 		link->dpcd_caps.branch_dev_name,
1034 		dp_id.ieee_device_id,
1035 		sizeof(dp_id.ieee_device_id));
1036 }
1037 
wake_up_aux_channel(struct dc_link * link)1038 static enum dc_status wake_up_aux_channel(struct dc_link *link)
1039 {
1040 	enum dc_status status = DC_ERROR_UNEXPECTED;
1041 	uint32_t aux_channel_retry_cnt = 0;
1042 	uint8_t dpcd_power_state = '\0';
1043 
1044 	while (status != DC_OK && aux_channel_retry_cnt < 10) {
1045 		status = core_link_read_dpcd(link, DP_SET_POWER,
1046 				&dpcd_power_state, sizeof(dpcd_power_state));
1047 
1048 		/* Delay 1 ms if AUX CH is in power down state. Based on spec
1049 		 * section 2.3.1.2, if AUX CH may be powered down due to
1050 		 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1051 		 * signal and may need up to 1 ms before being able to reply.
1052 		 */
1053 		if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1054 			fsleep(1000);
1055 			aux_channel_retry_cnt++;
1056 		}
1057 	}
1058 
1059 	if (status != DC_OK) {
1060 		dpcd_power_state = DP_SET_POWER_D0;
1061 		status = core_link_write_dpcd(
1062 				link,
1063 				DP_SET_POWER,
1064 				&dpcd_power_state,
1065 				sizeof(dpcd_power_state));
1066 
1067 		dpcd_power_state = DP_SET_POWER_D3;
1068 		status = core_link_write_dpcd(
1069 				link,
1070 				DP_SET_POWER,
1071 				&dpcd_power_state,
1072 				sizeof(dpcd_power_state));
1073 		DC_LOG_DC("%s: Failed to power up sink\n", __func__);
1074 		return DC_ERROR_UNEXPECTED;
1075 	}
1076 
1077 	return DC_OK;
1078 }
1079 
read_and_intersect_post_frl_lt_status(struct dc_link * link)1080 static void read_and_intersect_post_frl_lt_status(
1081 	struct dc_link *link)
1082 {
1083 	union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0};
1084 	union hdmi_tx_link_status hdmi_tx_link_status = {0};
1085 	union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0};
1086 
1087 	/* Check if dongle supports regulated autonomous mode. */
1088 	core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS,
1089 		&autonomous_mode_caps.raw, sizeof(autonomous_mode_caps));
1090 
1091 	link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support =
1092 			autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED;
1093 
1094 	if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) {
1095 		DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__);
1096 
1097 		core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS,
1098 				&hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status));
1099 	}
1100 
1101 	// Intersect reported max link bw support with the supported link rate post FRL link training
1102 	if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1103 			&hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1104 
1105 		if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support &&
1106 				(!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS ||
1107 						!hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) {
1108 			DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__);
1109 
1110 			/* Link training not finished, ignore values from this DPCD reg. */
1111 			return;
1112 		}
1113 
1114 		link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1115 				link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1116 				hdmi_encoded_link_bw);
1117 		DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,
1118 			link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);
1119 	}
1120 }
1121 
get_active_converter_info(uint8_t data,struct dc_link * link)1122 static void get_active_converter_info(
1123 	uint8_t data, struct dc_link *link)
1124 {
1125 	union dp_downstream_port_present ds_port = { .byte = data };
1126 	memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1127 
1128 	/* decode converter info*/
1129 	if (!ds_port.fields.PORT_PRESENT) {
1130 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1131 		set_dongle_type(link->ddc,
1132 				link->dpcd_caps.dongle_type);
1133 		link->dpcd_caps.is_branch_dev = false;
1134 		return;
1135 	}
1136 
1137 	/* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1138 	link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1139 
1140 	switch (ds_port.fields.PORT_TYPE) {
1141 	case DOWNSTREAM_VGA:
1142 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1143 		break;
1144 	case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1145 		/* At this point we don't know is it DVI or HDMI or DP++,
1146 		 * assume DVI.*/
1147 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1148 		break;
1149 	default:
1150 		link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1151 		break;
1152 	}
1153 
1154 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1155 		uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1156 		union dwnstream_port_caps_byte0 *port_caps =
1157 			(union dwnstream_port_caps_byte0 *)det_caps;
1158 		if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1159 				det_caps, sizeof(det_caps)) == DC_OK) {
1160 
1161 			switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1162 			/*Handle DP case as DONGLE_NONE*/
1163 			case DOWN_STREAM_DETAILED_DP:
1164 				link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1165 				break;
1166 			case DOWN_STREAM_DETAILED_VGA:
1167 				link->dpcd_caps.dongle_type =
1168 					DISPLAY_DONGLE_DP_VGA_CONVERTER;
1169 				break;
1170 			case DOWN_STREAM_DETAILED_DVI:
1171 				link->dpcd_caps.dongle_type =
1172 					DISPLAY_DONGLE_DP_DVI_CONVERTER;
1173 				break;
1174 			case DOWN_STREAM_DETAILED_HDMI:
1175 			case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1176 				/*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1177 				link->dpcd_caps.dongle_type =
1178 					DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1179 
1180 				link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1181 				if (ds_port.fields.DETAILED_CAPS) {
1182 
1183 					union dwnstream_port_caps_byte3_hdmi
1184 						hdmi_caps = {.raw = det_caps[3] };
1185 					union dwnstream_port_caps_byte2
1186 						hdmi_color_caps = {.raw = det_caps[2] };
1187 					link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1188 						det_caps[1] * 2500;
1189 
1190 					link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1191 						hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1192 					/*YCBCR capability only for HDMI case*/
1193 					if (port_caps->bits.DWN_STRM_PORTX_TYPE
1194 							== DOWN_STREAM_DETAILED_HDMI) {
1195 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1196 								hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1197 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1198 								hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1199 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1200 								hdmi_caps.bits.YCrCr422_CONVERSION;
1201 						link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1202 								hdmi_caps.bits.YCrCr420_CONVERSION;
1203 					}
1204 
1205 					link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1206 						translate_dpcd_max_bpc(
1207 							hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1208 
1209 					if (link->dc->caps.dp_hdmi21_pcon_support) {
1210 
1211 						link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1212 								link_bw_kbps_from_raw_frl_link_rate_data(
1213 										hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1214 
1215 						read_and_intersect_post_frl_lt_status(link);
1216 
1217 						if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1218 							link->dpcd_caps.dongle_caps.extendedCapValid = true;
1219 					}
1220 
1221 					if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1222 						link->dpcd_caps.dongle_caps.extendedCapValid = true;
1223 				}
1224 
1225 				break;
1226 			}
1227 		}
1228 	}
1229 
1230 	set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1231 
1232 	{
1233 		struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0};
1234 
1235 		core_link_read_dpcd(
1236 			link,
1237 			DP_BRANCH_REVISION_START,
1238 			(uint8_t *)&dp_hw_fw_revision,
1239 			sizeof(dp_hw_fw_revision));
1240 
1241 		link->dpcd_caps.branch_hw_revision =
1242 			dp_hw_fw_revision.ieee_hw_rev;
1243 
1244 		memmove(
1245 			link->dpcd_caps.branch_fw_revision,
1246 			dp_hw_fw_revision.ieee_fw_rev,
1247 			sizeof(dp_hw_fw_revision.ieee_fw_rev));
1248 	}
1249 
1250 	core_link_read_dpcd(
1251 		link,
1252 		DP_BRANCH_VENDOR_SPECIFIC_START,
1253 		(uint8_t *)link->dpcd_caps.branch_vendor_specific_data,
1254 		sizeof(link->dpcd_caps.branch_vendor_specific_data));
1255 
1256 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1257 			link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1258 		union dp_dfp_cap_ext dfp_cap_ext;
1259 		memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1260 		core_link_read_dpcd(
1261 				link,
1262 				DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1263 				dfp_cap_ext.raw,
1264 				sizeof(dfp_cap_ext.raw));
1265 		link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1266 		link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1267 				dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1268 				(dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1269 		link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1270 				dfp_cap_ext.fields.max_video_h_active_width[0] +
1271 				(dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1272 		link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1273 				dfp_cap_ext.fields.max_video_v_active_height[0] +
1274 				(dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1275 		link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1276 				dfp_cap_ext.fields.encoding_format_caps;
1277 		link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1278 				dfp_cap_ext.fields.rgb_color_depth_caps;
1279 		link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1280 				dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1281 		link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1282 				dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1283 		link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1284 				dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1285 		DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1286 		DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1287 		DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1288 		DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1289 		DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1290 	}
1291 }
1292 
apply_usbc_combo_phy_reset_wa(struct dc_link * link,struct dc_link_settings * link_settings)1293 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1294 		struct dc_link_settings *link_settings)
1295 {
1296 	/* Temporary Renoir-specific workaround PHY will sometimes be in bad
1297 	 * state on hotplugging display from certain USB-C dongle, so add extra
1298 	 * cycle of enabling and disabling the PHY before first link training.
1299 	 */
1300 	struct link_resource link_res = {0};
1301 	enum clock_source_id dp_cs_id = get_clock_source_id(link);
1302 
1303 	dp_enable_link_phy(link, &link_res, link->connector_signal,
1304 			dp_cs_id, link_settings);
1305 	dp_disable_link_phy(link, &link_res, link->connector_signal);
1306 }
1307 
dp_overwrite_extended_receiver_cap(struct dc_link * link)1308 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1309 {
1310 	uint8_t dpcd_data[16] = {0};
1311 	uint32_t read_dpcd_retry_cnt = 3;
1312 	enum dc_status status = DC_ERROR_UNEXPECTED;
1313 	union dp_downstream_port_present ds_port = { 0 };
1314 	union down_stream_port_count down_strm_port_count;
1315 	union edp_configuration_cap edp_config_cap;
1316 
1317 	int i;
1318 
1319 	for (i = 0; i < read_dpcd_retry_cnt; i++) {
1320 		status = core_link_read_dpcd(
1321 				link,
1322 				DP_DPCD_REV,
1323 				dpcd_data,
1324 				sizeof(dpcd_data));
1325 		if (status == DC_OK)
1326 			break;
1327 	}
1328 
1329 	link->dpcd_caps.dpcd_rev.raw =
1330 		dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1331 
1332 	if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1333 		return false;
1334 
1335 	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1336 			DP_DPCD_REV];
1337 
1338 	get_active_converter_info(ds_port.byte, link);
1339 
1340 	down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1341 			DP_DPCD_REV];
1342 
1343 	link->dpcd_caps.allow_invalid_MSA_timing_param =
1344 		down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1345 
1346 	link->dpcd_caps.max_ln_count.raw = dpcd_data[
1347 		DP_MAX_LANE_COUNT - DP_DPCD_REV];
1348 
1349 	link->dpcd_caps.max_down_spread.raw = dpcd_data[
1350 		DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1351 
1352 	link->reported_link_cap.lane_count =
1353 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1354 	link->reported_link_cap.link_rate = dpcd_data[
1355 		DP_MAX_LINK_RATE - DP_DPCD_REV];
1356 	link->reported_link_cap.link_spread =
1357 		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1358 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1359 
1360 	edp_config_cap.raw = dpcd_data[
1361 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1362 	link->dpcd_caps.panel_mode_edp =
1363 		edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1364 	link->dpcd_caps.dpcd_display_control_capable =
1365 		edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1366 
1367 	return true;
1368 }
1369 
dpcd_set_source_specific_data(struct dc_link * link)1370 void dpcd_set_source_specific_data(struct dc_link *link)
1371 {
1372 	if (!link->dc->vendor_signature.is_valid) {
1373 		enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
1374 		struct dpcd_amd_signature amd_signature = {0};
1375 		struct dpcd_amd_device_id amd_device_id = {0};
1376 
1377 		amd_device_id.device_id_byte1 =
1378 				(uint8_t)(link->ctx->asic_id.chip_id);
1379 		amd_device_id.device_id_byte2 =
1380 				(uint8_t)(link->ctx->asic_id.chip_id >> 8);
1381 		amd_device_id.dce_version =
1382 				(uint8_t)(link->ctx->dce_version);
1383 		amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1384 		amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1385 
1386 		core_link_read_dpcd(link, DP_SOURCE_OUI,
1387 				(uint8_t *)(&amd_signature),
1388 				sizeof(amd_signature));
1389 
1390 		if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1391 			(amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1392 			(amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1393 
1394 			amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1395 			amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1396 			amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1397 
1398 			core_link_write_dpcd(link, DP_SOURCE_OUI,
1399 				(uint8_t *)(&amd_signature),
1400 				sizeof(amd_signature));
1401 		}
1402 
1403 		core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1404 				(uint8_t *)(&amd_device_id),
1405 				sizeof(amd_device_id));
1406 
1407 		if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1408 			link->dc->caps.min_horizontal_blanking_period != 0) {
1409 
1410 			uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1411 
1412 			result_write_min_hblank = core_link_write_dpcd(link,
1413 				DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1414 				sizeof(hblank_size));
1415 		}
1416 		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1417 							WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1418 							"result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1419 							result_write_min_hblank,
1420 							link->link_index,
1421 							link->ctx->dce_version,
1422 							DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1423 							link->dc->caps.min_horizontal_blanking_period,
1424 							link->dpcd_caps.branch_dev_id,
1425 							link->dpcd_caps.branch_dev_name[0],
1426 							link->dpcd_caps.branch_dev_name[1],
1427 							link->dpcd_caps.branch_dev_name[2],
1428 							link->dpcd_caps.branch_dev_name[3],
1429 							link->dpcd_caps.branch_dev_name[4],
1430 							link->dpcd_caps.branch_dev_name[5]);
1431 	} else {
1432 		core_link_write_dpcd(link, DP_SOURCE_OUI,
1433 				link->dc->vendor_signature.data.raw,
1434 				sizeof(link->dc->vendor_signature.data.raw));
1435 	}
1436 }
1437 
dpcd_write_cable_id_to_dprx(struct dc_link * link)1438 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1439 {
1440 	if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1441 			link->dpcd_caps.cable_id.raw == 0 ||
1442 			link->dprx_states.cable_id_written)
1443 		return;
1444 
1445 	core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1446 			&link->dpcd_caps.cable_id.raw,
1447 			sizeof(link->dpcd_caps.cable_id.raw));
1448 
1449 	link->dprx_states.cable_id_written = 1;
1450 }
1451 
get_usbc_cable_id(struct dc_link * link,union dp_cable_id * cable_id)1452 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1453 {
1454 	union dmub_rb_cmd cmd;
1455 
1456 	if (!link->ctx->dmub_srv ||
1457 			link->ep_type != DISPLAY_ENDPOINT_PHY ||
1458 			link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1459 		return false;
1460 
1461 	memset(&cmd, 0, sizeof(cmd));
1462 	cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1463 	cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1464 	cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1465 			link->dc, link->link_enc->transmitter);
1466 	if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
1467 			cmd.cable_id.header.ret_status == 1) {
1468 		cable_id->raw = cmd.cable_id.data.output_raw;
1469 		DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1470 	}
1471 	return cmd.cable_id.header.ret_status == 1;
1472 }
1473 
retrieve_cable_id(struct dc_link * link)1474 static void retrieve_cable_id(struct dc_link *link)
1475 {
1476 	union dp_cable_id usbc_cable_id = {0};
1477 
1478 	link->dpcd_caps.cable_id.raw = 0;
1479 	core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1480 			&link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1481 
1482 	if (get_usbc_cable_id(link, &usbc_cable_id))
1483 		link->dpcd_caps.cable_id = intersect_cable_id(
1484 				&link->dpcd_caps.cable_id, &usbc_cable_id);
1485 }
1486 
read_is_mst_supported(struct dc_link * link)1487 bool read_is_mst_supported(struct dc_link *link)
1488 {
1489 	bool mst          = false;
1490 	enum dc_status st = DC_OK;
1491 	union dpcd_rev rev;
1492 	union mstm_cap cap;
1493 
1494 	if (link->preferred_training_settings.mst_enable &&
1495 		*link->preferred_training_settings.mst_enable == false) {
1496 		return false;
1497 	}
1498 
1499 	rev.raw  = 0;
1500 	cap.raw  = 0;
1501 
1502 	st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1503 			sizeof(rev));
1504 
1505 	if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1506 
1507 		st = core_link_read_dpcd(link, DP_MSTM_CAP,
1508 				&cap.raw, sizeof(cap));
1509 		if (st == DC_OK && cap.bits.MST_CAP == 1)
1510 			mst = true;
1511 	}
1512 	return mst;
1513 
1514 }
1515 
1516 /* Read additional sink caps defined in source specific DPCD area
1517  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1518  * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1519  */
dpcd_read_sink_ext_caps(struct dc_link * link)1520 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1521 {
1522 	uint8_t dpcd_data = 0;
1523 	uint8_t edp_general_cap2 = 0;
1524 
1525 	if (!link)
1526 		return false;
1527 
1528 	if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1529 		return false;
1530 
1531 	link->dpcd_sink_ext_caps.raw = dpcd_data;
1532 
1533 	if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
1534 		return false;
1535 
1536 	link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
1537 
1538 	return true;
1539 }
1540 
dp_retrieve_lttpr_cap(struct dc_link * link)1541 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1542 {
1543 	uint8_t lttpr_dpcd_data[10] = {0};
1544 	enum dc_status status;
1545 	bool is_lttpr_present;
1546 
1547 	/* Logic to determine LTTPR support*/
1548 	bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1549 
1550 	if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1551 		return DC_NOT_SUPPORTED;
1552 
1553 	/* By reading LTTPR capability, RX assumes that we will enable
1554 	 * LTTPR extended aux timeout if LTTPR is present.
1555 	 */
1556 	status = core_link_read_dpcd(
1557 			link,
1558 			DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1559 			lttpr_dpcd_data,
1560 			sizeof(lttpr_dpcd_data));
1561 
1562 	link->dpcd_caps.lttpr_caps.revision.raw =
1563 			lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1564 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1565 
1566 	link->dpcd_caps.lttpr_caps.max_link_rate =
1567 			lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1568 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1569 
1570 	link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1571 			lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1572 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1573 
1574 	link->dpcd_caps.lttpr_caps.max_lane_count =
1575 			lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1576 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1577 
1578 	link->dpcd_caps.lttpr_caps.mode =
1579 			lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1580 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1581 
1582 	link->dpcd_caps.lttpr_caps.max_ext_timeout =
1583 			lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1584 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1585 	link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1586 			lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1587 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1588 
1589 	link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1590 			lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1591 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1592 
1593 	link->dpcd_caps.lttpr_caps.alpm.raw =
1594 			lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES -
1595 							DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1596 
1597 	/* If this chip cap is set, at least one retimer must exist in the chain
1598 	 * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1599 	if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1600 			(dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1601 		/* If you see this message consistently, either the host platform has FIXED_VS flag
1602 		 * incorrectly configured or the sink device is returning an invalid count.
1603 		 */
1604 		DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",
1605 			     link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1606 		link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1607 		DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1608 	}
1609 
1610 	/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1611 	is_lttpr_present = dp_is_lttpr_present(link);
1612 
1613 	DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1614 
1615 	if (is_lttpr_present) {
1616 		CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1617 
1618 		core_link_read_dpcd(link, DP_LTTPR_IEEE_OUI, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
1619 		CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui), "LTTPR IEEE OUI: ");
1620 
1621 		core_link_read_dpcd(link, DP_LTTPR_DEVICE_ID, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id));
1622 		CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id), "LTTPR Device ID: ");
1623 	}
1624 
1625 	return status;
1626 }
1627 
retrieve_link_cap(struct dc_link * link)1628 static bool retrieve_link_cap(struct dc_link *link)
1629 {
1630 	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1631 	 * which means size 16 will be good for both of those DPCD register block reads
1632 	 */
1633 	uint8_t dpcd_data[16];
1634 	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1635 	 */
1636 	uint8_t dpcd_dprx_data = '\0';
1637 
1638 	struct dp_device_vendor_id sink_id;
1639 	union down_stream_port_count down_strm_port_count;
1640 	union edp_configuration_cap edp_config_cap;
1641 	union dp_downstream_port_present ds_port = { 0 };
1642 	enum dc_status status = DC_ERROR_UNEXPECTED;
1643 	uint32_t read_dpcd_retry_cnt = 3;
1644 	int i;
1645 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1646 	const uint32_t post_oui_delay = 30; // 30ms
1647 	bool is_fec_supported = false;
1648 	bool is_dsc_basic_supported = false;
1649 	bool is_dsc_passthrough_supported = false;
1650 
1651 	memset(dpcd_data, '\0', sizeof(dpcd_data));
1652 	memset(&down_strm_port_count,
1653 		'\0', sizeof(union down_stream_port_count));
1654 	memset(&edp_config_cap, '\0',
1655 		sizeof(union edp_configuration_cap));
1656 
1657 	/* if extended timeout is supported in hardware,
1658 	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1659 	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1660 	 */
1661 	try_to_configure_aux_timeout(link->ddc,
1662 			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1663 
1664 	status = dp_retrieve_lttpr_cap(link);
1665 
1666 	if (status != DC_OK) {
1667 		status = wake_up_aux_channel(link);
1668 		if (status == DC_OK)
1669 			dp_retrieve_lttpr_cap(link);
1670 		else
1671 			return false;
1672 	}
1673 
1674 	if (dp_is_lttpr_present(link)) {
1675 		configure_lttpr_mode_transparent(link);
1676 
1677 		// Echo TOTAL_LTTPR_CNT back downstream
1678 		core_link_write_dpcd(
1679 				link,
1680 				DP_TOTAL_LTTPR_CNT,
1681 				&link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
1682 				sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
1683 	}
1684 
1685 	dpcd_set_source_specific_data(link);
1686 	/* Sink may need to configure internals based on vendor, so allow some
1687 	 * time before proceeding with possibly vendor specific transactions
1688 	 */
1689 	msleep(post_oui_delay);
1690 
1691 	for (i = 0; i < read_dpcd_retry_cnt; i++) {
1692 		status = core_link_read_dpcd(
1693 				link,
1694 				DP_DPCD_REV,
1695 				dpcd_data,
1696 				sizeof(dpcd_data));
1697 		if (status == DC_OK)
1698 			break;
1699 	}
1700 
1701 
1702 	if (status != DC_OK) {
1703 		dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1704 		return false;
1705 	}
1706 
1707 	if (!dp_is_lttpr_present(link))
1708 		try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1709 
1710 
1711 	{
1712 		union training_aux_rd_interval aux_rd_interval;
1713 
1714 		aux_rd_interval.raw =
1715 			dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1716 
1717 		link->dpcd_caps.ext_receiver_cap_field_present =
1718 				aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1719 
1720 		if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1721 			uint8_t ext_cap_data[16];
1722 
1723 			memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1724 			for (i = 0; i < read_dpcd_retry_cnt; i++) {
1725 				status = core_link_read_dpcd(
1726 				link,
1727 				DP_DP13_DPCD_REV,
1728 				ext_cap_data,
1729 				sizeof(ext_cap_data));
1730 				if (status == DC_OK) {
1731 					memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1732 					break;
1733 				}
1734 			}
1735 			if (status != DC_OK)
1736 				dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1737 		}
1738 	}
1739 
1740 	link->dpcd_caps.dpcd_rev.raw =
1741 			dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1742 
1743 	if (link->dpcd_caps.ext_receiver_cap_field_present) {
1744 		for (i = 0; i < read_dpcd_retry_cnt; i++) {
1745 			status = core_link_read_dpcd(
1746 					link,
1747 					DP_DPRX_FEATURE_ENUMERATION_LIST,
1748 					&dpcd_dprx_data,
1749 					sizeof(dpcd_dprx_data));
1750 			if (status == DC_OK)
1751 				break;
1752 		}
1753 
1754 		link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1755 
1756 		if (status != DC_OK)
1757 			dm_error("%s: Read DPRX feature list failed.\n", __func__);
1758 
1759 		/* AdaptiveSyncCapability  */
1760 		dpcd_dprx_data = 0;
1761 		for (i = 0; i < read_dpcd_retry_cnt; i++) {
1762 			status = core_link_read_dpcd(
1763 					link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1764 					&dpcd_dprx_data, sizeof(dpcd_dprx_data));
1765 			if (status == DC_OK)
1766 				break;
1767 		}
1768 
1769 		link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1770 
1771 		if (status != DC_OK)
1772 			dm_error("%s: Read DPRX feature list_1 failed. Addr:%#x\n",
1773 					__func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1774 	}
1775 	else {
1776 		link->dpcd_caps.dprx_feature.raw = 0;
1777 	}
1778 
1779 	/* Error condition checking...
1780 	 * It is impossible for Sink to report Max Lane Count = 0.
1781 	 * It is possible for Sink to report Max Link Rate = 0, if it is
1782 	 * an eDP device that is reporting specialized link rates in the
1783 	 * SUPPORTED_LINK_RATE table.
1784 	 */
1785 	if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1786 		return false;
1787 
1788 	ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1789 				 DP_DPCD_REV];
1790 
1791 	read_dp_device_vendor_id(link);
1792 
1793 	/* TODO - decouple raw mst capability from policy decision */
1794 	link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1795 	DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable));
1796 
1797 	get_active_converter_info(ds_port.byte, link);
1798 
1799 	dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1800 
1801 	down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1802 				 DP_DPCD_REV];
1803 
1804 	link->dpcd_caps.allow_invalid_MSA_timing_param =
1805 		down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1806 
1807 	link->dpcd_caps.max_ln_count.raw = dpcd_data[
1808 		DP_MAX_LANE_COUNT - DP_DPCD_REV];
1809 
1810 	link->dpcd_caps.max_down_spread.raw = dpcd_data[
1811 		DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1812 
1813 	link->reported_link_cap.lane_count =
1814 		link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1815 	link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1816 			dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1817 	link->reported_link_cap.link_spread =
1818 		link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1819 		LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1820 
1821 	edp_config_cap.raw = dpcd_data[
1822 		DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1823 	link->dpcd_caps.panel_mode_edp =
1824 		edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1825 	link->dpcd_caps.dpcd_display_control_capable =
1826 		edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1827 	link->dpcd_caps.channel_coding_cap.raw =
1828 			dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1829 	link->test_pattern_enabled = false;
1830 	link->compliance_test_state.raw = 0;
1831 
1832 	link->dpcd_caps.receive_port0_cap.raw[0] =
1833 			dpcd_data[DP_RECEIVE_PORT_0_CAP_0 - DP_DPCD_REV];
1834 	link->dpcd_caps.receive_port0_cap.raw[1] =
1835 			dpcd_data[DP_RECEIVE_PORT_0_BUFFER_SIZE - DP_DPCD_REV];
1836 
1837 	/* read sink count */
1838 	core_link_read_dpcd(link,
1839 			DP_SINK_COUNT,
1840 			&link->dpcd_caps.sink_count.raw,
1841 			sizeof(link->dpcd_caps.sink_count.raw));
1842 
1843 	/* read sink ieee oui */
1844 	core_link_read_dpcd(link,
1845 			DP_SINK_OUI,
1846 			(uint8_t *)(&sink_id),
1847 			sizeof(sink_id));
1848 
1849 	link->dpcd_caps.sink_dev_id =
1850 			(sink_id.ieee_oui[0] << 16) +
1851 			(sink_id.ieee_oui[1] << 8) +
1852 			(sink_id.ieee_oui[2]);
1853 
1854 	memmove(
1855 		link->dpcd_caps.sink_dev_id_str,
1856 		sink_id.ieee_device_id,
1857 		sizeof(sink_id.ieee_device_id));
1858 
1859 	core_link_read_dpcd(
1860 		link,
1861 		DP_SINK_HW_REVISION_START,
1862 		(uint8_t *)&dp_hw_fw_revision,
1863 		sizeof(dp_hw_fw_revision));
1864 
1865 	link->dpcd_caps.sink_hw_revision =
1866 		dp_hw_fw_revision.ieee_hw_rev;
1867 
1868 	memmove(
1869 		link->dpcd_caps.sink_fw_revision,
1870 		dp_hw_fw_revision.ieee_fw_rev,
1871 		sizeof(dp_hw_fw_revision.ieee_fw_rev));
1872 
1873 	/* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1874 	{
1875 		uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1876 		uint8_t fwrev_mbp_2018[] = { 7, 4 };
1877 		uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1878 
1879 		/* We also check for the firmware revision as 16,1 models have an
1880 		 * identical device id and are incorrectly quirked otherwise.
1881 		 */
1882 		if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1883 		    !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1884 			     sizeof(str_mbp_2018)) &&
1885 		    (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1886 			     sizeof(fwrev_mbp_2018)) ||
1887 		    !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1888 			     sizeof(fwrev_mbp_2018_vega)))) {
1889 			link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1890 		}
1891 	}
1892 
1893 	memset(&link->dpcd_caps.dsc_caps, '\0',
1894 			sizeof(link->dpcd_caps.dsc_caps));
1895 	memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1896 	/* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1897 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1898 		status = core_link_read_dpcd(
1899 				link,
1900 				DP_FEC_CAPABILITY,
1901 				&link->dpcd_caps.fec_cap.raw,
1902 				sizeof(link->dpcd_caps.fec_cap.raw));
1903 		if (status != DC_OK)
1904 			DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_FEC_CAPABILITY) failed\n", __func__, __LINE__);
1905 
1906 		status = core_link_read_dpcd(
1907 				link,
1908 				DP_DSC_SUPPORT,
1909 				link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1910 				sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1911 		if (status == DC_OK) {
1912 			is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;
1913 			is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT;
1914 			is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT;
1915 			DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__,
1916 				  str_yes_no(is_fec_supported));
1917 			DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__,
1918 				  str_yes_no(is_dsc_basic_supported));
1919 			DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__,
1920 				  str_yes_no(is_dsc_passthrough_supported));
1921 		}
1922 		if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1923 			status = core_link_read_dpcd(
1924 					link,
1925 					DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1926 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1927 					sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1928 			if (status != DC_OK)
1929 				DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_DSC_BRANCH_OVERALL_THROUGHPUT_0) failed\n", __func__, __LINE__);
1930 
1931 			DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1932 			DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1933 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1934 			DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1935 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1936 			DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1937 					link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1938 		}
1939 
1940 		/* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1941 		 * only if required.
1942 		 */
1943 		if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1944 				link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1945 				link->dpcd_caps.is_branch_dev &&
1946 				link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1947 				link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1948 				(link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
1949 				link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
1950 			/* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
1951 			 * Clear FEC and DSC capabilities as a work around if that is not the case.
1952 			 */
1953 			link->wa_flags.dpia_forced_tbt3_mode = true;
1954 			memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
1955 			memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1956 			DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
1957 		} else
1958 			link->wa_flags.dpia_forced_tbt3_mode = false;
1959 	}
1960 
1961 	if (!dpcd_read_sink_ext_caps(link))
1962 		link->dpcd_sink_ext_caps.raw = 0;
1963 
1964 	if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
1965 		DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
1966 
1967 		/* Read 128b/132b suppoerted link rates */
1968 		core_link_read_dpcd(link,
1969 				DP_128B132B_SUPPORTED_LINK_RATES,
1970 				&link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
1971 				sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
1972 		if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
1973 			link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
1974 		else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
1975 			link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
1976 		else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
1977 			link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
1978 		else
1979 			dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
1980 		DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
1981 		DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
1982 				link->reported_link_cap.link_rate / 100,
1983 				link->reported_link_cap.link_rate % 100);
1984 
1985 		core_link_read_dpcd(link,
1986 				DP_SINK_VIDEO_FALLBACK_FORMATS,
1987 				&link->dpcd_caps.fallback_formats.raw,
1988 				sizeof(link->dpcd_caps.fallback_formats.raw));
1989 		DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
1990 		if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
1991 			DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
1992 		if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
1993 			DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
1994 		if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
1995 			DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
1996 		if (link->dpcd_caps.fallback_formats.raw == 0) {
1997 			DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
1998 			link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
1999 		}
2000 
2001 		core_link_read_dpcd(link,
2002 				DP_FEC_CAPABILITY_1,
2003 				&link->dpcd_caps.fec_cap1.raw,
2004 				sizeof(link->dpcd_caps.fec_cap1.raw));
2005 		DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
2006 		if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
2007 			DC_LOG_DP2("\tFEC aggregated error counters are supported");
2008 	}
2009 
2010 	core_link_read_dpcd(link,
2011 			DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP,
2012 			link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw,
2013 			sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw));
2014 
2015 	/* Read DP tunneling information. */
2016 	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
2017 		status = dpcd_get_tunneling_device_data(link);
2018 		if (status != DC_OK)
2019 			dm_error("%s: Read DP tunneling device data failed.\n", __func__);
2020 	}
2021 
2022 	retrieve_cable_id(link);
2023 	dpcd_write_cable_id_to_dprx(link);
2024 
2025 	/* Connectivity log: detection */
2026 	CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
2027 
2028 	return true;
2029 }
2030 
detect_dp_sink_caps(struct dc_link * link)2031 bool detect_dp_sink_caps(struct dc_link *link)
2032 {
2033 	return retrieve_link_cap(link);
2034 }
2035 
detect_edp_sink_caps(struct dc_link * link)2036 void detect_edp_sink_caps(struct dc_link *link)
2037 {
2038 	uint8_t supported_link_rates[16];
2039 	uint32_t entry;
2040 	uint32_t link_rate_in_khz;
2041 	enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
2042 	uint8_t backlight_adj_cap = 0;
2043 	uint8_t general_edp_cap = 0;
2044 
2045 	retrieve_link_cap(link);
2046 	link->dpcd_caps.edp_supported_link_rates_count = 0;
2047 	memset(supported_link_rates, 0, sizeof(supported_link_rates));
2048 
2049 	/*
2050 	 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2051 	 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2052 	 */
2053 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) {
2054 		// Read DPCD 00010h - 0001Fh 16 bytes at one shot
2055 		core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
2056 							supported_link_rates, sizeof(supported_link_rates));
2057 
2058 		for (entry = 0; entry < 16; entry += 2) {
2059 			// DPCD register reports per-lane link rate = 16-bit link rate capability
2060 			// value X 200 kHz. Need multiplier to find link rate in kHz.
2061 			link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2062 										supported_link_rates[entry]) * 200;
2063 
2064 			DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__,
2065 				  entry / 2, link_rate_in_khz);
2066 
2067 			if (link_rate_in_khz != 0) {
2068 				link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
2069 				link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
2070 				link->dpcd_caps.edp_supported_link_rates_count++;
2071 			}
2072 		}
2073 	}
2074 
2075 	core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
2076 						&backlight_adj_cap, sizeof(backlight_adj_cap));
2077 
2078 	link->dpcd_caps.dynamic_backlight_capable_edp =
2079 				(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
2080 
2081 	core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
2082 						&general_edp_cap, sizeof(general_edp_cap));
2083 
2084 	link->dpcd_caps.set_power_state_capable_edp =
2085 				(general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
2086 
2087 	set_default_brightness_aux(link);
2088 
2089 	core_link_read_dpcd(link, DP_EDP_DPCD_REV,
2090 		&link->dpcd_caps.edp_rev,
2091 		sizeof(link->dpcd_caps.edp_rev));
2092 	/*
2093 	 * PSR is only valid for eDP v1.3 or higher.
2094 	 */
2095 	if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
2096 		core_link_read_dpcd(link, DP_PSR_SUPPORT,
2097 			&link->dpcd_caps.psr_info.psr_version,
2098 			sizeof(link->dpcd_caps.psr_info.psr_version));
2099 		if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
2100 			core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
2101 						&link->dpcd_caps.psr_info.force_psrsu_cap,
2102 						sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
2103 		core_link_read_dpcd(link, DP_PSR_CAPS,
2104 			&link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
2105 			sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
2106 		if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
2107 			core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
2108 				&link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
2109 				sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
2110 		}
2111 	}
2112 
2113 	/*
2114 	 * ALPM is only valid for eDP v1.4 or higher.
2115 	 */
2116 	if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2117 		core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
2118 			&link->dpcd_caps.alpm_caps.raw,
2119 			sizeof(link->dpcd_caps.alpm_caps.raw));
2120 
2121 	/*
2122 	 * Read REPLAY info
2123 	 */
2124 	core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE,
2125 			&link->dpcd_caps.pr_info.pixel_deviation_per_line,
2126 			sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
2127 	core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
2128 			&link->dpcd_caps.pr_info.max_deviation_line,
2129 			sizeof(link->dpcd_caps.pr_info.max_deviation_line));
2130 
2131 	/*
2132 	 * OLED Emission Rate info
2133 	 */
2134 	if (link->dpcd_sink_ext_caps.bits.emission_output)
2135 		core_link_read_dpcd(link, DP_SINK_EMISSION_RATE,
2136 				(uint8_t *)&link->dpcd_caps.edp_oled_emission_rate,
2137 				sizeof(link->dpcd_caps.edp_oled_emission_rate));
2138 
2139 	/*
2140 	 * Read Multi-SST (Single Stream Transport) capability
2141 	 * for eDP version 1.4 or higher.
2142 	 */
2143 	if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2144 		core_link_read_dpcd(
2145 			link,
2146 			DP_EDP_MSO_LINK_CAPABILITIES,
2147 			(uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported,
2148 			sizeof(link->dpcd_caps.mso_cap_sst_links_supported));
2149 }
2150 
dp_get_max_link_enc_cap(const struct dc_link * link,struct dc_link_settings * max_link_enc_cap)2151 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2152 {
2153 	struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
2154 	struct resource_pool *res_pool = link->dc->res_pool;
2155 	struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
2156 
2157 	if (!max_link_enc_cap) {
2158 		DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2159 		return false;
2160 	}
2161 
2162 	if (!link->dc->config.unify_link_enc_assignment)
2163 		link_enc = link_enc_cfg_get_link_enc(link);
2164 	ASSERT(link_enc);
2165 
2166 	if (link_enc && link_enc->funcs->get_max_link_cap) {
2167 		link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2168 		return true;
2169 	}
2170 
2171 	DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2172 	max_link_enc_cap->lane_count = 1;
2173 	max_link_enc_cap->link_rate = 6;
2174 	return false;
2175 }
2176 
dp_get_verified_link_cap(const struct dc_link * link)2177 const struct dc_link_settings *dp_get_verified_link_cap(
2178 		const struct dc_link *link)
2179 {
2180 	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2181 			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2182 		return &link->preferred_link_setting;
2183 	return &link->verified_link_cap;
2184 }
2185 
dp_get_max_link_cap(struct dc_link * link)2186 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2187 {
2188 	struct dc_link_settings max_link_cap = {0};
2189 	enum dc_link_rate lttpr_max_link_rate;
2190 	enum dc_link_rate cable_max_link_rate;
2191 	struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
2192 	struct resource_pool *res_pool = link->dc->res_pool;
2193 	struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
2194 	bool is_uhbr13_5_supported = true;
2195 
2196 	if (!link->dc->config.unify_link_enc_assignment)
2197 		link_enc = link_enc_cfg_get_link_enc(link);
2198 	ASSERT(link_enc);
2199 
2200 	/* get max link encoder capability */
2201 	if (link_enc)
2202 		link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2203 
2204 	/* Lower link settings based on sink's link cap */
2205 	if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2206 		max_link_cap.lane_count =
2207 				link->reported_link_cap.lane_count;
2208 	if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2209 		max_link_cap.link_rate =
2210 				link->reported_link_cap.link_rate;
2211 	if (link->reported_link_cap.link_spread <
2212 			max_link_cap.link_spread)
2213 		max_link_cap.link_spread =
2214 				link->reported_link_cap.link_spread;
2215 
2216 	if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
2217 		is_uhbr13_5_supported = false;
2218 
2219 	/* Lower link settings based on cable attributes
2220 	 * Cable ID is a DP2 feature to identify max certified link rate that
2221 	 * a cable can carry. The cable identification method requires both
2222 	 * cable and display hardware support. Since the specs comes late, it is
2223 	 * anticipated that the first round of DP2 cables and displays may not
2224 	 * be fully compatible to reliably return cable ID data. Therefore the
2225 	 * decision of our cable id policy is that if the cable can return non
2226 	 * zero cable id data, we will take cable's link rate capability into
2227 	 * account. However if we get zero data, the cable link rate capability
2228 	 * is considered inconclusive. In this case, we will not take cable's
2229 	 * capability into account to avoid of over limiting hardware capability
2230 	 * from users. The max overall link rate capability is still determined
2231 	 * after actual dp pre-training. Cable id is considered as an auxiliary
2232 	 * method of determining max link bandwidth capability.
2233 	 */
2234 	cable_max_link_rate = get_cable_max_link_rate(link);
2235 
2236 	if (!link->dc->debug.ignore_cable_id &&
2237 			cable_max_link_rate != LINK_RATE_UNKNOWN) {
2238 		if (cable_max_link_rate < max_link_cap.link_rate)
2239 			max_link_cap.link_rate = cable_max_link_rate;
2240 
2241 		if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &&
2242 				link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)
2243 			is_uhbr13_5_supported = false;
2244 	}
2245 
2246 	/* account for lttpr repeaters cap
2247 	 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2248 	 */
2249 	if (dp_is_lttpr_present(link)) {
2250 
2251 		/* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */
2252 		if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) {
2253 			if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2254 				max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2255 			lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2256 
2257 			if (lttpr_max_link_rate < max_link_cap.link_rate)
2258 				max_link_cap.link_rate = lttpr_max_link_rate;
2259 
2260 			if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
2261 				is_uhbr13_5_supported = false;
2262 		}
2263 
2264 		DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2265 						__func__,
2266 						max_link_cap.lane_count,
2267 						max_link_cap.link_rate);
2268 	}
2269 
2270 	if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 &&
2271 			!is_uhbr13_5_supported)
2272 		max_link_cap.link_rate = LINK_RATE_UHBR10;
2273 
2274 	if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2275 			link->dc->debug.disable_uhbr)
2276 		max_link_cap.link_rate = LINK_RATE_HIGH3;
2277 
2278 	return max_link_cap;
2279 }
2280 
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)2281 static bool dp_verify_link_cap(
2282 	struct dc_link *link,
2283 	struct dc_link_settings *known_limit_link_setting,
2284 	int *fail_count)
2285 {
2286 	struct dc_link_settings cur_link_settings = {0};
2287 	struct dc_link_settings max_link_settings = *known_limit_link_setting;
2288 	bool success = false;
2289 	bool skip_video_pattern;
2290 	enum clock_source_id dp_cs_id = get_clock_source_id(link);
2291 	enum link_training_result status = LINK_TRAINING_SUCCESS;
2292 	union hpd_irq_data irq_data;
2293 	struct link_resource link_res;
2294 
2295 	memset(&irq_data, 0, sizeof(irq_data));
2296 	cur_link_settings = max_link_settings;
2297 
2298 	/* Grant extended timeout request */
2299 	if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2300 		uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2301 
2302 		core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2303 	}
2304 
2305 	do {
2306 		if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2307 			continue;
2308 
2309 		skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2310 		dp_enable_link_phy(
2311 				link,
2312 				&link_res,
2313 				link->connector_signal,
2314 				dp_cs_id,
2315 				&cur_link_settings);
2316 
2317 		status = dp_perform_link_training(
2318 				link,
2319 				&link_res,
2320 				&cur_link_settings,
2321 				skip_video_pattern);
2322 
2323 		if (status == LINK_TRAINING_SUCCESS) {
2324 			success = true;
2325 			fsleep(1000);
2326 			if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2327 					dp_parse_link_loss_status(
2328 							link,
2329 							&irq_data))
2330 				(*fail_count)++;
2331 		} else if (status == LINK_TRAINING_LINK_LOSS) {
2332 			success = true;
2333 			(*fail_count)++;
2334 		} else {
2335 			(*fail_count)++;
2336 		}
2337 		dp_trace_lt_total_count_increment(link, true);
2338 		dp_trace_lt_result_update(link, status, true);
2339 		dp_disable_link_phy(link, &link_res, link->connector_signal);
2340 	} while (!success && decide_fallback_link_setting(link,
2341 			&max_link_settings, &cur_link_settings, status));
2342 
2343 	link->verified_link_cap = success ?
2344 			cur_link_settings : fail_safe_link_settings;
2345 	return success;
2346 }
2347 
dp_verify_link_cap_with_retries(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int attempts)2348 bool dp_verify_link_cap_with_retries(
2349 	struct dc_link *link,
2350 	struct dc_link_settings *known_limit_link_setting,
2351 	int attempts)
2352 {
2353 	int i = 0;
2354 	bool success = false;
2355 	int fail_count = 0;
2356 	struct dc_link_settings last_verified_link_cap = fail_safe_link_settings;
2357 
2358 	dp_trace_detect_lt_init(link);
2359 
2360 	if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2361 			link->dc->debug.usbc_combo_phy_reset_wa)
2362 		apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2363 
2364 	dp_trace_set_lt_start_timestamp(link, false);
2365 	for (i = 0; i < attempts; i++) {
2366 		enum dc_connection_type type = dc_connection_none;
2367 
2368 		memset(&link->verified_link_cap, 0,
2369 				sizeof(struct dc_link_settings));
2370 		if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) {
2371 			link->verified_link_cap = fail_safe_link_settings;
2372 			break;
2373 		} else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
2374 			last_verified_link_cap = link->verified_link_cap;
2375 			if (fail_count == 0) {
2376 				success = true;
2377 				break;
2378 			}
2379 		} else {
2380 			link->verified_link_cap = last_verified_link_cap;
2381 		}
2382 
2383 		/* For Dp tunneling link, a pending HPD means that we have a race condition between processing
2384 		 * current link and processing the pending HPD. Since the training is failed, we should just brak
2385 		 * the loop so that we have chance to process the pending HPD.
2386 		 */
2387 		if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending)
2388 			break;
2389 
2390 		fsleep(10 * 1000);
2391 	}
2392 
2393 	dp_trace_lt_fail_count_update(link, fail_count, true);
2394 	dp_trace_set_lt_end_timestamp(link, true);
2395 
2396 	return success;
2397 }
2398 
2399 /*
2400  * Check if there is a native DP or passive DP-HDMI dongle connected
2401  */
dp_is_sink_present(struct dc_link * link)2402 bool dp_is_sink_present(struct dc_link *link)
2403 {
2404 	enum gpio_result gpio_result;
2405 	uint32_t clock_pin = 0;
2406 	uint8_t retry = 0;
2407 	struct ddc *ddc;
2408 
2409 	enum connector_id connector_id =
2410 		dal_graphics_object_id_get_connector_id(link->link_id);
2411 
2412 	bool present =
2413 		((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2414 		(connector_id == CONNECTOR_ID_EDP) ||
2415 		(connector_id == CONNECTOR_ID_USBC));
2416 
2417 	ddc = get_ddc_pin(link->ddc);
2418 
2419 	if (!ddc) {
2420 		BREAK_TO_DEBUGGER();
2421 		return present;
2422 	}
2423 
2424 	/* Open GPIO and set it to I2C mode */
2425 	/* Note: this GpioMode_Input will be converted
2426 	 * to GpioConfigType_I2cAuxDualMode in GPIO component,
2427 	 * which indicates we need additional delay
2428 	 */
2429 
2430 	if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2431 			 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2432 		dal_ddc_close(ddc);
2433 
2434 		return present;
2435 	}
2436 
2437 	/*
2438 	 * Read GPIO: DP sink is present if both clock and data pins are zero
2439 	 *
2440 	 * [W/A] plug-unplug DP cable, sometimes customer board has
2441 	 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2442 	 * then monitor can't br light up. Add retry 3 times
2443 	 * But in real passive dongle, it need additional 3ms to detect
2444 	 */
2445 	do {
2446 		gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2447 		ASSERT(gpio_result == GPIO_RESULT_OK);
2448 		if (clock_pin)
2449 			fsleep(1000);
2450 		else
2451 			break;
2452 	} while (retry++ < 3);
2453 
2454 	present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2455 
2456 	dal_ddc_close(ddc);
2457 
2458 	return present;
2459 }
2460