1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #include "link_hwss_dpia.h"
26 #include "core_types.h"
27 #include "link_hwss_dio.h"
28 #include "link_enc_cfg.h"
29 
30 #define DC_LOGGER \
31 	link->ctx->logger
32 #define DC_LOGGER_INIT(logger)
33 
update_dpia_stream_allocation_table(struct dc_link * link,const struct link_resource * link_res,const struct link_mst_stream_allocation_table * table)34 static void update_dpia_stream_allocation_table(struct dc_link *link,
35 		const struct link_resource *link_res,
36 		const struct link_mst_stream_allocation_table *table)
37 {
38 	struct link_encoder *link_enc = link_res->dio_link_enc;
39 	static enum dc_status status;
40 	uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
41 	int i;
42 	DC_LOGGER_INIT(link->ctx->logger);
43 
44 	if (!link->dc->config.unify_link_enc_assignment)
45 		link_enc = link_enc_cfg_get_link_enc(link);
46 
47 	for (i = 0; i < table->stream_count; i++)
48 		mst_alloc_slots += table->stream_allocations[i].slot_count;
49 
50 	status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
51 			mst_alloc_slots, &prev_mst_slots_in_use);
52 	ASSERT(status == DC_OK);
53 	DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
54 			status, mst_alloc_slots, prev_mst_slots_in_use);
55 
56 	if (link_enc)
57 		link_enc->funcs->update_mst_stream_allocation_table(link_enc, table);
58 }
59 
set_dio_dpia_link_test_pattern(struct dc_link * link,const struct link_resource * link_res,struct encoder_set_dp_phy_pattern_param * tp_params)60 static void set_dio_dpia_link_test_pattern(struct dc_link *link,
61 		const struct link_resource *link_res,
62 		struct encoder_set_dp_phy_pattern_param *tp_params)
63 {
64 	if (tp_params->dp_phy_pattern != DP_TEST_PATTERN_VIDEO_MODE)
65 		return;
66 
67 	struct link_encoder *link_enc = link_res->dio_link_enc;
68 
69 	if (!link->dc->config.unify_link_enc_assignment)
70 		link_enc = link_enc_cfg_get_link_enc(link);
71 
72 	if (!link_enc)
73 		return;
74 
75 	link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params);
76 	link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
77 }
78 
set_dio_dpia_lane_settings(struct dc_link * link,const struct link_resource * link_res,const struct dc_link_settings * link_settings,const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])79 static void set_dio_dpia_lane_settings(struct dc_link *link,
80 		const struct link_resource *link_res,
81 		const struct dc_link_settings *link_settings,
82 		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
83 {
84 }
85 
enable_dpia_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal,enum clock_source_id clock_source,const struct dc_link_settings * link_settings)86 static void enable_dpia_link_output(struct dc_link *link,
87 		const struct link_resource *link_res,
88 		enum signal_type signal,
89 		enum clock_source_id clock_source,
90 		const struct dc_link_settings *link_settings)
91 {
92 	struct link_encoder *link_enc = link_res->dio_link_enc;
93 	DC_LOGGER_INIT(link->ctx->logger);
94 
95 	if (!link->dc->config.unify_link_enc_assignment)
96 		link_enc = link_enc_cfg_get_link_enc(link);
97 
98 	if (link_enc != NULL) {
99 		if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {
100 			uint8_t fec_rdy = link->dc->link_srv->dp_should_enable_fec(link);
101 			uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;
102 
103 			if (link_enc->funcs->enable_dpia_output)
104 				link_enc->funcs->enable_dpia_output(
105 						link_enc,
106 						link_settings,
107 						link->ddc_hw_inst,
108 						digmode,
109 						fec_rdy);
110 			else
111 				DC_LOG_ERROR("%s: link encoder does not support enable_dpia_output\n", __func__);
112 		} else
113 			enable_dio_dp_link_output(link, link_res, signal, clock_source, link_settings);
114 
115 	}
116 
117 	link->dc->link_srv->dp_trace_source_sequence(link,
118 			DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
119 }
120 
disable_dpia_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)121 static void disable_dpia_link_output(struct dc_link *link,
122 		const struct link_resource *link_res,
123 		enum signal_type signal)
124 {
125 	struct link_encoder *link_enc = link_res->dio_link_enc;
126 	DC_LOGGER_INIT(link->ctx->logger);
127 
128 	if (!link->dc->config.unify_link_enc_assignment)
129 		link_enc = link_enc_cfg_get_link_enc(link);
130 
131 	if (link_enc != NULL) {
132 		if (link->dc->config.enable_dpia_pre_training || link->dc->config.unify_link_enc_assignment) {
133 			uint8_t digmode = dc_is_dp_sst_signal(signal) ? DIG_SST_MODE : DIG_MST_MODE;
134 
135 			if (link_enc->funcs->disable_dpia_output)
136 				link_enc->funcs->disable_dpia_output(link_enc, link->ddc_hw_inst, digmode);
137 			else
138 				DC_LOG_ERROR("%s: link encoder does not support disable_dpia_output\n", __func__);
139 		} else
140 			link_enc->funcs->disable_output(link_enc, signal);
141 	}
142 
143 	link->dc->link_srv->dp_trace_source_sequence(link,
144 			DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
145 }
146 
147 static const struct link_hwss dpia_link_hwss = {
148 	.setup_stream_encoder = setup_dio_stream_encoder,
149 	.reset_stream_encoder = reset_dio_stream_encoder,
150 	.setup_stream_attribute = setup_dio_stream_attribute,
151 	.disable_link_output = disable_dpia_link_output,
152 	.setup_audio_output = setup_dio_audio_output,
153 	.enable_audio_packet = enable_dio_audio_packet,
154 	.disable_audio_packet = disable_dio_audio_packet,
155 	.ext = {
156 		.set_throttled_vcp_size = set_dio_throttled_vcp_size,
157 		.enable_dp_link_output = enable_dpia_link_output,
158 		.set_dp_link_test_pattern = set_dio_dpia_link_test_pattern,
159 		.set_dp_lane_settings = set_dio_dpia_lane_settings,
160 		.update_stream_allocation_table = update_dpia_stream_allocation_table,
161 	},
162 };
163 
can_use_dpia_link_hwss(const struct dc_link * link,const struct link_resource * link_res)164 bool can_use_dpia_link_hwss(const struct dc_link *link,
165 		const struct link_resource *link_res)
166 {
167 	if (!link->dc->config.unify_link_enc_assignment)
168 		return link->is_dig_mapping_flexible && link->dc->res_pool->funcs->link_encs_assign;
169 	else
170 		return link->is_dig_mapping_flexible && link_res->dio_link_enc != NULL;
171 }
172 
get_dpia_link_hwss(void)173 const struct link_hwss *get_dpia_link_hwss(void)
174 {
175 	return &dpia_link_hwss;
176 }
177