1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include <drm/display/drm_dsc_helper.h>
6
7 #include "reg_helper.h"
8 #include "dcn401_dsc.h"
9 #include "dsc/dscc_types.h"
10 #include "dsc/rc_calc.h"
11
12 #define MAX_THROUGHPUT_PER_DSC_100HZ 20000000
13 #define MAX_DSC_UNIT_COMBINE 4
14
15 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
16
17 /* Object I/F functions */
18 //static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
19 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
20 static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
21 static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
22
23 static const struct dsc_funcs dcn401_dsc_funcs = {
24 .dsc_get_enc_caps = dsc401_get_enc_caps,
25 .dsc_read_state = dsc401_read_state,
26 .dsc_validate_stream = dsc401_validate_stream,
27 .dsc_set_config = dsc401_set_config,
28 .dsc_get_packed_pps = dsc2_get_packed_pps,
29 .dsc_enable = dsc401_enable,
30 .dsc_disable = dsc401_disable,
31 .dsc_disconnect = dsc401_disconnect,
32 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear,
33 };
34
35 /* Macro definitios for REG_SET macros*/
36 #define CTX \
37 dsc401->base.ctx
38
39 #define REG(reg)\
40 dsc401->dsc_regs->reg
41
42 #undef FN
43 #define FN(reg_name, field_name) \
44 dsc401->dsc_shift->field_name, dsc401->dsc_mask->field_name
45 #define DC_LOGGER \
46 dsc->ctx->logger
47
48 enum dsc_bits_per_comp {
49 DSC_BPC_8 = 8,
50 DSC_BPC_10 = 10,
51 DSC_BPC_12 = 12,
52 DSC_BPC_UNKNOWN
53 };
54
55 /* API functions (external or via structure->function_pointer) */
56
dsc401_construct(struct dcn401_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn401_dsc_registers * dsc_regs,const struct dcn401_dsc_shift * dsc_shift,const struct dcn401_dsc_mask * dsc_mask)57 void dsc401_construct(struct dcn401_dsc *dsc,
58 struct dc_context *ctx,
59 int inst,
60 const struct dcn401_dsc_registers *dsc_regs,
61 const struct dcn401_dsc_shift *dsc_shift,
62 const struct dcn401_dsc_mask *dsc_mask)
63 {
64 dsc->base.ctx = ctx;
65 dsc->base.inst = inst;
66 dsc->base.funcs = &dcn401_dsc_funcs;
67
68 dsc->dsc_regs = dsc_regs;
69 dsc->dsc_shift = dsc_shift;
70 dsc->dsc_mask = dsc_mask;
71
72 dsc->max_image_width = 5184;
73 }
74
dsc401_get_enc_caps(struct dsc_enc_caps * dsc_enc_caps,int pixel_clock_100Hz)75 static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
76 {
77 int min_dsc_unit_required = (pixel_clock_100Hz + MAX_THROUGHPUT_PER_DSC_100HZ - 1) / MAX_THROUGHPUT_PER_DSC_100HZ;
78
79 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
80
81 /* 1 slice is only supported with 1 DSC unit */
82 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = min_dsc_unit_required == 1 ? 1 : 0;
83 /* 2 slice is only supported with 1 or 2 DSC units */
84 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = (min_dsc_unit_required == 1 || min_dsc_unit_required == 2) ? 1 : 0;
85 /* 3 slice is only supported with 1 DSC unit */
86 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = min_dsc_unit_required == 1 ? 1 : 0;
87 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
88 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
89 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;
90 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;
91
92 dsc_enc_caps->lb_bit_depth = 13;
93 dsc_enc_caps->is_block_pred_supported = true;
94
95 dsc_enc_caps->color_formats.bits.RGB = 1;
96 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
97 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
98 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
99 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
100
101 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
102 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
103 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
104 dsc_enc_caps->max_total_throughput_mps = MAX_THROUGHPUT_PER_DSC_100HZ * MAX_DSC_UNIT_COMBINE;
105
106 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
107 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
108 }
109
110 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
111 * into a dcn_dsc_state struct.
112 */
dsc401_read_state(struct display_stream_compressor * dsc,struct dcn_dsc_state * s)113 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
114 {
115 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
116
117 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
118 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
119 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
120 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
121 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
122 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
123 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
124 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
125 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
126 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
127 }
128
129
dsc401_validate_stream(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg)130 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
131 {
132 struct dsc_optc_config dsc_optc_cfg;
133 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
134
135 if (dsc_cfg->pic_width > dsc401->max_image_width)
136 return false;
137
138 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg);
139 }
140
dsc401_set_config(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,struct dsc_optc_config * dsc_optc_cfg)141 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
142 struct dsc_optc_config *dsc_optc_cfg)
143 {
144 bool is_config_ok;
145 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
146
147 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
148 dsc_config_log(dsc, dsc_cfg);
149 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg);
150 ASSERT(is_config_ok);
151 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
152 dsc_log_pps(dsc, &dsc401->reg_vals.pps);
153 dsc_write_to_registers(dsc, &dsc401->reg_vals);
154 }
155
dsc401_enable(struct display_stream_compressor * dsc,int opp_pipe)156 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe)
157 {
158 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
159 int dsc_clock_en;
160 int dsc_fw_config;
161 int enabled_opp_pipe;
162
163 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
164
165 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
166 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
167 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
168 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
169 ASSERT(0);
170 }
171
172 REG_UPDATE(DSC_TOP_CONTROL,
173 DSC_CLOCK_EN, 1);
174
175 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
176 DSCRM_DSC_FORWARD_EN, 1,
177 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
178 }
179
180
dsc401_disable(struct display_stream_compressor * dsc)181 void dsc401_disable(struct display_stream_compressor *dsc)
182 {
183 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
184 int dsc_clock_en;
185
186 DC_LOG_DSC("disable DSC %d", dsc->inst);
187
188 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
189 if (!dsc_clock_en) {
190 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
191 }
192
193 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
194 DSCRM_DSC_FORWARD_EN, 0);
195
196 REG_UPDATE(DSC_TOP_CONTROL,
197 DSC_CLOCK_EN, 0);
198 }
199
dsc401_wait_disconnect_pending_clear(struct display_stream_compressor * dsc)200 static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
201 {
202 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
203
204 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000);
205 }
206
dsc401_disconnect(struct display_stream_compressor * dsc)207 void dsc401_disconnect(struct display_stream_compressor *dsc)
208 {
209 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
210
211 DC_LOG_DSC("disconnect DSC %d", dsc->inst);
212
213 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
214 DSCRM_DSC_FORWARD_EN, 0);
215 }
216
dsc_write_to_registers(struct display_stream_compressor * dsc,const struct dsc_reg_values * reg_vals)217 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
218 {
219 uint32_t temp_int;
220 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc);
221
222 REG_SET(DSC_DEBUG_CONTROL, 0,
223 DSC_DBG_EN, reg_vals->dsc_dbg_en);
224
225 // dsccif registers
226 REG_SET_2(DSCCIF_CONFIG0, 0,
227 //INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
228 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
229 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
230 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
231 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
232
233 /* REG_SET_2(DSCCIF_CONFIG1, 0,
234 PIC_WIDTH, reg_vals->pps.pic_width,
235 PIC_HEIGHT, reg_vals->pps.pic_height);
236 */
237 // dscc registers
238 if (dsc401->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
239 REG_SET_3(DSCC_CONFIG0, 0,
240 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
241 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
242 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
243 } else {
244 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
245 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
246 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
247 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
248 reg_vals->num_slices_v - 1);
249 }
250
251 REG_SET(DSCC_CONFIG1, 0,
252 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
253 /*REG_SET_2(DSCC_CONFIG1, 0,
254 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
255 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
256
257 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0,
258 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals->rc_buffer_model_overflow_int_en[0],
259 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals->rc_buffer_model_overflow_int_en[1],
260 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals->rc_buffer_model_overflow_int_en[2],
261 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals->rc_buffer_model_overflow_int_en[3]);
262
263 REG_SET_3(DSCC_PPS_CONFIG0, 0,
264 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
265 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
266 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
267
268 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
269 temp_int = reg_vals->bpp_x32;
270 else
271 temp_int = reg_vals->bpp_x32 >> 1;
272
273 REG_SET_7(DSCC_PPS_CONFIG1, 0,
274 BITS_PER_PIXEL, temp_int,
275 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
276 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
277 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
278 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
279 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
280 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
281
282 REG_SET_2(DSCC_PPS_CONFIG2, 0,
283 PIC_WIDTH, reg_vals->pps.pic_width,
284 PIC_HEIGHT, reg_vals->pps.pic_height);
285
286 REG_SET_2(DSCC_PPS_CONFIG3, 0,
287 SLICE_WIDTH, reg_vals->pps.slice_width,
288 SLICE_HEIGHT, reg_vals->pps.slice_height);
289
290 REG_SET(DSCC_PPS_CONFIG4, 0,
291 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
292
293 REG_SET_2(DSCC_PPS_CONFIG5, 0,
294 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
295 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
296
297 REG_SET_3(DSCC_PPS_CONFIG6, 0,
298 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
299 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
300 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
301
302 REG_SET_2(DSCC_PPS_CONFIG7, 0,
303 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
304 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
305
306 REG_SET_2(DSCC_PPS_CONFIG8, 0,
307 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
308 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
309
310 REG_SET_2(DSCC_PPS_CONFIG9, 0,
311 INITIAL_OFFSET, reg_vals->pps.initial_offset,
312 FINAL_OFFSET, reg_vals->pps.final_offset);
313
314 REG_SET_3(DSCC_PPS_CONFIG10, 0,
315 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
316 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
317 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
318
319 REG_SET_5(DSCC_PPS_CONFIG11, 0,
320 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
321 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
322 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
323 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
324 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
325
326 REG_SET_4(DSCC_PPS_CONFIG12, 0,
327 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
328 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
329 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
330 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
331
332 REG_SET_4(DSCC_PPS_CONFIG13, 0,
333 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
334 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
335 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
336 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
337
338 REG_SET_4(DSCC_PPS_CONFIG14, 0,
339 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
340 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
341 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
342 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
343
344 REG_SET_5(DSCC_PPS_CONFIG15, 0,
345 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
346 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
347 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
348 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
349 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
350
351 REG_SET_6(DSCC_PPS_CONFIG16, 0,
352 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
353 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
354 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
355 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
356 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
357 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
358
359 REG_SET_6(DSCC_PPS_CONFIG17, 0,
360 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
361 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
362 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
363 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
364 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
365 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
366
367 REG_SET_6(DSCC_PPS_CONFIG18, 0,
368 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
369 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
370 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
371 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
372 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
373 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
374
375 REG_SET_6(DSCC_PPS_CONFIG19, 0,
376 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
377 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
378 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
379 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
380 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
381 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
382
383 REG_SET_6(DSCC_PPS_CONFIG20, 0,
384 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
385 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
386 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
387 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
388 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
389 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
390
391 REG_SET_6(DSCC_PPS_CONFIG21, 0,
392 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
393 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
394 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
395 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
396 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
397 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
398
399 REG_SET_6(DSCC_PPS_CONFIG22, 0,
400 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
401 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
402 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
403 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
404 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
405 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
406 }
407
dsc401_set_fgcg(struct dcn401_dsc * dsc401,bool enable)408 void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable)
409 {
410 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable);
411 }
412