1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 /*
24  * dc_debug.c
25  *
26  *  Created on: Nov 3, 2016
27  *      Author: yonsun
28  */
29 
30 #include "dm_services.h"
31 
32 #include "dc.h"
33 
34 #include "core_status.h"
35 #include "core_types.h"
36 
37 #include "resource.h"
38 
39 #define DC_LOGGER \
40 	dc->ctx->logger
41 #define DC_LOGGER_INIT(logger)
42 
43 
44 #define SURFACE_TRACE(...) do {\
45 		if (dc->debug.surface_trace) \
46 			DC_LOG_IF_TRACE(__VA_ARGS__); \
47 } while (0)
48 
49 #define CLOCK_TRACE(...) do {\
50 	if (dc->debug.clock_trace) \
51 		DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
52 } while (0)
53 
update_surface_trace(struct dc * dc,const struct dc_surface_update * updates,int surface_count)54 void update_surface_trace(
55 		struct dc *dc,
56 		const struct dc_surface_update *updates,
57 		int surface_count)
58 {
59 	int i;
60 	DC_LOGGER_INIT(dc->ctx->logger);
61 
62 	for (i = 0; i < surface_count; i++) {
63 		const struct dc_surface_update *update = &updates[i];
64 
65 		SURFACE_TRACE("Update %d\n", i);
66 		if (update->flip_addr) {
67 			SURFACE_TRACE("flip_addr->address.type = %d;\n"
68 					"flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
69 					"flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
70 					"flip_addr->flip_immediate = %d;\n",
71 					update->flip_addr->address.type,
72 					update->flip_addr->address.grph.addr.quad_part,
73 					update->flip_addr->address.grph.meta_addr.quad_part,
74 					update->flip_addr->flip_immediate);
75 		}
76 
77 		if (update->plane_info) {
78 			SURFACE_TRACE(
79 					"plane_info->color_space = %d;\n"
80 					"plane_info->format = %d;\n"
81 					"plane_info->plane_size.surface_pitch = %d;\n"
82 					"plane_info->plane_size.surface_size.height = %d;\n"
83 					"plane_info->plane_size.surface_size.width = %d;\n"
84 					"plane_info->plane_size.surface_size.x = %d;\n"
85 					"plane_info->plane_size.surface_size.y = %d;\n"
86 					"plane_info->rotation = %d;\n"
87 					"plane_info->stereo_format = %d;\n",
88 					update->plane_info->color_space,
89 					update->plane_info->format,
90 					update->plane_info->plane_size.surface_pitch,
91 					update->plane_info->plane_size.surface_size.height,
92 					update->plane_info->plane_size.surface_size.width,
93 					update->plane_info->plane_size.surface_size.x,
94 					update->plane_info->plane_size.surface_size.y,
95 					update->plane_info->rotation,
96 					update->plane_info->stereo_format);
97 
98 			SURFACE_TRACE(
99 					"plane_info->tiling_info.gfx8.num_banks = %d;\n"
100 					"plane_info->tiling_info.gfx8.bank_width = %d;\n"
101 					"plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
102 					"plane_info->tiling_info.gfx8.bank_height = %d;\n"
103 					"plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
104 					"plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
105 					"plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
106 					"plane_info->tiling_info.gfx8.tile_split = %d;\n"
107 					"plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
108 					"plane_info->tiling_info.gfx8.tile_mode = %d;\n"
109 					"plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
110 					update->plane_info->tiling_info.gfx8.num_banks,
111 					update->plane_info->tiling_info.gfx8.bank_width,
112 					update->plane_info->tiling_info.gfx8.bank_width_c,
113 					update->plane_info->tiling_info.gfx8.bank_height,
114 					update->plane_info->tiling_info.gfx8.bank_height_c,
115 					update->plane_info->tiling_info.gfx8.tile_aspect,
116 					update->plane_info->tiling_info.gfx8.tile_aspect_c,
117 					update->plane_info->tiling_info.gfx8.tile_split,
118 					update->plane_info->tiling_info.gfx8.tile_split_c,
119 					update->plane_info->tiling_info.gfx8.tile_mode,
120 					update->plane_info->tiling_info.gfx8.tile_mode_c);
121 
122 			SURFACE_TRACE(
123 					"plane_info->tiling_info.gfx8.pipe_config = %d;\n"
124 					"plane_info->tiling_info.gfx8.array_mode = %d;\n"
125 					"plane_info->visible = %d;\n"
126 					"plane_info->per_pixel_alpha = %d;\n",
127 					update->plane_info->tiling_info.gfx8.pipe_config,
128 					update->plane_info->tiling_info.gfx8.array_mode,
129 					update->plane_info->visible,
130 					update->plane_info->per_pixel_alpha);
131 
132 			SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
133 					update->plane_info->tiling_info.gfx9.swizzle);
134 		}
135 
136 		if (update->scaling_info) {
137 			SURFACE_TRACE(
138 					"scaling_info->src_rect.x = %d;\n"
139 					"scaling_info->src_rect.y = %d;\n"
140 					"scaling_info->src_rect.width = %d;\n"
141 					"scaling_info->src_rect.height = %d;\n"
142 					"scaling_info->dst_rect.x = %d;\n"
143 					"scaling_info->dst_rect.y = %d;\n"
144 					"scaling_info->dst_rect.width = %d;\n"
145 					"scaling_info->dst_rect.height = %d;\n"
146 					"scaling_info->clip_rect.x = %d;\n"
147 					"scaling_info->clip_rect.y = %d;\n"
148 					"scaling_info->clip_rect.width = %d;\n"
149 					"scaling_info->clip_rect.height = %d;\n"
150 					"scaling_info->scaling_quality.h_taps = %d;\n"
151 					"scaling_info->scaling_quality.v_taps = %d;\n"
152 					"scaling_info->scaling_quality.h_taps_c = %d;\n"
153 					"scaling_info->scaling_quality.v_taps_c = %d;\n",
154 					update->scaling_info->src_rect.x,
155 					update->scaling_info->src_rect.y,
156 					update->scaling_info->src_rect.width,
157 					update->scaling_info->src_rect.height,
158 					update->scaling_info->dst_rect.x,
159 					update->scaling_info->dst_rect.y,
160 					update->scaling_info->dst_rect.width,
161 					update->scaling_info->dst_rect.height,
162 					update->scaling_info->clip_rect.x,
163 					update->scaling_info->clip_rect.y,
164 					update->scaling_info->clip_rect.width,
165 					update->scaling_info->clip_rect.height,
166 					update->scaling_info->scaling_quality.h_taps,
167 					update->scaling_info->scaling_quality.v_taps,
168 					update->scaling_info->scaling_quality.h_taps_c,
169 					update->scaling_info->scaling_quality.v_taps_c);
170 		}
171 		SURFACE_TRACE("\n");
172 	}
173 	SURFACE_TRACE("\n");
174 }
175 
post_surface_trace(struct dc * dc)176 void post_surface_trace(struct dc *dc)
177 {
178 	DC_LOGGER_INIT(dc->ctx->logger);
179 
180 	SURFACE_TRACE("post surface process.\n");
181 
182 }
183 
context_clock_trace(struct dc * dc,struct dc_state * context)184 void context_clock_trace(
185 		struct dc *dc,
186 		struct dc_state *context)
187 {
188 	DC_LOGGER_INIT(dc->ctx->logger);
189 	CLOCK_TRACE("Current: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"
190 			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
191 			context->bw_ctx.bw.dcn.clk.dispclk_khz,
192 			context->bw_ctx.bw.dcn.clk.dppclk_khz,
193 			context->bw_ctx.bw.dcn.clk.dcfclk_khz,
194 			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
195 			context->bw_ctx.bw.dcn.clk.fclk_khz,
196 			context->bw_ctx.bw.dcn.clk.socclk_khz);
197 	CLOCK_TRACE("Calculated: dispclk_khz:%d  max_dppclk_khz:%d  dcfclk_khz:%d\n"
198 			"dcfclk_deep_sleep_khz:%d  fclk_khz:%d  socclk_khz:%d\n",
199 			context->bw_ctx.bw.dcn.clk.dispclk_khz,
200 			context->bw_ctx.bw.dcn.clk.dppclk_khz,
201 			context->bw_ctx.bw.dcn.clk.dcfclk_khz,
202 			context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
203 			context->bw_ctx.bw.dcn.clk.fclk_khz,
204 			context->bw_ctx.bw.dcn.clk.socclk_khz);
205 }
206 
207 /**
208  * dc_status_to_str - convert dc_status to a human readable string
209  * @status: dc_status to be converted
210  *
211  * Return:
212  * A string describing the DC status.
213  */
dc_status_to_str(enum dc_status status)214 char *dc_status_to_str(enum dc_status status)
215 {
216 	switch (status) {
217 	case DC_OK:
218 		return "DC OK";
219 	case DC_NO_CONTROLLER_RESOURCE:
220 		return "No controller resource";
221 	case DC_NO_STREAM_ENC_RESOURCE:
222 		return "No stream encoder";
223 	case DC_NO_CLOCK_SOURCE_RESOURCE:
224 		return "No clock source";
225 	case DC_FAIL_CONTROLLER_VALIDATE:
226 		return "Controller validation failure";
227 	case DC_FAIL_ENC_VALIDATE:
228 		return "Encoder validation failure";
229 	case DC_FAIL_ATTACH_SURFACES:
230 		return "Surfaces attachment failure";
231 	case DC_FAIL_DETACH_SURFACES:
232 		return "Surfaces detachment failure";
233 	case DC_FAIL_SURFACE_VALIDATE:
234 		return "Surface validation failure";
235 	case DC_NO_DP_LINK_BANDWIDTH:
236 		return "No DP link bandwidth";
237 	case DC_EXCEED_DONGLE_CAP:
238 		return "Exceed dongle capability";
239 	case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED:
240 		return "Unsupported pixel format";
241 	case DC_FAIL_BANDWIDTH_VALIDATE:
242 		return "Bandwidth validation failure (BW and Watermark)";
243 	case DC_FAIL_SCALING:
244 		return "Scaling failure";
245 	case DC_FAIL_DP_LINK_TRAINING:
246 		return "DP link training failure";
247 	case DC_FAIL_DSC_VALIDATE:
248 		return "DSC validation failure";
249 	case DC_NO_DSC_RESOURCE:
250 		return "No DSC resource";
251 	case DC_FAIL_UNSUPPORTED_1:
252 		return "Unsupported";
253 	case DC_FAIL_CLK_EXCEED_MAX:
254 		return "Clk exceed max failure";
255 	case DC_FAIL_CLK_BELOW_MIN:
256 		return "Fail clk below minimum";
257 	case DC_FAIL_CLK_BELOW_CFG_REQUIRED:
258 		return "Fail clk below required CFG (hard_min in PPLIB)";
259 	case DC_NOT_SUPPORTED:
260 		return "The operation is not supported.";
261 	case DC_UNSUPPORTED_VALUE:
262 		return "The value specified is not supported.";
263 	case DC_NO_LINK_ENC_RESOURCE:
264 		return "No link encoder resource";
265 	case DC_FAIL_DP_PAYLOAD_ALLOCATION:
266 		return "Fail dp payload allocation";
267 	case DC_FAIL_DP_LINK_BANDWIDTH:
268 		return "Insufficient DP link bandwidth";
269 	case DC_ERROR_UNEXPECTED:
270 		return "Unexpected error";
271 	}
272 
273 	return "Unexpected status error";
274 }
275 
dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding)276 char *dc_pixel_encoding_to_str(enum dc_pixel_encoding pixel_encoding)
277 {
278 	switch (pixel_encoding) {
279 	case PIXEL_ENCODING_RGB:
280 		return "RGB";
281 	case PIXEL_ENCODING_YCBCR422:
282 		return "YUV422";
283 	case PIXEL_ENCODING_YCBCR444:
284 		return "YUV444";
285 	case PIXEL_ENCODING_YCBCR420:
286 		return "YUV420";
287 	default:
288 		return "Unknown";
289 	}
290 }
291 
dc_color_depth_to_str(enum dc_color_depth color_depth)292 char *dc_color_depth_to_str(enum dc_color_depth color_depth)
293 {
294 	switch (color_depth) {
295 	case COLOR_DEPTH_666:
296 		return "6-bpc";
297 	case COLOR_DEPTH_888:
298 		return "8-bpc";
299 	case COLOR_DEPTH_101010:
300 		return "10-bpc";
301 	case COLOR_DEPTH_121212:
302 		return "12-bpc";
303 	case COLOR_DEPTH_141414:
304 		return "14-bpc";
305 	case COLOR_DEPTH_161616:
306 		return "16-bpc";
307 	case COLOR_DEPTH_999:
308 		return "9-bpc";
309 	case COLOR_DEPTH_111111:
310 		return "11-bpc";
311 	default:
312 		return "Unknown";
313 	}
314 }
315