1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4 
5 #include "dccg.h"
6 #include "clk_mgr_internal.h"
7 #include "dcn401/dcn401_clk_mgr_smu_msg.h"
8 #include "dcn20/dcn20_clk_mgr.h"
9 #include "dce100/dce_clk_mgr.h"
10 #include "dcn31/dcn31_clk_mgr.h"
11 #include "dcn32/dcn32_clk_mgr.h"
12 #include "dcn401/dcn401_clk_mgr.h"
13 #include "reg_helper.h"
14 #include "core_types.h"
15 #include "dm_helpers.h"
16 #include "link.h"
17 #include "dc_state_priv.h"
18 #include "atomfirmware.h"
19 
20 #include "dcn401_smu14_driver_if.h"
21 
22 #include "dcn/dcn_4_1_0_offset.h"
23 #include "dcn/dcn_4_1_0_sh_mask.h"
24 
25 #include "dml/dcn401/dcn401_fpu.h"
26 
27 #define DCN_BASE__INST0_SEG1                       0x000000C0
28 
29 #define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E37
30 #define mmCLK01_CLK0_CLK0_DFS_CNTL                      0x16E69
31 #define mmCLK01_CLK0_CLK1_DFS_CNTL                      0x16E6C
32 #define mmCLK01_CLK0_CLK2_DFS_CNTL                      0x16E6F
33 #define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E72
34 #define mmCLK01_CLK0_CLK4_DFS_CNTL                      0x16E75
35 #define mmCLK20_CLK2_CLK2_DFS_CNTL                      0x1B051
36 
37 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK                  0x000001ffUL
38 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK                 0x0000f000UL
39 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK                 0xffff0000UL
40 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT                0x00000000
41 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT               0x0000000c
42 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT               0x00000010
43 
44 #undef FN
45 #define FN(reg_name, field_name) \
46 	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47 
48 #define REG(reg) \
49 	(clk_mgr->regs->reg)
50 
51 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
52 
53 #define BASE(seg) BASE_INNER(seg)
54 
55 #define SR(reg_name)\
56 		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
57 					reg ## reg_name
58 
59 #define CLK_SR_DCN401(reg_name, block, inst)\
60 	.reg_name = mm ## block ## _ ## reg_name
61 
62 static const struct clk_mgr_registers clk_mgr_regs_dcn401 = {
63 	CLK_REG_LIST_DCN401()
64 };
65 
66 static const struct clk_mgr_shift clk_mgr_shift_dcn401 = {
67 	CLK_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
68 };
69 
70 static const struct clk_mgr_mask clk_mgr_mask_dcn401 = {
71 	CLK_COMMON_MASK_SH_LIST_DCN401(_MASK)
72 };
73 
74 #define TO_DCN401_CLK_MGR(clk_mgr)\
75 	container_of(clk_mgr, struct dcn401_clk_mgr, base)
76 
dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)77 static bool dcn401_is_ppclk_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
78 {
79 	bool ppclk_dpm_enabled = false;
80 
81 	switch (clk) {
82 	case PPCLK_SOCCLK:
83 		ppclk_dpm_enabled =
84 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_socclk_levels > 1;
85 		break;
86 	case PPCLK_UCLK:
87 		ppclk_dpm_enabled =
88 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_memclk_levels > 1;
89 		break;
90 	case PPCLK_FCLK:
91 		ppclk_dpm_enabled =
92 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels > 1;
93 		break;
94 	case PPCLK_DISPCLK:
95 		ppclk_dpm_enabled =
96 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels > 1;
97 		break;
98 	case PPCLK_DPPCLK:
99 		ppclk_dpm_enabled =
100 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels > 1;
101 		break;
102 	case PPCLK_DPREFCLK:
103 		ppclk_dpm_enabled = false;
104 		break;
105 	case PPCLK_DCFCLK:
106 		ppclk_dpm_enabled =
107 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels > 1;
108 		break;
109 	case PPCLK_DTBCLK:
110 		ppclk_dpm_enabled =
111 				clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels > 1;
112 		break;
113 	default:
114 		ppclk_dpm_enabled = false;
115 	}
116 
117 	ppclk_dpm_enabled &= clk_mgr->smu_present;
118 
119 	return ppclk_dpm_enabled;
120 }
121 
dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal * clk_mgr,PPCLK_e clk)122 static bool dcn401_is_ppclk_idle_dpm_enabled(struct clk_mgr_internal *clk_mgr, PPCLK_e clk)
123 {
124 	bool ppclk_idle_dpm_enabled = false;
125 
126 	switch (clk) {
127 	case PPCLK_UCLK:
128 	case PPCLK_FCLK:
129 		if (ASICREV_IS_GC_12_0_0_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
130 				clk_mgr->smu_ver >= 0x681800) {
131 			ppclk_idle_dpm_enabled = true;
132 		} else if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
133 				clk_mgr->smu_ver >= 0x661300) {
134 			ppclk_idle_dpm_enabled = true;
135 		}
136 		break;
137 	default:
138 		ppclk_idle_dpm_enabled = false;
139 	}
140 
141 	ppclk_idle_dpm_enabled &= clk_mgr->smu_present;
142 
143 	return ppclk_idle_dpm_enabled;
144 }
145 
dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal * clk_mgr)146 static bool dcn401_is_df_throttle_opt_enabled(struct clk_mgr_internal *clk_mgr)
147 {
148 	bool is_df_throttle_opt_enabled = false;
149 
150 	if (ASICREV_IS_GC_12_0_1_A0(clk_mgr->base.ctx->asic_id.hw_internal_rev) &&
151 			clk_mgr->smu_ver >= 0x663500) {
152 		is_df_throttle_opt_enabled = !clk_mgr->base.ctx->dc->debug.force_subvp_df_throttle;
153 	}
154 
155 	is_df_throttle_opt_enabled &= clk_mgr->smu_present;
156 
157 	return is_df_throttle_opt_enabled;
158 }
159 
160 /* Query SMU for all clock states for a particular clock */
dcn401_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)161 static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
162 		unsigned int *num_levels)
163 {
164 	unsigned int i;
165 	char *entry_i = (char *)entry_0;
166 
167 	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
168 
169 	if (ret & (1 << 31))
170 		/* fine-grained, only min and max */
171 		*num_levels = 2;
172 	else
173 		/* discrete, a number of fixed states */
174 		/* will set num_levels to 0 on failure */
175 		*num_levels = ret & 0xFF;
176 
177 	/* if the initial message failed, num_levels will be 0 */
178 	for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
179 		*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
180 		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
181 	}
182 }
183 
dcn401_build_wm_range_table(struct clk_mgr * clk_mgr)184 static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
185 {
186 	/* legacy */
187 	DC_FP_START();
188 	dcn401_build_wm_range_table_fpu(clk_mgr);
189 	DC_FP_END();
190 
191 	if (clk_mgr->ctx->dc->debug.using_dml21) {
192 		/* For min clocks use as reported by PM FW and report those as min */
193 		uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
194 		uint16_t min_dcfclk_mhz	= clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
195 
196 		/* Set A - Normal - default values */
197 		clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
198 		clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
199 		clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
200 		clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
201 		clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
202 		clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
203 
204 		/* Set B - Unused on dcn4 */
205 		clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid = false;
206 
207 		/* Set 1A - Dummy P-State - P-State latency set to "dummy p-state" value */
208 		/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
209 		if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
210 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
211 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
212 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
213 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
214 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
215 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
216 		} else {
217 			clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
218 		}
219 
220 		/* Set 1B - Unused on dcn4 */
221 		clk_mgr->bw_params->wm_table.nv_entries[WM_1B].valid = false;
222 	}
223 }
224 
dcn401_init_clocks(struct clk_mgr * clk_mgr_base)225 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base)
226 {
227 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
228 	struct clk_limit_num_entries *num_entries_per_clk;
229 	unsigned int i;
230 
231 	if (!clk_mgr_base->bw_params)
232 		return;
233 
234 	num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
235 
236 	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
237 	clk_mgr_base->clks.p_state_change_support = true;
238 	clk_mgr_base->clks.prev_p_state_change_support = true;
239 	clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
240 	clk_mgr->smu_present = false;
241 	clk_mgr->dpm_present = false;
242 
243 	if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
244 		clk_mgr->smu_present = true;
245 
246 	if (!clk_mgr->smu_present)
247 		return;
248 
249 	dcn30_smu_check_driver_if_version(clk_mgr);
250 	dcn30_smu_check_msg_header_version(clk_mgr);
251 
252 	/* DCFCLK */
253 	dcn401_init_single_clock(clk_mgr, PPCLK_DCFCLK,
254 			&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
255 			&num_entries_per_clk->num_dcfclk_levels);
256 	clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
257 	if (num_entries_per_clk->num_dcfclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz ==
258 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dcfclk_levels - 1].dcfclk_mhz)
259 		clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = 0;
260 
261 	/* SOCCLK */
262 	dcn401_init_single_clock(clk_mgr, PPCLK_SOCCLK,
263 					&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
264 					&num_entries_per_clk->num_socclk_levels);
265 	clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
266 	if (num_entries_per_clk->num_socclk_levels && clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz ==
267 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_socclk_levels - 1].socclk_mhz)
268 		clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = 0;
269 
270 	/* DTBCLK */
271 	if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
272 		dcn401_init_single_clock(clk_mgr, PPCLK_DTBCLK,
273 				&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
274 				&num_entries_per_clk->num_dtbclk_levels);
275 		clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
276 		if (num_entries_per_clk->num_dtbclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz ==
277 				clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dtbclk_levels - 1].dtbclk_mhz)
278 			clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz = 0;
279 	}
280 
281 	/* DISPCLK */
282 	dcn401_init_single_clock(clk_mgr, PPCLK_DISPCLK,
283 			&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
284 			&num_entries_per_clk->num_dispclk_levels);
285 	clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
286 	if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz ==
287 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz)
288 		clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0;
289 
290 	/* DPPCLK */
291 	dcn401_init_single_clock(clk_mgr, PPCLK_DPPCLK,
292 			&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
293 			&num_entries_per_clk->num_dppclk_levels);
294 
295 	if (num_entries_per_clk->num_dcfclk_levels &&
296 			num_entries_per_clk->num_dtbclk_levels &&
297 			num_entries_per_clk->num_dispclk_levels)
298 		clk_mgr->dpm_present = true;
299 
300 	if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
301 		for (i = 0; i < num_entries_per_clk->num_dispclk_levels; i++)
302 			if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
303 					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
304 				clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
305 					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
306 	}
307 
308 	if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
309 		for (i = 0; i < num_entries_per_clk->num_dppclk_levels; i++)
310 			if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
311 					< khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
312 				clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
313 					= khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
314 	}
315 
316 	/* Get UCLK, update bounding box */
317 	clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
318 
319 	/* WM range table */
320 	dcn401_build_wm_range_table(clk_mgr_base);
321 }
322 
dcn401_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)323 static void dcn401_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
324 		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
325 {
326 		struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
327 		uint32_t dprefclk_did = 0;
328 		uint32_t dcfclk_did = 0;
329 		uint32_t dtbclk_did = 0;
330 		uint32_t dispclk_did = 0;
331 		uint32_t dppclk_did = 0;
332 		uint32_t fclk_did = 0;
333 		uint32_t target_div = 0;
334 
335 		/* DFS Slice 0 is used for DISPCLK */
336 		dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
337 		/* DFS Slice 1 is used for DPPCLK */
338 		dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
339 		/* DFS Slice 2 is used for DPREFCLK */
340 		dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
341 		/* DFS Slice 3 is used for DCFCLK */
342 		dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
343 		/* DFS Slice 4 is used for DTBCLK */
344 		dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
345 		/* DFS Slice _ is used for FCLK */
346 		fclk_did = REG_READ(CLK2_CLK2_DFS_CNTL);
347 
348 		/* Convert DISPCLK DFS Slice DID to divider*/
349 		target_div = dentist_get_divider_from_did(dispclk_did);
350 		//Get dispclk in khz
351 		regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
352 				* clk_mgr->base.dentist_vco_freq_khz) / target_div;
353 
354 		/* Convert DISPCLK DFS Slice DID to divider*/
355 		target_div = dentist_get_divider_from_did(dppclk_did);
356 		//Get dppclk in khz
357 		regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
358 				* clk_mgr->base.dentist_vco_freq_khz) / target_div;
359 
360 		/* Convert DPREFCLK DFS Slice DID to divider*/
361 		target_div = dentist_get_divider_from_did(dprefclk_did);
362 		//Get dprefclk in khz
363 		regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
364 				* clk_mgr->base.dentist_vco_freq_khz) / target_div;
365 
366 		/* Convert DCFCLK DFS Slice DID to divider*/
367 		target_div = dentist_get_divider_from_did(dcfclk_did);
368 		//Get dcfclk in khz
369 		regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
370 				* clk_mgr->base.dentist_vco_freq_khz) / target_div;
371 
372 		/* Convert DTBCLK DFS Slice DID to divider*/
373 		target_div = dentist_get_divider_from_did(dtbclk_did);
374 		//Get dtbclk in khz
375 		regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
376 				* clk_mgr->base.dentist_vco_freq_khz) / target_div;
377 
378 		/* Convert DTBCLK DFS Slice DID to divider*/
379 		target_div = dentist_get_divider_from_did(fclk_did);
380 		//Get fclk in khz
381 		regs_and_bypass->fclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
382 				* clk_mgr->base.dentist_vco_freq_khz) / target_div;
383 }
384 
dcn401_check_native_scaling(struct pipe_ctx * pipe)385 static bool dcn401_check_native_scaling(struct pipe_ctx *pipe)
386 {
387 	bool is_native_scaling = false;
388 	int width = pipe->plane_state->src_rect.width;
389 	int height = pipe->plane_state->src_rect.height;
390 
391 	if (pipe->stream->timing.h_addressable == width &&
392 			pipe->stream->timing.v_addressable == height &&
393 			pipe->plane_state->dst_rect.width == width &&
394 			pipe->plane_state->dst_rect.height == height)
395 		is_native_scaling = true;
396 
397 	return is_native_scaling;
398 }
399 
dcn401_auto_dpm_test_log(struct dc_clocks * new_clocks,struct clk_mgr_internal * clk_mgr,struct dc_state * context)400 static void dcn401_auto_dpm_test_log(
401 		struct dc_clocks *new_clocks,
402 		struct clk_mgr_internal *clk_mgr,
403 		struct dc_state *context)
404 {
405 	unsigned int mall_ss_size_bytes;
406 	int dramclk_khz_override, fclk_khz_override, num_fclk_levels;
407 
408 	struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
409 	int active_pipe_count = 0;
410 
411 	for (int i = 0; i < MAX_PIPES; i++) {
412 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
413 
414 		if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
415 			pipe_ctx_list[active_pipe_count] = pipe_ctx;
416 			active_pipe_count++;
417 		}
418 	}
419 
420 	msleep(5);
421 
422 	mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;
423 
424 	struct clk_log_info log_info = {0};
425 	struct clk_state_registers_and_bypass clk_register_dump;
426 
427 	dcn401_dump_clk_registers(&clk_register_dump, &clk_mgr->base, &log_info);
428 
429 	// Overrides for these clocks in case there is no p_state change support
430 	dramclk_khz_override = new_clocks->dramclk_khz;
431 	fclk_khz_override = new_clocks->fclk_khz;
432 
433 	num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
434 
435 	if (!new_clocks->p_state_change_support)
436 		dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
437 
438 	if (!new_clocks->fclk_p_state_change_support)
439 		fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
440 
441 
442 	////////////////////////////////////////////////////////////////////////////
443 	//	IMPORTANT: 	When adding more clocks to these logs, do NOT put a newline
444 	//	 			anywhere other than at the very end of the string.
445 	//
446 	//	Formatting example (make sure to have " - " between each entry):
447 	//
448 	//				AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
449 	////////////////////////////////////////////////////////////////////////////
450 	if (active_pipe_count > 0 &&
451 		new_clocks->dramclk_khz > 0 &&
452 		new_clocks->fclk_khz > 0 &&
453 		new_clocks->dcfclk_khz > 0 &&
454 		new_clocks->dppclk_khz > 0) {
455 
456 		uint32_t pix_clk_list[MAX_PIPES] = {0};
457 		int p_state_list[MAX_PIPES] = {0};
458 		int disp_src_width_list[MAX_PIPES] = {0};
459 		int disp_src_height_list[MAX_PIPES] = {0};
460 		uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
461 		bool is_scaled_list[MAX_PIPES] = {0};
462 
463 		for (int i = 0; i < active_pipe_count; i++) {
464 			struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];
465 			uint64_t refresh_rate;
466 
467 			pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
468 			p_state_list[i] = curr_pipe_ctx->p_state_type;
469 
470 			refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
471 				curr_pipe_ctx->stream->timing.v_total
472 				* (uint64_t) curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
473 			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
474 			refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
475 			disp_src_refresh_list[i] = refresh_rate;
476 
477 			if (curr_pipe_ctx->plane_state) {
478 				is_scaled_list[i] = !(dcn401_check_native_scaling(curr_pipe_ctx));
479 				disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;
480 				disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;
481 			}
482 		}
483 
484 		DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
485 			"dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
486 			"dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
487 			"dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "
488 			"pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "
489 			"p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "
490 			"pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "
491 			"pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "
492 			"pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "
493 			"pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",
494 			dramclk_khz_override,
495 			fclk_khz_override,
496 			new_clocks->dcfclk_khz,
497 			new_clocks->dppclk_khz,
498 			clk_register_dump.dispclk,
499 			clk_register_dump.dppclk,
500 			clk_register_dump.dprefclk,
501 			clk_register_dump.dcfclk,
502 			clk_register_dump.dtbclk,
503 			clk_register_dump.fclk,
504 			pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],
505 			mall_ss_size_bytes,
506 			p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],
507 			disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],
508 			disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],
509 			disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],
510 			disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);
511 	}
512 }
513 
dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)514 static void dcn401_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
515 			struct dc_state *context,
516 			int ref_dtbclk_khz)
517 {
518 	int i;
519 	struct dccg *dccg = clk_mgr->dccg;
520 	struct pipe_ctx *otg_master;
521 	bool use_hpo_encoder;
522 
523 
524 	for (i = 0; i < context->stream_count; i++) {
525 		otg_master = resource_get_otg_master_for_stream(
526 				&context->res_ctx, context->streams[i]);
527 		ASSERT(otg_master);
528 		ASSERT(otg_master->clock_source);
529 		ASSERT(otg_master->clock_source->funcs->program_pix_clk);
530 		ASSERT(otg_master->stream_res.pix_clk_params.controller_id >= CONTROLLER_ID_D0);
531 
532 		use_hpo_encoder = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(otg_master);
533 		if (!use_hpo_encoder)
534 			continue;
535 
536 		if (otg_master->stream_res.pix_clk_params.controller_id > CONTROLLER_ID_UNDEFINED)
537 			otg_master->clock_source->funcs->program_pix_clk(
538 				otg_master->clock_source,
539 				&otg_master->stream_res.pix_clk_params,
540 				dccg->ctx->dc->link_srv->dp_get_encoding_format(
541 					&otg_master->link_config.dp_link_settings),
542 				&otg_master->pll_settings);
543 	}
544 }
545 
dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower,int ref_dppclk_khz)546 static void dcn401_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
547 		struct dc_state *context, bool safe_to_lower, int ref_dppclk_khz)
548 {
549 	int i;
550 
551 	clk_mgr->dccg->ref_dppclk = ref_dppclk_khz;
552 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
553 		int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
554 
555 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
556 
557 		if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
558 			dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
559 		else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
560 			/* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
561 			 * In this case just continue in loop
562 			 */
563 			continue;
564 		} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
565 			/* The software state is not valid if dpp resource is NULL and
566 			 * dppclk_khz > 0.
567 			 */
568 			ASSERT(false);
569 			continue;
570 		}
571 
572 		prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
573 
574 		if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
575 			clk_mgr->dccg->funcs->update_dpp_dto(
576 							clk_mgr->dccg, dpp_inst, dppclk_khz);
577 	}
578 }
579 
dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,int requested_clk_khz)580 static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, int requested_clk_khz)
581 {
582 	if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, clk))
583 		return 0;
584 
585 	/*
586 	 * SMU set hard min interface takes requested clock in mhz and return
587 	 * actual clock configured in khz. If we floor requested clk to mhz,
588 	 * there is a chance that the actual clock configured in khz is less
589 	 * than requested. If we ceil it to mhz, there is a chance that it
590 	 * unnecessarily dumps up to a higher dpm level, which burns more power.
591 	 * The solution is to set by flooring it to mhz first. If the actual
592 	 * clock returned is less than requested, then we will ceil the
593 	 * requested value to mhz and call it again.
594 	 */
595 	int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
596 
597 	if (actual_clk_khz < requested_clk_khz)
598 		actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
599 
600 	return actual_clk_khz;
601 }
602 
dcn401_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)603 static void dcn401_update_clocks_update_dentist(
604 		struct clk_mgr_internal *clk_mgr,
605 		struct dc_state *context)
606 {
607 	uint32_t new_disp_divider = 0;
608 	uint32_t new_dispclk_wdivider = 0;
609 	uint32_t dentist_dispclk_wdivider_readback = 0;
610 	struct dc *dc = clk_mgr->base.ctx->dc;
611 
612 	if (clk_mgr->base.clks.dispclk_khz == 0)
613 		return;
614 
615 	new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
616 			* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
617 
618 	new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
619 
620 	if (dc->debug.override_dispclk_programming) {
621 		REG_GET(DENTIST_DISPCLK_CNTL,
622 				DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
623 
624 		if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
625 			REG_UPDATE(DENTIST_DISPCLK_CNTL,
626 					DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
627 			REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
628 		}
629 	}
630 
631 }
632 
dcn401_execute_block_sequence(struct clk_mgr * clk_mgr_base,unsigned int num_steps)633 static void dcn401_execute_block_sequence(struct clk_mgr *clk_mgr_base, unsigned int num_steps)
634 {
635 	struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
636 	struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
637 
638 	unsigned int i;
639 	union dcn401_clk_mgr_block_sequence_params *params;
640 
641 	/* execute sequence */
642 	for (i = 0; i < num_steps; i++) {
643 		params = &clk_mgr401->block_sequence[i].params;
644 
645 		switch (clk_mgr401->block_sequence[i].func) {
646 		case CLK_MGR401_READ_CLOCKS_FROM_DENTIST:
647 			dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
648 			break;
649 		case CLK_MGR401_UPDATE_NUM_DISPLAYS:
650 			dcn401_smu_set_num_of_displays(clk_mgr_internal,
651 					params->update_num_displays_params.num_displays);
652 			break;
653 		case CLK_MGR401_UPDATE_HARDMIN_PPCLK:
654 			if (params->update_hardmin_params.response)
655 				*params->update_hardmin_params.response = dcn401_smu_set_hard_min_by_freq(
656 						clk_mgr_internal,
657 						params->update_hardmin_params.ppclk,
658 						params->update_hardmin_params.freq_mhz);
659 			else
660 				dcn401_smu_set_hard_min_by_freq(clk_mgr_internal,
661 						params->update_hardmin_params.ppclk,
662 						params->update_hardmin_params.freq_mhz);
663 			break;
664 		case CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED:
665 			if (params->update_hardmin_optimized_params.response)
666 				*params->update_hardmin_optimized_params.response = dcn401_set_hard_min_by_freq_optimized(
667 						clk_mgr_internal,
668 						params->update_hardmin_optimized_params.ppclk,
669 						params->update_hardmin_optimized_params.freq_khz);
670 			else
671 				dcn401_set_hard_min_by_freq_optimized(clk_mgr_internal,
672 						params->update_hardmin_optimized_params.ppclk,
673 						params->update_hardmin_optimized_params.freq_khz);
674 			break;
675 		case CLK_MGR401_UPDATE_ACTIVE_HARDMINS:
676 			dcn401_smu_set_active_uclk_fclk_hardmin(
677 					clk_mgr_internal,
678 					params->update_idle_hardmin_params.uclk_mhz,
679 					params->update_idle_hardmin_params.fclk_mhz);
680 			break;
681 		case CLK_MGR401_UPDATE_IDLE_HARDMINS:
682 			dcn401_smu_set_idle_uclk_fclk_hardmin(
683 					clk_mgr_internal,
684 					params->update_idle_hardmin_params.uclk_mhz,
685 					params->update_idle_hardmin_params.fclk_mhz);
686 			break;
687 		case CLK_MGR401_UPDATE_SUBVP_HARDMINS:
688 			dcn401_smu_set_subvp_uclk_fclk_hardmin(
689 					clk_mgr_internal,
690 					params->update_idle_hardmin_params.uclk_mhz,
691 					params->update_idle_hardmin_params.fclk_mhz);
692 			break;
693 		case CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK:
694 			dcn401_smu_set_min_deep_sleep_dcef_clk(
695 					clk_mgr_internal,
696 					params->update_deep_sleep_dcfclk_params.freq_mhz);
697 			break;
698 		case CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT:
699 			dcn401_smu_send_fclk_pstate_message(
700 					clk_mgr_internal,
701 					params->update_pstate_support_params.support);
702 			break;
703 		case CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT:
704 			dcn401_smu_send_uclk_pstate_message(
705 					clk_mgr_internal,
706 					params->update_pstate_support_params.support);
707 			break;
708 		case CLK_MGR401_UPDATE_CAB_FOR_UCLK:
709 			dcn401_smu_send_cab_for_uclk_message(
710 				clk_mgr_internal,
711 				params->update_cab_for_uclk_params.num_ways);
712 			break;
713 		case CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK:
714 			dcn401_smu_wait_for_dmub_ack_mclk(
715 					clk_mgr_internal,
716 					params->update_wait_for_dmub_ack_params.enable);
717 			break;
718 		case CLK_MGR401_INDICATE_DRR_STATUS:
719 			dcn401_smu_indicate_drr_status(
720 					clk_mgr_internal,
721 					params->indicate_drr_status_params.mod_drr_for_pstate);
722 			break;
723 		case CLK_MGR401_UPDATE_DPPCLK_DTO:
724 			dcn401_update_clocks_update_dpp_dto(
725 					clk_mgr_internal,
726 					params->update_dppclk_dto_params.context,
727 					params->update_dppclk_dto_params.safe_to_lower,
728 					*params->update_dppclk_dto_params.ref_dppclk_khz);
729 			break;
730 		case CLK_MGR401_UPDATE_DTBCLK_DTO:
731 			dcn401_update_clocks_update_dtb_dto(
732 					clk_mgr_internal,
733 					params->update_dtbclk_dto_params.context,
734 					*params->update_dtbclk_dto_params.ref_dtbclk_khz);
735 			break;
736 		case CLK_MGR401_UPDATE_DENTIST:
737 			dcn401_update_clocks_update_dentist(
738 					clk_mgr_internal,
739 					params->update_dentist_params.context);
740 			break;
741 		case CLK_MGR401_UPDATE_PSR_WAIT_LOOP:
742 			params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(
743 					params->update_psr_wait_loop_params.dmcu,
744 					params->update_psr_wait_loop_params.wait);
745 			break;
746 		default:
747 			/* this should never happen */
748 			BREAK_TO_DEBUGGER();
749 			break;
750 		}
751 	}
752 }
753 
dcn401_build_update_bandwidth_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)754 static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
755 		struct clk_mgr *clk_mgr_base,
756 		struct dc_state *context,
757 		struct dc_clocks *new_clocks,
758 		bool safe_to_lower)
759 {
760 	struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
761 	struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
762 	struct dc *dc = clk_mgr_base->ctx->dc;
763 	struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
764 	bool enter_display_off = false;
765 	bool update_active_fclk = false;
766 	bool update_active_uclk = false;
767 	bool update_idle_fclk = false;
768 	bool update_idle_uclk = false;
769 	bool update_subvp_prefetch_dramclk = false;
770 	bool update_subvp_prefetch_fclk = false;
771 	bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
772 			dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK) &&
773 			dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) &&
774 			dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_FCLK);
775 	bool is_df_throttle_opt_enabled = is_idle_dpm_enabled &&
776 		dcn401_is_df_throttle_opt_enabled(clk_mgr_internal);
777 	int total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
778 	int active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
779 	int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
780 	int idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
781 	int idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
782 	int subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_dramclk_khz);
783 	int subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_fclk_khz);
784 
785 	unsigned int num_steps = 0;
786 
787 	int display_count;
788 	bool fclk_p_state_change_support, uclk_p_state_change_support;
789 
790 	/* CLK_MGR401_UPDATE_NUM_DISPLAYS */
791 	if (clk_mgr_internal->smu_present) {
792 		display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
793 
794 		if (display_count == 0)
795 			enter_display_off = true;
796 
797 		if (enter_display_off == safe_to_lower) {
798 			block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count;
799 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS;
800 			num_steps++;
801 		}
802 	}
803 
804 	/* CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT */
805 	clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
806 	fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
807 	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
808 		clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
809 		update_active_fclk = true;
810 		update_idle_fclk = true;
811 
812 		/* To enable FCLK P-state switching, send PSTATE_SUPPORTED message to PMFW (message not supported on DCN401)*/
813 		// if (clk_mgr_base->clks.fclk_p_state_change_support) {
814 		// 	/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
815 		// 	if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
816 		// 		block_sequence[num_steps].params.update_pstate_support_params.support = true;
817 		// 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
818 		// 		num_steps++;
819 		// 	}
820 		// }
821 	}
822 
823 	if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
824 		/* when P-State switching disabled, set UCLK min = max */
825 		idle_fclk_mhz =
826 				clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1].fclk_mhz;
827 		active_fclk_mhz = idle_fclk_mhz;
828 	}
829 
830 	/* UPDATE DCFCLK */
831 	if (dc->debug.force_min_dcfclk_mhz > 0)
832 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
833 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
834 
835 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
836 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
837 		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
838 			block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
839 			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
840 			block_sequence[num_steps].params.update_hardmin_params.response = NULL;
841 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
842 			num_steps++;
843 		}
844 	}
845 
846 	/* CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK */
847 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
848 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
849 		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
850 			block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
851 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
852 			num_steps++;
853 		}
854 	}
855 
856 	/* SOCCLK */
857 	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
858 		/* We don't actually care about socclk, don't notify SMU of hard min */
859 		clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
860 
861 	/* UCLK */
862 	if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
863 			new_clocks->fw_based_mclk_switching) {
864 		/* enable FAMS features */
865 		clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
866 
867 		block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
868 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
869 		num_steps++;
870 
871 		block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
872 		block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
873 		num_steps++;
874 	}
875 
876 	/* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
877 	clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
878 	if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
879 			clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
880 		/* increase num ways for subvp */
881 		clk_mgr_base->clks.num_ways = new_clocks->num_ways;
882 		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
883 			block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
884 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
885 			num_steps++;
886 		}
887 	}
888 
889 	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
890 	uclk_p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
891 	if (should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support)) {
892 		clk_mgr_base->clks.p_state_change_support = uclk_p_state_change_support;
893 		update_active_uclk = true;
894 		update_idle_uclk = true;
895 
896 		if (clk_mgr_base->clks.p_state_change_support) {
897 			/* enable UCLK switching  */
898 			if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
899 				block_sequence[num_steps].params.update_pstate_support_params.support = true;
900 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
901 				num_steps++;
902 			}
903 		}
904 	}
905 
906 	if (!clk_mgr_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
907 		/* when P-State switching disabled, set UCLK min = max */
908 		if (dc->clk_mgr->dc_mode_softmax_enabled) {
909 			/* will never have the functional UCLK min above the softmax
910 			* since we calculate mode support based on softmax being the max UCLK
911 			* frequency.
912 			*/
913 			active_uclk_mhz = clk_mgr_base->bw_params->dc_mode_softmax_memclk;
914 		} else {
915 			active_uclk_mhz = clk_mgr_base->bw_params->max_memclk_mhz;
916 		}
917 		idle_uclk_mhz = active_uclk_mhz;
918 	}
919 
920 	/* Always update saved value, even if new value not set due to P-State switching unsupported */
921 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
922 		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
923 
924 		if (clk_mgr_base->clks.p_state_change_support) {
925 			update_active_uclk = true;
926 			active_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz);
927 		}
928 	}
929 
930 	if (should_set_clock(safe_to_lower, new_clocks->idle_dramclk_khz, clk_mgr_base->clks.idle_dramclk_khz)) {
931 		clk_mgr_base->clks.idle_dramclk_khz = new_clocks->idle_dramclk_khz;
932 
933 		if (clk_mgr_base->clks.p_state_change_support) {
934 			update_idle_uclk = true;
935 			idle_uclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_dramclk_khz);
936 		}
937 	}
938 
939 	if (should_set_clock(safe_to_lower, new_clocks->subvp_prefetch_dramclk_khz, clk_mgr_base->clks.subvp_prefetch_dramclk_khz)) {
940 		clk_mgr_base->clks.subvp_prefetch_dramclk_khz = new_clocks->subvp_prefetch_dramclk_khz;
941 		update_subvp_prefetch_dramclk = true;
942 		subvp_prefetch_dramclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_dramclk_khz);
943 	}
944 
945 	/* FCLK */
946 	/* Always update saved value, even if new value not set due to P-State switching unsupported */
947 	if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
948 		clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
949 
950 		if (clk_mgr_base->clks.fclk_p_state_change_support) {
951 			update_active_fclk = true;
952 			active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz);
953 		}
954 	}
955 
956 	if (should_set_clock(safe_to_lower, new_clocks->idle_fclk_khz, clk_mgr_base->clks.idle_fclk_khz)) {
957 		clk_mgr_base->clks.idle_fclk_khz = new_clocks->idle_fclk_khz;
958 
959 		if (clk_mgr_base->clks.fclk_p_state_change_support) {
960 			update_idle_fclk = true;
961 			idle_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.idle_fclk_khz);
962 		}
963 	}
964 
965 	if (should_set_clock(safe_to_lower, new_clocks->subvp_prefetch_fclk_khz, clk_mgr_base->clks.subvp_prefetch_fclk_khz)) {
966 		clk_mgr_base->clks.subvp_prefetch_fclk_khz = new_clocks->subvp_prefetch_fclk_khz;
967 		update_subvp_prefetch_fclk = true;
968 		subvp_prefetch_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.subvp_prefetch_fclk_khz);
969 	}
970 
971 	/* When idle DPM is enabled, need to send active and idle hardmins separately */
972 	/* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
973 	if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
974 		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
975 		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
976 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
977 		num_steps++;
978 	}
979 
980 	/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
981 	if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
982 		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
983 		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
984 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
985 		num_steps++;
986 	}
987 
988 	/* CLK_MGR401_UPDATE_SUBVP_HARDMINS */
989 	if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) {
990 		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;
991 		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;
992 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;
993 		num_steps++;
994 	}
995 
996 	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
997 	if (update_active_uclk || update_idle_uclk) {
998 		if (!is_idle_dpm_enabled) {
999 			block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
1000 			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
1001 			block_sequence[num_steps].params.update_hardmin_params.response = NULL;
1002 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1003 			num_steps++;
1004 		}
1005 
1006 		/* disable UCLK P-State support if needed */
1007 		if (!uclk_p_state_change_support &&
1008 				should_update_pstate_support(safe_to_lower, uclk_p_state_change_support, clk_mgr_base->clks.prev_p_state_change_support) &&
1009 				dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1010 			block_sequence[num_steps].params.update_pstate_support_params.support = false;
1011 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_UCLK_PSTATE_SUPPORT;
1012 			num_steps++;
1013 		}
1014 	}
1015 
1016 	/* set FCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
1017 	if (update_active_fclk || update_idle_fclk) {
1018 		/* No need to send active FCLK hardmin, automatically set based on DCFCLK */
1019 		// if (!is_idle_dpm_enabled) {
1020 		// 	block_sequence[*num_steps].update_hardmin_params.clk_mgr = clk_mgr;
1021 		// 	block_sequence[*num_steps].update_hardmin_params.ppclk = PPCLK_FCLK;
1022 		// 	block_sequence[*num_steps].update_hardmin_params.freq_mhz = active_fclk_mhz;
1023 		// 	block_sequence[*num_steps].update_hardmin_params.response = NULL;
1024 		// 	block_sequence[*num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1025 		// 	(*num_steps)++;
1026 		// }
1027 
1028 		/* disable FCLK P-State support if needed (message not supported on DCN401)*/
1029 		// if (!fclk_p_state_change_support &&
1030 		// 		should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_prev_p_state_change_support) &&
1031 		// 		dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_FCLK)) {
1032 		// 	block_sequence[num_steps].params.update_pstate_support_params.support = false;
1033 		// 	block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT;
1034 		// 	num_steps++;
1035 		// }
1036 	}
1037 
1038 	if (new_clocks->fw_based_mclk_switching != clk_mgr_base->clks.fw_based_mclk_switching &&
1039 			safe_to_lower && !new_clocks->fw_based_mclk_switching) {
1040 		/* disable FAMS features */
1041 		clk_mgr_base->clks.fw_based_mclk_switching = new_clocks->fw_based_mclk_switching;
1042 
1043 		block_sequence[num_steps].params.update_wait_for_dmub_ack_params.enable = clk_mgr_base->clks.fw_based_mclk_switching;
1044 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_WAIT_FOR_DMUB_ACK;
1045 		num_steps++;
1046 
1047 		block_sequence[num_steps].params.indicate_drr_status_params.mod_drr_for_pstate = clk_mgr_base->clks.fw_based_mclk_switching;
1048 		block_sequence[num_steps].func = CLK_MGR401_INDICATE_DRR_STATUS;
1049 		num_steps++;
1050 	}
1051 
1052 	/* CLK_MGR401_UPDATE_CAB_FOR_UCLK */
1053 	if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
1054 			safe_to_lower && clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
1055 		/* decrease num ways for subvp */
1056 		clk_mgr_base->clks.num_ways = new_clocks->num_ways;
1057 		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) {
1058 			block_sequence[num_steps].params.update_cab_for_uclk_params.num_ways = clk_mgr_base->clks.num_ways;
1059 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_CAB_FOR_UCLK;
1060 			num_steps++;
1061 		}
1062 	}
1063 
1064 	return num_steps;
1065 }
1066 
dcn401_build_update_display_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower)1067 static unsigned int dcn401_build_update_display_clocks_sequence(
1068 		struct clk_mgr *clk_mgr_base,
1069 		struct dc_state *context,
1070 		struct dc_clocks *new_clocks,
1071 		bool safe_to_lower)
1072 {
1073 	struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1074 	struct dcn401_clk_mgr *clk_mgr401 = TO_DCN401_CLK_MGR(clk_mgr_internal);
1075 	struct dc *dc = clk_mgr_base->ctx->dc;
1076 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
1077 	struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence;
1078 	bool force_reset = false;
1079 	bool update_dispclk = false;
1080 	bool update_dppclk = false;
1081 	bool dppclk_lowered = false;
1082 
1083 	unsigned int num_steps = 0;
1084 
1085 	/* CLK_MGR401_READ_CLOCKS_FROM_DENTIST */
1086 	if (clk_mgr_base->clks.dispclk_khz == 0 ||
1087 			(dc->debug.force_clock_mode & 0x1)) {
1088 		/* This is from resume or boot up, if forced_clock cfg option used,
1089 		 * we bypass program dispclk and DPPCLK, but need set them for S3.
1090 		 * Force_clock_mode 0x1:  force reset the clock even it is the same clock
1091 		 * as long as it is in Passive level.
1092 		 */
1093 		force_reset = true;
1094 
1095 		clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk;
1096 		clk_mgr_base->clks.actual_dispclk_khz = clk_mgr_base->clks.dispclk_khz;
1097 
1098 		clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk;
1099 		clk_mgr_base->clks.actual_dppclk_khz = clk_mgr_base->clks.dppclk_khz;
1100 	}
1101 
1102 	/* DTBCLK */
1103 	if (!new_clocks->dtbclk_en && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1104 		new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
1105 	}
1106 
1107 	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
1108 	if (!dc->debug.disable_dtb_ref_clk_switch &&
1109 			should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000) && //TODO these should be ceiled
1110 			dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
1111 		/* DCCG requires KHz precision for DTBCLK */
1112 		block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
1113 		block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
1114 		block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
1115 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
1116 		num_steps++;
1117 
1118 		/* Update DTO in DCCG */
1119 		block_sequence[num_steps].params.update_dtbclk_dto_params.context = context;
1120 		block_sequence[num_steps].params.update_dtbclk_dto_params.ref_dtbclk_khz = &clk_mgr_base->clks.ref_dtbclk_khz;
1121 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_DTBCLK_DTO;
1122 		num_steps++;
1123 	}
1124 
1125 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
1126 		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
1127 			dppclk_lowered = true;
1128 
1129 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
1130 		clk_mgr_base->clks.actual_dppclk_khz = new_clocks->dppclk_khz;
1131 
1132 		update_dppclk = true;
1133 	}
1134 
1135 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
1136 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
1137 
1138 		block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DISPCLK;
1139 		block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dispclk_khz;
1140 		block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dispclk_khz;
1141 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1142 		num_steps++;
1143 
1144 		update_dispclk = true;
1145 	}
1146 
1147 	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
1148 		if (dppclk_lowered) {
1149 			/* if clock is being lowered, increase DTO before lowering refclk */
1150 			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1151 			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.dppclk_khz;
1152 			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1153 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1154 			num_steps++;
1155 
1156 			block_sequence[num_steps].params.update_dentist_params.context = context;
1157 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1158 			num_steps++;
1159 
1160 			if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1161 				block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1162 				block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1163 				block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1164 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1165 				num_steps++;
1166 
1167 				block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1168 				block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1169 				block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1170 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1171 				num_steps++;
1172 			}
1173 		} else {
1174 			/* if clock is being raised, increase refclk before lowering DTO */
1175 			if (update_dppclk && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DPPCLK)) {
1176 				block_sequence[num_steps].params.update_hardmin_optimized_params.ppclk = PPCLK_DPPCLK;
1177 				block_sequence[num_steps].params.update_hardmin_optimized_params.freq_khz = clk_mgr_base->clks.dppclk_khz;
1178 				block_sequence[num_steps].params.update_hardmin_optimized_params.response = &clk_mgr_base->clks.actual_dppclk_khz;
1179 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK_OPTIMIZED;
1180 				num_steps++;
1181 			}
1182 
1183 			if (update_dppclk || update_dispclk) {
1184 				block_sequence[num_steps].params.update_dentist_params.context = context;
1185 				block_sequence[num_steps].func = CLK_MGR401_UPDATE_DENTIST;
1186 				num_steps++;
1187 			}
1188 
1189 			block_sequence[num_steps].params.update_dppclk_dto_params.context = context;
1190 			block_sequence[num_steps].params.update_dppclk_dto_params.ref_dppclk_khz = &clk_mgr_base->clks.actual_dppclk_khz;
1191 			block_sequence[num_steps].params.update_dppclk_dto_params.safe_to_lower = safe_to_lower;
1192 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DPPCLK_DTO;
1193 			num_steps++;
1194 		}
1195 	}
1196 
1197 	if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
1198 		/*update dmcu for wait_loop count*/
1199 		block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;
1200 		block_sequence[num_steps].params.update_psr_wait_loop_params.wait = clk_mgr_base->clks.dispclk_khz / 1000 / 7;
1201 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_PSR_WAIT_LOOP;
1202 		num_steps++;
1203 	}
1204 
1205 	return num_steps;
1206 }
1207 
dcn401_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)1208 static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base,
1209 		struct dc_state *context,
1210 		bool safe_to_lower)
1211 {
1212 	struct dc *dc = clk_mgr_base->ctx->dc;
1213 
1214 	unsigned int num_steps = 0;
1215 
1216 	/* build bandwidth related clocks update sequence */
1217 	num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1218 			context,
1219 			&context->bw_ctx.bw.dcn.clk,
1220 			safe_to_lower);
1221 
1222 	/* execute sequence */
1223 	dcn401_execute_block_sequence(clk_mgr_base,	num_steps);
1224 
1225 	/* build display related clocks update sequence */
1226 	num_steps = dcn401_build_update_display_clocks_sequence(clk_mgr_base,
1227 			context,
1228 			&context->bw_ctx.bw.dcn.clk,
1229 			safe_to_lower);
1230 
1231 	/* execute sequence */
1232 	dcn401_execute_block_sequence(clk_mgr_base,	num_steps);
1233 
1234 	if (dc->config.enable_auto_dpm_test_logs)
1235 		dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context);
1236 
1237 }
1238 
1239 
dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)1240 static uint32_t dcn401_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
1241 {
1242 		struct fixed31_32 pll_req;
1243 		uint32_t pll_req_reg = 0;
1244 
1245 		/* get FbMult value */
1246 		pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
1247 
1248 		/* set up a fixed-point number
1249 		 * this works because the int part is on the right edge of the register
1250 		 * and the frac part is on the left edge
1251 		 */
1252 		pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
1253 		pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
1254 
1255 		/* multiply by REFCLK period */
1256 		pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
1257 
1258 		return dc_fixpt_floor(pll_req);
1259 }
1260 
dcn401_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)1261 static void dcn401_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
1262 {
1263 	struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
1264 	int ss_info_num = bp->funcs->get_ss_entry_number(
1265 			bp, AS_SIGNAL_TYPE_GPU_PLL);
1266 
1267 	if (ss_info_num) {
1268 		struct spread_spectrum_info info = { { 0 } };
1269 		enum bp_result result = bp->funcs->get_spread_spectrum_info(
1270 				bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
1271 
1272 		/* SSInfo.spreadSpectrumPercentage !=0 would be sign
1273 		 * that SS is enabled
1274 		 */
1275 		if (result == BP_RESULT_OK &&
1276 				info.spread_spectrum_percentage != 0) {
1277 			clk_mgr->ss_on_dprefclk = true;
1278 			clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
1279 
1280 			if (info.type.CENTER_MODE == 0) {
1281 				/* Currently for DP Reference clock we
1282 				 * need only SS percentage for
1283 				 * downspread
1284 				 */
1285 				clk_mgr->dprefclk_ss_percentage =
1286 						info.spread_spectrum_percentage;
1287 			}
1288 		}
1289 	}
1290 }
dcn401_notify_wm_ranges(struct clk_mgr * clk_mgr_base)1291 static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
1292 {
1293 	unsigned int i;
1294 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1295 	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
1296 
1297 	if (!clk_mgr->smu_present)
1298 		return;
1299 
1300 	if (!table)
1301 		return;
1302 
1303 	memset(table, 0, sizeof(*table));
1304 
1305 	/* collect valid ranges, place in pmfw table */
1306 	for (i = 0; i < WM_SET_COUNT; i++)
1307 		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
1308 			table->Watermarks.WatermarkRow[i].WmSetting = i;
1309 			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
1310 		}
1311 	dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
1312 	dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
1313 	dcn401_smu_transfer_wm_table_dram_2_smu(clk_mgr);
1314 }
1315 
1316 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn401_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)1317 static void dcn401_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
1318 {
1319 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1320 	const struct dc *dc = clk_mgr->base.ctx->dc;
1321 	struct dc_state *context = dc->current_state;
1322 	struct dc_clocks new_clocks;
1323 	int num_steps;
1324 
1325 	if (!clk_mgr->smu_present || !dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_UCLK))
1326 		return;
1327 
1328 	/* build clock update */
1329 	memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
1330 
1331 	if (current_mode) {
1332 		new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz;
1333 		new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz;
1334 		new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support;
1335 	} else {
1336 		new_clocks.dramclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz * 1000;
1337 		new_clocks.idle_dramclk_khz = new_clocks.dramclk_khz;
1338 		new_clocks.p_state_change_support = true;
1339 	}
1340 
1341 	num_steps = dcn401_build_update_bandwidth_clocks_sequence(clk_mgr_base,
1342 			context,
1343 			&new_clocks,
1344 			true);
1345 
1346 	/* execute sequence */
1347 	dcn401_execute_block_sequence(clk_mgr_base,	num_steps);
1348 }
1349 
dcn401_get_hard_min_memclk(struct clk_mgr * clk_mgr_base)1350 static int dcn401_get_hard_min_memclk(struct clk_mgr *clk_mgr_base)
1351 {
1352 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1353 
1354 	return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.dramclk_khz;
1355 }
1356 
dcn401_get_hard_min_fclk(struct clk_mgr * clk_mgr_base)1357 static int dcn401_get_hard_min_fclk(struct clk_mgr *clk_mgr_base)
1358 {
1359 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1360 
1361 	return clk_mgr->base.ctx->dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz;
1362 }
1363 
1364 /* Get current memclk states, update bounding box */
dcn401_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)1365 static void dcn401_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
1366 {
1367 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1368 	struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
1369 	unsigned int num_levels;
1370 
1371 	if (!clk_mgr->smu_present)
1372 		return;
1373 
1374 	/* Refresh memclk and fclk states */
1375 	dcn401_init_single_clock(clk_mgr, PPCLK_UCLK,
1376 			&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
1377 			&num_entries_per_clk->num_memclk_levels);
1378 	if (num_entries_per_clk->num_memclk_levels) {
1379 		clk_mgr_base->bw_params->max_memclk_mhz =
1380 				clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1381 	}
1382 
1383 	clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1384 	if (num_entries_per_clk->num_memclk_levels && clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz ==
1385 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz)
1386 		clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = 0;
1387 	clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
1388 
1389 	dcn401_init_single_clock(clk_mgr, PPCLK_FCLK,
1390 			&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
1391 			&num_entries_per_clk->num_fclk_levels);
1392 	clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1393 	if (num_entries_per_clk->num_fclk_levels && clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz ==
1394 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_fclk_levels - 1].fclk_mhz)
1395 		clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = 0;
1396 
1397 	if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
1398 		num_levels = num_entries_per_clk->num_memclk_levels;
1399 	} else {
1400 		num_levels = num_entries_per_clk->num_fclk_levels;
1401 	}
1402 
1403 	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1404 
1405 	if (clk_mgr->dpm_present && !num_levels)
1406 		clk_mgr->dpm_present = false;
1407 
1408 	clk_mgr_base->bw_params->num_channels = dcn401_smu_get_num_of_umc_channels(clk_mgr);
1409 	if (clk_mgr_base->ctx->dc_bios) {
1410 		/* use BIOS values if none provided by PMFW */
1411 		if (clk_mgr_base->bw_params->num_channels == 0) {
1412 			clk_mgr_base->bw_params->num_channels = clk_mgr_base->ctx->dc_bios->vram_info.num_chans;
1413 		}
1414 		clk_mgr_base->bw_params->dram_channel_width_bytes = clk_mgr_base->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1415 	}
1416 
1417 	/* Refresh bounding box */
1418 	clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1419 			clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1420 }
1421 
dcn401_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)1422 static bool dcn401_are_clock_states_equal(struct dc_clocks *a,
1423 					struct dc_clocks *b)
1424 {
1425 	if (a->dispclk_khz != b->dispclk_khz)
1426 		return false;
1427 	else if (a->dppclk_khz != b->dppclk_khz)
1428 		return false;
1429 	else if (a->dcfclk_khz != b->dcfclk_khz)
1430 		return false;
1431 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
1432 		return false;
1433 	else if (a->dramclk_khz != b->dramclk_khz)
1434 		return false;
1435 	else if (a->p_state_change_support != b->p_state_change_support)
1436 		return false;
1437 	else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
1438 		return false;
1439 
1440 	return true;
1441 }
1442 
dcn401_enable_pme_wa(struct clk_mgr * clk_mgr_base)1443 static void dcn401_enable_pme_wa(struct clk_mgr *clk_mgr_base)
1444 {
1445 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1446 
1447 	if (!clk_mgr->smu_present)
1448 		return;
1449 
1450 	dcn401_smu_set_pme_workaround(clk_mgr);
1451 }
1452 
dcn401_is_smu_present(struct clk_mgr * clk_mgr_base)1453 static bool dcn401_is_smu_present(struct clk_mgr *clk_mgr_base)
1454 {
1455 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1456 	return clk_mgr->smu_present;
1457 }
1458 
1459 
dcn401_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)1460 static int dcn401_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
1461 {
1462 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1463 
1464 	int dtb_ref_clk_khz = 0;
1465 
1466 	if (clk_mgr->smu_present && dcn401_is_ppclk_dpm_enabled(clk_mgr, PPCLK_DTBCLK)) {
1467 		/* DPM enabled, use currently set value */
1468 		dtb_ref_clk_khz = clk_mgr_base->clks.ref_dtbclk_khz;
1469 	} else {
1470 		/* DPM disabled, so use boot snapshot */
1471 		dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk;
1472 	}
1473 
1474 	return dtb_ref_clk_khz;
1475 }
1476 
dcn401_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)1477 static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
1478 {
1479 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1480 	uint32_t dispclk_wdivider;
1481 	int disp_divider;
1482 
1483 	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
1484 	disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
1485 
1486 	/* Return DISPCLK freq in Khz */
1487 	if (disp_divider)
1488 		return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
1489 
1490 	return 0;
1491 }
1492 
1493 static struct clk_mgr_funcs dcn401_funcs = {
1494 		.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1495 		.get_dtb_ref_clk_frequency = dcn401_get_dtb_ref_freq_khz,
1496 		.update_clocks = dcn401_update_clocks,
1497 		.dump_clk_registers = dcn401_dump_clk_registers,
1498 		.init_clocks = dcn401_init_clocks,
1499 		.notify_wm_ranges = dcn401_notify_wm_ranges,
1500 		.set_hard_min_memclk = dcn401_set_hard_min_memclk,
1501 		.get_memclk_states_from_smu = dcn401_get_memclk_states_from_smu,
1502 		.are_clock_states_equal = dcn401_are_clock_states_equal,
1503 		.enable_pme_wa = dcn401_enable_pme_wa,
1504 		.is_smu_present = dcn401_is_smu_present,
1505 		.get_dispclk_from_dentist = dcn401_get_dispclk_from_dentist,
1506 		.get_hard_min_memclk = dcn401_get_hard_min_memclk,
1507 		.get_hard_min_fclk = dcn401_get_hard_min_fclk,
1508 };
1509 
dcn401_clk_mgr_construct(struct dc_context * ctx,struct dccg * dccg)1510 struct clk_mgr_internal *dcn401_clk_mgr_construct(
1511 		struct dc_context *ctx,
1512 		struct dccg *dccg)
1513 {
1514 	struct clk_log_info log_info = {0};
1515 	struct dcn401_clk_mgr *clk_mgr401 = kzalloc(sizeof(struct dcn401_clk_mgr), GFP_KERNEL);
1516 	struct clk_mgr_internal *clk_mgr;
1517 
1518 	if (!clk_mgr401)
1519 		return NULL;
1520 
1521 	clk_mgr = &clk_mgr401->base;
1522 	clk_mgr->base.ctx = ctx;
1523 	clk_mgr->base.funcs = &dcn401_funcs;
1524 	clk_mgr->regs = &clk_mgr_regs_dcn401;
1525 	clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn401;
1526 	clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn401;
1527 
1528 	clk_mgr->dccg = dccg;
1529 	clk_mgr->dfs_bypass_disp_clk = 0;
1530 
1531 	clk_mgr->dprefclk_ss_percentage = 0;
1532 	clk_mgr->dprefclk_ss_divider = 1000;
1533 	clk_mgr->ss_on_dprefclk = false;
1534 	clk_mgr->dfs_ref_freq_khz = 100000;
1535 
1536 	/* Changed from DCN3.2_clock_frequency doc to match
1537 	 * dcn401_dump_clk_registers from 4 * dentist_vco_freq_khz /
1538 	 * dprefclk DID divider
1539 	 */
1540 	clk_mgr->base.dprefclk_khz = 720000; //TODO update from VBIOS
1541 
1542 	/* integer part is now VCO frequency in kHz */
1543 	clk_mgr->base.dentist_vco_freq_khz = dcn401_get_vco_frequency_from_reg(clk_mgr);
1544 
1545 	/* in case we don't get a value from the register, use default */
1546 	if (clk_mgr->base.dentist_vco_freq_khz == 0)
1547 		clk_mgr->base.dentist_vco_freq_khz = 4500000; //TODO Update from VBIOS
1548 
1549 	dcn401_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1550 
1551 	if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1552 			clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1553 		clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1554 	}
1555 
1556 	if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1557 		clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1558 	}
1559 	dcn401_clock_read_ss_info(clk_mgr);
1560 
1561 	clk_mgr->dfs_bypass_enabled = false;
1562 
1563 	clk_mgr->smu_present = false;
1564 
1565 	clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1566 	if (!clk_mgr->base.bw_params) {
1567 		BREAK_TO_DEBUGGER();
1568 		kfree(clk_mgr);
1569 		return NULL;
1570 	}
1571 
1572 	/* need physical address of table to give to PMFW */
1573 	clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1574 			DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1575 			&clk_mgr->wm_range_table_addr);
1576 	if (!clk_mgr->wm_range_table) {
1577 		BREAK_TO_DEBUGGER();
1578 		kfree(clk_mgr->base.bw_params);
1579 		return NULL;
1580 	}
1581 
1582 	return &clk_mgr401->base;
1583 }
1584 
dcn401_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1585 void dcn401_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1586 {
1587 	kfree(clk_mgr->base.bw_params);
1588 
1589 	if (clk_mgr->wm_range_table)
1590 		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1591 				clk_mgr->wm_range_table);
1592 }
1593 
1594