1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33 // For dcn20_update_clocks_update_dpp_dto
34 #include "dcn20/dcn20_clk_mgr.h"
35 #include "dcn31/dcn31_clk_mgr.h"
36 #include "dcn315_clk_mgr.h"
37
38 #include "core_types.h"
39 #include "dcn315_smu.h"
40 #include "dm_helpers.h"
41
42 #include "dc_dmub_srv.h"
43
44 #include "logger_types.h"
45 #undef DC_LOGGER
46 #define DC_LOGGER \
47 clk_mgr->base.base.ctx->logger
48
49 #include "link.h"
50
51 #define TO_CLK_MGR_DCN315(clk_mgr)\
52 container_of(clk_mgr, struct clk_mgr_dcn315, base)
53
54 #define UNSUPPORTED_DCFCLK 10000000
55 #define MIN_DPP_DISP_CLK 100000
56
dcn315_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)57 static int dcn315_get_active_display_cnt_wa(
58 struct dc *dc,
59 struct dc_state *context)
60 {
61 int i, display_count;
62 bool tmds_present = false;
63
64 display_count = 0;
65 for (i = 0; i < context->stream_count; i++) {
66 const struct dc_stream_state *stream = context->streams[i];
67
68 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
69 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
70 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
71 tmds_present = true;
72 }
73
74 for (i = 0; i < dc->link_count; i++) {
75 const struct dc_link *link = dc->links[i];
76
77 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
78 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
79 link->link_enc->funcs->is_dig_enabled(link->link_enc))
80 display_count++;
81 }
82
83 /* WA for hang on HDMI after display off back back on*/
84 if (display_count == 0 && tmds_present)
85 display_count = 1;
86
87 return display_count;
88 }
89
should_disable_otg(struct pipe_ctx * pipe)90 static bool should_disable_otg(struct pipe_ctx *pipe)
91 {
92 bool ret = true;
93
94 if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&
95 pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))
96 ret = false;
97 return ret;
98 }
99
dcn315_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
101 {
102 struct dc *dc = clk_mgr_base->ctx->dc;
103 int i;
104
105 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
106 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
107
108 if (pipe->top_pipe || pipe->prev_odm_pipe)
109 continue;
110 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
111 dc_is_virtual_signal(pipe->stream->signal))) {
112
113 /* This w/a should not trigger when we have a dig active */
114 if (should_disable_otg(pipe)) {
115 if (disable) {
116 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
117 reset_sync_context_for_pipe(dc, context, i);
118 } else
119 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
120 }
121 }
122 }
123 }
124
dcn315_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
126 struct dc_state *context,
127 bool safe_to_lower)
128 {
129 union dmub_rb_cmd cmd;
130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
131 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
132 struct dc *dc = clk_mgr_base->ctx->dc;
133 int display_count = 0;
134 bool update_dppclk = false;
135 bool update_dispclk = false;
136 bool dpp_clock_lowered = false;
137
138 if (dc->work_arounds.skip_clock_update)
139 return;
140
141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
142 /*
143 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
144 * also if safe to lower is false, we just go in the higher state
145 */
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
147 if (safe_to_lower) {
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
149 dcn315_smu_set_dtbclk(clk_mgr, false);
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
151 }
152 /* check that we're not already in lower */
153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
154 display_count = dcn315_get_active_display_cnt_wa(dc, context);
155 /* if we can go lower, go lower */
156 if (display_count == 0) {
157 union display_idle_optimization_u idle_info = { 0 };
158 idle_info.idle_info.df_request_disabled = 1;
159 idle_info.idle_info.phy_ref_clk_off = 1;
160 idle_info.idle_info.s0i2_rdy = 1;
161 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
162 /* update power state */
163 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
164 }
165 }
166 } else {
167 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
168 dcn315_smu_set_dtbclk(clk_mgr, true);
169 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
170 }
171 /* check that we're not already in D0 */
172 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
173 union display_idle_optimization_u idle_info = { 0 };
174 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
175 /* update power state */
176 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
177 }
178 }
179
180 /* Lock pstate by requesting unsupported dcfclk if change is unsupported */
181 if (!new_clocks->p_state_change_support)
182 new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
183 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
184 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
185 dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
186 }
187
188 if (should_set_clock(safe_to_lower,
189 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
190 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
191 dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
192 }
193
194 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
195 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
196 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
197
198 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
199 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
200 dpp_clock_lowered = true;
201 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
202 update_dppclk = true;
203 }
204
205 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
206 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
207 int requested_dispclk_khz = new_clocks->dispclk_khz;
208
209 dcn315_disable_otg_wa(clk_mgr_base, context, true);
210
211 /* Clamp the requested clock to PMFW based on their limit. */
212 if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
213 requested_dispclk_khz = dc->debug.min_disp_clk_khz;
214
215 dcn315_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
216 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
217 dcn315_disable_otg_wa(clk_mgr_base, context, false);
218
219 update_dispclk = true;
220 }
221
222 if (dpp_clock_lowered) {
223 // increase per DPP DTO before lowering global dppclk
224 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
225 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
226 } else {
227 // increase global DPPCLK before lowering per DPP DTO
228 if (update_dppclk || update_dispclk)
229 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
230 // always update dtos unless clock is lowered and not safe to lower
231 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
232 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
233 }
234
235 // notify DMCUB of latest clocks
236 memset(&cmd, 0, sizeof(cmd));
237 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
238 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
239 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
240 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
241 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
242 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
243 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
244
245 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
246 }
247
dcn315_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)248 static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
249 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
250 {
251 return;
252 }
253
254 static struct clk_bw_params dcn315_bw_params = {
255 .vram_type = Ddr4MemType,
256 .num_channels = 2,
257 .clk_table = {
258 .entries = {
259 {
260 .voltage = 0,
261 .dispclk_mhz = 640,
262 .dppclk_mhz = 640,
263 .phyclk_mhz = 810,
264 .phyclk_d18_mhz = 667,
265 .dtbclk_mhz = 600,
266 },
267 {
268 .voltage = 1,
269 .dispclk_mhz = 739,
270 .dppclk_mhz = 739,
271 .phyclk_mhz = 810,
272 .phyclk_d18_mhz = 667,
273 .dtbclk_mhz = 600,
274 },
275 {
276 .voltage = 2,
277 .dispclk_mhz = 960,
278 .dppclk_mhz = 960,
279 .phyclk_mhz = 810,
280 .phyclk_d18_mhz = 667,
281 .dtbclk_mhz = 600,
282 },
283 {
284 .voltage = 3,
285 .dispclk_mhz = 1200,
286 .dppclk_mhz = 1200,
287 .phyclk_mhz = 810,
288 .phyclk_d18_mhz = 667,
289 .dtbclk_mhz = 600,
290 },
291 {
292 .voltage = 4,
293 .dispclk_mhz = 1372,
294 .dppclk_mhz = 1372,
295 .phyclk_mhz = 810,
296 .phyclk_d18_mhz = 667,
297 .dtbclk_mhz = 600,
298 },
299 },
300 .num_entries = 5,
301 },
302
303 };
304
305 static struct wm_table ddr5_wm_table = {
306 .entries = {
307 {
308 .wm_inst = WM_A,
309 .wm_type = WM_TYPE_PSTATE_CHG,
310 .pstate_latency_us = 129.0,
311 .sr_exit_time_us = 11.5,
312 .sr_enter_plus_exit_time_us = 14.5,
313 .valid = true,
314 },
315 {
316 .wm_inst = WM_B,
317 .wm_type = WM_TYPE_PSTATE_CHG,
318 .pstate_latency_us = 129.0,
319 .sr_exit_time_us = 11.5,
320 .sr_enter_plus_exit_time_us = 14.5,
321 .valid = true,
322 },
323 {
324 .wm_inst = WM_C,
325 .wm_type = WM_TYPE_PSTATE_CHG,
326 .pstate_latency_us = 129.0,
327 .sr_exit_time_us = 11.5,
328 .sr_enter_plus_exit_time_us = 14.5,
329 .valid = true,
330 },
331 {
332 .wm_inst = WM_D,
333 .wm_type = WM_TYPE_PSTATE_CHG,
334 .pstate_latency_us = 129.0,
335 .sr_exit_time_us = 11.5,
336 .sr_enter_plus_exit_time_us = 14.5,
337 .valid = true,
338 },
339 }
340 };
341
342 static struct wm_table lpddr5_wm_table = {
343 .entries = {
344 {
345 .wm_inst = WM_A,
346 .wm_type = WM_TYPE_PSTATE_CHG,
347 .pstate_latency_us = 129.0,
348 .sr_exit_time_us = 11.5,
349 .sr_enter_plus_exit_time_us = 14.5,
350 .valid = true,
351 },
352 {
353 .wm_inst = WM_B,
354 .wm_type = WM_TYPE_PSTATE_CHG,
355 .pstate_latency_us = 129.0,
356 .sr_exit_time_us = 11.5,
357 .sr_enter_plus_exit_time_us = 14.5,
358 .valid = true,
359 },
360 {
361 .wm_inst = WM_C,
362 .wm_type = WM_TYPE_PSTATE_CHG,
363 .pstate_latency_us = 129.0,
364 .sr_exit_time_us = 11.5,
365 .sr_enter_plus_exit_time_us = 14.5,
366 .valid = true,
367 },
368 {
369 .wm_inst = WM_D,
370 .wm_type = WM_TYPE_PSTATE_CHG,
371 .pstate_latency_us = 129.0,
372 .sr_exit_time_us = 11.5,
373 .sr_enter_plus_exit_time_us = 14.5,
374 .valid = true,
375 },
376 }
377 };
378
379 /* Temporary Place holder until we can get them from fuse */
380 static DpmClocks_315_t dummy_clocks = { 0 };
381 static struct dcn315_watermarks dummy_wms = { 0 };
382
dcn315_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn315_watermarks * table)383 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
384 {
385 int i, num_valid_sets;
386
387 num_valid_sets = 0;
388
389 for (i = 0; i < WM_SET_COUNT; i++) {
390 /* skip empty entries, the smu array has no holes*/
391 if (!bw_params->wm_table.entries[i].valid)
392 continue;
393
394 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
396 /* We will not select WM based on fclk, so leave it as unconstrained */
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
399
400 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
401 if (i == 0)
402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
403 else {
404 /* add 1 to make it non-overlapping with next lvl */
405 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
406 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
407 }
408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
409 bw_params->clk_table.entries[i].dcfclk_mhz;
410
411 } else {
412 /* unconstrained for memory retraining */
413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
414 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
415
416 /* Modify previous watermark range to cover up to max */
417 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
418 }
419 num_valid_sets++;
420 }
421
422 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
423
424 /* modify the min and max to make sure we cover the whole range*/
425 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
426 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
427 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
428 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
429
430 /* This is for writeback only, does not matter currently as no writeback support*/
431 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
432 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
433 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
434 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
435 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
436 }
437
dcn315_notify_wm_ranges(struct clk_mgr * clk_mgr_base)438 static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
439 {
440 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
441 struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);
442 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
443
444 if (!clk_mgr->smu_ver)
445 return;
446
447 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
448 return;
449
450 memset(table, 0, sizeof(*table));
451
452 dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
453
454 dcn315_smu_set_dram_addr_high(clk_mgr,
455 clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
456 dcn315_smu_set_dram_addr_low(clk_mgr,
457 clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
458 dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);
459 }
460
dcn315_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn315_smu_dpm_clks * smu_dpm_clks)461 static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
462 struct dcn315_smu_dpm_clks *smu_dpm_clks)
463 {
464 DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
465
466 if (!clk_mgr->smu_ver)
467 return;
468
469 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
470 return;
471
472 memset(table, 0, sizeof(*table));
473
474 dcn315_smu_set_dram_addr_high(clk_mgr,
475 smu_dpm_clks->mc_address.high_part);
476 dcn315_smu_set_dram_addr_low(clk_mgr,
477 smu_dpm_clks->mc_address.low_part);
478 dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
479 }
480
dcn315_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_315_t * clock_table)481 static void dcn315_clk_mgr_helper_populate_bw_params(
482 struct clk_mgr_internal *clk_mgr,
483 struct integrated_info *bios_info,
484 const DpmClocks_315_t *clock_table)
485 {
486 int i;
487 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
488 uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;
489 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
490
491 /* For 315 we want to base clock table on dcfclk, need at least one entry regardless of pmfw table */
492 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
493 int j;
494
495 /* DF table is sorted with clocks decreasing */
496 for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) {
497 if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i])
498 max_pstate = j;
499 }
500 /* Max DCFCLK should match up with max pstate */
501 if (i == clock_table->NumDcfClkLevelsEnabled - 1)
502 max_pstate = 0;
503
504 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
505 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
506 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
507 break;
508 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
509 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
510 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
511
512 /* Now update clocks we do read */
513 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk;
514 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
515 bw_params->clk_table.entries[i].voltage = clock_table->SocVoltage[i];
516 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
517 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
518 bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
519 bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
520 bw_params->clk_table.entries[i].wck_ratio = 1;
521 }
522
523 /* Make sure to include at least one entry */
524 if (i == 0) {
525 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[0].FClk;
526 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk;
527 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[0].Voltage;
528 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
529 bw_params->clk_table.entries[i].wck_ratio = 1;
530 i++;
531 } else if (clock_table->NumDcfClkLevelsEnabled != clock_table->NumSocClkLevelsEnabled) {
532 bw_params->clk_table.entries[i-1].voltage = clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
533 bw_params->clk_table.entries[i-1].socclk_mhz = clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
534 bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
535 bw_params->clk_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];
536 }
537 bw_params->clk_table.num_entries = i;
538
539 /* Set any 0 clocks to max default setting. Not an issue for
540 * power since we aren't doing switching in such case anyway
541 */
542 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
543 if (!bw_params->clk_table.entries[i].fclk_mhz) {
544 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
545 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
546 bw_params->clk_table.entries[i].voltage = def_max.voltage;
547 }
548 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
549 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
550 if (!bw_params->clk_table.entries[i].socclk_mhz)
551 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
552 if (!bw_params->clk_table.entries[i].dispclk_mhz)
553 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
554 if (!bw_params->clk_table.entries[i].dppclk_mhz)
555 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
556 if (!bw_params->clk_table.entries[i].phyclk_mhz)
557 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
558 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
559 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
560 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
561 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
562 }
563
564 /* Make sure all highest default clocks are included*/
565 ASSERT(bw_params->clk_table.entries[i-1].phyclk_mhz == def_max.phyclk_mhz);
566 ASSERT(bw_params->clk_table.entries[i-1].phyclk_d18_mhz == def_max.phyclk_d18_mhz);
567 ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz);
568 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
569 bw_params->vram_type = bios_info->memory_type;
570 bw_params->num_channels = bios_info->ma_channel_number;
571 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
572
573 for (i = 0; i < WM_SET_COUNT; i++) {
574 bw_params->wm_table.entries[i].wm_inst = i;
575
576 if (i >= bw_params->clk_table.num_entries) {
577 bw_params->wm_table.entries[i].valid = false;
578 continue;
579 }
580
581 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
582 bw_params->wm_table.entries[i].valid = true;
583 }
584 }
585
dcn315_enable_pme_wa(struct clk_mgr * clk_mgr_base)586 static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)
587 {
588 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
589
590 dcn315_smu_enable_pme_wa(clk_mgr);
591 }
592
593 static struct clk_mgr_funcs dcn315_funcs = {
594 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
595 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
596 .update_clocks = dcn315_update_clocks,
597 .init_clocks = dcn31_init_clocks,
598 .enable_pme_wa = dcn315_enable_pme_wa,
599 .are_clock_states_equal = dcn31_are_clock_states_equal,
600 .notify_wm_ranges = dcn315_notify_wm_ranges
601 };
602 extern struct clk_mgr_funcs dcn3_fpga_funcs;
603
dcn315_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn315 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)604 void dcn315_clk_mgr_construct(
605 struct dc_context *ctx,
606 struct clk_mgr_dcn315 *clk_mgr,
607 struct pp_smu_funcs *pp_smu,
608 struct dccg *dccg)
609 {
610 struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
611 struct clk_log_info log_info = {0};
612
613 clk_mgr->base.base.ctx = ctx;
614 clk_mgr->base.base.funcs = &dcn315_funcs;
615
616 clk_mgr->base.pp_smu = pp_smu;
617
618 clk_mgr->base.dccg = dccg;
619 clk_mgr->base.dfs_bypass_disp_clk = 0;
620
621 clk_mgr->base.dprefclk_ss_percentage = 0;
622 clk_mgr->base.dprefclk_ss_divider = 1000;
623 clk_mgr->base.ss_on_dprefclk = false;
624 clk_mgr->base.dfs_ref_freq_khz = 48000;
625
626 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
627 clk_mgr->base.base.ctx,
628 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
629 sizeof(struct dcn315_watermarks),
630 &clk_mgr->smu_wm_set.mc_address.quad_part);
631
632 if (!clk_mgr->smu_wm_set.wm_set) {
633 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
634 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
635 }
636 ASSERT(clk_mgr->smu_wm_set.wm_set);
637
638 smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
639 clk_mgr->base.base.ctx,
640 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
641 sizeof(DpmClocks_315_t),
642 &smu_dpm_clks.mc_address.quad_part);
643
644 if (smu_dpm_clks.dpm_clks == NULL) {
645 smu_dpm_clks.dpm_clks = &dummy_clocks;
646 smu_dpm_clks.mc_address.quad_part = 0;
647 }
648
649 ASSERT(smu_dpm_clks.dpm_clks);
650
651 clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
652
653 if (clk_mgr->base.smu_ver > 0)
654 clk_mgr->base.smu_present = true;
655
656 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
657 dcn315_bw_params.wm_table = lpddr5_wm_table;
658 } else {
659 dcn315_bw_params.wm_table = ddr5_wm_table;
660 }
661 /* Saved clocks configured at boot for debug purposes */
662 dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
663 &clk_mgr->base.base, &log_info);
664
665 clk_mgr->base.base.dprefclk_khz = 600000;
666 clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
667 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
668 dce_clock_read_ss_info(&clk_mgr->base);
669 clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
670
671 clk_mgr->base.base.bw_params = &dcn315_bw_params;
672
673 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
674 int i;
675
676 dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
677 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
678 "NumDispClkLevelsEnabled: %d\n"
679 "NumSocClkLevelsEnabled: %d\n"
680 "VcnClkLevelsEnabled: %d\n"
681 "NumDfPst atesEnabled: %d\n"
682 "MinGfxClk: %d\n"
683 "MaxGfxClk: %d\n",
684 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
685 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
686 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
687 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
688 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
689 smu_dpm_clks.dpm_clks->MinGfxClk,
690 smu_dpm_clks.dpm_clks->MaxGfxClk);
691 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
692 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
693 i,
694 smu_dpm_clks.dpm_clks->DcfClocks[i]);
695 }
696 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
697 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
698 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
699 }
700 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
701 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
702 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
703 }
704 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
705 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
706 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
707
708 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
709 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
710 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
711 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
712 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
713 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
714 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
715 }
716
717 if (ctx->dc_bios->integrated_info) {
718 dcn315_clk_mgr_helper_populate_bw_params(
719 &clk_mgr->base,
720 ctx->dc_bios->integrated_info,
721 smu_dpm_clks.dpm_clks);
722 }
723 }
724
725 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
726 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
727 smu_dpm_clks.dpm_clks);
728 }
729
dcn315_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)730 void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
731 {
732 struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);
733
734 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
735 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
736 clk_mgr->smu_wm_set.wm_set);
737 }
738