1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28
29 #include "ObjectID.h"
30 #include "atomfirmware.h"
31
32 #include "dc_bios_types.h"
33 #include "include/grph_object_ctrl_defs.h"
34 #include "include/bios_parser_interface.h"
35 #include "include/logger_interface.h"
36
37 #include "command_table2.h"
38
39 #include "bios_parser_helper.h"
40 #include "command_table_helper2.h"
41 #include "bios_parser2.h"
42 #include "bios_parser_types_internal2.h"
43 #include "bios_parser_interface.h"
44
45 #include "bios_parser_common.h"
46
47 #define DC_LOGGER \
48 bp->base.ctx->logger
49
50 #define LAST_RECORD_TYPE 0xff
51 #define SMU9_SYSPLL0_ID 0
52
53 static enum bp_result get_gpio_i2c_info(struct bios_parser *bp,
54 struct atom_i2c_record *record,
55 struct graphics_object_i2c_info *info);
56
57 static enum bp_result bios_parser_get_firmware_info(
58 struct dc_bios *dcb,
59 struct dc_firmware_info *info);
60
61 static enum bp_result bios_parser_get_encoder_cap_info(
62 struct dc_bios *dcb,
63 struct graphics_object_id object_id,
64 struct bp_encoder_cap_info *info);
65
66 static enum bp_result get_firmware_info_v3_1(
67 struct bios_parser *bp,
68 struct dc_firmware_info *info);
69
70 static enum bp_result get_firmware_info_v3_2(
71 struct bios_parser *bp,
72 struct dc_firmware_info *info);
73
74 static enum bp_result get_firmware_info_v3_4(
75 struct bios_parser *bp,
76 struct dc_firmware_info *info);
77
78 static enum bp_result get_firmware_info_v3_5(
79 struct bios_parser *bp,
80 struct dc_firmware_info *info);
81
82 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
83 struct atom_display_object_path_v2 *object);
84
85 static struct atom_encoder_caps_record *get_encoder_cap_record(
86 struct bios_parser *bp,
87 struct atom_display_object_path_v2 *object);
88
89 #define BIOS_IMAGE_SIZE_OFFSET 2
90 #define BIOS_IMAGE_SIZE_UNIT 512
91
92 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
93
bios_parser2_destruct(struct bios_parser * bp)94 static void bios_parser2_destruct(struct bios_parser *bp)
95 {
96 kfree(bp->base.bios_local_image);
97 kfree(bp->base.integrated_info);
98 }
99
firmware_parser_destroy(struct dc_bios ** dcb)100 static void firmware_parser_destroy(struct dc_bios **dcb)
101 {
102 struct bios_parser *bp = BP_FROM_DCB(*dcb);
103
104 if (!bp) {
105 BREAK_TO_DEBUGGER();
106 return;
107 }
108
109 bios_parser2_destruct(bp);
110
111 kfree(bp);
112 *dcb = NULL;
113 }
114
get_atom_data_table_revision(struct atom_common_table_header * atom_data_tbl,struct atom_data_revision * tbl_revision)115 static void get_atom_data_table_revision(
116 struct atom_common_table_header *atom_data_tbl,
117 struct atom_data_revision *tbl_revision)
118 {
119 if (!tbl_revision)
120 return;
121
122 /* initialize the revision to 0 which is invalid revision */
123 tbl_revision->major = 0;
124 tbl_revision->minor = 0;
125
126 if (!atom_data_tbl)
127 return;
128
129 tbl_revision->major =
130 (uint32_t) atom_data_tbl->format_revision & 0x3f;
131 tbl_revision->minor =
132 (uint32_t) atom_data_tbl->content_revision & 0x3f;
133 }
134
135 /* BIOS oject table displaypath is per connector.
136 * There is extra path not for connector. BIOS fill its encoderid as 0
137 */
bios_parser_get_connectors_number(struct dc_bios * dcb)138 static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
139 {
140 struct bios_parser *bp = BP_FROM_DCB(dcb);
141 unsigned int count = 0;
142 unsigned int i;
143
144 switch (bp->object_info_tbl.revision.minor) {
145 default:
146 case 4:
147 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++)
148 if (bp->object_info_tbl.v1_4->display_path[i].encoderobjid != 0)
149 count++;
150
151 break;
152
153 case 5:
154 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++)
155 if (bp->object_info_tbl.v1_5->display_path[i].encoderobjid != 0)
156 count++;
157
158 break;
159 }
160 return count;
161 }
162
bios_parser_get_connector_id(struct dc_bios * dcb,uint8_t i)163 static struct graphics_object_id bios_parser_get_connector_id(
164 struct dc_bios *dcb,
165 uint8_t i)
166 {
167 struct bios_parser *bp = BP_FROM_DCB(dcb);
168 struct graphics_object_id object_id = dal_graphics_object_id_init(
169 0, ENUM_ID_UNKNOWN, OBJECT_TYPE_UNKNOWN);
170 struct object_info_table *tbl = &bp->object_info_tbl;
171 struct display_object_info_table_v1_4 *v1_4 = tbl->v1_4;
172
173 struct display_object_info_table_v1_5 *v1_5 = tbl->v1_5;
174
175 switch (bp->object_info_tbl.revision.minor) {
176 default:
177 case 4:
178 if (v1_4->number_of_path > i) {
179 /* If display_objid is generic object id, the encoderObj
180 * /extencoderobjId should be 0
181 */
182 if (v1_4->display_path[i].encoderobjid != 0 &&
183 v1_4->display_path[i].display_objid != 0)
184 object_id = object_id_from_bios_object_id(
185 v1_4->display_path[i].display_objid);
186 }
187 break;
188
189 case 5:
190 if (v1_5->number_of_path > i) {
191 /* If display_objid is generic object id, the encoderObjId
192 * should be 0
193 */
194 if (v1_5->display_path[i].encoderobjid != 0 &&
195 v1_5->display_path[i].display_objid != 0)
196 object_id = object_id_from_bios_object_id(
197 v1_5->display_path[i].display_objid);
198 }
199 break;
200 }
201 return object_id;
202 }
203
bios_parser_get_src_obj(struct dc_bios * dcb,struct graphics_object_id object_id,uint32_t index,struct graphics_object_id * src_object_id)204 static enum bp_result bios_parser_get_src_obj(struct dc_bios *dcb,
205 struct graphics_object_id object_id, uint32_t index,
206 struct graphics_object_id *src_object_id)
207 {
208 struct bios_parser *bp = BP_FROM_DCB(dcb);
209 unsigned int i;
210 enum bp_result bp_result = BP_RESULT_BADINPUT;
211 struct graphics_object_id obj_id = { 0 };
212 struct object_info_table *tbl = &bp->object_info_tbl;
213
214 if (!src_object_id)
215 return bp_result;
216
217 switch (object_id.type) {
218 /* Encoder's Source is GPU. BIOS does not provide GPU, since all
219 * displaypaths point to same GPU (0x1100). Hardcode GPU object type
220 */
221 case OBJECT_TYPE_ENCODER:
222 /* TODO: since num of src must be less than 2.
223 * If found in for loop, should break.
224 * DAL2 implementation may be changed too
225 */
226 switch (bp->object_info_tbl.revision.minor) {
227 default:
228 case 4:
229 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
230 obj_id = object_id_from_bios_object_id(
231 tbl->v1_4->display_path[i].encoderobjid);
232 if (object_id.type == obj_id.type &&
233 object_id.id == obj_id.id &&
234 object_id.enum_id == obj_id.enum_id) {
235 *src_object_id =
236 object_id_from_bios_object_id(
237 0x1100);
238 /* break; */
239 }
240 }
241 bp_result = BP_RESULT_OK;
242 break;
243
244 case 5:
245 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
246 obj_id = object_id_from_bios_object_id(
247 tbl->v1_5->display_path[i].encoderobjid);
248 if (object_id.type == obj_id.type &&
249 object_id.id == obj_id.id &&
250 object_id.enum_id == obj_id.enum_id) {
251 *src_object_id =
252 object_id_from_bios_object_id(
253 0x1100);
254 /* break; */
255 }
256 }
257 bp_result = BP_RESULT_OK;
258 break;
259 }
260 break;
261 case OBJECT_TYPE_CONNECTOR:
262 switch (bp->object_info_tbl.revision.minor) {
263 default:
264 case 4:
265 for (i = 0; i < tbl->v1_4->number_of_path; i++) {
266 obj_id = object_id_from_bios_object_id(
267 tbl->v1_4->display_path[i]
268 .display_objid);
269
270 if (object_id.type == obj_id.type &&
271 object_id.id == obj_id.id &&
272 object_id.enum_id == obj_id.enum_id) {
273 *src_object_id =
274 object_id_from_bios_object_id(
275 tbl->v1_4
276 ->display_path[i]
277 .encoderobjid);
278 /* break; */
279 }
280 }
281 bp_result = BP_RESULT_OK;
282 break;
283 }
284 bp_result = BP_RESULT_OK;
285 break;
286 case 5:
287 for (i = 0; i < tbl->v1_5->number_of_path; i++) {
288 obj_id = object_id_from_bios_object_id(
289 tbl->v1_5->display_path[i].display_objid);
290
291 if (object_id.type == obj_id.type &&
292 object_id.id == obj_id.id &&
293 object_id.enum_id == obj_id.enum_id) {
294 *src_object_id = object_id_from_bios_object_id(
295 tbl->v1_5->display_path[i].encoderobjid);
296 /* break; */
297 }
298 }
299 bp_result = BP_RESULT_OK;
300 break;
301
302 default:
303 bp_result = BP_RESULT_OK;
304 break;
305 }
306
307 return bp_result;
308 }
309
310 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object(struct bios_parser * bp,struct graphics_object_id id)311 static struct atom_display_object_path_v2 *get_bios_object(
312 struct bios_parser *bp,
313 struct graphics_object_id id)
314 {
315 unsigned int i;
316 struct graphics_object_id obj_id = {0};
317
318 switch (id.type) {
319 case OBJECT_TYPE_ENCODER:
320 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
321 obj_id = object_id_from_bios_object_id(
322 bp->object_info_tbl.v1_4->display_path[i].encoderobjid);
323 if (id.type == obj_id.type && id.id == obj_id.id
324 && id.enum_id == obj_id.enum_id)
325 return &bp->object_info_tbl.v1_4->display_path[i];
326 }
327 fallthrough;
328 case OBJECT_TYPE_CONNECTOR:
329 case OBJECT_TYPE_GENERIC:
330 /* Both Generic and Connector Object ID
331 * will be stored on display_objid
332 */
333 for (i = 0; i < bp->object_info_tbl.v1_4->number_of_path; i++) {
334 obj_id = object_id_from_bios_object_id(
335 bp->object_info_tbl.v1_4->display_path[i].display_objid);
336 if (id.type == obj_id.type && id.id == obj_id.id
337 && id.enum_id == obj_id.enum_id)
338 return &bp->object_info_tbl.v1_4->display_path[i];
339 }
340 fallthrough;
341 default:
342 return NULL;
343 }
344 }
345
346 /* from graphics_object_id, find display path which includes the object_id */
get_bios_object_from_path_v3(struct bios_parser * bp,struct graphics_object_id id)347 static struct atom_display_object_path_v3 *get_bios_object_from_path_v3(struct bios_parser *bp,
348 struct graphics_object_id id)
349 {
350 unsigned int i;
351 struct graphics_object_id obj_id = {0};
352
353 switch (id.type) {
354 case OBJECT_TYPE_ENCODER:
355 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
356 obj_id = object_id_from_bios_object_id(
357 bp->object_info_tbl.v1_5->display_path[i].encoderobjid);
358 if (id.type == obj_id.type && id.id == obj_id.id
359 && id.enum_id == obj_id.enum_id)
360 return &bp->object_info_tbl.v1_5->display_path[i];
361 }
362 break;
363
364 case OBJECT_TYPE_CONNECTOR:
365 case OBJECT_TYPE_GENERIC:
366 /* Both Generic and Connector Object ID
367 * will be stored on display_objid
368 */
369 for (i = 0; i < bp->object_info_tbl.v1_5->number_of_path; i++) {
370 obj_id = object_id_from_bios_object_id(
371 bp->object_info_tbl.v1_5->display_path[i].display_objid);
372 if (id.type == obj_id.type && id.id == obj_id.id
373 && id.enum_id == obj_id.enum_id)
374 return &bp->object_info_tbl.v1_5->display_path[i];
375 }
376 break;
377
378 default:
379 return NULL;
380 }
381
382 return NULL;
383 }
384
bios_parser_get_i2c_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_i2c_info * info)385 static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
386 struct graphics_object_id id,
387 struct graphics_object_i2c_info *info)
388 {
389 uint32_t offset;
390 struct atom_display_object_path_v2 *object;
391
392 struct atom_display_object_path_v3 *object_path_v3;
393
394 struct atom_common_record_header *header;
395 struct atom_i2c_record *record;
396 struct atom_i2c_record dummy_record = {0};
397 struct bios_parser *bp = BP_FROM_DCB(dcb);
398
399 if (!info)
400 return BP_RESULT_BADINPUT;
401
402 if (id.type == OBJECT_TYPE_GENERIC) {
403 dummy_record.i2c_id = id.id;
404
405 if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
406 return BP_RESULT_OK;
407 else
408 return BP_RESULT_NORECORD;
409 }
410
411 switch (bp->object_info_tbl.revision.minor) {
412 case 4:
413 default:
414 object = get_bios_object(bp, id);
415
416 if (!object)
417 return BP_RESULT_BADINPUT;
418
419 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
420 break;
421 case 5:
422 object_path_v3 = get_bios_object_from_path_v3(bp, id);
423
424 if (!object_path_v3)
425 return BP_RESULT_BADINPUT;
426
427 offset = object_path_v3->disp_recordoffset + bp->object_info_tbl_offset;
428 break;
429 }
430
431 for (;;) {
432 header = GET_IMAGE(struct atom_common_record_header, offset);
433
434 if (!header)
435 return BP_RESULT_BADBIOSTABLE;
436
437 if (header->record_type == LAST_RECORD_TYPE ||
438 !header->record_size)
439 break;
440
441 if (header->record_type == ATOM_I2C_RECORD_TYPE
442 && sizeof(struct atom_i2c_record) <=
443 header->record_size) {
444 /* get the I2C info */
445 record = (struct atom_i2c_record *) header;
446
447 if (get_gpio_i2c_info(bp, record, info) ==
448 BP_RESULT_OK)
449 return BP_RESULT_OK;
450 }
451
452 offset += header->record_size;
453 }
454
455 return BP_RESULT_NORECORD;
456 }
457
get_gpio_i2c_info(struct bios_parser * bp,struct atom_i2c_record * record,struct graphics_object_i2c_info * info)458 static enum bp_result get_gpio_i2c_info(
459 struct bios_parser *bp,
460 struct atom_i2c_record *record,
461 struct graphics_object_i2c_info *info)
462 {
463 struct atom_gpio_pin_lut_v2_1 *header;
464 uint32_t count = 0;
465 unsigned int table_index = 0;
466 bool find_valid = false;
467 struct atom_gpio_pin_assignment *pin;
468
469 if (!info)
470 return BP_RESULT_BADINPUT;
471
472 /* get the GPIO_I2C info */
473 if (!DATA_TABLES(gpio_pin_lut))
474 return BP_RESULT_BADBIOSTABLE;
475
476 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
477 DATA_TABLES(gpio_pin_lut));
478 if (!header)
479 return BP_RESULT_BADBIOSTABLE;
480
481 if (sizeof(struct atom_common_table_header) +
482 sizeof(struct atom_gpio_pin_assignment) >
483 le16_to_cpu(header->table_header.structuresize))
484 return BP_RESULT_BADBIOSTABLE;
485
486 /* TODO: is version change? */
487 if (header->table_header.content_revision != 1)
488 return BP_RESULT_UNSUPPORTED;
489
490 /* get data count */
491 count = (le16_to_cpu(header->table_header.structuresize)
492 - sizeof(struct atom_common_table_header))
493 / sizeof(struct atom_gpio_pin_assignment);
494
495 pin = (struct atom_gpio_pin_assignment *) header->gpio_pin;
496
497 for (table_index = 0; table_index < count; table_index++) {
498 if (((record->i2c_id & I2C_HW_CAP) == (pin->gpio_id & I2C_HW_CAP)) &&
499 ((record->i2c_id & I2C_HW_ENGINE_ID_MASK) == (pin->gpio_id & I2C_HW_ENGINE_ID_MASK)) &&
500 ((record->i2c_id & I2C_HW_LANE_MUX) == (pin->gpio_id & I2C_HW_LANE_MUX))) {
501 /* still valid */
502 find_valid = true;
503 break;
504 }
505 pin = (struct atom_gpio_pin_assignment *)((uint8_t *)pin + sizeof(struct atom_gpio_pin_assignment));
506 }
507
508 /* If we don't find the entry that we are looking for then
509 * we will return BP_Result_BadBiosTable.
510 */
511 if (find_valid == false)
512 return BP_RESULT_BADBIOSTABLE;
513
514 /* get the GPIO_I2C_INFO */
515 info->i2c_hw_assist = (record->i2c_id & I2C_HW_CAP) ? true : false;
516 info->i2c_line = record->i2c_id & I2C_HW_LANE_MUX;
517 info->i2c_engine_id = (record->i2c_id & I2C_HW_ENGINE_ID_MASK) >> 4;
518 info->i2c_slave_address = record->i2c_slave_addr;
519
520 /* TODO: check how to get register offset for en, Y, etc. */
521 info->gpio_info.clk_a_register_index = le16_to_cpu(pin->data_a_reg_index);
522 info->gpio_info.clk_a_shift = pin->gpio_bitshift;
523
524 return BP_RESULT_OK;
525 }
526
get_hpd_record_for_path_v3(struct bios_parser * bp,struct atom_display_object_path_v3 * object)527 static struct atom_hpd_int_record *get_hpd_record_for_path_v3(struct bios_parser *bp,
528 struct atom_display_object_path_v3 *object)
529 {
530 struct atom_common_record_header *header;
531 uint32_t offset;
532
533 if (!object) {
534 BREAK_TO_DEBUGGER(); /* Invalid object */
535 return NULL;
536 }
537
538 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
539
540 for (;;) {
541 header = GET_IMAGE(struct atom_common_record_header, offset);
542
543 if (!header)
544 return NULL;
545
546 if (header->record_type == ATOM_RECORD_END_TYPE ||
547 !header->record_size)
548 break;
549
550 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
551 && sizeof(struct atom_hpd_int_record) <=
552 header->record_size)
553 return (struct atom_hpd_int_record *) header;
554
555 offset += header->record_size;
556 }
557
558 return NULL;
559 }
560
bios_parser_get_hpd_info(struct dc_bios * dcb,struct graphics_object_id id,struct graphics_object_hpd_info * info)561 static enum bp_result bios_parser_get_hpd_info(
562 struct dc_bios *dcb,
563 struct graphics_object_id id,
564 struct graphics_object_hpd_info *info)
565 {
566 struct bios_parser *bp = BP_FROM_DCB(dcb);
567 struct atom_display_object_path_v2 *object;
568 struct atom_display_object_path_v3 *object_path_v3;
569 struct atom_hpd_int_record *record = NULL;
570
571 if (!info)
572 return BP_RESULT_BADINPUT;
573
574 switch (bp->object_info_tbl.revision.minor) {
575 case 4:
576 default:
577 object = get_bios_object(bp, id);
578
579 if (!object)
580 return BP_RESULT_BADINPUT;
581
582 record = get_hpd_record(bp, object);
583 break;
584 case 5:
585 object_path_v3 = get_bios_object_from_path_v3(bp, id);
586
587 if (!object_path_v3)
588 return BP_RESULT_BADINPUT;
589
590 record = get_hpd_record_for_path_v3(bp, object_path_v3);
591 break;
592 }
593
594 if (record != NULL) {
595 info->hpd_int_gpio_uid = record->pin_id;
596 info->hpd_active = record->plugin_pin_state;
597 return BP_RESULT_OK;
598 }
599
600 return BP_RESULT_NORECORD;
601 }
602
get_hpd_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)603 static struct atom_hpd_int_record *get_hpd_record(
604 struct bios_parser *bp,
605 struct atom_display_object_path_v2 *object)
606 {
607 struct atom_common_record_header *header;
608 uint32_t offset;
609
610 if (!object) {
611 BREAK_TO_DEBUGGER(); /* Invalid object */
612 return NULL;
613 }
614
615 offset = le16_to_cpu(object->disp_recordoffset)
616 + bp->object_info_tbl_offset;
617
618 for (;;) {
619 header = GET_IMAGE(struct atom_common_record_header, offset);
620
621 if (!header)
622 return NULL;
623
624 if (header->record_type == LAST_RECORD_TYPE ||
625 !header->record_size)
626 break;
627
628 if (header->record_type == ATOM_HPD_INT_RECORD_TYPE
629 && sizeof(struct atom_hpd_int_record) <=
630 header->record_size)
631 return (struct atom_hpd_int_record *) header;
632
633 offset += header->record_size;
634 }
635
636 return NULL;
637 }
638
639 /**
640 * bios_parser_get_gpio_pin_info
641 * Get GpioPin information of input gpio id
642 *
643 * @dcb: pointer to the DC BIOS
644 * @gpio_id: GPIO ID
645 * @info: GpioPin information structure
646 * return: Bios parser result code
647 * note:
648 * to get the GPIO PIN INFO, we need:
649 * 1. get the GPIO_ID from other object table, see GetHPDInfo()
650 * 2. in DATA_TABLE.GPIO_Pin_LUT, search all records,
651 * to get the registerA offset/mask
652 */
bios_parser_get_gpio_pin_info(struct dc_bios * dcb,uint32_t gpio_id,struct gpio_pin_info * info)653 static enum bp_result bios_parser_get_gpio_pin_info(
654 struct dc_bios *dcb,
655 uint32_t gpio_id,
656 struct gpio_pin_info *info)
657 {
658 struct bios_parser *bp = BP_FROM_DCB(dcb);
659 struct atom_gpio_pin_lut_v2_1 *header;
660 uint32_t count = 0;
661 uint32_t i = 0;
662
663 if (!DATA_TABLES(gpio_pin_lut))
664 return BP_RESULT_BADBIOSTABLE;
665
666 header = GET_IMAGE(struct atom_gpio_pin_lut_v2_1,
667 DATA_TABLES(gpio_pin_lut));
668 if (!header)
669 return BP_RESULT_BADBIOSTABLE;
670
671 if (sizeof(struct atom_common_table_header) +
672 sizeof(struct atom_gpio_pin_assignment)
673 > le16_to_cpu(header->table_header.structuresize))
674 return BP_RESULT_BADBIOSTABLE;
675
676 if (header->table_header.content_revision != 1)
677 return BP_RESULT_UNSUPPORTED;
678
679 /* Temporary hard code gpio pin info */
680 count = (le16_to_cpu(header->table_header.structuresize)
681 - sizeof(struct atom_common_table_header))
682 / sizeof(struct atom_gpio_pin_assignment);
683 for (i = 0; i < count; ++i) {
684 if (header->gpio_pin[i].gpio_id != gpio_id)
685 continue;
686
687 info->offset =
688 (uint32_t) le16_to_cpu(
689 header->gpio_pin[i].data_a_reg_index);
690 info->offset_y = info->offset + 2;
691 info->offset_en = info->offset + 1;
692 info->offset_mask = info->offset - 1;
693
694 info->mask = (uint32_t) (1 <<
695 header->gpio_pin[i].gpio_bitshift);
696 info->mask_y = info->mask + 2;
697 info->mask_en = info->mask + 1;
698 info->mask_mask = info->mask - 1;
699
700 return BP_RESULT_OK;
701 }
702
703 return BP_RESULT_NORECORD;
704 }
705
device_type_from_device_id(uint16_t device_id)706 static struct device_id device_type_from_device_id(uint16_t device_id)
707 {
708
709 struct device_id result_device_id;
710
711 result_device_id.raw_device_tag = device_id;
712
713 switch (device_id) {
714 case ATOM_DISPLAY_LCD1_SUPPORT:
715 result_device_id.device_type = DEVICE_TYPE_LCD;
716 result_device_id.enum_id = 1;
717 break;
718
719 case ATOM_DISPLAY_LCD2_SUPPORT:
720 result_device_id.device_type = DEVICE_TYPE_LCD;
721 result_device_id.enum_id = 2;
722 break;
723
724 case ATOM_DISPLAY_DFP1_SUPPORT:
725 result_device_id.device_type = DEVICE_TYPE_DFP;
726 result_device_id.enum_id = 1;
727 break;
728
729 case ATOM_DISPLAY_DFP2_SUPPORT:
730 result_device_id.device_type = DEVICE_TYPE_DFP;
731 result_device_id.enum_id = 2;
732 break;
733
734 case ATOM_DISPLAY_DFP3_SUPPORT:
735 result_device_id.device_type = DEVICE_TYPE_DFP;
736 result_device_id.enum_id = 3;
737 break;
738
739 case ATOM_DISPLAY_DFP4_SUPPORT:
740 result_device_id.device_type = DEVICE_TYPE_DFP;
741 result_device_id.enum_id = 4;
742 break;
743
744 case ATOM_DISPLAY_DFP5_SUPPORT:
745 result_device_id.device_type = DEVICE_TYPE_DFP;
746 result_device_id.enum_id = 5;
747 break;
748
749 case ATOM_DISPLAY_DFP6_SUPPORT:
750 result_device_id.device_type = DEVICE_TYPE_DFP;
751 result_device_id.enum_id = 6;
752 break;
753
754 default:
755 BREAK_TO_DEBUGGER(); /* Invalid device Id */
756 result_device_id.device_type = DEVICE_TYPE_UNKNOWN;
757 result_device_id.enum_id = 0;
758 }
759 return result_device_id;
760 }
761
bios_parser_get_device_tag(struct dc_bios * dcb,struct graphics_object_id connector_object_id,uint32_t device_tag_index,struct connector_device_tag_info * info)762 static enum bp_result bios_parser_get_device_tag(
763 struct dc_bios *dcb,
764 struct graphics_object_id connector_object_id,
765 uint32_t device_tag_index,
766 struct connector_device_tag_info *info)
767 {
768 struct bios_parser *bp = BP_FROM_DCB(dcb);
769 struct atom_display_object_path_v2 *object;
770
771 struct atom_display_object_path_v3 *object_path_v3;
772
773
774 if (!info)
775 return BP_RESULT_BADINPUT;
776
777 switch (bp->object_info_tbl.revision.minor) {
778 case 4:
779 default:
780 /* getBiosObject will return MXM object */
781 object = get_bios_object(bp, connector_object_id);
782
783 if (!object) {
784 BREAK_TO_DEBUGGER(); /* Invalid object id */
785 return BP_RESULT_BADINPUT;
786 }
787
788 info->acpi_device = 0; /* BIOS no longer provides this */
789 info->dev_id = device_type_from_device_id(object->device_tag);
790 break;
791 case 5:
792 object_path_v3 = get_bios_object_from_path_v3(bp, connector_object_id);
793
794 if (!object_path_v3) {
795 BREAK_TO_DEBUGGER(); /* Invalid object id */
796 return BP_RESULT_BADINPUT;
797 }
798 info->acpi_device = 0; /* BIOS no longer provides this */
799 info->dev_id = device_type_from_device_id(object_path_v3->device_tag);
800 break;
801 }
802
803 return BP_RESULT_OK;
804 }
805
get_ss_info_v4_1(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)806 static enum bp_result get_ss_info_v4_1(
807 struct bios_parser *bp,
808 uint32_t id,
809 uint32_t index,
810 struct spread_spectrum_info *ss_info)
811 {
812 enum bp_result result = BP_RESULT_OK;
813 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
814 struct atom_smu_info_v3_3 *smu_info = NULL;
815
816 if (!ss_info)
817 return BP_RESULT_BADINPUT;
818
819 if (!DATA_TABLES(dce_info))
820 return BP_RESULT_BADBIOSTABLE;
821
822 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
823 DATA_TABLES(dce_info));
824 if (!disp_cntl_tbl)
825 return BP_RESULT_BADBIOSTABLE;
826
827
828 ss_info->type.STEP_AND_DELAY_INFO = false;
829 ss_info->spread_percentage_divider = 1000;
830 /* BIOS no longer uses target clock. Always enable for now */
831 ss_info->target_clock_range = 0xffffffff;
832
833 switch (id) {
834 case AS_SIGNAL_TYPE_DVI:
835 ss_info->spread_spectrum_percentage =
836 disp_cntl_tbl->dvi_ss_percentage;
837 ss_info->spread_spectrum_range =
838 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
839 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
840 ss_info->type.CENTER_MODE = true;
841
842 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
843 break;
844 case AS_SIGNAL_TYPE_HDMI:
845 ss_info->spread_spectrum_percentage =
846 disp_cntl_tbl->hdmi_ss_percentage;
847 ss_info->spread_spectrum_range =
848 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
849 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
850 ss_info->type.CENTER_MODE = true;
851
852 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
853 break;
854 /* TODO LVDS not support anymore? */
855 case AS_SIGNAL_TYPE_DISPLAY_PORT:
856 ss_info->spread_spectrum_percentage =
857 disp_cntl_tbl->dp_ss_percentage;
858 ss_info->spread_spectrum_range =
859 disp_cntl_tbl->dp_ss_rate_10hz * 10;
860 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
861 ss_info->type.CENTER_MODE = true;
862
863 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
864 break;
865 case AS_SIGNAL_TYPE_GPU_PLL:
866 /* atom_firmware: DAL only get data from dce_info table.
867 * if data within smu_info is needed for DAL, VBIOS should
868 * copy it into dce_info
869 */
870 result = BP_RESULT_UNSUPPORTED;
871 break;
872 case AS_SIGNAL_TYPE_XGMI:
873 smu_info = GET_IMAGE(struct atom_smu_info_v3_3,
874 DATA_TABLES(smu_info));
875 if (!smu_info)
876 return BP_RESULT_BADBIOSTABLE;
877 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
878 ss_info->spread_spectrum_percentage =
879 smu_info->waflclk_ss_percentage;
880 ss_info->spread_spectrum_range =
881 smu_info->gpuclk_ss_rate_10hz * 10;
882 if (smu_info->waflclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
883 ss_info->type.CENTER_MODE = true;
884
885 DC_LOG_BIOS("AS_SIGNAL_TYPE_XGMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
886 break;
887 default:
888 result = BP_RESULT_UNSUPPORTED;
889 }
890
891 return result;
892 }
893
get_ss_info_v4_2(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)894 static enum bp_result get_ss_info_v4_2(
895 struct bios_parser *bp,
896 uint32_t id,
897 uint32_t index,
898 struct spread_spectrum_info *ss_info)
899 {
900 enum bp_result result = BP_RESULT_OK;
901 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
902 struct atom_smu_info_v3_1 *smu_info = NULL;
903
904 if (!ss_info)
905 return BP_RESULT_BADINPUT;
906
907 if (!DATA_TABLES(dce_info))
908 return BP_RESULT_BADBIOSTABLE;
909
910 if (!DATA_TABLES(smu_info))
911 return BP_RESULT_BADBIOSTABLE;
912
913 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
914 DATA_TABLES(dce_info));
915 if (!disp_cntl_tbl)
916 return BP_RESULT_BADBIOSTABLE;
917
918 smu_info = GET_IMAGE(struct atom_smu_info_v3_1, DATA_TABLES(smu_info));
919 if (!smu_info)
920 return BP_RESULT_BADBIOSTABLE;
921
922 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info->gpuclk_ss_percentage);
923 ss_info->type.STEP_AND_DELAY_INFO = false;
924 ss_info->spread_percentage_divider = 1000;
925 /* BIOS no longer uses target clock. Always enable for now */
926 ss_info->target_clock_range = 0xffffffff;
927
928 switch (id) {
929 case AS_SIGNAL_TYPE_DVI:
930 ss_info->spread_spectrum_percentage =
931 disp_cntl_tbl->dvi_ss_percentage;
932 ss_info->spread_spectrum_range =
933 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
934 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
935 ss_info->type.CENTER_MODE = true;
936
937 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
938 break;
939 case AS_SIGNAL_TYPE_HDMI:
940 ss_info->spread_spectrum_percentage =
941 disp_cntl_tbl->hdmi_ss_percentage;
942 ss_info->spread_spectrum_range =
943 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
944 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
945 ss_info->type.CENTER_MODE = true;
946
947 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
948 break;
949 /* TODO LVDS not support anymore? */
950 case AS_SIGNAL_TYPE_DISPLAY_PORT:
951 ss_info->spread_spectrum_percentage =
952 smu_info->gpuclk_ss_percentage;
953 ss_info->spread_spectrum_range =
954 smu_info->gpuclk_ss_rate_10hz * 10;
955 if (smu_info->gpuclk_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
956 ss_info->type.CENTER_MODE = true;
957
958 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
959 break;
960 case AS_SIGNAL_TYPE_GPU_PLL:
961 /* atom_firmware: DAL only get data from dce_info table.
962 * if data within smu_info is needed for DAL, VBIOS should
963 * copy it into dce_info
964 */
965 result = BP_RESULT_UNSUPPORTED;
966 break;
967 default:
968 result = BP_RESULT_UNSUPPORTED;
969 }
970
971 return result;
972 }
973
get_ss_info_v4_5(struct bios_parser * bp,uint32_t id,uint32_t index,struct spread_spectrum_info * ss_info)974 static enum bp_result get_ss_info_v4_5(
975 struct bios_parser *bp,
976 uint32_t id,
977 uint32_t index,
978 struct spread_spectrum_info *ss_info)
979 {
980 enum bp_result result = BP_RESULT_OK;
981 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
982
983 if (!ss_info)
984 return BP_RESULT_BADINPUT;
985
986 if (!DATA_TABLES(dce_info))
987 return BP_RESULT_BADBIOSTABLE;
988
989 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
990 DATA_TABLES(dce_info));
991 if (!disp_cntl_tbl)
992 return BP_RESULT_BADBIOSTABLE;
993
994 ss_info->type.STEP_AND_DELAY_INFO = false;
995 ss_info->spread_percentage_divider = 1000;
996 /* BIOS no longer uses target clock. Always enable for now */
997 ss_info->target_clock_range = 0xffffffff;
998
999 switch (id) {
1000 case AS_SIGNAL_TYPE_DVI:
1001 ss_info->spread_spectrum_percentage =
1002 disp_cntl_tbl->dvi_ss_percentage;
1003 ss_info->spread_spectrum_range =
1004 disp_cntl_tbl->dvi_ss_rate_10hz * 10;
1005 if (disp_cntl_tbl->dvi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1006 ss_info->type.CENTER_MODE = true;
1007
1008 DC_LOG_BIOS("AS_SIGNAL_TYPE_DVI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1009 break;
1010 case AS_SIGNAL_TYPE_HDMI:
1011 ss_info->spread_spectrum_percentage =
1012 disp_cntl_tbl->hdmi_ss_percentage;
1013 ss_info->spread_spectrum_range =
1014 disp_cntl_tbl->hdmi_ss_rate_10hz * 10;
1015 if (disp_cntl_tbl->hdmi_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1016 ss_info->type.CENTER_MODE = true;
1017
1018 DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1019 break;
1020 case AS_SIGNAL_TYPE_DISPLAY_PORT:
1021 if (bp->base.integrated_info) {
1022 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
1023 ss_info->spread_spectrum_percentage =
1024 bp->base.integrated_info->gpuclk_ss_percentage;
1025 ss_info->type.CENTER_MODE =
1026 bp->base.integrated_info->gpuclk_ss_type;
1027 } else {
1028 ss_info->spread_spectrum_percentage =
1029 disp_cntl_tbl->dp_ss_percentage;
1030 ss_info->spread_spectrum_range =
1031 disp_cntl_tbl->dp_ss_rate_10hz * 10;
1032 if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
1033 ss_info->type.CENTER_MODE = true;
1034 }
1035 DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n", ss_info->spread_spectrum_percentage);
1036 break;
1037 case AS_SIGNAL_TYPE_GPU_PLL:
1038 /* atom_smu_info_v4_0 does not have fields for SS for SMU Display PLL anymore.
1039 * SMU Display PLL supposed to be without spread.
1040 * Better place for it would be in atom_display_controller_info_v4_5 table.
1041 */
1042 result = BP_RESULT_UNSUPPORTED;
1043 break;
1044 default:
1045 result = BP_RESULT_UNSUPPORTED;
1046 break;
1047 }
1048
1049 return result;
1050 }
1051
1052 /**
1053 * bios_parser_get_spread_spectrum_info
1054 * Get spread spectrum information from the ASIC_InternalSS_Info(ver 2.1 or
1055 * ver 3.1) or SS_Info table from the VBIOS. Currently ASIC_InternalSS_Info
1056 * ver 2.1 can co-exist with SS_Info table. Expect ASIC_InternalSS_Info
1057 * ver 3.1,
1058 * there is only one entry for each signal /ss id. However, there is
1059 * no planning of supporting multiple spread Sprectum entry for EverGreen
1060 * @dcb: pointer to the DC BIOS
1061 * @signal: ASSignalType to be converted to info index
1062 * @index: number of entries that match the converted info index
1063 * @ss_info: sprectrum information structure,
1064 * return: Bios parser result code
1065 */
bios_parser_get_spread_spectrum_info(struct dc_bios * dcb,enum as_signal_type signal,uint32_t index,struct spread_spectrum_info * ss_info)1066 static enum bp_result bios_parser_get_spread_spectrum_info(
1067 struct dc_bios *dcb,
1068 enum as_signal_type signal,
1069 uint32_t index,
1070 struct spread_spectrum_info *ss_info)
1071 {
1072 struct bios_parser *bp = BP_FROM_DCB(dcb);
1073 enum bp_result result = BP_RESULT_UNSUPPORTED;
1074 struct atom_common_table_header *header;
1075 struct atom_data_revision tbl_revision;
1076
1077 if (!ss_info) /* check for bad input */
1078 return BP_RESULT_BADINPUT;
1079
1080 if (!DATA_TABLES(dce_info))
1081 return BP_RESULT_UNSUPPORTED;
1082
1083 header = GET_IMAGE(struct atom_common_table_header,
1084 DATA_TABLES(dce_info));
1085 get_atom_data_table_revision(header, &tbl_revision);
1086
1087 switch (tbl_revision.major) {
1088 case 4:
1089 switch (tbl_revision.minor) {
1090 case 1:
1091 return get_ss_info_v4_1(bp, signal, index, ss_info);
1092 case 2:
1093 case 3:
1094 case 4:
1095 return get_ss_info_v4_2(bp, signal, index, ss_info);
1096 case 5:
1097 return get_ss_info_v4_5(bp, signal, index, ss_info);
1098
1099 default:
1100 ASSERT(0);
1101 break;
1102 }
1103 break;
1104 default:
1105 break;
1106 }
1107 /* there can not be more then one entry for SS Info table */
1108 return result;
1109 }
1110
get_soc_bb_info_v4_4(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1111 static enum bp_result get_soc_bb_info_v4_4(
1112 struct bios_parser *bp,
1113 struct bp_soc_bb_info *soc_bb_info)
1114 {
1115 enum bp_result result = BP_RESULT_OK;
1116 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1117
1118 if (!soc_bb_info)
1119 return BP_RESULT_BADINPUT;
1120
1121 if (!DATA_TABLES(dce_info))
1122 return BP_RESULT_BADBIOSTABLE;
1123
1124 if (!DATA_TABLES(smu_info))
1125 return BP_RESULT_BADBIOSTABLE;
1126
1127 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1128 DATA_TABLES(dce_info));
1129 if (!disp_cntl_tbl)
1130 return BP_RESULT_BADBIOSTABLE;
1131
1132 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1133 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1134 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1135
1136 return result;
1137 }
1138
get_soc_bb_info_v4_5(struct bios_parser * bp,struct bp_soc_bb_info * soc_bb_info)1139 static enum bp_result get_soc_bb_info_v4_5(
1140 struct bios_parser *bp,
1141 struct bp_soc_bb_info *soc_bb_info)
1142 {
1143 enum bp_result result = BP_RESULT_OK;
1144 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1145
1146 if (!soc_bb_info)
1147 return BP_RESULT_BADINPUT;
1148
1149 if (!DATA_TABLES(dce_info))
1150 return BP_RESULT_BADBIOSTABLE;
1151
1152 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1153 DATA_TABLES(dce_info));
1154 if (!disp_cntl_tbl)
1155 return BP_RESULT_BADBIOSTABLE;
1156
1157 soc_bb_info->dram_clock_change_latency_100ns = disp_cntl_tbl->max_mclk_chg_lat;
1158 soc_bb_info->dram_sr_enter_exit_latency_100ns = disp_cntl_tbl->max_sr_enter_exit_lat;
1159 soc_bb_info->dram_sr_exit_latency_100ns = disp_cntl_tbl->max_sr_exit_lat;
1160
1161 return result;
1162 }
1163
bios_parser_get_soc_bb_info(struct dc_bios * dcb,struct bp_soc_bb_info * soc_bb_info)1164 static enum bp_result bios_parser_get_soc_bb_info(
1165 struct dc_bios *dcb,
1166 struct bp_soc_bb_info *soc_bb_info)
1167 {
1168 struct bios_parser *bp = BP_FROM_DCB(dcb);
1169 enum bp_result result = BP_RESULT_UNSUPPORTED;
1170 struct atom_common_table_header *header;
1171 struct atom_data_revision tbl_revision;
1172
1173 if (!soc_bb_info) /* check for bad input */
1174 return BP_RESULT_BADINPUT;
1175
1176 if (!DATA_TABLES(dce_info))
1177 return BP_RESULT_UNSUPPORTED;
1178
1179 header = GET_IMAGE(struct atom_common_table_header,
1180 DATA_TABLES(dce_info));
1181 get_atom_data_table_revision(header, &tbl_revision);
1182
1183 switch (tbl_revision.major) {
1184 case 4:
1185 switch (tbl_revision.minor) {
1186 case 1:
1187 case 2:
1188 case 3:
1189 break;
1190 case 4:
1191 result = get_soc_bb_info_v4_4(bp, soc_bb_info);
1192 break;
1193 case 5:
1194 result = get_soc_bb_info_v4_5(bp, soc_bb_info);
1195 break;
1196 default:
1197 break;
1198 }
1199 break;
1200 default:
1201 break;
1202 }
1203
1204 return result;
1205 }
1206
get_disp_caps_v4_1(struct bios_parser * bp,uint8_t * dce_caps)1207 static enum bp_result get_disp_caps_v4_1(
1208 struct bios_parser *bp,
1209 uint8_t *dce_caps)
1210 {
1211 enum bp_result result = BP_RESULT_OK;
1212 struct atom_display_controller_info_v4_1 *disp_cntl_tbl = NULL;
1213
1214 if (!dce_caps)
1215 return BP_RESULT_BADINPUT;
1216
1217 if (!DATA_TABLES(dce_info))
1218 return BP_RESULT_BADBIOSTABLE;
1219
1220 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_1,
1221 DATA_TABLES(dce_info));
1222
1223 if (!disp_cntl_tbl)
1224 return BP_RESULT_BADBIOSTABLE;
1225
1226 *dce_caps = disp_cntl_tbl->display_caps;
1227
1228 return result;
1229 }
1230
get_disp_caps_v4_2(struct bios_parser * bp,uint8_t * dce_caps)1231 static enum bp_result get_disp_caps_v4_2(
1232 struct bios_parser *bp,
1233 uint8_t *dce_caps)
1234 {
1235 enum bp_result result = BP_RESULT_OK;
1236 struct atom_display_controller_info_v4_2 *disp_cntl_tbl = NULL;
1237
1238 if (!dce_caps)
1239 return BP_RESULT_BADINPUT;
1240
1241 if (!DATA_TABLES(dce_info))
1242 return BP_RESULT_BADBIOSTABLE;
1243
1244 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_2,
1245 DATA_TABLES(dce_info));
1246
1247 if (!disp_cntl_tbl)
1248 return BP_RESULT_BADBIOSTABLE;
1249
1250 *dce_caps = disp_cntl_tbl->display_caps;
1251
1252 return result;
1253 }
1254
get_disp_caps_v4_3(struct bios_parser * bp,uint8_t * dce_caps)1255 static enum bp_result get_disp_caps_v4_3(
1256 struct bios_parser *bp,
1257 uint8_t *dce_caps)
1258 {
1259 enum bp_result result = BP_RESULT_OK;
1260 struct atom_display_controller_info_v4_3 *disp_cntl_tbl = NULL;
1261
1262 if (!dce_caps)
1263 return BP_RESULT_BADINPUT;
1264
1265 if (!DATA_TABLES(dce_info))
1266 return BP_RESULT_BADBIOSTABLE;
1267
1268 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_3,
1269 DATA_TABLES(dce_info));
1270
1271 if (!disp_cntl_tbl)
1272 return BP_RESULT_BADBIOSTABLE;
1273
1274 *dce_caps = disp_cntl_tbl->display_caps;
1275
1276 return result;
1277 }
1278
get_disp_caps_v4_4(struct bios_parser * bp,uint8_t * dce_caps)1279 static enum bp_result get_disp_caps_v4_4(
1280 struct bios_parser *bp,
1281 uint8_t *dce_caps)
1282 {
1283 enum bp_result result = BP_RESULT_OK;
1284 struct atom_display_controller_info_v4_4 *disp_cntl_tbl = NULL;
1285
1286 if (!dce_caps)
1287 return BP_RESULT_BADINPUT;
1288
1289 if (!DATA_TABLES(dce_info))
1290 return BP_RESULT_BADBIOSTABLE;
1291
1292 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_4,
1293 DATA_TABLES(dce_info));
1294
1295 if (!disp_cntl_tbl)
1296 return BP_RESULT_BADBIOSTABLE;
1297
1298 *dce_caps = disp_cntl_tbl->display_caps;
1299
1300 return result;
1301 }
1302
get_disp_caps_v4_5(struct bios_parser * bp,uint8_t * dce_caps)1303 static enum bp_result get_disp_caps_v4_5(
1304 struct bios_parser *bp,
1305 uint8_t *dce_caps)
1306 {
1307 enum bp_result result = BP_RESULT_OK;
1308 struct atom_display_controller_info_v4_5 *disp_cntl_tbl = NULL;
1309
1310 if (!dce_caps)
1311 return BP_RESULT_BADINPUT;
1312
1313 if (!DATA_TABLES(dce_info))
1314 return BP_RESULT_BADBIOSTABLE;
1315
1316 disp_cntl_tbl = GET_IMAGE(struct atom_display_controller_info_v4_5,
1317 DATA_TABLES(dce_info));
1318
1319 if (!disp_cntl_tbl)
1320 return BP_RESULT_BADBIOSTABLE;
1321
1322 *dce_caps = disp_cntl_tbl->display_caps;
1323
1324 return result;
1325 }
1326
bios_parser_get_lttpr_interop(struct dc_bios * dcb,uint8_t * dce_caps)1327 static enum bp_result bios_parser_get_lttpr_interop(
1328 struct dc_bios *dcb,
1329 uint8_t *dce_caps)
1330 {
1331 struct bios_parser *bp = BP_FROM_DCB(dcb);
1332 enum bp_result result = BP_RESULT_UNSUPPORTED;
1333 struct atom_common_table_header *header;
1334 struct atom_data_revision tbl_revision;
1335
1336 if (!DATA_TABLES(dce_info))
1337 return BP_RESULT_UNSUPPORTED;
1338
1339 header = GET_IMAGE(struct atom_common_table_header,
1340 DATA_TABLES(dce_info));
1341 get_atom_data_table_revision(header, &tbl_revision);
1342 switch (tbl_revision.major) {
1343 case 4:
1344 switch (tbl_revision.minor) {
1345 case 1:
1346 result = get_disp_caps_v4_1(bp, dce_caps);
1347 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1348 break;
1349 case 2:
1350 result = get_disp_caps_v4_2(bp, dce_caps);
1351 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1352 break;
1353 case 3:
1354 result = get_disp_caps_v4_3(bp, dce_caps);
1355 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1356 break;
1357 case 4:
1358 result = get_disp_caps_v4_4(bp, dce_caps);
1359 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1360 break;
1361 case 5:
1362 result = get_disp_caps_v4_5(bp, dce_caps);
1363 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE);
1364 break;
1365
1366 default:
1367 break;
1368 }
1369 break;
1370 default:
1371 break;
1372 }
1373 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1374 return result;
1375 }
1376
bios_parser_get_lttpr_caps(struct dc_bios * dcb,uint8_t * dce_caps)1377 static enum bp_result bios_parser_get_lttpr_caps(
1378 struct dc_bios *dcb,
1379 uint8_t *dce_caps)
1380 {
1381 struct bios_parser *bp = BP_FROM_DCB(dcb);
1382 enum bp_result result = BP_RESULT_UNSUPPORTED;
1383 struct atom_common_table_header *header;
1384 struct atom_data_revision tbl_revision;
1385
1386 if (!DATA_TABLES(dce_info))
1387 return BP_RESULT_UNSUPPORTED;
1388
1389 *dce_caps = 0;
1390 header = GET_IMAGE(struct atom_common_table_header,
1391 DATA_TABLES(dce_info));
1392 get_atom_data_table_revision(header, &tbl_revision);
1393 switch (tbl_revision.major) {
1394 case 4:
1395 switch (tbl_revision.minor) {
1396 case 1:
1397 result = get_disp_caps_v4_1(bp, dce_caps);
1398 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1399 break;
1400 case 2:
1401 result = get_disp_caps_v4_2(bp, dce_caps);
1402 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1403 break;
1404 case 3:
1405 result = get_disp_caps_v4_3(bp, dce_caps);
1406 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1407 break;
1408 case 4:
1409 result = get_disp_caps_v4_4(bp, dce_caps);
1410 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1411 break;
1412 case 5:
1413 result = get_disp_caps_v4_5(bp, dce_caps);
1414 *dce_caps = !!(*dce_caps & DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE);
1415 break;
1416 default:
1417 break;
1418 }
1419 break;
1420 default:
1421 break;
1422 }
1423 DC_LOG_BIOS("DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE: %d tbl_revision.major = %d tbl_revision.minor = %d\n", *dce_caps, tbl_revision.major, tbl_revision.minor);
1424 if (dcb->ctx->dc->config.force_bios_enable_lttpr && *dce_caps == 0) {
1425 *dce_caps = 1;
1426 DC_LOG_BIOS("DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE: forced enabled");
1427 }
1428 return result;
1429 }
1430
get_embedded_panel_info_v2_1(struct bios_parser * bp,struct embedded_panel_info * info)1431 static enum bp_result get_embedded_panel_info_v2_1(
1432 struct bios_parser *bp,
1433 struct embedded_panel_info *info)
1434 {
1435 struct lcd_info_v2_1 *lvds;
1436
1437 if (!info)
1438 return BP_RESULT_BADINPUT;
1439
1440 if (!DATA_TABLES(lcd_info))
1441 return BP_RESULT_UNSUPPORTED;
1442
1443 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
1444
1445 if (!lvds)
1446 return BP_RESULT_BADBIOSTABLE;
1447
1448 /* TODO: previous vv1_3, should v2_1 */
1449 if (!((lvds->table_header.format_revision == 2)
1450 && (lvds->table_header.content_revision >= 1)))
1451 return BP_RESULT_UNSUPPORTED;
1452
1453 memset(info, 0, sizeof(struct embedded_panel_info));
1454
1455 /* We need to convert from 10KHz units into KHz units */
1456 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
1457 /* usHActive does not include borders, according to VBIOS team */
1458 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
1459 /* usHBlanking_Time includes borders, so we should really be
1460 * subtractingborders duing this translation, but LVDS generally
1461 * doesn't have borders, so we should be okay leaving this as is for
1462 * now. May need to revisit if we ever have LVDS with borders
1463 */
1464 info->lcd_timing.horizontal_blanking_time = le16_to_cpu(lvds->lcd_timing.h_blanking_time);
1465 /* usVActive does not include borders, according to VBIOS team*/
1466 info->lcd_timing.vertical_addressable = le16_to_cpu(lvds->lcd_timing.v_active);
1467 /* usVBlanking_Time includes borders, so we should really be
1468 * subtracting borders duing this translation, but LVDS generally
1469 * doesn't have borders, so we should be okay leaving this as is for
1470 * now. May need to revisit if we ever have LVDS with borders
1471 */
1472 info->lcd_timing.vertical_blanking_time = le16_to_cpu(lvds->lcd_timing.v_blanking_time);
1473 info->lcd_timing.horizontal_sync_offset = le16_to_cpu(lvds->lcd_timing.h_sync_offset);
1474 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width);
1475 info->lcd_timing.vertical_sync_offset = le16_to_cpu(lvds->lcd_timing.v_sync_offset);
1476 info->lcd_timing.vertical_sync_width = le16_to_cpu(lvds->lcd_timing.v_syncwidth);
1477 info->lcd_timing.horizontal_border = lvds->lcd_timing.h_border;
1478 info->lcd_timing.vertical_border = lvds->lcd_timing.v_border;
1479
1480 /* not provided by VBIOS */
1481 info->lcd_timing.misc_info.HORIZONTAL_CUT_OFF = 0;
1482
1483 info->lcd_timing.misc_info.H_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1484 & ATOM_HSYNC_POLARITY);
1485 info->lcd_timing.misc_info.V_SYNC_POLARITY = ~(uint32_t) (lvds->lcd_timing.miscinfo
1486 & ATOM_VSYNC_POLARITY);
1487
1488 /* not provided by VBIOS */
1489 info->lcd_timing.misc_info.VERTICAL_CUT_OFF = 0;
1490
1491 info->lcd_timing.misc_info.H_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1492 & ATOM_H_REPLICATIONBY2);
1493 info->lcd_timing.misc_info.V_REPLICATION_BY2 = !!(lvds->lcd_timing.miscinfo
1494 & ATOM_V_REPLICATIONBY2);
1495 info->lcd_timing.misc_info.COMPOSITE_SYNC = !!(lvds->lcd_timing.miscinfo
1496 & ATOM_COMPOSITESYNC);
1497 info->lcd_timing.misc_info.INTERLACE = !!(lvds->lcd_timing.miscinfo & ATOM_INTERLACE);
1498
1499 /* not provided by VBIOS*/
1500 info->lcd_timing.misc_info.DOUBLE_CLOCK = 0;
1501 /* not provided by VBIOS*/
1502 info->ss_id = 0;
1503
1504 info->realtek_eDPToLVDS = !!(lvds->dplvdsrxid == eDP_TO_LVDS_REALTEK_ID);
1505
1506 return BP_RESULT_OK;
1507 }
1508
bios_parser_get_embedded_panel_info(struct dc_bios * dcb,struct embedded_panel_info * info)1509 static enum bp_result bios_parser_get_embedded_panel_info(
1510 struct dc_bios *dcb,
1511 struct embedded_panel_info *info)
1512 {
1513 struct bios_parser
1514 *bp = BP_FROM_DCB(dcb);
1515 struct atom_common_table_header *header;
1516 struct atom_data_revision tbl_revision;
1517
1518 if (!DATA_TABLES(lcd_info))
1519 return BP_RESULT_FAILURE;
1520
1521 header = GET_IMAGE(struct atom_common_table_header, DATA_TABLES(lcd_info));
1522
1523 if (!header)
1524 return BP_RESULT_BADBIOSTABLE;
1525
1526 get_atom_data_table_revision(header, &tbl_revision);
1527
1528 switch (tbl_revision.major) {
1529 case 2:
1530 switch (tbl_revision.minor) {
1531 case 1:
1532 return get_embedded_panel_info_v2_1(bp, info);
1533 default:
1534 break;
1535 }
1536 break;
1537 default:
1538 break;
1539 }
1540
1541 return BP_RESULT_FAILURE;
1542 }
1543
get_support_mask_for_device_id(struct device_id device_id)1544 static uint32_t get_support_mask_for_device_id(struct device_id device_id)
1545 {
1546 enum dal_device_type device_type = device_id.device_type;
1547 uint32_t enum_id = device_id.enum_id;
1548
1549 switch (device_type) {
1550 case DEVICE_TYPE_LCD:
1551 switch (enum_id) {
1552 case 1:
1553 return ATOM_DISPLAY_LCD1_SUPPORT;
1554 default:
1555 break;
1556 }
1557 break;
1558 case DEVICE_TYPE_DFP:
1559 switch (enum_id) {
1560 case 1:
1561 return ATOM_DISPLAY_DFP1_SUPPORT;
1562 case 2:
1563 return ATOM_DISPLAY_DFP2_SUPPORT;
1564 case 3:
1565 return ATOM_DISPLAY_DFP3_SUPPORT;
1566 case 4:
1567 return ATOM_DISPLAY_DFP4_SUPPORT;
1568 case 5:
1569 return ATOM_DISPLAY_DFP5_SUPPORT;
1570 case 6:
1571 return ATOM_DISPLAY_DFP6_SUPPORT;
1572 default:
1573 break;
1574 }
1575 break;
1576 default:
1577 break;
1578 }
1579
1580 /* Unidentified device ID, return empty support mask. */
1581 return 0;
1582 }
1583
bios_parser_is_device_id_supported(struct dc_bios * dcb,struct device_id id)1584 static bool bios_parser_is_device_id_supported(
1585 struct dc_bios *dcb,
1586 struct device_id id)
1587 {
1588 struct bios_parser *bp = BP_FROM_DCB(dcb);
1589
1590 uint32_t mask = get_support_mask_for_device_id(id);
1591
1592 switch (bp->object_info_tbl.revision.minor) {
1593 case 4:
1594 default:
1595 return (le16_to_cpu(bp->object_info_tbl.v1_4->supporteddevices) & mask) != 0;
1596 break;
1597 case 5:
1598 return (le16_to_cpu(bp->object_info_tbl.v1_5->supporteddevices) & mask) != 0;
1599 break;
1600 }
1601 }
1602
bios_parser_get_ss_entry_number(struct dc_bios * dcb,enum as_signal_type signal)1603 static uint32_t bios_parser_get_ss_entry_number(
1604 struct dc_bios *dcb,
1605 enum as_signal_type signal)
1606 {
1607 /* TODO: DAL2 atomfirmware implementation does not need this.
1608 * why DAL3 need this?
1609 */
1610 return 1;
1611 }
1612
bios_parser_transmitter_control(struct dc_bios * dcb,struct bp_transmitter_control * cntl)1613 static enum bp_result bios_parser_transmitter_control(
1614 struct dc_bios *dcb,
1615 struct bp_transmitter_control *cntl)
1616 {
1617 struct bios_parser *bp = BP_FROM_DCB(dcb);
1618
1619 if (!bp->cmd_tbl.transmitter_control)
1620 return BP_RESULT_FAILURE;
1621
1622 return bp->cmd_tbl.transmitter_control(bp, cntl);
1623 }
1624
bios_parser_encoder_control(struct dc_bios * dcb,struct bp_encoder_control * cntl)1625 static enum bp_result bios_parser_encoder_control(
1626 struct dc_bios *dcb,
1627 struct bp_encoder_control *cntl)
1628 {
1629 struct bios_parser *bp = BP_FROM_DCB(dcb);
1630
1631 if (!bp->cmd_tbl.dig_encoder_control)
1632 return BP_RESULT_FAILURE;
1633
1634 return bp->cmd_tbl.dig_encoder_control(bp, cntl);
1635 }
1636
bios_parser_set_pixel_clock(struct dc_bios * dcb,struct bp_pixel_clock_parameters * bp_params)1637 static enum bp_result bios_parser_set_pixel_clock(
1638 struct dc_bios *dcb,
1639 struct bp_pixel_clock_parameters *bp_params)
1640 {
1641 struct bios_parser *bp = BP_FROM_DCB(dcb);
1642
1643 if (!bp->cmd_tbl.set_pixel_clock)
1644 return BP_RESULT_FAILURE;
1645
1646 return bp->cmd_tbl.set_pixel_clock(bp, bp_params);
1647 }
1648
bios_parser_set_dce_clock(struct dc_bios * dcb,struct bp_set_dce_clock_parameters * bp_params)1649 static enum bp_result bios_parser_set_dce_clock(
1650 struct dc_bios *dcb,
1651 struct bp_set_dce_clock_parameters *bp_params)
1652 {
1653 struct bios_parser *bp = BP_FROM_DCB(dcb);
1654
1655 if (!bp->cmd_tbl.set_dce_clock)
1656 return BP_RESULT_FAILURE;
1657
1658 return bp->cmd_tbl.set_dce_clock(bp, bp_params);
1659 }
1660
bios_parser_program_crtc_timing(struct dc_bios * dcb,struct bp_hw_crtc_timing_parameters * bp_params)1661 static enum bp_result bios_parser_program_crtc_timing(
1662 struct dc_bios *dcb,
1663 struct bp_hw_crtc_timing_parameters *bp_params)
1664 {
1665 struct bios_parser *bp = BP_FROM_DCB(dcb);
1666
1667 if (!bp->cmd_tbl.set_crtc_timing)
1668 return BP_RESULT_FAILURE;
1669
1670 return bp->cmd_tbl.set_crtc_timing(bp, bp_params);
1671 }
1672
bios_parser_enable_crtc(struct dc_bios * dcb,enum controller_id id,bool enable)1673 static enum bp_result bios_parser_enable_crtc(
1674 struct dc_bios *dcb,
1675 enum controller_id id,
1676 bool enable)
1677 {
1678 struct bios_parser *bp = BP_FROM_DCB(dcb);
1679
1680 if (!bp->cmd_tbl.enable_crtc)
1681 return BP_RESULT_FAILURE;
1682
1683 return bp->cmd_tbl.enable_crtc(bp, id, enable);
1684 }
1685
bios_parser_enable_disp_power_gating(struct dc_bios * dcb,enum controller_id controller_id,enum bp_pipe_control_action action)1686 static enum bp_result bios_parser_enable_disp_power_gating(
1687 struct dc_bios *dcb,
1688 enum controller_id controller_id,
1689 enum bp_pipe_control_action action)
1690 {
1691 struct bios_parser *bp = BP_FROM_DCB(dcb);
1692
1693 if (!bp->cmd_tbl.enable_disp_power_gating)
1694 return BP_RESULT_FAILURE;
1695
1696 return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,
1697 action);
1698 }
1699
bios_parser_enable_lvtma_control(struct dc_bios * dcb,uint8_t uc_pwr_on,uint8_t pwrseq_instance,uint8_t bypass_panel_control_wait)1700 static enum bp_result bios_parser_enable_lvtma_control(
1701 struct dc_bios *dcb,
1702 uint8_t uc_pwr_on,
1703 uint8_t pwrseq_instance,
1704 uint8_t bypass_panel_control_wait)
1705 {
1706 struct bios_parser *bp = BP_FROM_DCB(dcb);
1707
1708 if (!bp->cmd_tbl.enable_lvtma_control)
1709 return BP_RESULT_FAILURE;
1710
1711 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on, pwrseq_instance, bypass_panel_control_wait);
1712 }
1713
bios_parser_is_accelerated_mode(struct dc_bios * dcb)1714 static bool bios_parser_is_accelerated_mode(
1715 struct dc_bios *dcb)
1716 {
1717 return bios_is_accelerated_mode(dcb);
1718 }
1719
1720 /**
1721 * bios_parser_set_scratch_critical_state - update critical state bit
1722 * in VBIOS scratch register
1723 *
1724 * @dcb: pointer to the DC BIO
1725 * @state: set or reset state
1726 */
bios_parser_set_scratch_critical_state(struct dc_bios * dcb,bool state)1727 static void bios_parser_set_scratch_critical_state(
1728 struct dc_bios *dcb,
1729 bool state)
1730 {
1731 bios_set_scratch_critical_state(dcb, state);
1732 }
1733
bios_parser_get_firmware_info(struct dc_bios * dcb,struct dc_firmware_info * info)1734 static enum bp_result bios_parser_get_firmware_info(
1735 struct dc_bios *dcb,
1736 struct dc_firmware_info *info)
1737 {
1738 struct bios_parser *bp = BP_FROM_DCB(dcb);
1739 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
1740 struct atom_common_table_header *header;
1741
1742 struct atom_data_revision revision;
1743
1744 if (info && DATA_TABLES(firmwareinfo)) {
1745 header = GET_IMAGE(struct atom_common_table_header,
1746 DATA_TABLES(firmwareinfo));
1747 get_atom_data_table_revision(header, &revision);
1748 switch (revision.major) {
1749 case 3:
1750 switch (revision.minor) {
1751 case 1:
1752 result = get_firmware_info_v3_1(bp, info);
1753 break;
1754 case 2:
1755 case 3:
1756 result = get_firmware_info_v3_2(bp, info);
1757 break;
1758 case 4:
1759 result = get_firmware_info_v3_4(bp, info);
1760 break;
1761 case 5:
1762 result = get_firmware_info_v3_5(bp, info);
1763 break;
1764 default:
1765 break;
1766 }
1767 break;
1768 default:
1769 break;
1770 }
1771 }
1772
1773 return result;
1774 }
1775
get_firmware_info_v3_1(struct bios_parser * bp,struct dc_firmware_info * info)1776 static enum bp_result get_firmware_info_v3_1(
1777 struct bios_parser *bp,
1778 struct dc_firmware_info *info)
1779 {
1780 struct atom_firmware_info_v3_1 *firmware_info;
1781 struct atom_firmware_info_v3_2 *firmware_info32;
1782 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1783
1784 if (!info)
1785 return BP_RESULT_BADINPUT;
1786
1787 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_1,
1788 DATA_TABLES(firmwareinfo));
1789 firmware_info32 = GET_IMAGE(struct atom_firmware_info_v3_2,
1790 DATA_TABLES(firmwareinfo));
1791
1792 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1793 DATA_TABLES(dce_info));
1794
1795 if (!firmware_info || !firmware_info32 || !dce_info)
1796 return BP_RESULT_BADBIOSTABLE;
1797
1798 memset(info, 0, sizeof(*info));
1799
1800 /* Pixel clock pll information. */
1801 /* We need to convert from 10KHz units into KHz units */
1802 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1803 info->default_engine_clk = firmware_info->bootup_sclk_in10khz * 10;
1804
1805 /* 27MHz for Vega10: */
1806 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1807
1808 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1809 if (info->pll_info.crystal_frequency == 0)
1810 info->pll_info.crystal_frequency = 27000;
1811 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1812 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1813 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1814
1815 /* Get GPU PLL VCO Clock */
1816
1817 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1818 /* VBIOS gives in 10KHz */
1819 info->smu_gpu_pll_output_freq =
1820 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1821 }
1822
1823 /* These fields are marked as reserved in v3_1, but they appear to be populated
1824 * properly.
1825 */
1826 if (firmware_info32 && firmware_info32->board_i2c_feature_id == 0x2) {
1827 info->oem_i2c_present = true;
1828 info->oem_i2c_obj_id = firmware_info32->board_i2c_feature_gpio_id;
1829 } else {
1830 info->oem_i2c_present = false;
1831 }
1832
1833 return BP_RESULT_OK;
1834 }
1835
get_firmware_info_v3_2(struct bios_parser * bp,struct dc_firmware_info * info)1836 static enum bp_result get_firmware_info_v3_2(
1837 struct bios_parser *bp,
1838 struct dc_firmware_info *info)
1839 {
1840 struct atom_firmware_info_v3_2 *firmware_info;
1841 struct atom_display_controller_info_v4_1 *dce_info = NULL;
1842 struct atom_common_table_header *header;
1843 struct atom_data_revision revision;
1844 struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
1845 struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
1846
1847 if (!info)
1848 return BP_RESULT_BADINPUT;
1849
1850 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
1851 DATA_TABLES(firmwareinfo));
1852
1853 dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
1854 DATA_TABLES(dce_info));
1855
1856 if (!firmware_info || !dce_info)
1857 return BP_RESULT_BADBIOSTABLE;
1858
1859 memset(info, 0, sizeof(*info));
1860
1861 header = GET_IMAGE(struct atom_common_table_header,
1862 DATA_TABLES(smu_info));
1863 get_atom_data_table_revision(header, &revision);
1864
1865 if (revision.minor == 2) {
1866 /* Vega12 */
1867 smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
1868 DATA_TABLES(smu_info));
1869 if (!smu_info_v3_2)
1870 return BP_RESULT_BADBIOSTABLE;
1871
1872 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_2->gpuclk_ss_percentage);
1873
1874 info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
1875 } else if (revision.minor == 3) {
1876 /* Vega20 */
1877 smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
1878 DATA_TABLES(smu_info));
1879 if (!smu_info_v3_3)
1880 return BP_RESULT_BADBIOSTABLE;
1881
1882 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_3->gpuclk_ss_percentage);
1883
1884 info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
1885 }
1886
1887 // We need to convert from 10KHz units into KHz units.
1888 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
1889
1890 /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
1891 info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
1892 /* Hardcode frequency if BIOS gives no DCE Ref Clk */
1893 if (info->pll_info.crystal_frequency == 0) {
1894 if (revision.minor == 2)
1895 info->pll_info.crystal_frequency = 27000;
1896 else if (revision.minor == 3)
1897 info->pll_info.crystal_frequency = 100000;
1898 }
1899 /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
1900 info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
1901 info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
1902
1903 /* Get GPU PLL VCO Clock */
1904 if (bp->cmd_tbl.get_smu_clock_info != NULL) {
1905 if (revision.minor == 2)
1906 info->smu_gpu_pll_output_freq =
1907 bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
1908 else if (revision.minor == 3)
1909 info->smu_gpu_pll_output_freq =
1910 bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
1911 }
1912
1913 if (firmware_info->board_i2c_feature_id == 0x2) {
1914 info->oem_i2c_present = true;
1915 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
1916 } else {
1917 info->oem_i2c_present = false;
1918 }
1919
1920 return BP_RESULT_OK;
1921 }
1922
get_firmware_info_v3_4(struct bios_parser * bp,struct dc_firmware_info * info)1923 static enum bp_result get_firmware_info_v3_4(
1924 struct bios_parser *bp,
1925 struct dc_firmware_info *info)
1926 {
1927 struct atom_firmware_info_v3_4 *firmware_info;
1928 struct atom_common_table_header *header;
1929 struct atom_data_revision revision;
1930 struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
1931 struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
1932
1933 struct atom_smu_info_v3_5 *smu_info_v3_5 = NULL;
1934 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
1935 struct atom_smu_info_v4_0 *smu_info_v4_0 = NULL;
1936
1937 if (!info)
1938 return BP_RESULT_BADINPUT;
1939
1940 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
1941 DATA_TABLES(firmwareinfo));
1942
1943 if (!firmware_info)
1944 return BP_RESULT_BADBIOSTABLE;
1945
1946 memset(info, 0, sizeof(*info));
1947
1948 header = GET_IMAGE(struct atom_common_table_header,
1949 DATA_TABLES(dce_info));
1950
1951 get_atom_data_table_revision(header, &revision);
1952
1953 switch (revision.major) {
1954 case 4:
1955 switch (revision.minor) {
1956 case 5:
1957 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
1958 DATA_TABLES(dce_info));
1959
1960 if (!dce_info_v4_5)
1961 return BP_RESULT_BADBIOSTABLE;
1962
1963 /* 100MHz expected */
1964 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
1965 info->dp_phy_ref_clk = dce_info_v4_5->dpphy_refclk_10khz * 10;
1966 /* 50MHz expected */
1967 info->i2c_engine_ref_clk = dce_info_v4_5->i2c_engine_refclk_10khz * 10;
1968
1969 /* For DCN32/321 Display PLL VCO Frequency from dce_info_v4_5 may not be reliable */
1970 break;
1971
1972 case 4:
1973 dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
1974 DATA_TABLES(dce_info));
1975
1976 if (!dce_info_v4_4)
1977 return BP_RESULT_BADBIOSTABLE;
1978
1979 /* 100MHz expected */
1980 info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
1981 info->dp_phy_ref_clk = dce_info_v4_4->dpphy_refclk_10khz * 10;
1982 /* 50MHz expected */
1983 info->i2c_engine_ref_clk = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
1984
1985 /* Get SMU Display PLL VCO Frequency in KHz*/
1986 info->smu_gpu_pll_output_freq = dce_info_v4_4->dispclk_pll_vco_freq * 10;
1987 break;
1988
1989 default:
1990 /* should not come here, keep as backup, as was before */
1991 dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
1992 DATA_TABLES(dce_info));
1993
1994 if (!dce_info_v4_1)
1995 return BP_RESULT_BADBIOSTABLE;
1996
1997 info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
1998 info->dp_phy_ref_clk = dce_info_v4_1->dpphy_refclk_10khz * 10;
1999 info->i2c_engine_ref_clk = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
2000 break;
2001 }
2002 break;
2003
2004 default:
2005 ASSERT(0);
2006 break;
2007 }
2008
2009 header = GET_IMAGE(struct atom_common_table_header,
2010 DATA_TABLES(smu_info));
2011 get_atom_data_table_revision(header, &revision);
2012
2013 switch (revision.major) {
2014 case 3:
2015 switch (revision.minor) {
2016 case 5:
2017 smu_info_v3_5 = GET_IMAGE(struct atom_smu_info_v3_5,
2018 DATA_TABLES(smu_info));
2019
2020 if (!smu_info_v3_5)
2021 return BP_RESULT_BADBIOSTABLE;
2022 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", smu_info_v3_5->gpuclk_ss_percentage);
2023 info->default_engine_clk = smu_info_v3_5->bootup_dcefclk_10khz * 10;
2024 break;
2025
2026 default:
2027 break;
2028 }
2029 break;
2030
2031 case 4:
2032 switch (revision.minor) {
2033 case 0:
2034 smu_info_v4_0 = GET_IMAGE(struct atom_smu_info_v4_0,
2035 DATA_TABLES(smu_info));
2036
2037 if (!smu_info_v4_0)
2038 return BP_RESULT_BADBIOSTABLE;
2039
2040 /* For DCN32/321 bootup DCFCLK from smu_info_v4_0 may not be reliable */
2041 break;
2042
2043 default:
2044 break;
2045 }
2046 break;
2047
2048 default:
2049 break;
2050 }
2051
2052 // We need to convert from 10KHz units into KHz units.
2053 info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
2054
2055 if (firmware_info->board_i2c_feature_id == 0x2) {
2056 info->oem_i2c_present = true;
2057 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2058 } else {
2059 info->oem_i2c_present = false;
2060 }
2061
2062 return BP_RESULT_OK;
2063 }
2064
get_firmware_info_v3_5(struct bios_parser * bp,struct dc_firmware_info * info)2065 static enum bp_result get_firmware_info_v3_5(
2066 struct bios_parser *bp,
2067 struct dc_firmware_info *info)
2068 {
2069 struct atom_firmware_info_v3_5 *firmware_info;
2070 struct atom_common_table_header *header;
2071 struct atom_data_revision revision;
2072 struct atom_display_controller_info_v4_5 *dce_info_v4_5 = NULL;
2073
2074 if (!info)
2075 return BP_RESULT_BADINPUT;
2076
2077 firmware_info = GET_IMAGE(struct atom_firmware_info_v3_5,
2078 DATA_TABLES(firmwareinfo));
2079
2080 if (!firmware_info)
2081 return BP_RESULT_BADBIOSTABLE;
2082
2083 memset(info, 0, sizeof(*info));
2084
2085 if (firmware_info->board_i2c_feature_id == 0x2) {
2086 info->oem_i2c_present = true;
2087 info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
2088 } else {
2089 info->oem_i2c_present = false;
2090 }
2091
2092 header = GET_IMAGE(struct atom_common_table_header,
2093 DATA_TABLES(dce_info));
2094
2095 get_atom_data_table_revision(header, &revision);
2096
2097 switch (revision.major) {
2098 case 4:
2099 switch (revision.minor) {
2100 case 5:
2101 dce_info_v4_5 = GET_IMAGE(struct atom_display_controller_info_v4_5,
2102 DATA_TABLES(dce_info));
2103
2104 if (!dce_info_v4_5)
2105 return BP_RESULT_BADBIOSTABLE;
2106
2107 /* 100MHz expected */
2108 info->pll_info.crystal_frequency = dce_info_v4_5->dce_refclk_10khz * 10;
2109 break;
2110 default:
2111 break;
2112 }
2113 break;
2114 default:
2115 break;
2116 }
2117
2118
2119 return BP_RESULT_OK;
2120 }
2121
bios_parser_get_encoder_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_encoder_cap_info * info)2122 static enum bp_result bios_parser_get_encoder_cap_info(
2123 struct dc_bios *dcb,
2124 struct graphics_object_id object_id,
2125 struct bp_encoder_cap_info *info)
2126 {
2127 struct bios_parser *bp = BP_FROM_DCB(dcb);
2128 struct atom_display_object_path_v2 *object;
2129 struct atom_encoder_caps_record *record = NULL;
2130
2131 if (!info)
2132 return BP_RESULT_BADINPUT;
2133
2134 #if defined(CONFIG_DRM_AMD_DC_FP)
2135 /* encoder cap record not available in v1_5 */
2136 if (bp->object_info_tbl.revision.minor == 5)
2137 return BP_RESULT_NORECORD;
2138 #endif
2139
2140 object = get_bios_object(bp, object_id);
2141
2142 if (!object)
2143 return BP_RESULT_BADINPUT;
2144
2145 record = get_encoder_cap_record(bp, object);
2146 if (!record)
2147 return BP_RESULT_NORECORD;
2148 DC_LOG_BIOS("record->encodercaps 0x%x for object_id 0x%x", record->encodercaps, object_id.id);
2149
2150 info->DP_HBR2_CAP = (record->encodercaps &
2151 ATOM_ENCODER_CAP_RECORD_HBR2) ? 1 : 0;
2152 info->DP_HBR2_EN = (record->encodercaps &
2153 ATOM_ENCODER_CAP_RECORD_HBR2_EN) ? 1 : 0;
2154 info->DP_HBR3_EN = (record->encodercaps &
2155 ATOM_ENCODER_CAP_RECORD_HBR3_EN) ? 1 : 0;
2156 info->HDMI_6GB_EN = (record->encodercaps &
2157 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN) ? 1 : 0;
2158 info->IS_DP2_CAPABLE = (record->encodercaps &
2159 ATOM_ENCODER_CAP_RECORD_DP2) ? 1 : 0;
2160 info->DP_UHBR10_EN = (record->encodercaps &
2161 ATOM_ENCODER_CAP_RECORD_UHBR10_EN) ? 1 : 0;
2162 info->DP_UHBR13_5_EN = (record->encodercaps &
2163 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN) ? 1 : 0;
2164 info->DP_UHBR20_EN = (record->encodercaps &
2165 ATOM_ENCODER_CAP_RECORD_UHBR20_EN) ? 1 : 0;
2166 info->DP_IS_USB_C = (record->encodercaps &
2167 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE) ? 1 : 0;
2168 DC_LOG_BIOS("\t info->DP_IS_USB_C %d", info->DP_IS_USB_C);
2169
2170 return BP_RESULT_OK;
2171 }
2172
2173
get_encoder_cap_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2174 static struct atom_encoder_caps_record *get_encoder_cap_record(
2175 struct bios_parser *bp,
2176 struct atom_display_object_path_v2 *object)
2177 {
2178 struct atom_common_record_header *header;
2179 uint32_t offset;
2180
2181 if (!object) {
2182 BREAK_TO_DEBUGGER(); /* Invalid object */
2183 return NULL;
2184 }
2185
2186 offset = object->encoder_recordoffset + bp->object_info_tbl_offset;
2187
2188 for (;;) {
2189 header = GET_IMAGE(struct atom_common_record_header, offset);
2190
2191 if (!header)
2192 return NULL;
2193
2194 offset += header->record_size;
2195
2196 if (header->record_type == LAST_RECORD_TYPE ||
2197 !header->record_size)
2198 break;
2199
2200 if (header->record_type != ATOM_ENCODER_CAP_RECORD_TYPE)
2201 continue;
2202
2203 if (sizeof(struct atom_encoder_caps_record) <=
2204 header->record_size)
2205 return (struct atom_encoder_caps_record *)header;
2206 }
2207
2208 return NULL;
2209 }
2210
get_disp_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v2 * object)2211 static struct atom_disp_connector_caps_record *get_disp_connector_caps_record(
2212 struct bios_parser *bp,
2213 struct atom_display_object_path_v2 *object)
2214 {
2215 struct atom_common_record_header *header;
2216 uint32_t offset;
2217
2218 if (!object) {
2219 BREAK_TO_DEBUGGER(); /* Invalid object */
2220 return NULL;
2221 }
2222
2223 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2224
2225 for (;;) {
2226 header = GET_IMAGE(struct atom_common_record_header, offset);
2227
2228 if (!header)
2229 return NULL;
2230
2231 offset += header->record_size;
2232
2233 if (header->record_type == LAST_RECORD_TYPE ||
2234 !header->record_size)
2235 break;
2236
2237 if (header->record_type != ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE)
2238 continue;
2239
2240 if (sizeof(struct atom_disp_connector_caps_record) <=
2241 header->record_size)
2242 return (struct atom_disp_connector_caps_record *)header;
2243 }
2244
2245 return NULL;
2246 }
2247
get_connector_caps_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2248 static struct atom_connector_caps_record *get_connector_caps_record(struct bios_parser *bp,
2249 struct atom_display_object_path_v3 *object)
2250 {
2251 struct atom_common_record_header *header;
2252 uint32_t offset;
2253
2254 if (!object) {
2255 BREAK_TO_DEBUGGER(); /* Invalid object */
2256 return NULL;
2257 }
2258
2259 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2260
2261 for (;;) {
2262 header = GET_IMAGE(struct atom_common_record_header, offset);
2263
2264 if (!header)
2265 return NULL;
2266
2267 offset += header->record_size;
2268
2269 if (header->record_type == ATOM_RECORD_END_TYPE ||
2270 !header->record_size)
2271 break;
2272
2273 if (header->record_type != ATOM_CONNECTOR_CAP_RECORD_TYPE)
2274 continue;
2275
2276 if (sizeof(struct atom_connector_caps_record) <= header->record_size)
2277 return (struct atom_connector_caps_record *)header;
2278 }
2279
2280 return NULL;
2281 }
2282
bios_parser_get_disp_connector_caps_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_disp_connector_caps_info * info)2283 static enum bp_result bios_parser_get_disp_connector_caps_info(
2284 struct dc_bios *dcb,
2285 struct graphics_object_id object_id,
2286 struct bp_disp_connector_caps_info *info)
2287 {
2288 struct bios_parser *bp = BP_FROM_DCB(dcb);
2289 struct atom_display_object_path_v2 *object;
2290 struct atom_display_object_path_v3 *object_path_v3;
2291 struct atom_connector_caps_record *record_path_v3;
2292 struct atom_disp_connector_caps_record *record = NULL;
2293
2294 if (!info)
2295 return BP_RESULT_BADINPUT;
2296
2297 switch (bp->object_info_tbl.revision.minor) {
2298 case 4:
2299 default:
2300 object = get_bios_object(bp, object_id);
2301
2302 if (!object)
2303 return BP_RESULT_BADINPUT;
2304
2305 record = get_disp_connector_caps_record(bp, object);
2306 if (!record)
2307 return BP_RESULT_NORECORD;
2308
2309 info->INTERNAL_DISPLAY =
2310 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY) ? 1 : 0;
2311 info->INTERNAL_DISPLAY_BL =
2312 (record->connectcaps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL) ? 1 : 0;
2313 break;
2314 case 5:
2315 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2316
2317 if (!object_path_v3)
2318 return BP_RESULT_BADINPUT;
2319
2320 record_path_v3 = get_connector_caps_record(bp, object_path_v3);
2321 if (!record_path_v3)
2322 return BP_RESULT_NORECORD;
2323
2324 info->INTERNAL_DISPLAY = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY)
2325 ? 1 : 0;
2326 info->INTERNAL_DISPLAY_BL = (record_path_v3->connector_caps & ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL)
2327 ? 1 : 0;
2328 break;
2329 }
2330
2331 return BP_RESULT_OK;
2332 }
2333
get_connector_speed_cap_record(struct bios_parser * bp,struct atom_display_object_path_v3 * object)2334 static struct atom_connector_speed_record *get_connector_speed_cap_record(struct bios_parser *bp,
2335 struct atom_display_object_path_v3 *object)
2336 {
2337 struct atom_common_record_header *header;
2338 uint32_t offset;
2339
2340 if (!object) {
2341 BREAK_TO_DEBUGGER(); /* Invalid object */
2342 return NULL;
2343 }
2344
2345 offset = object->disp_recordoffset + bp->object_info_tbl_offset;
2346
2347 for (;;) {
2348 header = GET_IMAGE(struct atom_common_record_header, offset);
2349
2350 if (!header)
2351 return NULL;
2352
2353 offset += header->record_size;
2354
2355 if (header->record_type == ATOM_RECORD_END_TYPE ||
2356 !header->record_size)
2357 break;
2358
2359 if (header->record_type != ATOM_CONNECTOR_SPEED_UPTO)
2360 continue;
2361
2362 if (sizeof(struct atom_connector_speed_record) <= header->record_size)
2363 return (struct atom_connector_speed_record *)header;
2364 }
2365
2366 return NULL;
2367 }
2368
bios_parser_get_connector_speed_cap_info(struct dc_bios * dcb,struct graphics_object_id object_id,struct bp_connector_speed_cap_info * info)2369 static enum bp_result bios_parser_get_connector_speed_cap_info(
2370 struct dc_bios *dcb,
2371 struct graphics_object_id object_id,
2372 struct bp_connector_speed_cap_info *info)
2373 {
2374 struct bios_parser *bp = BP_FROM_DCB(dcb);
2375 struct atom_display_object_path_v3 *object_path_v3;
2376 //struct atom_connector_speed_record *record = NULL;
2377 struct atom_connector_speed_record *record;
2378
2379 if (!info)
2380 return BP_RESULT_BADINPUT;
2381
2382 object_path_v3 = get_bios_object_from_path_v3(bp, object_id);
2383
2384 if (!object_path_v3)
2385 return BP_RESULT_BADINPUT;
2386
2387 record = get_connector_speed_cap_record(bp, object_path_v3);
2388 if (!record)
2389 return BP_RESULT_NORECORD;
2390
2391 info->DP_HBR2_EN = (record->connector_max_speed >= 5400) ? 1 : 0;
2392 info->DP_HBR3_EN = (record->connector_max_speed >= 8100) ? 1 : 0;
2393 info->HDMI_6GB_EN = (record->connector_max_speed >= 5940) ? 1 : 0;
2394 info->DP_UHBR10_EN = (record->connector_max_speed >= 10000) ? 1 : 0;
2395 info->DP_UHBR13_5_EN = (record->connector_max_speed >= 13500) ? 1 : 0;
2396 info->DP_UHBR20_EN = (record->connector_max_speed >= 20000) ? 1 : 0;
2397 return BP_RESULT_OK;
2398 }
2399
get_vram_info_v23(struct bios_parser * bp,struct dc_vram_info * info)2400 static enum bp_result get_vram_info_v23(
2401 struct bios_parser *bp,
2402 struct dc_vram_info *info)
2403 {
2404 struct atom_vram_info_header_v2_3 *info_v23;
2405 static enum bp_result result = BP_RESULT_OK;
2406
2407 info_v23 = GET_IMAGE(struct atom_vram_info_header_v2_3,
2408 DATA_TABLES(vram_info));
2409
2410 if (info_v23 == NULL)
2411 return BP_RESULT_BADBIOSTABLE;
2412
2413 info->num_chans = info_v23->vram_module[0].channel_num;
2414 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2415
2416 return result;
2417 }
2418
get_vram_info_v24(struct bios_parser * bp,struct dc_vram_info * info)2419 static enum bp_result get_vram_info_v24(
2420 struct bios_parser *bp,
2421 struct dc_vram_info *info)
2422 {
2423 struct atom_vram_info_header_v2_4 *info_v24;
2424 static enum bp_result result = BP_RESULT_OK;
2425
2426 info_v24 = GET_IMAGE(struct atom_vram_info_header_v2_4,
2427 DATA_TABLES(vram_info));
2428
2429 if (info_v24 == NULL)
2430 return BP_RESULT_BADBIOSTABLE;
2431
2432 info->num_chans = info_v24->vram_module[0].channel_num;
2433 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8;
2434
2435 return result;
2436 }
2437
get_vram_info_v25(struct bios_parser * bp,struct dc_vram_info * info)2438 static enum bp_result get_vram_info_v25(
2439 struct bios_parser *bp,
2440 struct dc_vram_info *info)
2441 {
2442 struct atom_vram_info_header_v2_5 *info_v25;
2443 static enum bp_result result = BP_RESULT_OK;
2444
2445 info_v25 = GET_IMAGE(struct atom_vram_info_header_v2_5,
2446 DATA_TABLES(vram_info));
2447
2448 if (info_v25 == NULL)
2449 return BP_RESULT_BADBIOSTABLE;
2450
2451 info->num_chans = info_v25->vram_module[0].channel_num;
2452 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8;
2453
2454 return result;
2455 }
2456
get_vram_info_v30(struct bios_parser * bp,struct dc_vram_info * info)2457 static enum bp_result get_vram_info_v30(
2458 struct bios_parser *bp,
2459 struct dc_vram_info *info)
2460 {
2461 struct atom_vram_info_header_v3_0 *info_v30;
2462 enum bp_result result = BP_RESULT_OK;
2463
2464 info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2465 DATA_TABLES(vram_info));
2466
2467 if (info_v30 == NULL)
2468 return BP_RESULT_BADBIOSTABLE;
2469
2470 info->num_chans = info_v30->channel_num;
2471 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2472
2473 return result;
2474 }
2475
get_vram_info_from_umc_info_v40(struct bios_parser * bp,struct dc_vram_info * info)2476 static enum bp_result get_vram_info_from_umc_info_v40(
2477 struct bios_parser *bp,
2478 struct dc_vram_info *info)
2479 {
2480 struct atom_umc_info_v4_0 *info_v40;
2481 enum bp_result result = BP_RESULT_OK;
2482
2483 info_v40 = GET_IMAGE(struct atom_umc_info_v4_0,
2484 DATA_TABLES(umc_info));
2485
2486 if (info_v40 == NULL)
2487 return BP_RESULT_BADBIOSTABLE;
2488
2489 info->num_chans = info_v40->channel_num;
2490 info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8;
2491
2492 return result;
2493 }
2494
2495 /*
2496 * get_integrated_info_v11
2497 *
2498 * @brief
2499 * Get V8 integrated BIOS information
2500 *
2501 * @param
2502 * bios_parser *bp - [in]BIOS parser handler to get master data table
2503 * integrated_info *info - [out] store and output integrated info
2504 *
2505 * @return
2506 * static enum bp_result - BP_RESULT_OK if information is available,
2507 * BP_RESULT_BADBIOSTABLE otherwise.
2508 */
get_integrated_info_v11(struct bios_parser * bp,struct integrated_info * info)2509 static enum bp_result get_integrated_info_v11(
2510 struct bios_parser *bp,
2511 struct integrated_info *info)
2512 {
2513 struct atom_integrated_system_info_v1_11 *info_v11;
2514 uint32_t i;
2515
2516 info_v11 = GET_IMAGE(struct atom_integrated_system_info_v1_11,
2517 DATA_TABLES(integratedsysteminfo));
2518
2519 if (info_v11 == NULL)
2520 return BP_RESULT_BADBIOSTABLE;
2521
2522 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v11->gpuclk_ss_percentage);
2523
2524 info->gpu_cap_info =
2525 le32_to_cpu(info_v11->gpucapinfo);
2526 /*
2527 * system_config: Bit[0] = 0 : PCIE power gating disabled
2528 * = 1 : PCIE power gating enabled
2529 * Bit[1] = 0 : DDR-PLL shut down disabled
2530 * = 1 : DDR-PLL shut down enabled
2531 * Bit[2] = 0 : DDR-PLL power down disabled
2532 * = 1 : DDR-PLL power down enabled
2533 */
2534 info->system_config = le32_to_cpu(info_v11->system_config);
2535 info->cpu_cap_info = le32_to_cpu(info_v11->cpucapinfo);
2536 info->memory_type = info_v11->memorytype;
2537 info->ma_channel_number = info_v11->umachannelnumber;
2538 info->lvds_ss_percentage =
2539 le16_to_cpu(info_v11->lvds_ss_percentage);
2540 info->dp_ss_control =
2541 le16_to_cpu(info_v11->reserved1);
2542 info->lvds_sspread_rate_in_10hz =
2543 le16_to_cpu(info_v11->lvds_ss_rate_10hz);
2544 info->hdmi_ss_percentage =
2545 le16_to_cpu(info_v11->hdmi_ss_percentage);
2546 info->hdmi_sspread_rate_in_10hz =
2547 le16_to_cpu(info_v11->hdmi_ss_rate_10hz);
2548 info->dvi_ss_percentage =
2549 le16_to_cpu(info_v11->dvi_ss_percentage);
2550 info->dvi_sspread_rate_in_10_hz =
2551 le16_to_cpu(info_v11->dvi_ss_rate_10hz);
2552 info->lvds_misc = info_v11->lvds_misc;
2553 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2554 info->ext_disp_conn_info.gu_id[i] =
2555 info_v11->extdispconninfo.guid[i];
2556 }
2557
2558 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2559 info->ext_disp_conn_info.path[i].device_connector_id =
2560 object_id_from_bios_object_id(
2561 le16_to_cpu(info_v11->extdispconninfo.path[i].connectorobjid));
2562
2563 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2564 object_id_from_bios_object_id(
2565 le16_to_cpu(
2566 info_v11->extdispconninfo.path[i].ext_encoder_objid));
2567
2568 info->ext_disp_conn_info.path[i].device_tag =
2569 le16_to_cpu(
2570 info_v11->extdispconninfo.path[i].device_tag);
2571 info->ext_disp_conn_info.path[i].device_acpi_enum =
2572 le16_to_cpu(
2573 info_v11->extdispconninfo.path[i].device_acpi_enum);
2574 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2575 info_v11->extdispconninfo.path[i].auxddclut_index;
2576 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2577 info_v11->extdispconninfo.path[i].hpdlut_index;
2578 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2579 info_v11->extdispconninfo.path[i].channelmapping;
2580 info->ext_disp_conn_info.path[i].caps =
2581 le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
2582 }
2583 info->ext_disp_conn_info.checksum =
2584 info_v11->extdispconninfo.checksum;
2585
2586 info->dp0_ext_hdmi_slv_addr = info_v11->dp0_retimer_set.HdmiSlvAddr;
2587 info->dp0_ext_hdmi_reg_num = info_v11->dp0_retimer_set.HdmiRegNum;
2588 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2589 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2590 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2591 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2592 info_v11->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2593 }
2594 info->dp0_ext_hdmi_6g_reg_num = info_v11->dp0_retimer_set.Hdmi6GRegNum;
2595 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2596 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2597 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2598 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2599 info_v11->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2600 }
2601
2602 info->dp1_ext_hdmi_slv_addr = info_v11->dp1_retimer_set.HdmiSlvAddr;
2603 info->dp1_ext_hdmi_reg_num = info_v11->dp1_retimer_set.HdmiRegNum;
2604 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2605 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2606 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2607 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2608 info_v11->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2609 }
2610 info->dp1_ext_hdmi_6g_reg_num = info_v11->dp1_retimer_set.Hdmi6GRegNum;
2611 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2612 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2613 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2614 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2615 info_v11->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2616 }
2617
2618 info->dp2_ext_hdmi_slv_addr = info_v11->dp2_retimer_set.HdmiSlvAddr;
2619 info->dp2_ext_hdmi_reg_num = info_v11->dp2_retimer_set.HdmiRegNum;
2620 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2621 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2622 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2623 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2624 info_v11->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2625 }
2626 info->dp2_ext_hdmi_6g_reg_num = info_v11->dp2_retimer_set.Hdmi6GRegNum;
2627 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2628 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2629 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2630 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2631 info_v11->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2632 }
2633
2634 info->dp3_ext_hdmi_slv_addr = info_v11->dp3_retimer_set.HdmiSlvAddr;
2635 info->dp3_ext_hdmi_reg_num = info_v11->dp3_retimer_set.HdmiRegNum;
2636 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2637 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2638 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2639 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2640 info_v11->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2641 }
2642 info->dp3_ext_hdmi_6g_reg_num = info_v11->dp3_retimer_set.Hdmi6GRegNum;
2643 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2644 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2645 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2646 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2647 info_v11->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2648 }
2649
2650
2651 /** TODO - review **/
2652 #if 0
2653 info->boot_up_engine_clock = le32_to_cpu(info_v11->ulBootUpEngineClock)
2654 * 10;
2655 info->dentist_vco_freq = le32_to_cpu(info_v11->ulDentistVCOFreq) * 10;
2656 info->boot_up_uma_clock = le32_to_cpu(info_v8->ulBootUpUMAClock) * 10;
2657
2658 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
2659 /* Convert [10KHz] into [KHz] */
2660 info->disp_clk_voltage[i].max_supported_clk =
2661 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].
2662 ulMaximumSupportedCLK) * 10;
2663 info->disp_clk_voltage[i].voltage_index =
2664 le32_to_cpu(info_v11->sDISPCLK_Voltage[i].ulVoltageIndex);
2665 }
2666
2667 info->boot_up_req_display_vector =
2668 le32_to_cpu(info_v11->ulBootUpReqDisplayVector);
2669 info->boot_up_nb_voltage =
2670 le16_to_cpu(info_v11->usBootUpNBVoltage);
2671 info->ext_disp_conn_info_offset =
2672 le16_to_cpu(info_v11->usExtDispConnInfoOffset);
2673 info->gmc_restore_reset_time =
2674 le32_to_cpu(info_v11->ulGMCRestoreResetTime);
2675 info->minimum_n_clk =
2676 le32_to_cpu(info_v11->ulNbpStateNClkFreq[0]);
2677 for (i = 1; i < 4; ++i)
2678 info->minimum_n_clk =
2679 info->minimum_n_clk <
2680 le32_to_cpu(info_v11->ulNbpStateNClkFreq[i]) ?
2681 info->minimum_n_clk : le32_to_cpu(
2682 info_v11->ulNbpStateNClkFreq[i]);
2683
2684 info->idle_n_clk = le32_to_cpu(info_v11->ulIdleNClk);
2685 info->ddr_dll_power_up_time =
2686 le32_to_cpu(info_v11->ulDDR_DLL_PowerUpTime);
2687 info->ddr_pll_power_up_time =
2688 le32_to_cpu(info_v11->ulDDR_PLL_PowerUpTime);
2689 info->pcie_clk_ss_type = le16_to_cpu(info_v11->usPCIEClkSSType);
2690 info->max_lvds_pclk_freq_in_single_link =
2691 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2692 info->max_lvds_pclk_freq_in_single_link =
2693 le16_to_cpu(info_v11->usMaxLVDSPclkFreqInSingleLink);
2694 info->lvds_pwr_on_seq_dig_on_to_de_in_4ms =
2695 info_v11->ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
2696 info->lvds_pwr_on_seq_de_to_vary_bl_in_4ms =
2697 info_v11->ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
2698 info->lvds_pwr_on_seq_vary_bl_to_blon_in_4ms =
2699 info_v11->ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
2700 info->lvds_pwr_off_seq_vary_bl_to_de_in4ms =
2701 info_v11->ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
2702 info->lvds_pwr_off_seq_de_to_dig_on_in4ms =
2703 info_v11->ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
2704 info->lvds_pwr_off_seq_blon_to_vary_bl_in_4ms =
2705 info_v11->ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
2706 info->lvds_off_to_on_delay_in_4ms =
2707 info_v11->ucLVDSOffToOnDelay_in4Ms;
2708 info->lvds_bit_depth_control_val =
2709 le32_to_cpu(info_v11->ulLCDBitDepthControlVal);
2710
2711 for (i = 0; i < NUMBER_OF_AVAILABLE_SCLK; ++i) {
2712 /* Convert [10KHz] into [KHz] */
2713 info->avail_s_clk[i].supported_s_clk =
2714 le32_to_cpu(info_v11->sAvail_SCLK[i].ulSupportedSCLK)
2715 * 10;
2716 info->avail_s_clk[i].voltage_index =
2717 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageIndex);
2718 info->avail_s_clk[i].voltage_id =
2719 le16_to_cpu(info_v11->sAvail_SCLK[i].usVoltageID);
2720 }
2721 #endif /* TODO*/
2722
2723 return BP_RESULT_OK;
2724 }
2725
get_integrated_info_v2_1(struct bios_parser * bp,struct integrated_info * info)2726 static enum bp_result get_integrated_info_v2_1(
2727 struct bios_parser *bp,
2728 struct integrated_info *info)
2729 {
2730 struct atom_integrated_system_info_v2_1 *info_v2_1;
2731 uint32_t i;
2732
2733 info_v2_1 = GET_IMAGE(struct atom_integrated_system_info_v2_1,
2734 DATA_TABLES(integratedsysteminfo));
2735
2736 if (info_v2_1 == NULL)
2737 return BP_RESULT_BADBIOSTABLE;
2738
2739 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_1->gpuclk_ss_percentage);
2740
2741 info->gpu_cap_info =
2742 le32_to_cpu(info_v2_1->gpucapinfo);
2743 /*
2744 * system_config: Bit[0] = 0 : PCIE power gating disabled
2745 * = 1 : PCIE power gating enabled
2746 * Bit[1] = 0 : DDR-PLL shut down disabled
2747 * = 1 : DDR-PLL shut down enabled
2748 * Bit[2] = 0 : DDR-PLL power down disabled
2749 * = 1 : DDR-PLL power down enabled
2750 */
2751 info->system_config = le32_to_cpu(info_v2_1->system_config);
2752 info->cpu_cap_info = le32_to_cpu(info_v2_1->cpucapinfo);
2753 info->memory_type = info_v2_1->memorytype;
2754 info->ma_channel_number = info_v2_1->umachannelnumber;
2755 info->dp_ss_control =
2756 le16_to_cpu(info_v2_1->reserved1);
2757
2758 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2759 info->ext_disp_conn_info.gu_id[i] =
2760 info_v2_1->extdispconninfo.guid[i];
2761 }
2762
2763 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2764 info->ext_disp_conn_info.path[i].device_connector_id =
2765 object_id_from_bios_object_id(
2766 le16_to_cpu(info_v2_1->extdispconninfo.path[i].connectorobjid));
2767
2768 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2769 object_id_from_bios_object_id(
2770 le16_to_cpu(
2771 info_v2_1->extdispconninfo.path[i].ext_encoder_objid));
2772
2773 info->ext_disp_conn_info.path[i].device_tag =
2774 le16_to_cpu(
2775 info_v2_1->extdispconninfo.path[i].device_tag);
2776 info->ext_disp_conn_info.path[i].device_acpi_enum =
2777 le16_to_cpu(
2778 info_v2_1->extdispconninfo.path[i].device_acpi_enum);
2779 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2780 info_v2_1->extdispconninfo.path[i].auxddclut_index;
2781 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2782 info_v2_1->extdispconninfo.path[i].hpdlut_index;
2783 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2784 info_v2_1->extdispconninfo.path[i].channelmapping;
2785 info->ext_disp_conn_info.path[i].caps =
2786 le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
2787 }
2788
2789 info->ext_disp_conn_info.checksum =
2790 info_v2_1->extdispconninfo.checksum;
2791 info->dp0_ext_hdmi_slv_addr = info_v2_1->dp0_retimer_set.HdmiSlvAddr;
2792 info->dp0_ext_hdmi_reg_num = info_v2_1->dp0_retimer_set.HdmiRegNum;
2793 for (i = 0; i < info->dp0_ext_hdmi_reg_num; i++) {
2794 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_index =
2795 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2796 info->dp0_ext_hdmi_reg_settings[i].i2c_reg_val =
2797 info_v2_1->dp0_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2798 }
2799 info->dp0_ext_hdmi_6g_reg_num = info_v2_1->dp0_retimer_set.Hdmi6GRegNum;
2800 for (i = 0; i < info->dp0_ext_hdmi_6g_reg_num; i++) {
2801 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2802 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2803 info->dp0_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2804 info_v2_1->dp0_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2805 }
2806 info->dp1_ext_hdmi_slv_addr = info_v2_1->dp1_retimer_set.HdmiSlvAddr;
2807 info->dp1_ext_hdmi_reg_num = info_v2_1->dp1_retimer_set.HdmiRegNum;
2808 for (i = 0; i < info->dp1_ext_hdmi_reg_num; i++) {
2809 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_index =
2810 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2811 info->dp1_ext_hdmi_reg_settings[i].i2c_reg_val =
2812 info_v2_1->dp1_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2813 }
2814 info->dp1_ext_hdmi_6g_reg_num = info_v2_1->dp1_retimer_set.Hdmi6GRegNum;
2815 for (i = 0; i < info->dp1_ext_hdmi_6g_reg_num; i++) {
2816 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2817 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2818 info->dp1_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2819 info_v2_1->dp1_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2820 }
2821 info->dp2_ext_hdmi_slv_addr = info_v2_1->dp2_retimer_set.HdmiSlvAddr;
2822 info->dp2_ext_hdmi_reg_num = info_v2_1->dp2_retimer_set.HdmiRegNum;
2823 for (i = 0; i < info->dp2_ext_hdmi_reg_num; i++) {
2824 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_index =
2825 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2826 info->dp2_ext_hdmi_reg_settings[i].i2c_reg_val =
2827 info_v2_1->dp2_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2828 }
2829 info->dp2_ext_hdmi_6g_reg_num = info_v2_1->dp2_retimer_set.Hdmi6GRegNum;
2830 for (i = 0; i < info->dp2_ext_hdmi_6g_reg_num; i++) {
2831 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2832 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2833 info->dp2_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2834 info_v2_1->dp2_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2835 }
2836 info->dp3_ext_hdmi_slv_addr = info_v2_1->dp3_retimer_set.HdmiSlvAddr;
2837 info->dp3_ext_hdmi_reg_num = info_v2_1->dp3_retimer_set.HdmiRegNum;
2838 for (i = 0; i < info->dp3_ext_hdmi_reg_num; i++) {
2839 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_index =
2840 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegIndex;
2841 info->dp3_ext_hdmi_reg_settings[i].i2c_reg_val =
2842 info_v2_1->dp3_retimer_set.HdmiRegSetting[i].ucI2cRegVal;
2843 }
2844 info->dp3_ext_hdmi_6g_reg_num = info_v2_1->dp3_retimer_set.Hdmi6GRegNum;
2845 for (i = 0; i < info->dp3_ext_hdmi_6g_reg_num; i++) {
2846 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_index =
2847 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegIndex;
2848 info->dp3_ext_hdmi_6g_reg_settings[i].i2c_reg_val =
2849 info_v2_1->dp3_retimer_set.Hdmi6GhzRegSetting[i].ucI2cRegVal;
2850 }
2851
2852 info->edp1_info.edp_backlight_pwm_hz =
2853 le16_to_cpu(info_v2_1->edp1_info.edp_backlight_pwm_hz);
2854 info->edp1_info.edp_ss_percentage =
2855 le16_to_cpu(info_v2_1->edp1_info.edp_ss_percentage);
2856 info->edp1_info.edp_ss_rate_10hz =
2857 le16_to_cpu(info_v2_1->edp1_info.edp_ss_rate_10hz);
2858 info->edp1_info.edp_pwr_on_off_delay =
2859 info_v2_1->edp1_info.edp_pwr_on_off_delay;
2860 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2861 info_v2_1->edp1_info.edp_pwr_on_vary_bl_to_blon;
2862 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2863 info_v2_1->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2864 info->edp1_info.edp_panel_bpc =
2865 info_v2_1->edp1_info.edp_panel_bpc;
2866 info->edp1_info.edp_bootup_bl_level = info_v2_1->edp1_info.edp_bootup_bl_level;
2867
2868 info->edp2_info.edp_backlight_pwm_hz =
2869 le16_to_cpu(info_v2_1->edp2_info.edp_backlight_pwm_hz);
2870 info->edp2_info.edp_ss_percentage =
2871 le16_to_cpu(info_v2_1->edp2_info.edp_ss_percentage);
2872 info->edp2_info.edp_ss_rate_10hz =
2873 le16_to_cpu(info_v2_1->edp2_info.edp_ss_rate_10hz);
2874 info->edp2_info.edp_pwr_on_off_delay =
2875 info_v2_1->edp2_info.edp_pwr_on_off_delay;
2876 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2877 info_v2_1->edp2_info.edp_pwr_on_vary_bl_to_blon;
2878 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2879 info_v2_1->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2880 info->edp2_info.edp_panel_bpc =
2881 info_v2_1->edp2_info.edp_panel_bpc;
2882 info->edp2_info.edp_bootup_bl_level =
2883 info_v2_1->edp2_info.edp_bootup_bl_level;
2884
2885 return BP_RESULT_OK;
2886 }
2887
get_integrated_info_v2_2(struct bios_parser * bp,struct integrated_info * info)2888 static enum bp_result get_integrated_info_v2_2(
2889 struct bios_parser *bp,
2890 struct integrated_info *info)
2891 {
2892 struct atom_integrated_system_info_v2_2 *info_v2_2;
2893 uint32_t i;
2894
2895 info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
2896 DATA_TABLES(integratedsysteminfo));
2897
2898 if (info_v2_2 == NULL)
2899 return BP_RESULT_BADBIOSTABLE;
2900
2901 DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", info_v2_2->gpuclk_ss_percentage);
2902
2903 info->gpu_cap_info =
2904 le32_to_cpu(info_v2_2->gpucapinfo);
2905 /*
2906 * system_config: Bit[0] = 0 : PCIE power gating disabled
2907 * = 1 : PCIE power gating enabled
2908 * Bit[1] = 0 : DDR-PLL shut down disabled
2909 * = 1 : DDR-PLL shut down enabled
2910 * Bit[2] = 0 : DDR-PLL power down disabled
2911 * = 1 : DDR-PLL power down enabled
2912 */
2913 info->system_config = le32_to_cpu(info_v2_2->system_config);
2914 info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
2915 info->memory_type = info_v2_2->memorytype;
2916 info->ma_channel_number = info_v2_2->umachannelnumber;
2917 info->dp_ss_control =
2918 le16_to_cpu(info_v2_2->reserved1);
2919 info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
2920 info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
2921
2922 for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
2923 info->ext_disp_conn_info.gu_id[i] =
2924 info_v2_2->extdispconninfo.guid[i];
2925 }
2926
2927 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
2928 info->ext_disp_conn_info.path[i].device_connector_id =
2929 object_id_from_bios_object_id(
2930 le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
2931
2932 info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
2933 object_id_from_bios_object_id(
2934 le16_to_cpu(
2935 info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
2936
2937 info->ext_disp_conn_info.path[i].device_tag =
2938 le16_to_cpu(
2939 info_v2_2->extdispconninfo.path[i].device_tag);
2940 info->ext_disp_conn_info.path[i].device_acpi_enum =
2941 le16_to_cpu(
2942 info_v2_2->extdispconninfo.path[i].device_acpi_enum);
2943 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
2944 info_v2_2->extdispconninfo.path[i].auxddclut_index;
2945 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
2946 info_v2_2->extdispconninfo.path[i].hpdlut_index;
2947 info->ext_disp_conn_info.path[i].channel_mapping.raw =
2948 info_v2_2->extdispconninfo.path[i].channelmapping;
2949 info->ext_disp_conn_info.path[i].caps =
2950 le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
2951 }
2952
2953 info->ext_disp_conn_info.checksum =
2954 info_v2_2->extdispconninfo.checksum;
2955 info->ext_disp_conn_info.fixdpvoltageswing =
2956 info_v2_2->extdispconninfo.fixdpvoltageswing;
2957
2958 info->edp1_info.edp_backlight_pwm_hz =
2959 le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
2960 info->edp1_info.edp_ss_percentage =
2961 le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
2962 info->edp1_info.edp_ss_rate_10hz =
2963 le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
2964 info->edp1_info.edp_pwr_on_off_delay =
2965 info_v2_2->edp1_info.edp_pwr_on_off_delay;
2966 info->edp1_info.edp_pwr_on_vary_bl_to_blon =
2967 info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
2968 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
2969 info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
2970 info->edp1_info.edp_panel_bpc =
2971 info_v2_2->edp1_info.edp_panel_bpc;
2972 info->edp1_info.edp_bootup_bl_level =
2973
2974 info->edp2_info.edp_backlight_pwm_hz =
2975 le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
2976 info->edp2_info.edp_ss_percentage =
2977 le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
2978 info->edp2_info.edp_ss_rate_10hz =
2979 le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
2980 info->edp2_info.edp_pwr_on_off_delay =
2981 info_v2_2->edp2_info.edp_pwr_on_off_delay;
2982 info->edp2_info.edp_pwr_on_vary_bl_to_blon =
2983 info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
2984 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
2985 info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
2986 info->edp2_info.edp_panel_bpc =
2987 info_v2_2->edp2_info.edp_panel_bpc;
2988 info->edp2_info.edp_bootup_bl_level =
2989 info_v2_2->edp2_info.edp_bootup_bl_level;
2990
2991 return BP_RESULT_OK;
2992 }
2993
2994 /*
2995 * construct_integrated_info
2996 *
2997 * @brief
2998 * Get integrated BIOS information based on table revision
2999 *
3000 * @param
3001 * bios_parser *bp - [in]BIOS parser handler to get master data table
3002 * integrated_info *info - [out] store and output integrated info
3003 *
3004 * @return
3005 * static enum bp_result - BP_RESULT_OK if information is available,
3006 * BP_RESULT_BADBIOSTABLE otherwise.
3007 */
construct_integrated_info(struct bios_parser * bp,struct integrated_info * info)3008 static enum bp_result construct_integrated_info(
3009 struct bios_parser *bp,
3010 struct integrated_info *info)
3011 {
3012 static enum bp_result result = BP_RESULT_BADBIOSTABLE;
3013
3014 struct atom_common_table_header *header;
3015 struct atom_data_revision revision;
3016
3017 int32_t i;
3018 int32_t j;
3019
3020 if (!info)
3021 return result;
3022
3023 if (info && DATA_TABLES(integratedsysteminfo)) {
3024 header = GET_IMAGE(struct atom_common_table_header,
3025 DATA_TABLES(integratedsysteminfo));
3026
3027 get_atom_data_table_revision(header, &revision);
3028
3029 switch (revision.major) {
3030 case 1:
3031 switch (revision.minor) {
3032 case 11:
3033 case 12:
3034 result = get_integrated_info_v11(bp, info);
3035 break;
3036 default:
3037 return result;
3038 }
3039 break;
3040 case 2:
3041 switch (revision.minor) {
3042 case 1:
3043 result = get_integrated_info_v2_1(bp, info);
3044 break;
3045 case 2:
3046 case 3:
3047 result = get_integrated_info_v2_2(bp, info);
3048 break;
3049 default:
3050 return result;
3051 }
3052 break;
3053 default:
3054 return result;
3055 }
3056 if (result == BP_RESULT_OK) {
3057
3058 DC_LOG_BIOS("edp1:\n"
3059 "\tedp_pwr_on_off_delay = %d\n"
3060 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
3061 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
3062 "\tedp_bootup_bl_level = %d\n",
3063 info->edp1_info.edp_pwr_on_off_delay,
3064 info->edp1_info.edp_pwr_on_vary_bl_to_blon,
3065 info->edp1_info.edp_pwr_down_bloff_to_vary_bloff,
3066 info->edp1_info.edp_bootup_bl_level);
3067 DC_LOG_BIOS("edp2:\n"
3068 "\tedp_pwr_on_off_delayv = %d\n"
3069 "\tedp_pwr_on_vary_bl_to_blon = %d\n"
3070 "\tedp_pwr_down_bloff_to_vary_bloff = %d\n"
3071 "\tedp_bootup_bl_level = %d\n",
3072 info->edp2_info.edp_pwr_on_off_delay,
3073 info->edp2_info.edp_pwr_on_vary_bl_to_blon,
3074 info->edp2_info.edp_pwr_down_bloff_to_vary_bloff,
3075 info->edp2_info.edp_bootup_bl_level);
3076 }
3077 }
3078
3079 if (result != BP_RESULT_OK)
3080 return result;
3081 else {
3082 // Log each external path
3083 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
3084 if (info->ext_disp_conn_info.path[i].device_tag != 0)
3085 DC_LOG_BIOS("integrated_info:For EXTERNAL DISPLAY PATH %d --------------\n"
3086 "DEVICE_TAG: 0x%x\n"
3087 "DEVICE_ACPI_ENUM: 0x%x\n"
3088 "DEVICE_CONNECTOR_ID: 0x%x\n"
3089 "EXT_AUX_DDC_LUT_INDEX: %d\n"
3090 "EXT_HPD_PIN_LUT_INDEX: %d\n"
3091 "EXT_ENCODER_OBJ_ID: 0x%x\n"
3092 "Encoder CAPS: 0x%x\n",
3093 i,
3094 info->ext_disp_conn_info.path[i].device_tag,
3095 info->ext_disp_conn_info.path[i].device_acpi_enum,
3096 info->ext_disp_conn_info.path[i].device_connector_id.id,
3097 info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index,
3098 info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index,
3099 info->ext_disp_conn_info.path[i].ext_encoder_obj_id.id,
3100 info->ext_disp_conn_info.path[i].caps
3101 );
3102 if ((info->ext_disp_conn_info.path[i].caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
3103 DC_LOG_BIOS("BIOS AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3104 else if (bp->base.ctx->dc->config.force_bios_fixed_vs) {
3105 info->ext_disp_conn_info.path[i].caps &= ~AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3106 info->ext_disp_conn_info.path[i].caps |= AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN;
3107 DC_LOG_BIOS("driver forced AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN on path %d\n", i);
3108 }
3109 }
3110 // Log the Checksum and Voltage Swing
3111 DC_LOG_BIOS("Integrated info table CHECKSUM: %d\n"
3112 "Integrated info table FIX_DP_VOLTAGE_SWING: %d\n",
3113 info->ext_disp_conn_info.checksum,
3114 info->ext_disp_conn_info.fixdpvoltageswing);
3115 if (bp->base.ctx->dc->config.force_bios_fixed_vs && info->ext_disp_conn_info.fixdpvoltageswing == 0) {
3116 info->ext_disp_conn_info.fixdpvoltageswing = bp->base.ctx->dc->config.force_bios_fixed_vs & 0xF;
3117 DC_LOG_BIOS("driver forced fixdpvoltageswing = %d\n", info->ext_disp_conn_info.fixdpvoltageswing);
3118 }
3119 }
3120 /* Sort voltage table from low to high*/
3121 for (i = 1; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
3122 for (j = i; j > 0; --j) {
3123 if (info->disp_clk_voltage[j].max_supported_clk <
3124 info->disp_clk_voltage[j-1].max_supported_clk)
3125 swap(info->disp_clk_voltage[j-1], info->disp_clk_voltage[j]);
3126 }
3127 }
3128
3129 return result;
3130 }
3131
bios_parser_get_vram_info(struct dc_bios * dcb,struct dc_vram_info * info)3132 static enum bp_result bios_parser_get_vram_info(
3133 struct dc_bios *dcb,
3134 struct dc_vram_info *info)
3135 {
3136 struct bios_parser *bp = BP_FROM_DCB(dcb);
3137 enum bp_result result = BP_RESULT_BADBIOSTABLE;
3138 struct atom_common_table_header *header;
3139 struct atom_data_revision revision;
3140
3141 // vram info moved to umc_info for DCN4x
3142 if (info && DATA_TABLES(umc_info)) {
3143 header = GET_IMAGE(struct atom_common_table_header,
3144 DATA_TABLES(umc_info));
3145
3146 get_atom_data_table_revision(header, &revision);
3147
3148 switch (revision.major) {
3149 case 4:
3150 switch (revision.minor) {
3151 case 0:
3152 result = get_vram_info_from_umc_info_v40(bp, info);
3153 break;
3154 default:
3155 break;
3156 }
3157 break;
3158 default:
3159 break;
3160 }
3161 }
3162
3163 if (result != BP_RESULT_OK && info && DATA_TABLES(vram_info)) {
3164 header = GET_IMAGE(struct atom_common_table_header,
3165 DATA_TABLES(vram_info));
3166
3167 get_atom_data_table_revision(header, &revision);
3168
3169 switch (revision.major) {
3170 case 2:
3171 switch (revision.minor) {
3172 case 3:
3173 result = get_vram_info_v23(bp, info);
3174 break;
3175 case 4:
3176 result = get_vram_info_v24(bp, info);
3177 break;
3178 case 5:
3179 result = get_vram_info_v25(bp, info);
3180 break;
3181 default:
3182 break;
3183 }
3184 break;
3185
3186 case 3:
3187 switch (revision.minor) {
3188 case 0:
3189 result = get_vram_info_v30(bp, info);
3190 break;
3191 default:
3192 break;
3193 }
3194 break;
3195
3196 default:
3197 return result;
3198 }
3199
3200 }
3201 return result;
3202 }
3203
bios_parser_create_integrated_info(struct dc_bios * dcb)3204 static struct integrated_info *bios_parser_create_integrated_info(
3205 struct dc_bios *dcb)
3206 {
3207 struct bios_parser *bp = BP_FROM_DCB(dcb);
3208 struct integrated_info *info;
3209
3210 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL);
3211
3212 if (info == NULL) {
3213 ASSERT_CRITICAL(0);
3214 return NULL;
3215 }
3216
3217 if (construct_integrated_info(bp, info) == BP_RESULT_OK)
3218 return info;
3219
3220 kfree(info);
3221
3222 return NULL;
3223 }
3224
update_slot_layout_info(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3225 static enum bp_result update_slot_layout_info(
3226 struct dc_bios *dcb,
3227 unsigned int i,
3228 struct slot_layout_info *slot_layout_info)
3229 {
3230 unsigned int record_offset;
3231 unsigned int j;
3232 struct atom_display_object_path_v2 *object;
3233 struct atom_bracket_layout_record *record;
3234 struct atom_common_record_header *record_header;
3235 static enum bp_result result;
3236 struct bios_parser *bp;
3237 struct object_info_table *tbl;
3238 struct display_object_info_table_v1_4 *v1_4;
3239
3240 record = NULL;
3241 record_header = NULL;
3242 result = BP_RESULT_NORECORD;
3243
3244 bp = BP_FROM_DCB(dcb);
3245 tbl = &bp->object_info_tbl;
3246 v1_4 = tbl->v1_4;
3247
3248 object = &v1_4->display_path[i];
3249 record_offset = (unsigned int)
3250 (object->disp_recordoffset) +
3251 (unsigned int)(bp->object_info_tbl_offset);
3252
3253 for (;;) {
3254
3255 record_header = (struct atom_common_record_header *)
3256 GET_IMAGE(struct atom_common_record_header,
3257 record_offset);
3258 if (record_header == NULL) {
3259 result = BP_RESULT_BADBIOSTABLE;
3260 break;
3261 }
3262
3263 /* the end of the list */
3264 if (record_header->record_type == 0xff ||
3265 record_header->record_size == 0) {
3266 break;
3267 }
3268
3269 if (record_header->record_type ==
3270 ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
3271 sizeof(struct atom_bracket_layout_record)
3272 <= record_header->record_size) {
3273 record = (struct atom_bracket_layout_record *)
3274 (record_header);
3275 result = BP_RESULT_OK;
3276 break;
3277 }
3278
3279 record_offset += record_header->record_size;
3280 }
3281
3282 /* return if the record not found */
3283 if (result != BP_RESULT_OK)
3284 return result;
3285
3286 /* get slot sizes */
3287 slot_layout_info->length = record->bracketlen;
3288 slot_layout_info->width = record->bracketwidth;
3289
3290 /* get info for each connector in the slot */
3291 slot_layout_info->num_of_connectors = record->conn_num;
3292 for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
3293 slot_layout_info->connectors[j].connector_type =
3294 (enum connector_layout_type)
3295 (record->conn_info[j].connector_type);
3296 switch (record->conn_info[j].connector_type) {
3297 case CONNECTOR_TYPE_DVI_D:
3298 slot_layout_info->connectors[j].connector_type =
3299 CONNECTOR_LAYOUT_TYPE_DVI_D;
3300 slot_layout_info->connectors[j].length =
3301 CONNECTOR_SIZE_DVI;
3302 break;
3303
3304 case CONNECTOR_TYPE_HDMI:
3305 slot_layout_info->connectors[j].connector_type =
3306 CONNECTOR_LAYOUT_TYPE_HDMI;
3307 slot_layout_info->connectors[j].length =
3308 CONNECTOR_SIZE_HDMI;
3309 break;
3310
3311 case CONNECTOR_TYPE_DISPLAY_PORT:
3312 slot_layout_info->connectors[j].connector_type =
3313 CONNECTOR_LAYOUT_TYPE_DP;
3314 slot_layout_info->connectors[j].length =
3315 CONNECTOR_SIZE_DP;
3316 break;
3317
3318 case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
3319 slot_layout_info->connectors[j].connector_type =
3320 CONNECTOR_LAYOUT_TYPE_MINI_DP;
3321 slot_layout_info->connectors[j].length =
3322 CONNECTOR_SIZE_MINI_DP;
3323 break;
3324
3325 default:
3326 slot_layout_info->connectors[j].connector_type =
3327 CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3328 slot_layout_info->connectors[j].length =
3329 CONNECTOR_SIZE_UNKNOWN;
3330 }
3331
3332 slot_layout_info->connectors[j].position =
3333 record->conn_info[j].position;
3334 slot_layout_info->connectors[j].connector_id =
3335 object_id_from_bios_object_id(
3336 record->conn_info[j].connectorobjid);
3337 }
3338 return result;
3339 }
3340
update_slot_layout_info_v2(struct dc_bios * dcb,unsigned int i,struct slot_layout_info * slot_layout_info)3341 static enum bp_result update_slot_layout_info_v2(
3342 struct dc_bios *dcb,
3343 unsigned int i,
3344 struct slot_layout_info *slot_layout_info)
3345 {
3346 unsigned int record_offset;
3347 struct atom_display_object_path_v3 *object;
3348 struct atom_bracket_layout_record_v2 *record;
3349 struct atom_common_record_header *record_header;
3350 static enum bp_result result;
3351 struct bios_parser *bp;
3352 struct object_info_table *tbl;
3353 struct display_object_info_table_v1_5 *v1_5;
3354 struct graphics_object_id connector_id;
3355
3356 record = NULL;
3357 record_header = NULL;
3358 result = BP_RESULT_NORECORD;
3359
3360 bp = BP_FROM_DCB(dcb);
3361 tbl = &bp->object_info_tbl;
3362 v1_5 = tbl->v1_5;
3363
3364 object = &v1_5->display_path[i];
3365 record_offset = (unsigned int)
3366 (object->disp_recordoffset) +
3367 (unsigned int)(bp->object_info_tbl_offset);
3368
3369 for (;;) {
3370
3371 record_header = (struct atom_common_record_header *)
3372 GET_IMAGE(struct atom_common_record_header,
3373 record_offset);
3374 if (record_header == NULL) {
3375 result = BP_RESULT_BADBIOSTABLE;
3376 break;
3377 }
3378
3379 /* the end of the list */
3380 if (record_header->record_type == ATOM_RECORD_END_TYPE ||
3381 record_header->record_size == 0) {
3382 break;
3383 }
3384
3385 if (record_header->record_type ==
3386 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE &&
3387 sizeof(struct atom_bracket_layout_record_v2)
3388 <= record_header->record_size) {
3389 record = (struct atom_bracket_layout_record_v2 *)
3390 (record_header);
3391 result = BP_RESULT_OK;
3392 break;
3393 }
3394
3395 record_offset += record_header->record_size;
3396 }
3397
3398 /* return if the record not found */
3399 if (result != BP_RESULT_OK)
3400 return result;
3401
3402 /* get slot sizes */
3403 connector_id = object_id_from_bios_object_id(object->display_objid);
3404
3405 slot_layout_info->length = record->bracketlen;
3406 slot_layout_info->width = record->bracketwidth;
3407 slot_layout_info->num_of_connectors = v1_5->number_of_path;
3408 slot_layout_info->connectors[i].position = record->conn_num;
3409 slot_layout_info->connectors[i].connector_id = connector_id;
3410
3411 switch (connector_id.id) {
3412 case CONNECTOR_ID_SINGLE_LINK_DVID:
3413 case CONNECTOR_ID_DUAL_LINK_DVID:
3414 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DVI_D;
3415 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DVI;
3416 break;
3417
3418 case CONNECTOR_ID_HDMI_TYPE_A:
3419 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_HDMI;
3420 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_HDMI;
3421 break;
3422
3423 case CONNECTOR_ID_DISPLAY_PORT:
3424 case CONNECTOR_ID_USBC:
3425 if (record->mini_type == MINI_TYPE_NORMAL) {
3426 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_DP;
3427 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_DP;
3428 } else {
3429 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_MINI_DP;
3430 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_MINI_DP;
3431 }
3432 break;
3433
3434 default:
3435 slot_layout_info->connectors[i].connector_type = CONNECTOR_LAYOUT_TYPE_UNKNOWN;
3436 slot_layout_info->connectors[i].length = CONNECTOR_SIZE_UNKNOWN;
3437 }
3438 return result;
3439 }
3440
get_bracket_layout_record(struct dc_bios * dcb,unsigned int bracket_layout_id,struct slot_layout_info * slot_layout_info)3441 static enum bp_result get_bracket_layout_record(
3442 struct dc_bios *dcb,
3443 unsigned int bracket_layout_id,
3444 struct slot_layout_info *slot_layout_info)
3445 {
3446 unsigned int i;
3447 struct bios_parser *bp = BP_FROM_DCB(dcb);
3448 static enum bp_result result;
3449 struct object_info_table *tbl;
3450 struct display_object_info_table_v1_4 *v1_4;
3451 struct display_object_info_table_v1_5 *v1_5;
3452
3453 if (slot_layout_info == NULL) {
3454 DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
3455 return BP_RESULT_BADINPUT;
3456 }
3457
3458 tbl = &bp->object_info_tbl;
3459 v1_4 = tbl->v1_4;
3460 v1_5 = tbl->v1_5;
3461
3462 result = BP_RESULT_NORECORD;
3463 switch (bp->object_info_tbl.revision.minor) {
3464 case 4:
3465 default:
3466 for (i = 0; i < v1_4->number_of_path; ++i) {
3467 if (bracket_layout_id == v1_4->display_path[i].display_objid) {
3468 result = update_slot_layout_info(dcb, i, slot_layout_info);
3469 break;
3470 }
3471 }
3472 break;
3473 case 5:
3474 for (i = 0; i < v1_5->number_of_path; ++i)
3475 result = update_slot_layout_info_v2(dcb, i, slot_layout_info);
3476 break;
3477 }
3478
3479 return result;
3480 }
3481
bios_get_board_layout_info(struct dc_bios * dcb,struct board_layout_info * board_layout_info)3482 static enum bp_result bios_get_board_layout_info(
3483 struct dc_bios *dcb,
3484 struct board_layout_info *board_layout_info)
3485 {
3486 unsigned int i;
3487 struct bios_parser *bp;
3488 static enum bp_result record_result;
3489 unsigned int max_slots;
3490
3491 const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
3492 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
3493 GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
3494 0, 0
3495 };
3496
3497 bp = BP_FROM_DCB(dcb);
3498
3499 if (board_layout_info == NULL) {
3500 DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
3501 return BP_RESULT_BADINPUT;
3502 }
3503
3504 board_layout_info->num_of_slots = 0;
3505 max_slots = MAX_BOARD_SLOTS;
3506
3507 // Assume single slot on v1_5
3508 if (bp->object_info_tbl.revision.minor == 5) {
3509 max_slots = 1;
3510 }
3511
3512 for (i = 0; i < max_slots; ++i) {
3513 record_result = get_bracket_layout_record(dcb,
3514 slot_index_to_vbios_id[i],
3515 &board_layout_info->slots[i]);
3516
3517 if (record_result == BP_RESULT_NORECORD && i > 0)
3518 break; /* no more slots present in bios */
3519 else if (record_result != BP_RESULT_OK)
3520 return record_result; /* fail */
3521
3522 ++board_layout_info->num_of_slots;
3523 }
3524
3525 /* all data is valid */
3526 board_layout_info->is_number_of_slots_valid = 1;
3527 board_layout_info->is_slots_size_valid = 1;
3528 board_layout_info->is_connector_offsets_valid = 1;
3529 board_layout_info->is_connector_lengths_valid = 1;
3530
3531 return BP_RESULT_OK;
3532 }
3533
3534
bios_parser_pack_data_tables(struct dc_bios * dcb,void * dst)3535 static uint16_t bios_parser_pack_data_tables(
3536 struct dc_bios *dcb,
3537 void *dst)
3538 {
3539 // TODO: There is data bytes alignment issue, disable it for now.
3540 return 0;
3541 }
3542
bios_get_golden_table(struct bios_parser * bp,uint32_t rev_major,uint32_t rev_minor,uint16_t * dc_golden_table_ver)3543 static struct atom_dc_golden_table_v1 *bios_get_golden_table(
3544 struct bios_parser *bp,
3545 uint32_t rev_major,
3546 uint32_t rev_minor,
3547 uint16_t *dc_golden_table_ver)
3548 {
3549 struct atom_display_controller_info_v4_4 *disp_cntl_tbl_4_4 = NULL;
3550 uint32_t dc_golden_offset = 0;
3551 *dc_golden_table_ver = 0;
3552
3553 if (!DATA_TABLES(dce_info))
3554 return NULL;
3555
3556 /* ver.4.4 or higher */
3557 switch (rev_major) {
3558 case 4:
3559 switch (rev_minor) {
3560 case 4:
3561 disp_cntl_tbl_4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
3562 DATA_TABLES(dce_info));
3563 if (!disp_cntl_tbl_4_4)
3564 return NULL;
3565 dc_golden_offset = DATA_TABLES(dce_info) + disp_cntl_tbl_4_4->dc_golden_table_offset;
3566 *dc_golden_table_ver = disp_cntl_tbl_4_4->dc_golden_table_ver;
3567 break;
3568 case 5:
3569 default:
3570 /* For atom_display_controller_info_v4_5 there is no need to get golden table from
3571 * dc_golden_table_offset as all these fields previously in golden table used for AUX
3572 * pre-charge settings are now available directly in atom_display_controller_info_v4_5.
3573 */
3574 break;
3575 }
3576 break;
3577 }
3578
3579 if (!dc_golden_offset)
3580 return NULL;
3581
3582 if (*dc_golden_table_ver != 1)
3583 return NULL;
3584
3585 return GET_IMAGE(struct atom_dc_golden_table_v1,
3586 dc_golden_offset);
3587 }
3588
bios_get_atom_dc_golden_table(struct dc_bios * dcb)3589 static enum bp_result bios_get_atom_dc_golden_table(
3590 struct dc_bios *dcb)
3591 {
3592 struct bios_parser *bp = BP_FROM_DCB(dcb);
3593 enum bp_result result = BP_RESULT_OK;
3594 struct atom_dc_golden_table_v1 *atom_dc_golden_table = NULL;
3595 struct atom_common_table_header *header;
3596 struct atom_data_revision tbl_revision;
3597 uint16_t dc_golden_table_ver = 0;
3598
3599 header = GET_IMAGE(struct atom_common_table_header,
3600 DATA_TABLES(dce_info));
3601 if (!header)
3602 return BP_RESULT_UNSUPPORTED;
3603
3604 get_atom_data_table_revision(header, &tbl_revision);
3605
3606 atom_dc_golden_table = bios_get_golden_table(bp,
3607 tbl_revision.major,
3608 tbl_revision.minor,
3609 &dc_golden_table_ver);
3610
3611 if (!atom_dc_golden_table)
3612 return BP_RESULT_UNSUPPORTED;
3613
3614 dcb->golden_table.dc_golden_table_ver = dc_golden_table_ver;
3615 dcb->golden_table.aux_dphy_rx_control0_val = atom_dc_golden_table->aux_dphy_rx_control0_val;
3616 dcb->golden_table.aux_dphy_rx_control1_val = atom_dc_golden_table->aux_dphy_rx_control1_val;
3617 dcb->golden_table.aux_dphy_tx_control_val = atom_dc_golden_table->aux_dphy_tx_control_val;
3618 dcb->golden_table.dc_gpio_aux_ctrl_0_val = atom_dc_golden_table->dc_gpio_aux_ctrl_0_val;
3619 dcb->golden_table.dc_gpio_aux_ctrl_1_val = atom_dc_golden_table->dc_gpio_aux_ctrl_1_val;
3620 dcb->golden_table.dc_gpio_aux_ctrl_2_val = atom_dc_golden_table->dc_gpio_aux_ctrl_2_val;
3621 dcb->golden_table.dc_gpio_aux_ctrl_3_val = atom_dc_golden_table->dc_gpio_aux_ctrl_3_val;
3622 dcb->golden_table.dc_gpio_aux_ctrl_4_val = atom_dc_golden_table->dc_gpio_aux_ctrl_4_val;
3623 dcb->golden_table.dc_gpio_aux_ctrl_5_val = atom_dc_golden_table->dc_gpio_aux_ctrl_5_val;
3624
3625 return result;
3626 }
3627
3628
3629 static const struct dc_vbios_funcs vbios_funcs = {
3630 .get_connectors_number = bios_parser_get_connectors_number,
3631
3632 .get_connector_id = bios_parser_get_connector_id,
3633
3634 .get_src_obj = bios_parser_get_src_obj,
3635
3636 .get_i2c_info = bios_parser_get_i2c_info,
3637
3638 .get_hpd_info = bios_parser_get_hpd_info,
3639
3640 .get_device_tag = bios_parser_get_device_tag,
3641
3642 .get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
3643
3644 .get_ss_entry_number = bios_parser_get_ss_entry_number,
3645
3646 .get_embedded_panel_info = bios_parser_get_embedded_panel_info,
3647
3648 .get_gpio_pin_info = bios_parser_get_gpio_pin_info,
3649
3650 .get_encoder_cap_info = bios_parser_get_encoder_cap_info,
3651
3652 .is_device_id_supported = bios_parser_is_device_id_supported,
3653
3654 .is_accelerated_mode = bios_parser_is_accelerated_mode,
3655
3656 .set_scratch_critical_state = bios_parser_set_scratch_critical_state,
3657
3658
3659 /* COMMANDS */
3660 .encoder_control = bios_parser_encoder_control,
3661
3662 .transmitter_control = bios_parser_transmitter_control,
3663
3664 .enable_crtc = bios_parser_enable_crtc,
3665
3666 .set_pixel_clock = bios_parser_set_pixel_clock,
3667
3668 .set_dce_clock = bios_parser_set_dce_clock,
3669
3670 .program_crtc_timing = bios_parser_program_crtc_timing,
3671
3672 .enable_disp_power_gating = bios_parser_enable_disp_power_gating,
3673
3674 .bios_parser_destroy = firmware_parser_destroy,
3675
3676 .get_board_layout_info = bios_get_board_layout_info,
3677 .pack_data_tables = bios_parser_pack_data_tables,
3678
3679 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
3680
3681 .enable_lvtma_control = bios_parser_enable_lvtma_control,
3682
3683 .get_soc_bb_info = bios_parser_get_soc_bb_info,
3684
3685 .get_disp_connector_caps_info = bios_parser_get_disp_connector_caps_info,
3686
3687 .get_lttpr_caps = bios_parser_get_lttpr_caps,
3688
3689 .get_lttpr_interop = bios_parser_get_lttpr_interop,
3690
3691 .get_connector_speed_cap_info = bios_parser_get_connector_speed_cap_info,
3692 };
3693
bios_parser2_construct(struct bios_parser * bp,struct bp_init_data * init,enum dce_version dce_version)3694 static bool bios_parser2_construct(
3695 struct bios_parser *bp,
3696 struct bp_init_data *init,
3697 enum dce_version dce_version)
3698 {
3699 uint16_t *rom_header_offset = NULL;
3700 struct atom_rom_header_v2_2 *rom_header = NULL;
3701 struct display_object_info_table_v1_4 *object_info_tbl;
3702 struct atom_data_revision tbl_rev = {0};
3703
3704 if (!init)
3705 return false;
3706
3707 if (!init->bios)
3708 return false;
3709
3710 bp->base.funcs = &vbios_funcs;
3711 bp->base.bios = init->bios;
3712 bp->base.bios_size = bp->base.bios[OFFSET_TO_ATOM_ROM_IMAGE_SIZE] * BIOS_IMAGE_SIZE_UNIT;
3713
3714 bp->base.ctx = init->ctx;
3715
3716 bp->base.bios_local_image = NULL;
3717
3718 rom_header_offset =
3719 GET_IMAGE(uint16_t, OFFSET_TO_ATOM_ROM_HEADER_POINTER);
3720
3721 if (!rom_header_offset)
3722 return false;
3723
3724 rom_header = GET_IMAGE(struct atom_rom_header_v2_2, *rom_header_offset);
3725
3726 if (!rom_header)
3727 return false;
3728
3729 get_atom_data_table_revision(&rom_header->table_header, &tbl_rev);
3730 if (!(tbl_rev.major >= 2 && tbl_rev.minor >= 2))
3731 return false;
3732
3733 bp->master_data_tbl =
3734 GET_IMAGE(struct atom_master_data_table_v2_1,
3735 rom_header->masterdatatable_offset);
3736
3737 if (!bp->master_data_tbl)
3738 return false;
3739
3740 bp->object_info_tbl_offset = DATA_TABLES(displayobjectinfo);
3741
3742 if (!bp->object_info_tbl_offset)
3743 return false;
3744
3745 object_info_tbl =
3746 GET_IMAGE(struct display_object_info_table_v1_4,
3747 bp->object_info_tbl_offset);
3748
3749 if (!object_info_tbl)
3750 return false;
3751
3752 get_atom_data_table_revision(&object_info_tbl->table_header,
3753 &bp->object_info_tbl.revision);
3754
3755 if (bp->object_info_tbl.revision.major == 1
3756 && bp->object_info_tbl.revision.minor == 4) {
3757 struct display_object_info_table_v1_4 *tbl_v1_4;
3758
3759 tbl_v1_4 = GET_IMAGE(struct display_object_info_table_v1_4,
3760 bp->object_info_tbl_offset);
3761 if (!tbl_v1_4)
3762 return false;
3763
3764 bp->object_info_tbl.v1_4 = tbl_v1_4;
3765 } else if (bp->object_info_tbl.revision.major == 1
3766 && bp->object_info_tbl.revision.minor == 5) {
3767 struct display_object_info_table_v1_5 *tbl_v1_5;
3768
3769 tbl_v1_5 = GET_IMAGE(struct display_object_info_table_v1_5,
3770 bp->object_info_tbl_offset);
3771 if (!tbl_v1_5)
3772 return false;
3773
3774 bp->object_info_tbl.v1_5 = tbl_v1_5;
3775 } else {
3776 ASSERT(0);
3777 return false;
3778 }
3779
3780 dal_firmware_parser_init_cmd_tbl(bp);
3781 dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
3782
3783 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
3784 bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
3785 bios_parser_get_vram_info(&bp->base, &bp->base.vram_info);
3786 bios_parser_get_soc_bb_info(&bp->base, &bp->base.bb_info);
3787 return true;
3788 }
3789
firmware_parser_create(struct bp_init_data * init,enum dce_version dce_version)3790 struct dc_bios *firmware_parser_create(
3791 struct bp_init_data *init,
3792 enum dce_version dce_version)
3793 {
3794 struct bios_parser *bp;
3795
3796 bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL);
3797 if (!bp)
3798 return NULL;
3799
3800 if (bios_parser2_construct(bp, init, dce_version))
3801 return &bp->base;
3802
3803 kfree(bp);
3804 return NULL;
3805 }
3806
3807
3808