1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26 #include <drm/drm_vblank.h>
27 #include <drm/drm_atomic_helper.h>
28
29 #include "dc.h"
30 #include "amdgpu.h"
31 #include "amdgpu_dm_psr.h"
32 #include "amdgpu_dm_replay.h"
33 #include "amdgpu_dm_crtc.h"
34 #include "amdgpu_dm_plane.h"
35 #include "amdgpu_dm_trace.h"
36 #include "amdgpu_dm_debugfs.h"
37
38 #define HPD_DETECTION_PERIOD_uS 2000000
39 #define HPD_DETECTION_TIME_uS 100000
40
amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc * acrtc)41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
42 {
43 struct drm_crtc *crtc = &acrtc->base;
44 struct drm_device *dev = crtc->dev;
45 unsigned long flags;
46
47 drm_crtc_handle_vblank(crtc);
48
49 spin_lock_irqsave(&dev->event_lock, flags);
50
51 /* Send completion event for cursor-only commits */
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
53 drm_crtc_send_vblank_event(crtc, acrtc->event);
54 drm_crtc_vblank_put(crtc);
55 acrtc->event = NULL;
56 }
57
58 spin_unlock_irqrestore(&dev->event_lock, flags);
59 }
60
amdgpu_dm_crtc_modeset_required(struct drm_crtc_state * crtc_state,struct dc_stream_state * new_stream,struct dc_stream_state * old_stream)61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
62 struct dc_stream_state *new_stream,
63 struct dc_stream_state *old_stream)
64 {
65 return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
66 }
67
amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc * acrtc)68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
69
70 {
71 return acrtc->dm_irq_params.freesync_config.state ==
72 VRR_STATE_ACTIVE_VARIABLE ||
73 acrtc->dm_irq_params.freesync_config.state ==
74 VRR_STATE_ACTIVE_FIXED;
75 }
76
amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc * crtc,bool enable)77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
78 {
79 enum dc_irq_source irq_source;
80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
81 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
82 int rc;
83
84 if (acrtc->otg_inst == -1)
85 return 0;
86
87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
88
89 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
90
91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
92 acrtc->crtc_id, enable ? "en" : "dis", rc);
93 return rc;
94 }
95
amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state * dm_state)96 bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
97 {
98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
100 }
101
102 /**
103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
104 *
105 * @vblank_work: is a pointer to a struct vblank_control_work object.
106 * @vblank_enabled: indicates whether the DRM vblank counter is currently
107 * enabled (true) or disabled (false).
108 * @allow_sr_entry: represents whether entry into the self-refresh mode is
109 * allowed (true) or not allowed (false).
110 *
111 * The DRM vblank counter enable/disable action is used as the trigger to enable
112 * or disable various panel self-refresh features:
113 *
114 * Panel Replay and PSR SU
115 * - Enable when:
116 * - VRR is disabled
117 * - vblank counter is disabled
118 * - entry is allowed: usermode demonstrates an adequate number of fast
119 * commits)
120 * - CRC capture window isn't active
121 * - Keep enabled even when vblank counter gets enabled
122 *
123 * PSR1
124 * - Enable condition same as above
125 * - Disable when vblank counter is enabled
126 */
amdgpu_dm_crtc_set_panel_sr_feature(struct vblank_control_work * vblank_work,bool vblank_enabled,bool allow_sr_entry)127 static void amdgpu_dm_crtc_set_panel_sr_feature(
128 struct vblank_control_work *vblank_work,
129 bool vblank_enabled, bool allow_sr_entry)
130 {
131 struct dc_link *link = vblank_work->stream->link;
132 bool is_sr_active = (link->replay_settings.replay_allow_active ||
133 link->psr_settings.psr_allow_active);
134 bool is_crc_window_active = false;
135 bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(vblank_work->acrtc);
136
137 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
138 is_crc_window_active =
139 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
140 #endif
141
142 if (link->replay_settings.replay_feature_enabled && !vrr_active &&
143 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
144 amdgpu_dm_replay_enable(vblank_work->stream, true);
145 } else if (vblank_enabled) {
146 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
147 amdgpu_dm_psr_disable(vblank_work->stream, false);
148 } else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
149 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
150
151 struct amdgpu_dm_connector *aconn =
152 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
153
154 if (!aconn->disallow_edp_enter_psr) {
155 struct amdgpu_display_manager *dm = vblank_work->dm;
156
157 amdgpu_dm_psr_enable(vblank_work->stream);
158 if (dm->idle_workqueue &&
159 (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&
160 dm->dc->idle_optimizations_allowed &&
161 dm->idle_workqueue->enable &&
162 !dm->idle_workqueue->running)
163 schedule_work(&dm->idle_workqueue->work);
164 }
165 }
166 }
167
amdgpu_dm_is_headless(struct amdgpu_device * adev)168 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
169 {
170 struct drm_connector *connector;
171 struct drm_connector_list_iter iter;
172 struct drm_device *dev;
173 bool is_headless = true;
174
175 if (adev == NULL)
176 return true;
177
178 dev = adev->dm.ddev;
179
180 drm_connector_list_iter_begin(dev, &iter);
181 drm_for_each_connector_iter(connector, &iter) {
182
183 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
184 continue;
185
186 if (connector->status == connector_status_connected) {
187 is_headless = false;
188 break;
189 }
190 }
191 drm_connector_list_iter_end(&iter);
192 return is_headless;
193 }
194
amdgpu_dm_idle_worker(struct work_struct * work)195 static void amdgpu_dm_idle_worker(struct work_struct *work)
196 {
197 struct idle_workqueue *idle_work;
198
199 idle_work = container_of(work, struct idle_workqueue, work);
200 idle_work->dm->idle_workqueue->running = true;
201
202 while (idle_work->enable) {
203 fsleep(HPD_DETECTION_PERIOD_uS);
204 mutex_lock(&idle_work->dm->dc_lock);
205 if (!idle_work->dm->dc->idle_optimizations_allowed) {
206 mutex_unlock(&idle_work->dm->dc_lock);
207 break;
208 }
209 dc_allow_idle_optimizations(idle_work->dm->dc, false);
210
211 mutex_unlock(&idle_work->dm->dc_lock);
212 fsleep(HPD_DETECTION_TIME_uS);
213 mutex_lock(&idle_work->dm->dc_lock);
214
215 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
216 !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
217 mutex_unlock(&idle_work->dm->dc_lock);
218 break;
219 }
220
221 if (idle_work->enable)
222 dc_allow_idle_optimizations(idle_work->dm->dc, true);
223 mutex_unlock(&idle_work->dm->dc_lock);
224 }
225 idle_work->dm->idle_workqueue->running = false;
226 }
227
idle_create_workqueue(struct amdgpu_device * adev)228 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
229 {
230 struct idle_workqueue *idle_work;
231
232 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);
233 if (ZERO_OR_NULL_PTR(idle_work))
234 return NULL;
235
236 idle_work->dm = &adev->dm;
237 idle_work->enable = false;
238 idle_work->running = false;
239 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
240
241 return idle_work;
242 }
243
amdgpu_dm_crtc_vblank_control_worker(struct work_struct * work)244 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
245 {
246 struct vblank_control_work *vblank_work =
247 container_of(work, struct vblank_control_work, work);
248 struct amdgpu_display_manager *dm = vblank_work->dm;
249 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
250 int r;
251
252 mutex_lock(&dm->dc_lock);
253
254 if (vblank_work->enable)
255 dm->active_vblank_irq_count++;
256 else if (dm->active_vblank_irq_count)
257 dm->active_vblank_irq_count--;
258
259 if (dm->active_vblank_irq_count > 0)
260 dc_allow_idle_optimizations(dm->dc, false);
261
262 /*
263 * Control PSR based on vblank requirements from OS
264 *
265 * If panel supports PSR SU, there's no need to disable PSR when OS is
266 * submitting fast atomic commits (we infer this by whether the OS
267 * requests vblank events). Fast atomic commits will simply trigger a
268 * full-frame-update (FFU); a specific case of selective-update (SU)
269 * where the SU region is the full hactive*vactive region. See
270 * fill_dc_dirty_rects().
271 */
272 if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
273 amdgpu_dm_crtc_set_panel_sr_feature(
274 vblank_work, vblank_work->enable,
275 vblank_work->acrtc->dm_irq_params.allow_sr_entry);
276 }
277
278 if (dm->active_vblank_irq_count == 0) {
279 r = amdgpu_dpm_pause_power_profile(adev, true);
280 if (r)
281 dev_warn(adev->dev, "failed to set default power profile mode\n");
282 dc_allow_idle_optimizations(dm->dc, true);
283 r = amdgpu_dpm_pause_power_profile(adev, false);
284 if (r)
285 dev_warn(adev->dev, "failed to restore the power profile mode\n");
286 }
287
288 mutex_unlock(&dm->dc_lock);
289
290 dc_stream_release(vblank_work->stream);
291
292 kfree(vblank_work);
293 }
294
amdgpu_dm_crtc_set_vblank(struct drm_crtc * crtc,bool enable)295 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
296 {
297 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
298 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
299 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
300 struct amdgpu_display_manager *dm = &adev->dm;
301 struct vblank_control_work *work;
302 int irq_type;
303 int rc = 0;
304
305 if (acrtc->otg_inst == -1)
306 goto skip;
307
308 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
309
310 if (enable) {
311 /* vblank irq on -> Only need vupdate irq in vrr mode */
312 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
313 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
314 } else {
315 /* vblank irq off -> vupdate irq off */
316 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
317 }
318
319 if (rc)
320 return rc;
321
322 /* crtc vblank or vstartup interrupt */
323 if (enable) {
324 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
325 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
326 } else {
327 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
328 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
329 }
330
331 if (rc)
332 return rc;
333
334 /*
335 * hubp surface flip interrupt
336 *
337 * We have no guarantee that the frontend index maps to the same
338 * backend index - some even map to more than one.
339 *
340 * TODO: Use a different interrupt or check DC itself for the mapping.
341 */
342 if (enable) {
343 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
344 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
345 } else {
346 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
347 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
348 }
349
350 if (rc)
351 return rc;
352
353 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
354 /* crtc vline0 interrupt, only available on DCN+ */
355 if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
356 if (enable) {
357 rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
358 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
359 } else {
360 rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
361 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
362 }
363
364 if (rc)
365 return rc;
366 }
367 #endif
368 skip:
369 if (amdgpu_in_reset(adev))
370 return 0;
371
372 if (dm->vblank_control_workqueue) {
373 work = kzalloc(sizeof(*work), GFP_ATOMIC);
374 if (!work)
375 return -ENOMEM;
376
377 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
378 work->dm = dm;
379 work->acrtc = acrtc;
380 work->enable = enable;
381
382 if (acrtc_state->stream) {
383 dc_stream_retain(acrtc_state->stream);
384 work->stream = acrtc_state->stream;
385 }
386
387 queue_work(dm->vblank_control_workqueue, &work->work);
388 }
389
390 return 0;
391 }
392
amdgpu_dm_crtc_enable_vblank(struct drm_crtc * crtc)393 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
394 {
395 return amdgpu_dm_crtc_set_vblank(crtc, true);
396 }
397
amdgpu_dm_crtc_disable_vblank(struct drm_crtc * crtc)398 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
399 {
400 amdgpu_dm_crtc_set_vblank(crtc, false);
401 }
402
amdgpu_dm_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)403 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
404 struct drm_crtc_state *state)
405 {
406 struct dm_crtc_state *cur = to_dm_crtc_state(state);
407
408 /* TODO Destroy dc_stream objects are stream object is flattened */
409 if (cur->stream)
410 dc_stream_release(cur->stream);
411
412
413 __drm_atomic_helper_crtc_destroy_state(state);
414
415
416 kfree(state);
417 }
418
amdgpu_dm_crtc_duplicate_state(struct drm_crtc * crtc)419 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
420 {
421 struct dm_crtc_state *state, *cur;
422
423 cur = to_dm_crtc_state(crtc->state);
424
425 if (WARN_ON(!crtc->state))
426 return NULL;
427
428 state = kzalloc(sizeof(*state), GFP_KERNEL);
429 if (!state)
430 return NULL;
431
432 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
433
434 if (cur->stream) {
435 state->stream = cur->stream;
436 dc_stream_retain(state->stream);
437 }
438
439 state->active_planes = cur->active_planes;
440 state->vrr_infopacket = cur->vrr_infopacket;
441 state->abm_level = cur->abm_level;
442 state->vrr_supported = cur->vrr_supported;
443 state->freesync_config = cur->freesync_config;
444 state->cm_has_degamma = cur->cm_has_degamma;
445 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
446 state->regamma_tf = cur->regamma_tf;
447 state->crc_skip_count = cur->crc_skip_count;
448 state->mpo_requested = cur->mpo_requested;
449 state->cursor_mode = cur->cursor_mode;
450 /* TODO Duplicate dc_stream after objects are stream object is flattened */
451
452 return &state->base;
453 }
454
amdgpu_dm_crtc_destroy(struct drm_crtc * crtc)455 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
456 {
457 drm_crtc_cleanup(crtc);
458 kfree(crtc);
459 }
460
amdgpu_dm_crtc_reset_state(struct drm_crtc * crtc)461 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
462 {
463 struct dm_crtc_state *state;
464
465 if (crtc->state)
466 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
467
468 state = kzalloc(sizeof(*state), GFP_KERNEL);
469 if (WARN_ON(!state))
470 return;
471
472 __drm_atomic_helper_crtc_reset(crtc, &state->base);
473 }
474
475 #ifdef CONFIG_DEBUG_FS
amdgpu_dm_crtc_late_register(struct drm_crtc * crtc)476 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
477 {
478 crtc_debugfs_init(crtc);
479
480 return 0;
481 }
482 #endif
483
484 #ifdef AMD_PRIVATE_COLOR
485 /**
486 * dm_crtc_additional_color_mgmt - enable additional color properties
487 * @crtc: DRM CRTC
488 *
489 * This function lets the driver enable post-blending CRTC regamma transfer
490 * function property in addition to DRM CRTC gamma LUT. Default value means
491 * linear transfer function, which is the default CRTC gamma LUT behaviour
492 * without this property.
493 */
494 static void
dm_crtc_additional_color_mgmt(struct drm_crtc * crtc)495 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
496 {
497 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
498
499 if (adev->dm.dc->caps.color.mpc.ogam_ram)
500 drm_object_attach_property(&crtc->base,
501 adev->mode_info.regamma_tf_property,
502 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
503 }
504
505 static int
amdgpu_dm_atomic_crtc_set_property(struct drm_crtc * crtc,struct drm_crtc_state * state,struct drm_property * property,uint64_t val)506 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
507 struct drm_crtc_state *state,
508 struct drm_property *property,
509 uint64_t val)
510 {
511 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
512 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
513
514 if (property == adev->mode_info.regamma_tf_property) {
515 if (acrtc_state->regamma_tf != val) {
516 acrtc_state->regamma_tf = val;
517 acrtc_state->base.color_mgmt_changed |= 1;
518 }
519 } else {
520 drm_dbg_atomic(crtc->dev,
521 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
522 crtc->base.id, crtc->name,
523 property->base.id, property->name);
524 return -EINVAL;
525 }
526
527 return 0;
528 }
529
530 static int
amdgpu_dm_atomic_crtc_get_property(struct drm_crtc * crtc,const struct drm_crtc_state * state,struct drm_property * property,uint64_t * val)531 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
532 const struct drm_crtc_state *state,
533 struct drm_property *property,
534 uint64_t *val)
535 {
536 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
537 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
538
539 if (property == adev->mode_info.regamma_tf_property)
540 *val = acrtc_state->regamma_tf;
541 else
542 return -EINVAL;
543
544 return 0;
545 }
546 #endif
547
548 /* Implemented only the options currently available for the driver */
549 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
550 .reset = amdgpu_dm_crtc_reset_state,
551 .destroy = amdgpu_dm_crtc_destroy,
552 .set_config = drm_atomic_helper_set_config,
553 .page_flip = drm_atomic_helper_page_flip,
554 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
555 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
556 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
557 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
558 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
559 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
560 .enable_vblank = amdgpu_dm_crtc_enable_vblank,
561 .disable_vblank = amdgpu_dm_crtc_disable_vblank,
562 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
563 #if defined(CONFIG_DEBUG_FS)
564 .late_register = amdgpu_dm_crtc_late_register,
565 #endif
566 #ifdef AMD_PRIVATE_COLOR
567 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
568 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
569 #endif
570 };
571
amdgpu_dm_crtc_helper_disable(struct drm_crtc * crtc)572 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
573 {
574 }
575
amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state * new_crtc_state)576 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
577 {
578 struct drm_atomic_state *state = new_crtc_state->state;
579 struct drm_plane *plane;
580 int num_active = 0;
581
582 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
583 struct drm_plane_state *new_plane_state;
584
585 /* Cursor planes are "fake". */
586 if (plane->type == DRM_PLANE_TYPE_CURSOR)
587 continue;
588
589 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
590
591 if (!new_plane_state) {
592 /*
593 * The plane is enable on the CRTC and hasn't changed
594 * state. This means that it previously passed
595 * validation and is therefore enabled.
596 */
597 num_active += 1;
598 continue;
599 }
600
601 /* We need a framebuffer to be considered enabled. */
602 num_active += (new_plane_state->fb != NULL);
603 }
604
605 return num_active;
606 }
607
amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc * crtc,struct drm_crtc_state * new_crtc_state)608 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
609 struct drm_crtc_state *new_crtc_state)
610 {
611 struct dm_crtc_state *dm_new_crtc_state =
612 to_dm_crtc_state(new_crtc_state);
613
614 dm_new_crtc_state->active_planes = 0;
615
616 if (!dm_new_crtc_state->stream)
617 return;
618
619 dm_new_crtc_state->active_planes =
620 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
621 }
622
amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)623 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
624 const struct drm_display_mode *mode,
625 struct drm_display_mode *adjusted_mode)
626 {
627 return true;
628 }
629
amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)630 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
631 struct drm_atomic_state *state)
632 {
633 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
634 crtc);
635 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
636 struct dc *dc = adev->dm.dc;
637 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
638 int ret = -EINVAL;
639
640 trace_amdgpu_dm_crtc_atomic_check(crtc_state);
641
642 amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
643
644 if (WARN_ON(unlikely(!dm_crtc_state->stream &&
645 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
646 return ret;
647 }
648
649 /*
650 * We require the primary plane to be enabled whenever the CRTC is, otherwise
651 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
652 * planes are disabled, which is not supported by the hardware. And there is legacy
653 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
654 */
655 if (crtc_state->enable &&
656 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
657 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
658 return -EINVAL;
659 }
660
661 /*
662 * Only allow async flips for fast updates that don't change the FB
663 * pitch, the DCC state, rotation, etc.
664 */
665 if (crtc_state->async_flip &&
666 dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
667 drm_dbg_atomic(crtc->dev,
668 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
669 crtc->base.id, crtc->name);
670 return -EINVAL;
671 }
672
673 /* In some use cases, like reset, no stream is attached */
674 if (!dm_crtc_state->stream)
675 return 0;
676
677 if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
678 return 0;
679
680 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
681 return ret;
682 }
683
684 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
685 .disable = amdgpu_dm_crtc_helper_disable,
686 .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
687 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
688 .get_scanout_position = amdgpu_crtc_get_scanout_position,
689 };
690
amdgpu_dm_crtc_init(struct amdgpu_display_manager * dm,struct drm_plane * plane,uint32_t crtc_index)691 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
692 struct drm_plane *plane,
693 uint32_t crtc_index)
694 {
695 struct amdgpu_crtc *acrtc = NULL;
696 struct drm_plane *cursor_plane;
697 bool is_dcn;
698 int res = -ENOMEM;
699
700 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
701 if (!cursor_plane)
702 goto fail;
703
704 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
705 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
706
707 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
708 if (!acrtc)
709 goto fail;
710
711 res = drm_crtc_init_with_planes(
712 dm->ddev,
713 &acrtc->base,
714 plane,
715 cursor_plane,
716 &amdgpu_dm_crtc_funcs, NULL);
717
718 if (res)
719 goto fail;
720
721 drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
722
723 /* Create (reset) the plane state */
724 if (acrtc->base.funcs->reset)
725 acrtc->base.funcs->reset(&acrtc->base);
726
727 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
728 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
729
730 acrtc->crtc_id = crtc_index;
731 acrtc->base.enabled = false;
732 acrtc->otg_inst = -1;
733
734 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
735
736 /* Don't enable DRM CRTC degamma property for DCE since it doesn't
737 * support programmable degamma anywhere.
738 */
739 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
740 drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
741 true, MAX_COLOR_LUT_ENTRIES);
742
743 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
744
745 #ifdef AMD_PRIVATE_COLOR
746 dm_crtc_additional_color_mgmt(&acrtc->base);
747 #endif
748 return 0;
749
750 fail:
751 kfree(acrtc);
752 kfree(cursor_plane);
753 return res;
754 }
755
756