1 /*
2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
28
29 #include <drm/display/drm_dp_mst_helper.h>
30 #include <drm/drm_atomic.h>
31 #include <drm/drm_connector.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_plane.h>
34 #include "link_service_types.h"
35 #include <drm/drm_writeback.h>
36
37 /*
38 * This file contains the definition for amdgpu_display_manager
39 * and its API for amdgpu driver's use.
40 * This component provides all the display related functionality
41 * and this is the only component that calls DAL API.
42 * The API contained here intended for amdgpu driver use.
43 * The API that is called directly from KMS framework is located
44 * in amdgpu_dm_kms.h file
45 */
46
47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
48
49 #define AMDGPU_DM_MAX_CRTC 6
50
51 #define AMDGPU_DM_MAX_NUM_EDP 2
52
53 #define AMDGPU_DMUB_NOTIFICATION_MAX 7
54
55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A
56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40
57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3
58
59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)
60
61 /*
62 #include "include/amdgpu_dal_power_if.h"
63 #include "amdgpu_dm_irq.h"
64 */
65
66 #include "irq_types.h"
67 #include "signal_types.h"
68 #include "amdgpu_dm_crc.h"
69 #include "mod_info_packet.h"
70 struct aux_payload;
71 struct set_config_cmd_payload;
72 enum aux_return_code_type;
73 enum set_config_status;
74
75 /* Forward declarations */
76 struct amdgpu_device;
77 struct amdgpu_crtc;
78 struct drm_device;
79 struct dc;
80 struct amdgpu_bo;
81 struct dmub_srv;
82 struct dc_plane_state;
83 struct dmub_notification;
84
85 struct amd_vsdb_block {
86 unsigned char ieee_id[3];
87 unsigned char version;
88 unsigned char feature_caps;
89 };
90
91 struct common_irq_params {
92 struct amdgpu_device *adev;
93 enum dc_irq_source irq_src;
94 atomic64_t previous_timestamp;
95 };
96
97 /**
98 * struct dm_compressor_info - Buffer info used by frame buffer compression
99 * @cpu_addr: MMIO cpu addr
100 * @bo_ptr: Pointer to the buffer object
101 * @gpu_addr: MMIO gpu addr
102 */
103 struct dm_compressor_info {
104 void *cpu_addr;
105 struct amdgpu_bo *bo_ptr;
106 uint64_t gpu_addr;
107 };
108
109 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
110
111 /**
112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
113 *
114 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq
115 * @dmub_notify: notification for callback function
116 * @adev: amdgpu_device pointer
117 */
118 struct dmub_hpd_work {
119 struct work_struct handle_hpd_work;
120 struct dmub_notification *dmub_notify;
121 struct amdgpu_device *adev;
122 };
123
124 /**
125 * struct vblank_control_work - Work data for vblank control
126 * @work: Kernel work data for the work event
127 * @dm: amdgpu display manager device
128 * @acrtc: amdgpu CRTC instance for which the event has occurred
129 * @stream: DC stream for which the event has occurred
130 * @enable: true if enabling vblank
131 */
132 struct vblank_control_work {
133 struct work_struct work;
134 struct amdgpu_display_manager *dm;
135 struct amdgpu_crtc *acrtc;
136 struct dc_stream_state *stream;
137 bool enable;
138 };
139
140 /**
141 * struct idle_workqueue - Work data for periodic action in idle
142 * @work: Kernel work data for the work event
143 * @dm: amdgpu display manager device
144 * @enable: true if idle worker is enabled
145 * @running: true if idle worker is running
146 */
147 struct idle_workqueue {
148 struct work_struct work;
149 struct amdgpu_display_manager *dm;
150 bool enable;
151 bool running;
152 };
153
154 #define MAX_LUMINANCE_DATA_POINTS 99
155
156 /**
157 * struct amdgpu_dm_luminance_data - Custom luminance data
158 * @luminance: Luminance in percent
159 * @input_signal: Input signal in range 0-255
160 */
161 struct amdgpu_dm_luminance_data {
162 u8 luminance;
163 u8 input_signal;
164 } __packed;
165
166 /**
167 * struct amdgpu_dm_backlight_caps - Information about backlight
168 *
169 * Describe the backlight support for ACPI or eDP AUX.
170 */
171 struct amdgpu_dm_backlight_caps {
172 /**
173 * @ext_caps: Keep the data struct with all the information about the
174 * display support for HDR.
175 */
176 union dpcd_sink_ext_caps *ext_caps;
177 /**
178 * @aux_min_input_signal: Min brightness value supported by the display
179 */
180 u32 aux_min_input_signal;
181 /**
182 * @aux_max_input_signal: Max brightness value supported by the display
183 * in nits.
184 */
185 u32 aux_max_input_signal;
186 /**
187 * @min_input_signal: minimum possible input in range 0-255.
188 */
189 int min_input_signal;
190 /**
191 * @max_input_signal: maximum possible input in range 0-255.
192 */
193 int max_input_signal;
194 /**
195 * @caps_valid: true if these values are from the ACPI interface.
196 */
197 bool caps_valid;
198 /**
199 * @aux_support: Describes if the display supports AUX backlight.
200 */
201 bool aux_support;
202 /**
203 * @ac_level: the default brightness if booted on AC
204 */
205 u8 ac_level;
206 /**
207 * @dc_level: the default brightness if booted on DC
208 */
209 u8 dc_level;
210 /**
211 * @data_points: the number of custom luminance data points
212 */
213 u8 data_points;
214 /**
215 * @luminance_data: custom luminance data
216 */
217 struct amdgpu_dm_luminance_data luminance_data[MAX_LUMINANCE_DATA_POINTS];
218 };
219
220 /**
221 * struct dal_allocation - Tracks mapped FB memory for SMU communication
222 * @list: list of dal allocations
223 * @bo: GPU buffer object
224 * @cpu_ptr: CPU virtual address of the GPU buffer object
225 * @gpu_addr: GPU virtual address of the GPU buffer object
226 */
227 struct dal_allocation {
228 struct list_head list;
229 struct amdgpu_bo *bo;
230 void *cpu_ptr;
231 u64 gpu_addr;
232 };
233
234 /**
235 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
236 * offload work
237 */
238 struct hpd_rx_irq_offload_work_queue {
239 /**
240 * @wq: workqueue structure to queue offload work.
241 */
242 struct workqueue_struct *wq;
243 /**
244 * @offload_lock: To protect fields of offload work queue.
245 */
246 spinlock_t offload_lock;
247 /**
248 * @is_handling_link_loss: Used to prevent inserting link loss event when
249 * we're handling link loss
250 */
251 bool is_handling_link_loss;
252 /**
253 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message
254 * ready event when we're already handling mst message ready event
255 */
256 bool is_handling_mst_msg_rdy_event;
257 /**
258 * @aconnector: The aconnector that this work queue is attached to
259 */
260 struct amdgpu_dm_connector *aconnector;
261 };
262
263 /**
264 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure
265 */
266 struct hpd_rx_irq_offload_work {
267 /**
268 * @work: offload work
269 */
270 struct work_struct work;
271 /**
272 * @data: reference irq data which is used while handling offload work
273 */
274 union hpd_irq_data data;
275 /**
276 * @offload_wq: offload work queue that this work is queued to
277 */
278 struct hpd_rx_irq_offload_work_queue *offload_wq;
279 };
280
281 /**
282 * struct amdgpu_display_manager - Central amdgpu display manager device
283 *
284 * @dc: Display Core control structure
285 * @adev: AMDGPU base driver structure
286 * @ddev: DRM base driver structure
287 * @display_indexes_num: Max number of display streams supported
288 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
289 * @backlight_dev: Backlight control device
290 * @backlight_link: Link on which to control backlight
291 * @backlight_caps: Capabilities of the backlight device
292 * @freesync_module: Module handling freesync calculations
293 * @hdcp_workqueue: AMDGPU content protection queue
294 * @fw_dmcu: Reference to DMCU firmware
295 * @dmcu_fw_version: Version of the DMCU firmware
296 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
297 * @cached_state: Caches device atomic state for suspend/resume
298 * @cached_dc_state: Cached state of content streams
299 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
300 * @force_timing_sync: set via debugfs. When set, indicates that all connected
301 * displays will be forced to synchronize.
302 * @dmcub_trace_event_en: enable dmcub trace events
303 * @dmub_outbox_params: DMUB Outbox parameters
304 * @num_of_edps: number of backlight eDPs
305 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the
306 * driver when true
307 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB
308 * transfers are done
309 * @delayed_hpd_wq: work queue used to delay DMUB HPD work
310 */
311 struct amdgpu_display_manager {
312
313 struct dc *dc;
314
315 /**
316 * @dmub_srv:
317 *
318 * DMUB service, used for controlling the DMUB on hardware
319 * that supports it. The pointer to the dmub_srv will be
320 * NULL on hardware that does not support it.
321 */
322 struct dmub_srv *dmub_srv;
323
324 /**
325 * @dmub_notify:
326 *
327 * Notification from DMUB.
328 */
329
330 struct dmub_notification *dmub_notify;
331
332 /**
333 * @dmub_callback:
334 *
335 * Callback functions to handle notification from DMUB.
336 */
337
338 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
339
340 /**
341 * @dmub_thread_offload:
342 *
343 * Flag to indicate if callback is offload.
344 */
345
346 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
347
348 /**
349 * @dmub_fb_info:
350 *
351 * Framebuffer regions for the DMUB.
352 */
353 struct dmub_srv_fb_info *dmub_fb_info;
354
355 /**
356 * @dmub_fw:
357 *
358 * DMUB firmware, required on hardware that has DMUB support.
359 */
360 const struct firmware *dmub_fw;
361
362 /**
363 * @dmub_bo:
364 *
365 * Buffer object for the DMUB.
366 */
367 struct amdgpu_bo *dmub_bo;
368
369 /**
370 * @dmub_bo_gpu_addr:
371 *
372 * GPU virtual address for the DMUB buffer object.
373 */
374 u64 dmub_bo_gpu_addr;
375
376 /**
377 * @dmub_bo_cpu_addr:
378 *
379 * CPU address for the DMUB buffer object.
380 */
381 void *dmub_bo_cpu_addr;
382
383 /**
384 * @dmcub_fw_version:
385 *
386 * DMCUB firmware version.
387 */
388 uint32_t dmcub_fw_version;
389
390 /**
391 * @cgs_device:
392 *
393 * The Common Graphics Services device. It provides an interface for
394 * accessing registers.
395 */
396 struct cgs_device *cgs_device;
397
398 struct amdgpu_device *adev;
399 struct drm_device *ddev;
400 u16 display_indexes_num;
401
402 /**
403 * @atomic_obj:
404 *
405 * In combination with &dm_atomic_state it helps manage
406 * global atomic state that doesn't map cleanly into existing
407 * drm resources, like &dc_context.
408 */
409 struct drm_private_obj atomic_obj;
410
411 /**
412 * @dc_lock:
413 *
414 * Guards access to DC functions that can issue register write
415 * sequences.
416 */
417 struct mutex dc_lock;
418
419 /**
420 * @audio_lock:
421 *
422 * Guards access to audio instance changes.
423 */
424 struct mutex audio_lock;
425
426 /**
427 * @audio_component:
428 *
429 * Used to notify ELD changes to sound driver.
430 */
431 struct drm_audio_component *audio_component;
432
433 /**
434 * @audio_registered:
435 *
436 * True if the audio component has been registered
437 * successfully, false otherwise.
438 */
439 bool audio_registered;
440
441 /**
442 * @irq_handler_list_low_tab:
443 *
444 * Low priority IRQ handler table.
445 *
446 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
447 * source. Low priority IRQ handlers are deferred to a workqueue to be
448 * processed. Hence, they can sleep.
449 *
450 * Note that handlers are called in the same order as they were
451 * registered (FIFO).
452 */
453 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
454
455 /**
456 * @irq_handler_list_high_tab:
457 *
458 * High priority IRQ handler table.
459 *
460 * It is a n*m table, same as &irq_handler_list_low_tab. However,
461 * handlers in this table are not deferred and are called immediately.
462 */
463 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
464
465 /**
466 * @pflip_params:
467 *
468 * Page flip IRQ parameters, passed to registered handlers when
469 * triggered.
470 */
471 struct common_irq_params
472 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
473
474 /**
475 * @vblank_params:
476 *
477 * Vertical blanking IRQ parameters, passed to registered handlers when
478 * triggered.
479 */
480 struct common_irq_params
481 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
482
483 /**
484 * @vline0_params:
485 *
486 * OTG vertical interrupt0 IRQ parameters, passed to registered
487 * handlers when triggered.
488 */
489 struct common_irq_params
490 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
491
492 /**
493 * @vupdate_params:
494 *
495 * Vertical update IRQ parameters, passed to registered handlers when
496 * triggered.
497 */
498 struct common_irq_params
499 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
500
501 /**
502 * @dmub_trace_params:
503 *
504 * DMUB trace event IRQ parameters, passed to registered handlers when
505 * triggered.
506 */
507 struct common_irq_params
508 dmub_trace_params[1];
509
510 struct common_irq_params
511 dmub_outbox_params[1];
512
513 spinlock_t irq_handler_list_table_lock;
514
515 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
516
517 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
518
519 uint8_t num_of_edps;
520
521 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
522
523 struct mod_freesync *freesync_module;
524 struct hdcp_workqueue *hdcp_workqueue;
525
526 /**
527 * @vblank_control_workqueue:
528 *
529 * Deferred work for vblank control events.
530 */
531 struct workqueue_struct *vblank_control_workqueue;
532
533 /**
534 * @idle_workqueue:
535 *
536 * Periodic work for idle events.
537 */
538 struct idle_workqueue *idle_workqueue;
539
540 struct drm_atomic_state *cached_state;
541 struct dc_state *cached_dc_state;
542
543 struct dm_compressor_info compressor;
544
545 const struct firmware *fw_dmcu;
546 uint32_t dmcu_fw_version;
547 /**
548 * @soc_bounding_box:
549 *
550 * gpu_info FW provided soc bounding box struct or 0 if not
551 * available in FW
552 */
553 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
554
555 /**
556 * @active_vblank_irq_count:
557 *
558 * number of currently active vblank irqs
559 */
560 uint32_t active_vblank_irq_count;
561
562 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
563 /**
564 * @secure_display_ctx:
565 *
566 * Store secure display relevant info. e.g. the ROI information
567 * , the work_struct to command dmub, etc.
568 */
569 struct secure_display_context secure_display_ctx;
570 #endif
571 /**
572 * @hpd_rx_offload_wq:
573 *
574 * Work queue to offload works of hpd_rx_irq
575 */
576 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
577 /**
578 * @mst_encoders:
579 *
580 * fake encoders used for DP MST.
581 */
582 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
583 bool force_timing_sync;
584 bool disable_hpd_irq;
585 bool dmcub_trace_event_en;
586 /**
587 * @da_list:
588 *
589 * DAL fb memory allocation list, for communication with SMU.
590 */
591 struct list_head da_list;
592 struct completion dmub_aux_transfer_done;
593 struct workqueue_struct *delayed_hpd_wq;
594
595 /**
596 * @brightness:
597 *
598 * cached backlight values.
599 */
600 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
601 /**
602 * @actual_brightness:
603 *
604 * last successfully applied backlight values.
605 */
606 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
607
608 /**
609 * @aux_hpd_discon_quirk:
610 *
611 * quirk for hpd discon while aux is on-going.
612 * occurred on certain intel platform
613 */
614 bool aux_hpd_discon_quirk;
615
616 /**
617 * @dpia_aux_lock:
618 *
619 * Guards access to DPIA AUX
620 */
621 struct mutex dpia_aux_lock;
622
623 /**
624 * @bb_from_dmub:
625 *
626 * Bounding box data read from dmub during early initialization for DCN4+
627 */
628 struct dml2_soc_bb *bb_from_dmub;
629
630 /**
631 * @oem_i2c:
632 *
633 * OEM i2c bus
634 */
635 struct amdgpu_i2c_adapter *oem_i2c;
636 };
637
638 enum dsc_clock_force_state {
639 DSC_CLK_FORCE_DEFAULT = 0,
640 DSC_CLK_FORCE_ENABLE,
641 DSC_CLK_FORCE_DISABLE,
642 };
643
644 struct dsc_preferred_settings {
645 enum dsc_clock_force_state dsc_force_enable;
646 uint32_t dsc_num_slices_v;
647 uint32_t dsc_num_slices_h;
648 uint32_t dsc_bits_per_pixel;
649 bool dsc_force_disable_passthrough;
650 };
651
652 enum mst_progress_status {
653 MST_STATUS_DEFAULT = 0,
654 MST_PROBE = BIT(0),
655 MST_REMOTE_EDID = BIT(1),
656 MST_ALLOCATE_NEW_PAYLOAD = BIT(2),
657 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),
658 };
659
660 /**
661 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info
662 *
663 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this
664 * struct is useful to keep track of the display-specific information about
665 * FreeSync.
666 */
667 struct amdgpu_hdmi_vsdb_info {
668 /**
669 * @amd_vsdb_version: Vendor Specific Data Block Version, should be
670 * used to determine which Vendor Specific InfoFrame (VSIF) to send.
671 */
672 unsigned int amd_vsdb_version;
673
674 /**
675 * @freesync_supported: FreeSync Supported.
676 */
677 bool freesync_supported;
678
679 /**
680 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.
681 */
682 unsigned int min_refresh_rate_hz;
683
684 /**
685 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz
686 */
687 unsigned int max_refresh_rate_hz;
688
689 /**
690 * @replay_mode: Replay supported
691 */
692 bool replay_mode;
693 };
694
695 struct amdgpu_dm_connector {
696
697 struct drm_connector base;
698 uint32_t connector_id;
699 int bl_idx;
700
701 struct cec_notifier *notifier;
702
703 /* we need to mind the EDID between detect
704 and get modes due to analog/digital/tvencoder */
705 const struct drm_edid *drm_edid;
706
707 /* shared with amdgpu */
708 struct amdgpu_hpd hpd;
709
710 /* number of modes generated from EDID at 'dc_sink' */
711 int num_modes;
712
713 /* The 'old' sink - before an HPD.
714 * The 'current' sink is in dc_link->sink. */
715 struct dc_sink *dc_sink;
716 struct dc_link *dc_link;
717
718 /**
719 * @dc_em_sink: Reference to the emulated (virtual) sink.
720 */
721 struct dc_sink *dc_em_sink;
722
723 /* DM only */
724 struct drm_dp_mst_topology_mgr mst_mgr;
725 struct amdgpu_dm_dp_aux dm_dp_aux;
726 struct drm_dp_mst_port *mst_output_port;
727 struct amdgpu_dm_connector *mst_root;
728 struct drm_dp_aux *dsc_aux;
729 uint32_t mst_local_bw;
730 uint16_t vc_full_pbn;
731 struct mutex handle_mst_msg_ready;
732
733 /* TODO see if we can merge with ddc_bus or make a dm_connector */
734 struct amdgpu_i2c_adapter *i2c;
735
736 /* Monitor range limits */
737 /**
738 * @min_vfreq: Minimal frequency supported by the display in Hz. This
739 * value is set to zero when there is no FreeSync support.
740 */
741 int min_vfreq;
742
743 /**
744 * @max_vfreq: Maximum frequency supported by the display in Hz. This
745 * value is set to zero when there is no FreeSync support.
746 */
747 int max_vfreq ;
748
749 /* Audio instance - protected by audio_lock. */
750 int audio_inst;
751
752 struct mutex hpd_lock;
753
754 bool fake_enable;
755 bool force_yuv420_output;
756 struct dsc_preferred_settings dsc_settings;
757 union dp_downstream_port_present mst_downstream_port_present;
758 /* Cached display modes */
759 struct drm_display_mode freesync_vid_base;
760
761 int sr_skip_count;
762 bool disallow_edp_enter_psr;
763
764 /* Record progress status of mst*/
765 uint8_t mst_status;
766
767 /* Automated testing */
768 bool timing_changed;
769 struct dc_crtc_timing *timing_requested;
770
771 /* Adaptive Sync */
772 bool pack_sdp_v1_3;
773 enum adaptive_sync_type as_type;
774 struct amdgpu_hdmi_vsdb_info vsdb_info;
775 };
776
amdgpu_dm_set_mst_status(uint8_t * status,uint8_t flags,bool set)777 static inline void amdgpu_dm_set_mst_status(uint8_t *status,
778 uint8_t flags, bool set)
779 {
780 if (set)
781 *status |= flags;
782 else
783 *status &= ~flags;
784 }
785
786 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
787
788 struct amdgpu_dm_wb_connector {
789 struct drm_writeback_connector base;
790 struct dc_link *link;
791 };
792
793 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)
794
795 extern const struct amdgpu_ip_block_version dm_ip_block;
796
797 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.
798 *
799 * It includes standardized transfer functions and pure power functions. The
800 * transfer function coefficients are available at modules/color/color_gamma.c
801 */
802 enum amdgpu_transfer_function {
803 AMDGPU_TRANSFER_FUNCTION_DEFAULT,
804 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
805 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
806 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
807 AMDGPU_TRANSFER_FUNCTION_IDENTITY,
808 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
809 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
810 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
811 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
812 AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
813 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
814 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
815 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
816 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
817 AMDGPU_TRANSFER_FUNCTION_COUNT
818 };
819
820 struct dm_plane_state {
821 struct drm_plane_state base;
822 struct dc_plane_state *dc_state;
823
824 /* Plane color mgmt */
825 /**
826 * @degamma_lut:
827 *
828 * 1D LUT for mapping framebuffer/plane pixel data before sampling or
829 * blending operations. It's usually applied to linearize input space.
830 * The blob (if not NULL) is an array of &struct drm_color_lut.
831 */
832 struct drm_property_blob *degamma_lut;
833 /**
834 * @degamma_tf:
835 *
836 * Predefined transfer function to tell DC driver the input space to
837 * linearize.
838 */
839 enum amdgpu_transfer_function degamma_tf;
840 /**
841 * @hdr_mult:
842 *
843 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed
844 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
845 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
846 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
847 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
848 * S31.32 sign-magnitude.
849 *
850 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ
851 * TF is needed for any subsequent linear-to-non-linear transforms.
852 */
853 __u64 hdr_mult;
854 /**
855 * @ctm:
856 *
857 * Color transformation matrix. The blob (if not NULL) is a &struct
858 * drm_color_ctm_3x4.
859 */
860 struct drm_property_blob *ctm;
861 /**
862 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
863 * array of &struct drm_color_lut.
864 */
865 struct drm_property_blob *shaper_lut;
866 /**
867 * @shaper_tf:
868 *
869 * Predefined transfer function to delinearize color space.
870 */
871 enum amdgpu_transfer_function shaper_tf;
872 /**
873 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
874 * &struct drm_color_lut.
875 */
876 struct drm_property_blob *lut3d;
877 /**
878 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an
879 * array of &struct drm_color_lut.
880 */
881 struct drm_property_blob *blend_lut;
882 /**
883 * @blend_tf:
884 *
885 * Pre-defined transfer function for converting plane pixel data before
886 * applying blend LUT.
887 */
888 enum amdgpu_transfer_function blend_tf;
889 };
890
891 enum amdgpu_dm_cursor_mode {
892 DM_CURSOR_NATIVE_MODE = 0,
893 DM_CURSOR_OVERLAY_MODE,
894 };
895
896 struct dm_crtc_state {
897 struct drm_crtc_state base;
898 struct dc_stream_state *stream;
899
900 bool cm_has_degamma;
901 bool cm_is_degamma_srgb;
902
903 bool mpo_requested;
904
905 int update_type;
906 int active_planes;
907
908 int crc_skip_count;
909
910 bool freesync_vrr_info_changed;
911
912 bool dsc_force_changed;
913 bool vrr_supported;
914 struct mod_freesync_config freesync_config;
915 struct dc_info_packet vrr_infopacket;
916
917 int abm_level;
918
919 /**
920 * @regamma_tf:
921 *
922 * Pre-defined transfer function for converting internal FB -> wire
923 * encoding.
924 */
925 enum amdgpu_transfer_function regamma_tf;
926
927 enum amdgpu_dm_cursor_mode cursor_mode;
928 };
929
930 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
931
932 struct dm_atomic_state {
933 struct drm_private_state base;
934
935 struct dc_state *context;
936 };
937
938 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
939
940 struct dm_connector_state {
941 struct drm_connector_state base;
942
943 enum amdgpu_rmx_type scaling;
944 uint8_t underscan_vborder;
945 uint8_t underscan_hborder;
946 bool underscan_enable;
947 bool freesync_capable;
948 bool update_hdcp;
949 uint8_t abm_level;
950 int vcpi_slots;
951 uint64_t pbn;
952 };
953
954 #define to_dm_connector_state(x)\
955 container_of((x), struct dm_connector_state, base)
956
957 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
958 struct drm_connector_state *
959 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
960 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
961 struct drm_connector_state *state,
962 struct drm_property *property,
963 uint64_t val);
964
965 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
966 const struct drm_connector_state *state,
967 struct drm_property *property,
968 uint64_t *val);
969
970 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
971
972 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
973 struct amdgpu_dm_connector *aconnector,
974 int connector_type,
975 struct dc_link *link,
976 int link_index);
977
978 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
979 const struct drm_display_mode *mode);
980
981 void dm_restore_drm_connector_state(struct drm_device *dev,
982 struct drm_connector *connector);
983
984 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
985 const struct drm_edid *drm_edid);
986
987 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
988
989 /* 3D LUT max size is 17x17x17 (4913 entries) */
990 #define MAX_COLOR_3DLUT_SIZE 17
991 #define MAX_COLOR_3DLUT_BITDEPTH 12
992 int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev,
993 struct drm_plane_state *plane_state);
994 /* 1D LUT size */
995 #define MAX_COLOR_LUT_ENTRIES 4096
996 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
997 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
998
999 void amdgpu_dm_init_color_mod(void);
1000 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);
1001 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
1002 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
1003 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
1004 struct drm_plane_state *plane_state,
1005 struct dc_plane_state *dc_plane_state);
1006
1007 void amdgpu_dm_update_connector_after_detect(
1008 struct amdgpu_dm_connector *aconnector);
1009
1010 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
1011
1012 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,
1013 struct aux_payload *payload, enum aux_return_code_type *operation_result);
1014
1015 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,
1016 struct set_config_cmd_payload *payload, enum set_config_status *operation_result);
1017
1018 struct dc_stream_state *
1019 create_validate_stream_for_sink(struct drm_connector *connector,
1020 const struct drm_display_mode *drm_mode,
1021 const struct dm_connector_state *dm_state,
1022 const struct dc_stream_state *old_stream);
1023
1024 int dm_atomic_get_state(struct drm_atomic_state *state,
1025 struct dm_atomic_state **dm_state);
1026
1027 struct drm_connector *
1028 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1029 struct drm_crtc *crtc);
1030
1031 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
1032 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);
1033
1034 void *dm_allocate_gpu_mem(struct amdgpu_device *adev,
1035 enum dc_gpu_mem_alloc_type type,
1036 size_t size,
1037 long long *addr);
1038 void dm_free_gpu_mem(struct amdgpu_device *adev,
1039 enum dc_gpu_mem_alloc_type type,
1040 void *addr);
1041
1042 bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
1043
1044 void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector);
1045 void hdmi_cec_unset_edid(struct amdgpu_dm_connector *aconnector);
1046 int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector);
1047
1048 #endif /* __AMDGPU_DM_H__ */
1049