1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/firmware.h>
25 #include <drm/drm_drv.h>
26 
27 #include "amdgpu.h"
28 #include "amdgpu_vcn.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "amdgpu_pm.h"
32 #include "amdgpu_psp.h"
33 #include "mmsch_v2_0.h"
34 #include "vcn_v2_0.h"
35 
36 #include "vcn/vcn_2_0_0_offset.h"
37 #include "vcn/vcn_2_0_0_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39 
40 #define VCN_VID_SOC_ADDRESS_2_0					0x1fa00
41 #define VCN1_VID_SOC_ADDRESS_3_0				0x48200
42 #define VCN1_AON_SOC_ADDRESS_3_0				0x48000
43 
44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x1fd
45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x503
46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x504
47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET			0x505
48 #define mmUVD_NO_OP_INTERNAL_OFFSET				0x53f
49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET			0x54a
50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET				0xc01d
51 
52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET			0x1e1
53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x5a6
54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x5a7
55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x1e2
56 
57 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
58 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
59 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
60 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
61 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
62 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
63 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
64 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
65 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
66 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
67 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
68 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
69 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
70 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
71 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
72 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
73 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
74 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
75 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
76 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
77 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
78 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
79 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
80 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
81 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
82 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
83 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
84 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
85 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
86 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
87 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
88 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
89 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
90 	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
91 };
92 
93 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
94 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
95 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
96 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
97 				 enum amd_powergating_state state);
98 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
99 				   struct dpg_pause_state *new_state);
100 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
101 /**
102  * vcn_v2_0_early_init - set function pointers and load microcode
103  *
104  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
105  *
106  * Set ring and irq function pointers
107  * Load microcode from filesystem
108  */
vcn_v2_0_early_init(struct amdgpu_ip_block * ip_block)109 static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
110 {
111 	struct amdgpu_device *adev = ip_block->adev;
112 
113 	if (amdgpu_sriov_vf(adev))
114 		adev->vcn.inst[0].num_enc_rings = 1;
115 	else
116 		adev->vcn.inst[0].num_enc_rings = 2;
117 
118 	adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state;
119 	vcn_v2_0_set_dec_ring_funcs(adev);
120 	vcn_v2_0_set_enc_ring_funcs(adev);
121 	vcn_v2_0_set_irq_funcs(adev);
122 
123 	return amdgpu_vcn_early_init(adev, 0);
124 }
125 
126 /**
127  * vcn_v2_0_sw_init - sw init for VCN block
128  *
129  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
130  *
131  * Load firmware and sw initialization
132  */
vcn_v2_0_sw_init(struct amdgpu_ip_block * ip_block)133 static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
134 {
135 	struct amdgpu_ring *ring;
136 	int i, r;
137 	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
138 	uint32_t *ptr;
139 	struct amdgpu_device *adev = ip_block->adev;
140 	volatile struct amdgpu_fw_shared *fw_shared;
141 
142 	/* VCN DEC TRAP */
143 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
144 			      VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
145 			      &adev->vcn.inst->irq);
146 	if (r)
147 		return r;
148 
149 	/* VCN ENC TRAP */
150 	for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
151 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
152 				      i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
153 				      &adev->vcn.inst->irq);
154 		if (r)
155 			return r;
156 	}
157 
158 	r = amdgpu_vcn_sw_init(adev, 0);
159 	if (r)
160 		return r;
161 
162 	amdgpu_vcn_setup_ucode(adev, 0);
163 
164 	r = amdgpu_vcn_resume(adev, 0);
165 	if (r)
166 		return r;
167 
168 	ring = &adev->vcn.inst->ring_dec;
169 
170 	ring->use_doorbell = true;
171 	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
172 	ring->vm_hub = AMDGPU_MMHUB0(0);
173 
174 	sprintf(ring->name, "vcn_dec");
175 	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
176 			     AMDGPU_RING_PRIO_DEFAULT, NULL);
177 	if (r)
178 		return r;
179 
180 	adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
181 	adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
182 	adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
183 	adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
184 	adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
185 	adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
186 
187 	adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
188 	adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
189 	adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
190 	adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
191 	adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
192 	adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
193 	adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
194 	adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
195 	adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
196 	adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
197 
198 	for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
199 		enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
200 
201 		ring = &adev->vcn.inst->ring_enc[i];
202 		ring->use_doorbell = true;
203 		ring->vm_hub = AMDGPU_MMHUB0(0);
204 		if (!amdgpu_sriov_vf(adev))
205 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
206 		else
207 			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
208 		sprintf(ring->name, "vcn_enc%d", i);
209 		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
210 				     hw_prio, NULL);
211 		if (r)
212 			return r;
213 	}
214 
215 	adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
216 
217 	r = amdgpu_virt_alloc_mm_table(adev);
218 	if (r)
219 		return r;
220 
221 	fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
222 	fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
223 
224 	if (amdgpu_vcnfw_log)
225 		amdgpu_vcn_fwlog_init(adev->vcn.inst);
226 
227 	/* Allocate memory for VCN IP Dump buffer */
228 	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
229 	if (!ptr) {
230 		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
231 		adev->vcn.ip_dump = NULL;
232 	} else {
233 		adev->vcn.ip_dump = ptr;
234 	}
235 
236 	return 0;
237 }
238 
239 /**
240  * vcn_v2_0_sw_fini - sw fini for VCN block
241  *
242  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
243  *
244  * VCN suspend and free up sw allocation
245  */
vcn_v2_0_sw_fini(struct amdgpu_ip_block * ip_block)246 static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
247 {
248 	int r, idx;
249 	struct amdgpu_device *adev = ip_block->adev;
250 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
251 
252 	if (drm_dev_enter(adev_to_drm(adev), &idx)) {
253 		fw_shared->present_flag_0 = 0;
254 		drm_dev_exit(idx);
255 	}
256 
257 	amdgpu_virt_free_mm_table(adev);
258 
259 	r = amdgpu_vcn_suspend(adev, 0);
260 	if (r)
261 		return r;
262 
263 	r = amdgpu_vcn_sw_fini(adev, 0);
264 
265 	kfree(adev->vcn.ip_dump);
266 
267 	return r;
268 }
269 
270 /**
271  * vcn_v2_0_hw_init - start and test VCN block
272  *
273  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
274  *
275  * Initialize the hardware, boot up the VCPU and do some testing
276  */
vcn_v2_0_hw_init(struct amdgpu_ip_block * ip_block)277 static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block)
278 {
279 	struct amdgpu_device *adev = ip_block->adev;
280 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
281 	int i, r;
282 
283 	adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
284 					     ring->doorbell_index, 0);
285 
286 	if (amdgpu_sriov_vf(adev))
287 		vcn_v2_0_start_sriov(adev);
288 
289 	r = amdgpu_ring_test_helper(ring);
290 	if (r)
291 		return r;
292 
293 	//Disable vcn decode for sriov
294 	if (amdgpu_sriov_vf(adev))
295 		ring->sched.ready = false;
296 
297 	for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
298 		ring = &adev->vcn.inst->ring_enc[i];
299 		r = amdgpu_ring_test_helper(ring);
300 		if (r)
301 			return r;
302 	}
303 
304 	return 0;
305 }
306 
307 /**
308  * vcn_v2_0_hw_fini - stop the hardware block
309  *
310  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
311  *
312  * Stop the VCN block, mark ring as not ready any more
313  */
vcn_v2_0_hw_fini(struct amdgpu_ip_block * ip_block)314 static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
315 {
316 	struct amdgpu_device *adev = ip_block->adev;
317 	struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
318 
319 	cancel_delayed_work_sync(&vinst->idle_work);
320 
321 	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
322 	    (vinst->cur_state != AMD_PG_STATE_GATE &&
323 	     RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
324 		vinst->set_pg_state(vinst, AMD_PG_STATE_GATE);
325 
326 	return 0;
327 }
328 
329 /**
330  * vcn_v2_0_suspend - suspend VCN block
331  *
332  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
333  *
334  * HW fini and suspend VCN block
335  */
vcn_v2_0_suspend(struct amdgpu_ip_block * ip_block)336 static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block)
337 {
338 	int r;
339 
340 	r = vcn_v2_0_hw_fini(ip_block);
341 	if (r)
342 		return r;
343 
344 	r = amdgpu_vcn_suspend(ip_block->adev, 0);
345 
346 	return r;
347 }
348 
349 /**
350  * vcn_v2_0_resume - resume VCN block
351  *
352  * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
353  *
354  * Resume firmware and hw init VCN block
355  */
vcn_v2_0_resume(struct amdgpu_ip_block * ip_block)356 static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block)
357 {
358 	int r;
359 
360 	r = amdgpu_vcn_resume(ip_block->adev, 0);
361 	if (r)
362 		return r;
363 
364 	r = vcn_v2_0_hw_init(ip_block);
365 
366 	return r;
367 }
368 
369 /**
370  * vcn_v2_0_mc_resume - memory controller programming
371  *
372  * @vinst: Pointer to the VCN instance structure
373  *
374  * Let the VCN memory controller know it's offsets
375  */
vcn_v2_0_mc_resume(struct amdgpu_vcn_inst * vinst)376 static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst)
377 {
378 	struct amdgpu_device *adev = vinst->adev;
379 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
380 	uint32_t offset;
381 
382 	if (amdgpu_sriov_vf(adev))
383 		return;
384 
385 	/* cache window 0: fw */
386 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
387 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
388 			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
389 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
390 			(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
391 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
392 		offset = 0;
393 	} else {
394 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
395 			lower_32_bits(adev->vcn.inst->gpu_addr));
396 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
397 			upper_32_bits(adev->vcn.inst->gpu_addr));
398 		offset = size;
399 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
400 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
401 	}
402 
403 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
404 
405 	/* cache window 1: stack */
406 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
407 		lower_32_bits(adev->vcn.inst->gpu_addr + offset));
408 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
409 		upper_32_bits(adev->vcn.inst->gpu_addr + offset));
410 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
411 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
412 
413 	/* cache window 2: context */
414 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
415 		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
416 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
417 		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
418 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
419 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
420 
421 	/* non-cache window */
422 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
423 		lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
424 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
425 		upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
426 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
427 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
428 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
429 
430 	WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
431 }
432 
vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)433 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
434 					bool indirect)
435 {
436 	struct amdgpu_device *adev = vinst->adev;
437 	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
438 	uint32_t offset;
439 
440 	/* cache window 0: fw */
441 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
442 		if (!indirect) {
443 			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
444 				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
445 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
446 			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
447 				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
448 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
449 			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
450 				UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
451 		} else {
452 			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
453 				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
454 			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
455 				UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
456 			WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
457 				UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
458 		}
459 		offset = 0;
460 	} else {
461 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
462 			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
463 			lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
464 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
465 			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
466 			upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
467 		offset = size;
468 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
469 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
470 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
471 	}
472 
473 	if (!indirect)
474 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
475 			UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
476 	else
477 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
478 			UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
479 
480 	/* cache window 1: stack */
481 	if (!indirect) {
482 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
483 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
484 			lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
485 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
486 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
487 			upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
488 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
489 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
490 	} else {
491 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
492 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
493 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
494 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
495 		WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
496 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
497 	}
498 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
499 		UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
500 
501 	/* cache window 2: context */
502 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
503 		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
504 		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
505 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
506 		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
507 		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
508 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
509 		UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
510 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
511 		UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
512 
513 	/* non-cache window */
514 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
515 		UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
516 		lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
517 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
518 		UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
519 		upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect);
520 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
521 		UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
522 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
523 		UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
524 		AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
525 
526 	/* VCN global tiling registers */
527 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
528 		UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
529 }
530 
531 /**
532  * vcn_v2_0_disable_clock_gating - disable VCN clock gating
533  *
534  * @vinst: VCN instance
535  *
536  * Disable clock gating for VCN block
537  */
vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst * vinst)538 static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
539 {
540 	struct amdgpu_device *adev = vinst->adev;
541 	uint32_t data;
542 
543 	if (amdgpu_sriov_vf(adev))
544 		return;
545 
546 	/* UVD disable CGC */
547 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
548 	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
549 		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
550 	else
551 		data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
552 	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
553 	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
554 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
555 
556 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
557 	data &= ~(UVD_CGC_GATE__SYS_MASK
558 		| UVD_CGC_GATE__UDEC_MASK
559 		| UVD_CGC_GATE__MPEG2_MASK
560 		| UVD_CGC_GATE__REGS_MASK
561 		| UVD_CGC_GATE__RBC_MASK
562 		| UVD_CGC_GATE__LMI_MC_MASK
563 		| UVD_CGC_GATE__LMI_UMC_MASK
564 		| UVD_CGC_GATE__IDCT_MASK
565 		| UVD_CGC_GATE__MPRD_MASK
566 		| UVD_CGC_GATE__MPC_MASK
567 		| UVD_CGC_GATE__LBSI_MASK
568 		| UVD_CGC_GATE__LRBBM_MASK
569 		| UVD_CGC_GATE__UDEC_RE_MASK
570 		| UVD_CGC_GATE__UDEC_CM_MASK
571 		| UVD_CGC_GATE__UDEC_IT_MASK
572 		| UVD_CGC_GATE__UDEC_DB_MASK
573 		| UVD_CGC_GATE__UDEC_MP_MASK
574 		| UVD_CGC_GATE__WCB_MASK
575 		| UVD_CGC_GATE__VCPU_MASK
576 		| UVD_CGC_GATE__SCPU_MASK);
577 	WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
578 
579 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
580 	data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
581 		| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
582 		| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
583 		| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
584 		| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
585 		| UVD_CGC_CTRL__SYS_MODE_MASK
586 		| UVD_CGC_CTRL__UDEC_MODE_MASK
587 		| UVD_CGC_CTRL__MPEG2_MODE_MASK
588 		| UVD_CGC_CTRL__REGS_MODE_MASK
589 		| UVD_CGC_CTRL__RBC_MODE_MASK
590 		| UVD_CGC_CTRL__LMI_MC_MODE_MASK
591 		| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
592 		| UVD_CGC_CTRL__IDCT_MODE_MASK
593 		| UVD_CGC_CTRL__MPRD_MODE_MASK
594 		| UVD_CGC_CTRL__MPC_MODE_MASK
595 		| UVD_CGC_CTRL__LBSI_MODE_MASK
596 		| UVD_CGC_CTRL__LRBBM_MODE_MASK
597 		| UVD_CGC_CTRL__WCB_MODE_MASK
598 		| UVD_CGC_CTRL__VCPU_MODE_MASK
599 		| UVD_CGC_CTRL__SCPU_MODE_MASK);
600 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
601 
602 	/* turn on */
603 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
604 	data |= (UVD_SUVD_CGC_GATE__SRE_MASK
605 		| UVD_SUVD_CGC_GATE__SIT_MASK
606 		| UVD_SUVD_CGC_GATE__SMP_MASK
607 		| UVD_SUVD_CGC_GATE__SCM_MASK
608 		| UVD_SUVD_CGC_GATE__SDB_MASK
609 		| UVD_SUVD_CGC_GATE__SRE_H264_MASK
610 		| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
611 		| UVD_SUVD_CGC_GATE__SIT_H264_MASK
612 		| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
613 		| UVD_SUVD_CGC_GATE__SCM_H264_MASK
614 		| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
615 		| UVD_SUVD_CGC_GATE__SDB_H264_MASK
616 		| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
617 		| UVD_SUVD_CGC_GATE__SCLR_MASK
618 		| UVD_SUVD_CGC_GATE__UVD_SC_MASK
619 		| UVD_SUVD_CGC_GATE__ENT_MASK
620 		| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
621 		| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
622 		| UVD_SUVD_CGC_GATE__SITE_MASK
623 		| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
624 		| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
625 		| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
626 		| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
627 		| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
628 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
629 
630 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
631 	data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
632 		| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
633 		| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
634 		| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
635 		| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
636 		| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
637 		| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
638 		| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
639 		| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
640 		| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
641 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
642 }
643 
vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst * vinst,uint8_t sram_sel,uint8_t indirect)644 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
645 		uint8_t sram_sel, uint8_t indirect)
646 {
647 	struct amdgpu_device *adev = vinst->adev;
648 	uint32_t reg_data = 0;
649 
650 	/* enable sw clock gating control */
651 	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
652 		reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
653 	else
654 		reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
655 	reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
656 	reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
657 	reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
658 		 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
659 		 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
660 		 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
661 		 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
662 		 UVD_CGC_CTRL__SYS_MODE_MASK |
663 		 UVD_CGC_CTRL__UDEC_MODE_MASK |
664 		 UVD_CGC_CTRL__MPEG2_MODE_MASK |
665 		 UVD_CGC_CTRL__REGS_MODE_MASK |
666 		 UVD_CGC_CTRL__RBC_MODE_MASK |
667 		 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
668 		 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
669 		 UVD_CGC_CTRL__IDCT_MODE_MASK |
670 		 UVD_CGC_CTRL__MPRD_MODE_MASK |
671 		 UVD_CGC_CTRL__MPC_MODE_MASK |
672 		 UVD_CGC_CTRL__LBSI_MODE_MASK |
673 		 UVD_CGC_CTRL__LRBBM_MODE_MASK |
674 		 UVD_CGC_CTRL__WCB_MODE_MASK |
675 		 UVD_CGC_CTRL__VCPU_MODE_MASK |
676 		 UVD_CGC_CTRL__SCPU_MODE_MASK);
677 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
678 		UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
679 
680 	/* turn off clock gating */
681 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
682 		UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
683 
684 	/* turn on SUVD clock gating */
685 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
686 		UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
687 
688 	/* turn on sw mode in UVD_SUVD_CGC_CTRL */
689 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
690 		UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
691 }
692 
693 /**
694  * vcn_v2_0_enable_clock_gating - enable VCN clock gating
695  *
696  * @vinst: VCN instance
697  *
698  * Enable clock gating for VCN block
699  */
vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst * vinst)700 static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
701 {
702 	struct amdgpu_device *adev = vinst->adev;
703 	uint32_t data = 0;
704 
705 	if (amdgpu_sriov_vf(adev))
706 		return;
707 
708 	/* enable UVD CGC */
709 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
710 	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
711 		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
712 	else
713 		data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
714 	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
715 	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
716 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
717 
718 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
719 	data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
720 		| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
721 		| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
722 		| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
723 		| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
724 		| UVD_CGC_CTRL__SYS_MODE_MASK
725 		| UVD_CGC_CTRL__UDEC_MODE_MASK
726 		| UVD_CGC_CTRL__MPEG2_MODE_MASK
727 		| UVD_CGC_CTRL__REGS_MODE_MASK
728 		| UVD_CGC_CTRL__RBC_MODE_MASK
729 		| UVD_CGC_CTRL__LMI_MC_MODE_MASK
730 		| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
731 		| UVD_CGC_CTRL__IDCT_MODE_MASK
732 		| UVD_CGC_CTRL__MPRD_MODE_MASK
733 		| UVD_CGC_CTRL__MPC_MODE_MASK
734 		| UVD_CGC_CTRL__LBSI_MODE_MASK
735 		| UVD_CGC_CTRL__LRBBM_MODE_MASK
736 		| UVD_CGC_CTRL__WCB_MODE_MASK
737 		| UVD_CGC_CTRL__VCPU_MODE_MASK
738 		| UVD_CGC_CTRL__SCPU_MODE_MASK);
739 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
740 
741 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
742 	data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
743 		| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
744 		| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
745 		| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
746 		| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
747 		| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
748 		| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
749 		| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
750 		| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
751 		| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
752 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
753 }
754 
vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst * vinst)755 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
756 {
757 	struct amdgpu_device *adev = vinst->adev;
758 	uint32_t data = 0;
759 
760 	if (amdgpu_sriov_vf(adev))
761 		return;
762 
763 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
764 		data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
765 			| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
766 			| 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
767 			| 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
768 			| 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
769 			| 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
770 			| 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
771 			| 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
772 			| 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
773 			| 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
774 
775 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
776 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
777 			UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);
778 	} else {
779 		data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
780 			| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
781 			| 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
782 			| 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
783 			| 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
784 			| 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
785 			| 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
786 			| 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
787 			| 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
788 			| 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
789 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
790 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFF);
791 	}
792 
793 	/* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
794 	 * UVDU_PWR_STATUS are 0 (power on) */
795 
796 	data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
797 	data &= ~0x103;
798 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
799 		data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
800 			UVD_POWER_STATUS__UVD_PG_EN_MASK;
801 
802 	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
803 }
804 
vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst * vinst)805 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
806 {
807 	struct amdgpu_device *adev = vinst->adev;
808 	uint32_t data = 0;
809 
810 	if (amdgpu_sriov_vf(adev))
811 		return;
812 
813 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
814 		/* Before power off, this indicator has to be turned on */
815 		data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
816 		data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
817 		data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
818 		WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
819 
820 
821 		data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
822 			| 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
823 			| 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
824 			| 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
825 			| 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
826 			| 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
827 			| 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
828 			| 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
829 			| 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
830 			| 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
831 
832 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
833 
834 		data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
835 			| 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
836 			| 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
837 			| 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
838 			| 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
839 			| 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
840 			| 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
841 			| 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
842 			| 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
843 			| 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
844 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);
845 	}
846 }
847 
vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst * vinst,bool indirect)848 static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
849 {
850 	struct amdgpu_device *adev = vinst->adev;
851 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
852 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
853 	uint32_t rb_bufsz, tmp;
854 
855 	vcn_v2_0_enable_static_power_gating(vinst);
856 
857 	/* enable dynamic power gating mode */
858 	tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
859 	tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
860 	tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
861 	WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
862 
863 	if (indirect)
864 		adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr;
865 
866 	/* enable clock gating */
867 	vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect);
868 
869 	/* enable VCPU clock */
870 	tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
871 	tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
872 	tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
873 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
874 		UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
875 
876 	/* disable master interupt */
877 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
878 		UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
879 
880 	/* setup mmUVD_LMI_CTRL */
881 	tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
882 		UVD_LMI_CTRL__REQ_MODE_MASK |
883 		UVD_LMI_CTRL__CRC_RESET_MASK |
884 		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
885 		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
886 		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
887 		(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
888 		0x00100000L);
889 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
890 		UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
891 
892 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
893 		UVD, 0, mmUVD_MPC_CNTL),
894 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
895 
896 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
897 		UVD, 0, mmUVD_MPC_SET_MUXA0),
898 		((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
899 		 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
900 		 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
901 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
902 
903 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
904 		UVD, 0, mmUVD_MPC_SET_MUXB0),
905 		((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
906 		 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
907 		 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
908 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
909 
910 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
911 		UVD, 0, mmUVD_MPC_SET_MUX),
912 		((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
913 		 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
914 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
915 
916 	vcn_v2_0_mc_resume_dpg_mode(vinst, indirect);
917 
918 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
919 		UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
920 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
921 		UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
922 
923 	/* release VCPU reset to boot */
924 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
925 		UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
926 
927 	/* enable LMI MC and UMC channels */
928 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
929 		UVD, 0, mmUVD_LMI_CTRL2),
930 		0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
931 
932 	/* enable master interrupt */
933 	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
934 		UVD, 0, mmUVD_MASTINT_EN),
935 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
936 
937 	if (indirect)
938 		amdgpu_vcn_psp_update_sram(adev, 0, 0);
939 
940 	/* force RBC into idle state */
941 	rb_bufsz = order_base_2(ring->ring_size);
942 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
943 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
944 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
945 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
946 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
947 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
948 
949 	/* Stall DPG before WPTR/RPTR reset */
950 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
951 		UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
952 		~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
953 	fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
954 
955 	/* set the write pointer delay */
956 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
957 
958 	/* set the wb address */
959 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
960 		(upper_32_bits(ring->gpu_addr) >> 2));
961 
962 	/* program the RB_BASE for ring buffer */
963 	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
964 		lower_32_bits(ring->gpu_addr));
965 	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
966 		upper_32_bits(ring->gpu_addr));
967 
968 	/* Initialize the ring buffer's read and write pointers */
969 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
970 
971 	WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
972 
973 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
974 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
975 		lower_32_bits(ring->wptr));
976 
977 	fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
978 	/* Unstall DPG */
979 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
980 		0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
981 	return 0;
982 }
983 
vcn_v2_0_start(struct amdgpu_vcn_inst * vinst)984 static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
985 {
986 	struct amdgpu_device *adev = vinst->adev;
987 	volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
988 	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
989 	uint32_t rb_bufsz, tmp;
990 	uint32_t lmi_swap_cntl;
991 	int i, j, r;
992 
993 	if (adev->pm.dpm_enabled)
994 		amdgpu_dpm_enable_vcn(adev, true, 0);
995 
996 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
997 		return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram);
998 
999 	vcn_v2_0_disable_static_power_gating(vinst);
1000 
1001 	/* set uvd status busy */
1002 	tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1003 	WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
1004 
1005 	/*SW clock gating */
1006 	vcn_v2_0_disable_clock_gating(vinst);
1007 
1008 	/* enable VCPU clock */
1009 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
1010 		UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1011 
1012 	/* disable master interrupt */
1013 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
1014 		~UVD_MASTINT_EN__VCPU_EN_MASK);
1015 
1016 	/* setup mmUVD_LMI_CTRL */
1017 	tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
1018 	WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
1019 		UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|
1020 		UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1021 		UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1022 		UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1023 
1024 	/* setup mmUVD_MPC_CNTL */
1025 	tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
1026 	tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1027 	tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1028 	WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
1029 
1030 	/* setup UVD_MPC_SET_MUXA0 */
1031 	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
1032 		((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1033 		(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1034 		(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1035 		(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1036 
1037 	/* setup UVD_MPC_SET_MUXB0 */
1038 	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
1039 		((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1040 		(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1041 		(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1042 		(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1043 
1044 	/* setup mmUVD_MPC_SET_MUX */
1045 	WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
1046 		((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1047 		(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1048 		(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1049 
1050 	vcn_v2_0_mc_resume(vinst);
1051 
1052 	/* release VCPU reset to boot */
1053 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1054 		~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1055 
1056 	/* enable LMI MC and UMC channels */
1057 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1058 		~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1059 
1060 	tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1061 	tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1062 	tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1063 	WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1064 
1065 	/* disable byte swapping */
1066 	lmi_swap_cntl = 0;
1067 #ifdef __BIG_ENDIAN
1068 	/* swap (8 in 32) RB and IB */
1069 	lmi_swap_cntl = 0xa;
1070 #endif
1071 	WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1072 
1073 	for (i = 0; i < 10; ++i) {
1074 		uint32_t status;
1075 
1076 		for (j = 0; j < 100; ++j) {
1077 			status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1078 			if (status & 2)
1079 				break;
1080 			mdelay(10);
1081 		}
1082 		r = 0;
1083 		if (status & 2)
1084 			break;
1085 
1086 		DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1087 		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1088 			UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1089 			~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1090 		mdelay(10);
1091 		WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1092 			~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1093 		mdelay(10);
1094 		r = -1;
1095 	}
1096 
1097 	if (r) {
1098 		DRM_ERROR("VCN decode not responding, giving up!!!\n");
1099 		return r;
1100 	}
1101 
1102 	/* enable master interrupt */
1103 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1104 		UVD_MASTINT_EN__VCPU_EN_MASK,
1105 		~UVD_MASTINT_EN__VCPU_EN_MASK);
1106 
1107 	/* clear the busy bit of VCN_STATUS */
1108 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1109 		~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1110 
1111 	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1112 
1113 	/* force RBC into idle state */
1114 	rb_bufsz = order_base_2(ring->ring_size);
1115 	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1116 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1117 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1118 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1119 	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1120 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1121 
1122 	fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1123 	/* program the RB_BASE for ring buffer */
1124 	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1125 		lower_32_bits(ring->gpu_addr));
1126 	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1127 		upper_32_bits(ring->gpu_addr));
1128 
1129 	/* Initialize the ring buffer's read and write pointers */
1130 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1131 
1132 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1133 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1134 			lower_32_bits(ring->wptr));
1135 	fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1136 
1137 	fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1138 	ring = &adev->vcn.inst->ring_enc[0];
1139 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1140 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1141 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1142 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1143 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1144 	fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1145 
1146 	fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1147 	ring = &adev->vcn.inst->ring_enc[1];
1148 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1149 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1150 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1151 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1152 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1153 	fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1154 
1155 	return 0;
1156 }
1157 
vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst * vinst)1158 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
1159 {
1160 	struct amdgpu_device *adev = vinst->adev;
1161 	struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
1162 	uint32_t tmp;
1163 
1164 	vcn_v2_0_pause_dpg_mode(vinst, &state);
1165 	/* Wait for power status to be 1 */
1166 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1167 		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1168 
1169 	/* wait for read ptr to be equal to write ptr */
1170 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1171 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1172 
1173 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1174 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1175 
1176 	tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1177 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1178 
1179 	SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1180 		UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1181 
1182 	/* disable dynamic power gating mode */
1183 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1184 			~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1185 
1186 	return 0;
1187 }
1188 
vcn_v2_0_stop(struct amdgpu_vcn_inst * vinst)1189 static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)
1190 {
1191 	struct amdgpu_device *adev = vinst->adev;
1192 	uint32_t tmp;
1193 	int r;
1194 
1195 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1196 		r = vcn_v2_0_stop_dpg_mode(vinst);
1197 		if (r)
1198 			return r;
1199 		goto power_off;
1200 	}
1201 
1202 	/* wait for uvd idle */
1203 	r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1204 	if (r)
1205 		return r;
1206 
1207 	tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1208 		UVD_LMI_STATUS__READ_CLEAN_MASK |
1209 		UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1210 		UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1211 	r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1212 	if (r)
1213 		return r;
1214 
1215 	/* stall UMC channel */
1216 	tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1217 	tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1218 	WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1219 
1220 	tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1221 		UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1222 	r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1223 	if (r)
1224 		return r;
1225 
1226 	/* disable VCPU clock */
1227 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1228 		~(UVD_VCPU_CNTL__CLK_EN_MASK));
1229 
1230 	/* reset LMI UMC */
1231 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1232 		UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1233 		~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1234 
1235 	/* reset LMI */
1236 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1237 		UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1238 		~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1239 
1240 	/* reset VCPU */
1241 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1242 		UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1243 		~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1244 
1245 	/* clear status */
1246 	WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1247 
1248 	vcn_v2_0_enable_clock_gating(vinst);
1249 	vcn_v2_0_enable_static_power_gating(vinst);
1250 
1251 power_off:
1252 	if (adev->pm.dpm_enabled)
1253 		amdgpu_dpm_enable_vcn(adev, false, 0);
1254 
1255 	return 0;
1256 }
1257 
vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst * vinst,struct dpg_pause_state * new_state)1258 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
1259 				   struct dpg_pause_state *new_state)
1260 {
1261 	struct amdgpu_device *adev = vinst->adev;
1262 	int inst_idx = vinst->inst;
1263 	struct amdgpu_ring *ring;
1264 	uint32_t reg_data = 0;
1265 	int ret_code;
1266 
1267 	/* pause/unpause if state is changed */
1268 	if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1269 		DRM_DEBUG("dpg pause state changed %d -> %d",
1270 			adev->vcn.inst[inst_idx].pause_state.fw_based,	new_state->fw_based);
1271 		reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1272 			(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1273 
1274 		if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1275 			ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1276 				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1277 
1278 			if (!ret_code) {
1279 				volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
1280 				/* pause DPG */
1281 				reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1282 				WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1283 
1284 				/* wait for ACK */
1285 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1286 					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1287 					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1288 
1289 				/* Stall DPG before WPTR/RPTR reset */
1290 				WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1291 					   UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1292 					   ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1293 				/* Restore */
1294 				fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1295 				ring = &adev->vcn.inst->ring_enc[0];
1296 				ring->wptr = 0;
1297 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1298 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1299 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1300 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1301 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1302 				fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1303 
1304 				fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1305 				ring = &adev->vcn.inst->ring_enc[1];
1306 				ring->wptr = 0;
1307 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1308 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1309 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1310 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1311 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1312 				fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1313 
1314 				fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1315 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1316 					   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1317 				fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1318 				/* Unstall DPG */
1319 				WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1320 					   0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1321 
1322 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1323 					   UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1324 					   UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1325 			}
1326 		} else {
1327 			/* unpause dpg, no need to wait */
1328 			reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1329 			WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1330 		}
1331 		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1332 	}
1333 
1334 	return 0;
1335 }
1336 
vcn_v2_0_is_idle(struct amdgpu_ip_block * ip_block)1337 static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
1338 {
1339 	struct amdgpu_device *adev = ip_block->adev;
1340 
1341 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1342 }
1343 
vcn_v2_0_wait_for_idle(struct amdgpu_ip_block * ip_block)1344 static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1345 {
1346 	struct amdgpu_device *adev = ip_block->adev;
1347 	int ret;
1348 
1349 	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1350 		UVD_STATUS__IDLE);
1351 
1352 	return ret;
1353 }
1354 
vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1355 static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1356 					  enum amd_clockgating_state state)
1357 {
1358 	struct amdgpu_device *adev = ip_block->adev;
1359 	bool enable = (state == AMD_CG_STATE_GATE);
1360 
1361 	if (amdgpu_sriov_vf(adev))
1362 		return 0;
1363 
1364 	if (enable) {
1365 		/* wait for STATUS to clear */
1366 		if (!vcn_v2_0_is_idle(ip_block))
1367 			return -EBUSY;
1368 		vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]);
1369 	} else {
1370 		/* disable HW gating and enable Sw gating */
1371 		vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]);
1372 	}
1373 	return 0;
1374 }
1375 
1376 /**
1377  * vcn_v2_0_dec_ring_get_rptr - get read pointer
1378  *
1379  * @ring: amdgpu_ring pointer
1380  *
1381  * Returns the current hardware read pointer
1382  */
vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1383 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1384 {
1385 	struct amdgpu_device *adev = ring->adev;
1386 
1387 	return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1388 }
1389 
1390 /**
1391  * vcn_v2_0_dec_ring_get_wptr - get write pointer
1392  *
1393  * @ring: amdgpu_ring pointer
1394  *
1395  * Returns the current hardware write pointer
1396  */
vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1397 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1398 {
1399 	struct amdgpu_device *adev = ring->adev;
1400 
1401 	if (ring->use_doorbell)
1402 		return *ring->wptr_cpu_addr;
1403 	else
1404 		return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1405 }
1406 
1407 /**
1408  * vcn_v2_0_dec_ring_set_wptr - set write pointer
1409  *
1410  * @ring: amdgpu_ring pointer
1411  *
1412  * Commits the write pointer to the hardware
1413  */
vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1414 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1415 {
1416 	struct amdgpu_device *adev = ring->adev;
1417 
1418 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1419 		WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1420 			lower_32_bits(ring->wptr) | 0x80000000);
1421 
1422 	if (ring->use_doorbell) {
1423 		*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1424 		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1425 	} else {
1426 		WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1427 	}
1428 }
1429 
1430 /**
1431  * vcn_v2_0_dec_ring_insert_start - insert a start command
1432  *
1433  * @ring: amdgpu_ring pointer
1434  *
1435  * Write a start command to the ring.
1436  */
vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)1437 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1438 {
1439 	struct amdgpu_device *adev = ring->adev;
1440 
1441 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1442 	amdgpu_ring_write(ring, 0);
1443 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1444 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1445 }
1446 
1447 /**
1448  * vcn_v2_0_dec_ring_insert_end - insert a end command
1449  *
1450  * @ring: amdgpu_ring pointer
1451  *
1452  * Write a end command to the ring.
1453  */
vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)1454 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1455 {
1456 	struct amdgpu_device *adev = ring->adev;
1457 
1458 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0));
1459 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1460 }
1461 
1462 /**
1463  * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1464  *
1465  * @ring: amdgpu_ring pointer
1466  * @count: the number of NOP packets to insert
1467  *
1468  * Write a nop command to the ring.
1469  */
vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1470 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1471 {
1472 	struct amdgpu_device *adev = ring->adev;
1473 	int i;
1474 
1475 	WARN_ON(ring->wptr % 2 || count % 2);
1476 
1477 	for (i = 0; i < count / 2; i++) {
1478 		amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0));
1479 		amdgpu_ring_write(ring, 0);
1480 	}
1481 }
1482 
1483 /**
1484  * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1485  *
1486  * @ring: amdgpu_ring pointer
1487  * @addr: address
1488  * @seq: sequence number
1489  * @flags: fence related flags
1490  *
1491  * Write a fence and a trap command to the ring.
1492  */
vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1493 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1494 				unsigned flags)
1495 {
1496 	struct amdgpu_device *adev = ring->adev;
1497 
1498 	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1499 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0));
1500 	amdgpu_ring_write(ring, seq);
1501 
1502 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1503 	amdgpu_ring_write(ring, addr & 0xffffffff);
1504 
1505 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1506 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1507 
1508 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1509 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1510 
1511 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1512 	amdgpu_ring_write(ring, 0);
1513 
1514 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1515 	amdgpu_ring_write(ring, 0);
1516 
1517 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1518 
1519 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1520 }
1521 
1522 /**
1523  * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1524  *
1525  * @ring: amdgpu_ring pointer
1526  * @job: job to retrieve vmid from
1527  * @ib: indirect buffer to execute
1528  * @flags: unused
1529  *
1530  * Write ring commands to execute the indirect buffer
1531  */
vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1532 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1533 			       struct amdgpu_job *job,
1534 			       struct amdgpu_ib *ib,
1535 			       uint32_t flags)
1536 {
1537 	struct amdgpu_device *adev = ring->adev;
1538 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1539 
1540 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0));
1541 	amdgpu_ring_write(ring, vmid);
1542 
1543 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0));
1544 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1545 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0));
1546 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1547 	amdgpu_ring_write(ring,	PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0));
1548 	amdgpu_ring_write(ring, ib->length_dw);
1549 }
1550 
vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1551 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1552 				uint32_t val, uint32_t mask)
1553 {
1554 	struct amdgpu_device *adev = ring->adev;
1555 
1556 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1557 	amdgpu_ring_write(ring, reg << 2);
1558 
1559 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1560 	amdgpu_ring_write(ring, val);
1561 
1562 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0));
1563 	amdgpu_ring_write(ring, mask);
1564 
1565 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1566 
1567 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1568 }
1569 
vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1570 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1571 				unsigned vmid, uint64_t pd_addr)
1572 {
1573 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1574 	uint32_t data0, data1, mask;
1575 
1576 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1577 
1578 	/* wait for register write */
1579 	data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1580 	data1 = lower_32_bits(pd_addr);
1581 	mask = 0xffffffff;
1582 	vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1583 }
1584 
vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1585 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1586 				uint32_t reg, uint32_t val)
1587 {
1588 	struct amdgpu_device *adev = ring->adev;
1589 
1590 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0));
1591 	amdgpu_ring_write(ring, reg << 2);
1592 
1593 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0));
1594 	amdgpu_ring_write(ring, val);
1595 
1596 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1597 
1598 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1599 }
1600 
1601 /**
1602  * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1603  *
1604  * @ring: amdgpu_ring pointer
1605  *
1606  * Returns the current hardware enc read pointer
1607  */
vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1608 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1609 {
1610 	struct amdgpu_device *adev = ring->adev;
1611 
1612 	if (ring == &adev->vcn.inst->ring_enc[0])
1613 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1614 	else
1615 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1616 }
1617 
1618  /**
1619  * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1620  *
1621  * @ring: amdgpu_ring pointer
1622  *
1623  * Returns the current hardware enc write pointer
1624  */
vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1625 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1626 {
1627 	struct amdgpu_device *adev = ring->adev;
1628 
1629 	if (ring == &adev->vcn.inst->ring_enc[0]) {
1630 		if (ring->use_doorbell)
1631 			return *ring->wptr_cpu_addr;
1632 		else
1633 			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1634 	} else {
1635 		if (ring->use_doorbell)
1636 			return *ring->wptr_cpu_addr;
1637 		else
1638 			return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1639 	}
1640 }
1641 
1642  /**
1643  * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1644  *
1645  * @ring: amdgpu_ring pointer
1646  *
1647  * Commits the enc write pointer to the hardware
1648  */
vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1649 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1650 {
1651 	struct amdgpu_device *adev = ring->adev;
1652 
1653 	if (ring == &adev->vcn.inst->ring_enc[0]) {
1654 		if (ring->use_doorbell) {
1655 			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1656 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1657 		} else {
1658 			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1659 		}
1660 	} else {
1661 		if (ring->use_doorbell) {
1662 			*ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1663 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1664 		} else {
1665 			WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1666 		}
1667 	}
1668 }
1669 
1670 /**
1671  * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1672  *
1673  * @ring: amdgpu_ring pointer
1674  * @addr: address
1675  * @seq: sequence number
1676  * @flags: fence related flags
1677  *
1678  * Write enc a fence and a trap command to the ring.
1679  */
vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1680 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1681 				u64 seq, unsigned flags)
1682 {
1683 	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1684 
1685 	amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1686 	amdgpu_ring_write(ring, addr);
1687 	amdgpu_ring_write(ring, upper_32_bits(addr));
1688 	amdgpu_ring_write(ring, seq);
1689 	amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1690 }
1691 
vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring * ring)1692 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1693 {
1694 	amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1695 }
1696 
1697 /**
1698  * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1699  *
1700  * @ring: amdgpu_ring pointer
1701  * @job: job to retrive vmid from
1702  * @ib: indirect buffer to execute
1703  * @flags: unused
1704  *
1705  * Write enc ring commands to execute the indirect buffer
1706  */
vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1707 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1708 			       struct amdgpu_job *job,
1709 			       struct amdgpu_ib *ib,
1710 			       uint32_t flags)
1711 {
1712 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1713 
1714 	amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1715 	amdgpu_ring_write(ring, vmid);
1716 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1717 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1718 	amdgpu_ring_write(ring, ib->length_dw);
1719 }
1720 
vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1721 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1722 				uint32_t val, uint32_t mask)
1723 {
1724 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1725 	amdgpu_ring_write(ring, reg << 2);
1726 	amdgpu_ring_write(ring, mask);
1727 	amdgpu_ring_write(ring, val);
1728 }
1729 
vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1730 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1731 				unsigned int vmid, uint64_t pd_addr)
1732 {
1733 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1734 
1735 	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1736 
1737 	/* wait for reg writes */
1738 	vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1739 					vmid * hub->ctx_addr_distance,
1740 					lower_32_bits(pd_addr), 0xffffffff);
1741 }
1742 
vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1743 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1744 {
1745 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1746 	amdgpu_ring_write(ring,	reg << 2);
1747 	amdgpu_ring_write(ring, val);
1748 }
1749 
vcn_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1750 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1751 					struct amdgpu_irq_src *source,
1752 					unsigned type,
1753 					enum amdgpu_interrupt_state state)
1754 {
1755 	return 0;
1756 }
1757 
vcn_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1758 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1759 				      struct amdgpu_irq_src *source,
1760 				      struct amdgpu_iv_entry *entry)
1761 {
1762 	DRM_DEBUG("IH: VCN TRAP\n");
1763 
1764 	switch (entry->src_id) {
1765 	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1766 		amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1767 		break;
1768 	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1769 		amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1770 		break;
1771 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1772 		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1773 		break;
1774 	default:
1775 		DRM_ERROR("Unhandled interrupt: %d %d\n",
1776 			  entry->src_id, entry->src_data[0]);
1777 		break;
1778 	}
1779 
1780 	return 0;
1781 }
1782 
vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring * ring)1783 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1784 {
1785 	struct amdgpu_device *adev = ring->adev;
1786 	uint32_t tmp = 0;
1787 	unsigned i;
1788 	int r;
1789 
1790 	if (amdgpu_sriov_vf(adev))
1791 		return 0;
1792 
1793 	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1794 	r = amdgpu_ring_alloc(ring, 4);
1795 	if (r)
1796 		return r;
1797 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0));
1798 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1799 	amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0));
1800 	amdgpu_ring_write(ring, 0xDEADBEEF);
1801 	amdgpu_ring_commit(ring);
1802 	for (i = 0; i < adev->usec_timeout; i++) {
1803 		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1804 		if (tmp == 0xDEADBEEF)
1805 			break;
1806 		udelay(1);
1807 	}
1808 
1809 	if (i >= adev->usec_timeout)
1810 		r = -ETIMEDOUT;
1811 
1812 	return r;
1813 }
1814 
1815 
vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst * vinst,enum amd_powergating_state state)1816 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
1817 				 enum amd_powergating_state state)
1818 {
1819 	/* This doesn't actually powergate the VCN block.
1820 	 * That's done in the dpm code via the SMC.  This
1821 	 * just re-inits the block as necessary.  The actual
1822 	 * gating still happens in the dpm code.  We should
1823 	 * revisit this when there is a cleaner line between
1824 	 * the smc and the hw blocks
1825 	 */
1826 	int ret;
1827 	struct amdgpu_device *adev = vinst->adev;
1828 
1829 	if (amdgpu_sriov_vf(adev)) {
1830 		vinst->cur_state = AMD_PG_STATE_UNGATE;
1831 		return 0;
1832 	}
1833 
1834 	if (state == vinst->cur_state)
1835 		return 0;
1836 
1837 	if (state == AMD_PG_STATE_GATE)
1838 		ret = vcn_v2_0_stop(vinst);
1839 	else
1840 		ret = vcn_v2_0_start(vinst);
1841 
1842 	if (!ret)
1843 		vinst->cur_state = state;
1844 
1845 	return ret;
1846 }
1847 
vcn_v2_0_start_mmsch(struct amdgpu_device * adev,struct amdgpu_mm_table * table)1848 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1849 				struct amdgpu_mm_table *table)
1850 {
1851 	uint32_t data = 0, loop;
1852 	uint64_t addr = table->gpu_addr;
1853 	struct mmsch_v2_0_init_header *header;
1854 	uint32_t size;
1855 	int i;
1856 
1857 	header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1858 	size = header->header_size + header->vcn_table_size;
1859 
1860 	/* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1861 	 * of memory descriptor location
1862 	 */
1863 	WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1864 	WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1865 
1866 	/* 2, update vmid of descriptor */
1867 	data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1868 	data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1869 	/* use domain0 for MM scheduler */
1870 	data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1871 	WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1872 
1873 	/* 3, notify mmsch about the size of this descriptor */
1874 	WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1875 
1876 	/* 4, set resp to zero */
1877 	WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1878 
1879 	adev->vcn.inst->ring_dec.wptr = 0;
1880 	adev->vcn.inst->ring_dec.wptr_old = 0;
1881 	vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1882 
1883 	for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
1884 		adev->vcn.inst->ring_enc[i].wptr = 0;
1885 		adev->vcn.inst->ring_enc[i].wptr_old = 0;
1886 		vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1887 	}
1888 
1889 	/* 5, kick off the initialization and wait until
1890 	 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1891 	 */
1892 	WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1893 
1894 	data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1895 	loop = 1000;
1896 	while ((data & 0x10000002) != 0x10000002) {
1897 		udelay(10);
1898 		data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1899 		loop--;
1900 		if (!loop)
1901 			break;
1902 	}
1903 
1904 	if (!loop) {
1905 		DRM_ERROR("failed to init MMSCH, " \
1906 			"mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1907 		return -EBUSY;
1908 	}
1909 
1910 	return 0;
1911 }
1912 
vcn_v2_0_start_sriov(struct amdgpu_device * adev)1913 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1914 {
1915 	int r;
1916 	uint32_t tmp;
1917 	struct amdgpu_ring *ring;
1918 	uint32_t offset, size;
1919 	uint32_t table_size = 0;
1920 	struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1921 	struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1922 	struct mmsch_v2_0_cmd_end end = { {0} };
1923 	struct mmsch_v2_0_init_header *header;
1924 	uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1925 	uint8_t i = 0;
1926 
1927 	header = (struct mmsch_v2_0_init_header *)init_table;
1928 	direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1929 	direct_rd_mod_wt.cmd_header.command_type =
1930 		MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1931 	end.cmd_header.command_type = MMSCH_COMMAND__END;
1932 
1933 	if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1934 		header->version = MMSCH_VERSION;
1935 		header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1936 
1937 		header->vcn_table_offset = header->header_size;
1938 
1939 		init_table += header->vcn_table_offset;
1940 
1941 		size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
1942 
1943 		MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1944 			SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1945 			0xFFFFFFFF, 0x00000004);
1946 
1947 		/* mc resume*/
1948 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1949 			MMSCH_V2_0_INSERT_DIRECT_WT(
1950 				SOC15_REG_OFFSET(UVD, i,
1951 					mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1952 				adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo);
1953 			MMSCH_V2_0_INSERT_DIRECT_WT(
1954 				SOC15_REG_OFFSET(UVD, i,
1955 					mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1956 				adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi);
1957 			offset = 0;
1958 		} else {
1959 			MMSCH_V2_0_INSERT_DIRECT_WT(
1960 				SOC15_REG_OFFSET(UVD, i,
1961 					mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1962 				lower_32_bits(adev->vcn.inst->gpu_addr));
1963 			MMSCH_V2_0_INSERT_DIRECT_WT(
1964 				SOC15_REG_OFFSET(UVD, i,
1965 					mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1966 				upper_32_bits(adev->vcn.inst->gpu_addr));
1967 			offset = size;
1968 		}
1969 
1970 		MMSCH_V2_0_INSERT_DIRECT_WT(
1971 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1972 			0);
1973 		MMSCH_V2_0_INSERT_DIRECT_WT(
1974 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1975 			size);
1976 
1977 		MMSCH_V2_0_INSERT_DIRECT_WT(
1978 			SOC15_REG_OFFSET(UVD, i,
1979 				mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1980 			lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1981 		MMSCH_V2_0_INSERT_DIRECT_WT(
1982 			SOC15_REG_OFFSET(UVD, i,
1983 				mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1984 			upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1985 		MMSCH_V2_0_INSERT_DIRECT_WT(
1986 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1987 			0);
1988 		MMSCH_V2_0_INSERT_DIRECT_WT(
1989 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1990 			AMDGPU_VCN_STACK_SIZE);
1991 
1992 		MMSCH_V2_0_INSERT_DIRECT_WT(
1993 			SOC15_REG_OFFSET(UVD, i,
1994 				mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1995 			lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1996 				AMDGPU_VCN_STACK_SIZE));
1997 		MMSCH_V2_0_INSERT_DIRECT_WT(
1998 			SOC15_REG_OFFSET(UVD, i,
1999 				mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
2000 			upper_32_bits(adev->vcn.inst->gpu_addr + offset +
2001 				AMDGPU_VCN_STACK_SIZE));
2002 		MMSCH_V2_0_INSERT_DIRECT_WT(
2003 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
2004 			0);
2005 		MMSCH_V2_0_INSERT_DIRECT_WT(
2006 			SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
2007 			AMDGPU_VCN_CONTEXT_SIZE);
2008 
2009 		for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) {
2010 			ring = &adev->vcn.inst->ring_enc[r];
2011 			ring->wptr = 0;
2012 			MMSCH_V2_0_INSERT_DIRECT_WT(
2013 				SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
2014 				lower_32_bits(ring->gpu_addr));
2015 			MMSCH_V2_0_INSERT_DIRECT_WT(
2016 				SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
2017 				upper_32_bits(ring->gpu_addr));
2018 			MMSCH_V2_0_INSERT_DIRECT_WT(
2019 				SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
2020 				ring->ring_size / 4);
2021 		}
2022 
2023 		ring = &adev->vcn.inst->ring_dec;
2024 		ring->wptr = 0;
2025 		MMSCH_V2_0_INSERT_DIRECT_WT(
2026 			SOC15_REG_OFFSET(UVD, i,
2027 				mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
2028 			lower_32_bits(ring->gpu_addr));
2029 		MMSCH_V2_0_INSERT_DIRECT_WT(
2030 			SOC15_REG_OFFSET(UVD, i,
2031 				mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
2032 			upper_32_bits(ring->gpu_addr));
2033 		/* force RBC into idle state */
2034 		tmp = order_base_2(ring->ring_size);
2035 		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
2036 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
2037 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
2038 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
2039 		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
2040 		MMSCH_V2_0_INSERT_DIRECT_WT(
2041 			SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
2042 
2043 		/* add end packet */
2044 		tmp = sizeof(struct mmsch_v2_0_cmd_end);
2045 		memcpy((void *)init_table, &end, tmp);
2046 		table_size += (tmp / 4);
2047 		header->vcn_table_size = table_size;
2048 
2049 	}
2050 	return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
2051 }
2052 
vcn_v2_0_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)2053 static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2054 {
2055 	struct amdgpu_device *adev = ip_block->adev;
2056 	int i, j;
2057 	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
2058 	uint32_t inst_off, is_powered;
2059 
2060 	if (!adev->vcn.ip_dump)
2061 		return;
2062 
2063 	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
2064 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2065 		if (adev->vcn.harvest_config & (1 << i)) {
2066 			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
2067 			continue;
2068 		}
2069 
2070 		inst_off = i * reg_count;
2071 		is_powered = (adev->vcn.ip_dump[inst_off] &
2072 				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2073 
2074 		if (is_powered) {
2075 			drm_printf(p, "\nActive Instance:VCN%d\n", i);
2076 			for (j = 0; j < reg_count; j++)
2077 				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
2078 					   adev->vcn.ip_dump[inst_off + j]);
2079 		} else {
2080 			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
2081 		}
2082 	}
2083 }
2084 
vcn_v2_0_dump_ip_state(struct amdgpu_ip_block * ip_block)2085 static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
2086 {
2087 	struct amdgpu_device *adev = ip_block->adev;
2088 	int i, j;
2089 	bool is_powered;
2090 	uint32_t inst_off;
2091 	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
2092 
2093 	if (!adev->vcn.ip_dump)
2094 		return;
2095 
2096 	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2097 		if (adev->vcn.harvest_config & (1 << i))
2098 			continue;
2099 
2100 		inst_off = i * reg_count;
2101 		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
2102 		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
2103 		is_powered = (adev->vcn.ip_dump[inst_off] &
2104 				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2105 
2106 		if (is_powered)
2107 			for (j = 1; j < reg_count; j++)
2108 				adev->vcn.ip_dump[inst_off + j] =
2109 					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
2110 	}
2111 }
2112 
2113 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
2114 	.name = "vcn_v2_0",
2115 	.early_init = vcn_v2_0_early_init,
2116 	.sw_init = vcn_v2_0_sw_init,
2117 	.sw_fini = vcn_v2_0_sw_fini,
2118 	.hw_init = vcn_v2_0_hw_init,
2119 	.hw_fini = vcn_v2_0_hw_fini,
2120 	.suspend = vcn_v2_0_suspend,
2121 	.resume = vcn_v2_0_resume,
2122 	.is_idle = vcn_v2_0_is_idle,
2123 	.wait_for_idle = vcn_v2_0_wait_for_idle,
2124 	.set_clockgating_state = vcn_v2_0_set_clockgating_state,
2125 	.set_powergating_state = vcn_set_powergating_state,
2126 	.dump_ip_state = vcn_v2_0_dump_ip_state,
2127 	.print_ip_state = vcn_v2_0_print_ip_state,
2128 };
2129 
2130 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2131 	.type = AMDGPU_RING_TYPE_VCN_DEC,
2132 	.align_mask = 0xf,
2133 	.secure_submission_supported = true,
2134 	.get_rptr = vcn_v2_0_dec_ring_get_rptr,
2135 	.get_wptr = vcn_v2_0_dec_ring_get_wptr,
2136 	.set_wptr = vcn_v2_0_dec_ring_set_wptr,
2137 	.emit_frame_size =
2138 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2139 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2140 		8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2141 		14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2142 		6,
2143 	.emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2144 	.emit_ib = vcn_v2_0_dec_ring_emit_ib,
2145 	.emit_fence = vcn_v2_0_dec_ring_emit_fence,
2146 	.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2147 	.test_ring = vcn_v2_0_dec_ring_test_ring,
2148 	.test_ib = amdgpu_vcn_dec_ring_test_ib,
2149 	.insert_nop = vcn_v2_0_dec_ring_insert_nop,
2150 	.insert_start = vcn_v2_0_dec_ring_insert_start,
2151 	.insert_end = vcn_v2_0_dec_ring_insert_end,
2152 	.pad_ib = amdgpu_ring_generic_pad_ib,
2153 	.begin_use = amdgpu_vcn_ring_begin_use,
2154 	.end_use = amdgpu_vcn_ring_end_use,
2155 	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2156 	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2157 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2158 };
2159 
2160 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2161 	.type = AMDGPU_RING_TYPE_VCN_ENC,
2162 	.align_mask = 0x3f,
2163 	.nop = VCN_ENC_CMD_NO_OP,
2164 	.get_rptr = vcn_v2_0_enc_ring_get_rptr,
2165 	.get_wptr = vcn_v2_0_enc_ring_get_wptr,
2166 	.set_wptr = vcn_v2_0_enc_ring_set_wptr,
2167 	.emit_frame_size =
2168 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2169 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2170 		4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2171 		5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2172 		1, /* vcn_v2_0_enc_ring_insert_end */
2173 	.emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2174 	.emit_ib = vcn_v2_0_enc_ring_emit_ib,
2175 	.emit_fence = vcn_v2_0_enc_ring_emit_fence,
2176 	.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2177 	.test_ring = amdgpu_vcn_enc_ring_test_ring,
2178 	.test_ib = amdgpu_vcn_enc_ring_test_ib,
2179 	.insert_nop = amdgpu_ring_insert_nop,
2180 	.insert_end = vcn_v2_0_enc_ring_insert_end,
2181 	.pad_ib = amdgpu_ring_generic_pad_ib,
2182 	.begin_use = amdgpu_vcn_ring_begin_use,
2183 	.end_use = amdgpu_vcn_ring_end_use,
2184 	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2185 	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2186 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2187 };
2188 
vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)2189 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2190 {
2191 	adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
2192 }
2193 
vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device * adev)2194 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2195 {
2196 	int i;
2197 
2198 	for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
2199 		adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2200 }
2201 
2202 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2203 	.set = vcn_v2_0_set_interrupt_state,
2204 	.process = vcn_v2_0_process_interrupt,
2205 };
2206 
vcn_v2_0_set_irq_funcs(struct amdgpu_device * adev)2207 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2208 {
2209 	adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1;
2210 	adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2211 }
2212 
2213 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2214 {
2215 		.type = AMD_IP_BLOCK_TYPE_VCN,
2216 		.major = 2,
2217 		.minor = 0,
2218 		.rev = 0,
2219 		.funcs = &vcn_v2_0_ip_funcs,
2220 };
2221