1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_cs.h"
28 #include "amdgpu_vcn.h"
29 #include "amdgpu_pm.h"
30 #include "soc15.h"
31 #include "soc15d.h"
32 #include "soc15_common.h"
33
34 #include "vcn/vcn_1_0_offset.h"
35 #include "vcn/vcn_1_0_sh_mask.h"
36 #include "mmhub/mmhub_9_1_offset.h"
37 #include "mmhub/mmhub_9_1_sh_mask.h"
38
39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
40 #include "jpeg_v1_0.h"
41 #include "vcn_v1_0.h"
42
43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
45 #define mmUVD_REG_XX_MASK_1_0 0x05ac
46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
47
48 static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {
49 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
50 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
51 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
52 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2),
53 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
54 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
55 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
56 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
57 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL),
79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA),
80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
82 };
83
84 static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst);
85 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
86 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
87 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
88 static int vcn_v1_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
89 enum amd_powergating_state state);
90 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
91 struct dpg_pause_state *new_state);
92
93 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
94 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
95
96 /**
97 * vcn_v1_0_early_init - set function pointers and load microcode
98 *
99 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
100 *
101 * Set ring and irq function pointers
102 * Load microcode from filesystem
103 */
vcn_v1_0_early_init(struct amdgpu_ip_block * ip_block)104 static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)
105 {
106 struct amdgpu_device *adev = ip_block->adev;
107
108 adev->vcn.inst[0].num_enc_rings = 2;
109 adev->vcn.inst[0].set_pg_state = vcn_v1_0_set_pg_state;
110
111 vcn_v1_0_set_dec_ring_funcs(adev);
112 vcn_v1_0_set_enc_ring_funcs(adev);
113 vcn_v1_0_set_irq_funcs(adev);
114
115 jpeg_v1_0_early_init(ip_block);
116
117 return amdgpu_vcn_early_init(adev, 0);
118 }
119
120 /**
121 * vcn_v1_0_sw_init - sw init for VCN block
122 *
123 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
124 *
125 * Load firmware and sw initialization
126 */
vcn_v1_0_sw_init(struct amdgpu_ip_block * ip_block)127 static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
128 {
129 struct amdgpu_ring *ring;
130 int i, r;
131 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
132 uint32_t *ptr;
133 struct amdgpu_device *adev = ip_block->adev;
134
135 /* VCN DEC TRAP */
136 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
137 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
138 if (r)
139 return r;
140
141 /* VCN ENC TRAP */
142 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
143 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
144 &adev->vcn.inst->irq);
145 if (r)
146 return r;
147 }
148
149 r = amdgpu_vcn_sw_init(adev, 0);
150 if (r)
151 return r;
152
153 /* Override the work func */
154 adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;
155
156 amdgpu_vcn_setup_ucode(adev, 0);
157
158 r = amdgpu_vcn_resume(adev, 0);
159 if (r)
160 return r;
161
162 ring = &adev->vcn.inst->ring_dec;
163 ring->vm_hub = AMDGPU_MMHUB0(0);
164 sprintf(ring->name, "vcn_dec");
165 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
166 AMDGPU_RING_PRIO_DEFAULT, NULL);
167 if (r)
168 return r;
169
170 adev->vcn.inst[0].internal.scratch9 = adev->vcn.inst->external.scratch9 =
171 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
172 adev->vcn.inst[0].internal.data0 = adev->vcn.inst->external.data0 =
173 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
174 adev->vcn.inst[0].internal.data1 = adev->vcn.inst->external.data1 =
175 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
176 adev->vcn.inst[0].internal.cmd = adev->vcn.inst->external.cmd =
177 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
178 adev->vcn.inst[0].internal.nop = adev->vcn.inst->external.nop =
179 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
180
181 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
182 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
183
184 ring = &adev->vcn.inst->ring_enc[i];
185 ring->vm_hub = AMDGPU_MMHUB0(0);
186 sprintf(ring->name, "vcn_enc%d", i);
187 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
188 hw_prio, NULL);
189 if (r)
190 return r;
191 }
192
193 adev->vcn.inst[0].pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
194
195 if (amdgpu_vcnfw_log) {
196 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
197
198 fw_shared->present_flag_0 = 0;
199 amdgpu_vcn_fwlog_init(adev->vcn.inst);
200 }
201
202 r = jpeg_v1_0_sw_init(ip_block);
203
204 /* Allocate memory for VCN IP Dump buffer */
205 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
206 if (!ptr) {
207 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
208 adev->vcn.ip_dump = NULL;
209 } else {
210 adev->vcn.ip_dump = ptr;
211 }
212 return r;
213 }
214
215 /**
216 * vcn_v1_0_sw_fini - sw fini for VCN block
217 *
218 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
219 *
220 * VCN suspend and free up sw allocation
221 */
vcn_v1_0_sw_fini(struct amdgpu_ip_block * ip_block)222 static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
223 {
224 int r;
225 struct amdgpu_device *adev = ip_block->adev;
226
227 r = amdgpu_vcn_suspend(adev, 0);
228 if (r)
229 return r;
230
231 jpeg_v1_0_sw_fini(ip_block);
232
233 r = amdgpu_vcn_sw_fini(adev, 0);
234
235 kfree(adev->vcn.ip_dump);
236
237 return r;
238 }
239
240 /**
241 * vcn_v1_0_hw_init - start and test VCN block
242 *
243 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
244 *
245 * Initialize the hardware, boot up the VCPU and do some testing
246 */
vcn_v1_0_hw_init(struct amdgpu_ip_block * ip_block)247 static int vcn_v1_0_hw_init(struct amdgpu_ip_block *ip_block)
248 {
249 struct amdgpu_device *adev = ip_block->adev;
250 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
251 int i, r;
252
253 r = amdgpu_ring_test_helper(ring);
254 if (r)
255 return r;
256
257 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) {
258 ring = &adev->vcn.inst->ring_enc[i];
259 r = amdgpu_ring_test_helper(ring);
260 if (r)
261 return r;
262 }
263
264 ring = adev->jpeg.inst->ring_dec;
265 r = amdgpu_ring_test_helper(ring);
266
267 return r;
268 }
269
270 /**
271 * vcn_v1_0_hw_fini - stop the hardware block
272 *
273 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
274 *
275 * Stop the VCN block, mark ring as not ready any more
276 */
vcn_v1_0_hw_fini(struct amdgpu_ip_block * ip_block)277 static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block)
278 {
279 struct amdgpu_device *adev = ip_block->adev;
280 struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
281
282 cancel_delayed_work_sync(&vinst->idle_work);
283
284 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
285 (vinst->cur_state != AMD_PG_STATE_GATE &&
286 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
287 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE);
288 }
289
290 return 0;
291 }
292
293 /**
294 * vcn_v1_0_suspend - suspend VCN block
295 *
296 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
297 *
298 * HW fini and suspend VCN block
299 */
vcn_v1_0_suspend(struct amdgpu_ip_block * ip_block)300 static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block)
301 {
302 int r;
303 struct amdgpu_device *adev = ip_block->adev;
304 bool idle_work_unexecuted;
305
306 idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
307 if (idle_work_unexecuted) {
308 if (adev->pm.dpm_enabled)
309 amdgpu_dpm_enable_vcn(adev, false, 0);
310 }
311
312 r = vcn_v1_0_hw_fini(ip_block);
313 if (r)
314 return r;
315
316 r = amdgpu_vcn_suspend(adev, 0);
317
318 return r;
319 }
320
321 /**
322 * vcn_v1_0_resume - resume VCN block
323 *
324 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
325 *
326 * Resume firmware and hw init VCN block
327 */
vcn_v1_0_resume(struct amdgpu_ip_block * ip_block)328 static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block)
329 {
330 int r;
331
332 r = amdgpu_vcn_resume(ip_block->adev, 0);
333 if (r)
334 return r;
335
336 r = vcn_v1_0_hw_init(ip_block);
337
338 return r;
339 }
340
341 /**
342 * vcn_v1_0_mc_resume_spg_mode - memory controller programming
343 *
344 * @vinst: VCN instance
345 *
346 * Let the VCN memory controller know it's offsets
347 */
vcn_v1_0_mc_resume_spg_mode(struct amdgpu_vcn_inst * vinst)348 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_vcn_inst *vinst)
349 {
350 struct amdgpu_device *adev = vinst->adev;
351 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
352 uint32_t offset;
353
354 /* cache window 0: fw */
355 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
356 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
357 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
358 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
359 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
360 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
361 offset = 0;
362 } else {
363 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
364 lower_32_bits(adev->vcn.inst->gpu_addr));
365 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
366 upper_32_bits(adev->vcn.inst->gpu_addr));
367 offset = size;
368 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
369 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
370 }
371
372 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
373
374 /* cache window 1: stack */
375 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
376 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
377 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
378 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
379 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
380 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
381
382 /* cache window 2: context */
383 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
384 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
385 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
386 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
387 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
388 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
389
390 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
391 adev->gfx.config.gb_addr_config);
392 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
393 adev->gfx.config.gb_addr_config);
394 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
395 adev->gfx.config.gb_addr_config);
396 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
397 adev->gfx.config.gb_addr_config);
398 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
399 adev->gfx.config.gb_addr_config);
400 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
401 adev->gfx.config.gb_addr_config);
402 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
403 adev->gfx.config.gb_addr_config);
404 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
405 adev->gfx.config.gb_addr_config);
406 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
407 adev->gfx.config.gb_addr_config);
408 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
409 adev->gfx.config.gb_addr_config);
410 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
411 adev->gfx.config.gb_addr_config);
412 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
413 adev->gfx.config.gb_addr_config);
414 }
415
vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst * vinst)416 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst)
417 {
418 struct amdgpu_device *adev = vinst->adev;
419 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4);
420 uint32_t offset;
421
422 /* cache window 0: fw */
423 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
424 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
425 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
426 0xFFFFFFFF, 0);
427 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
428 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
429 0xFFFFFFFF, 0);
430 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
431 0xFFFFFFFF, 0);
432 offset = 0;
433 } else {
434 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
435 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
436 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
437 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
438 offset = size;
439 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
440 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
441 }
442
443 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
444
445 /* cache window 1: stack */
446 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
447 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
448 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
449 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
450 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
451 0xFFFFFFFF, 0);
452 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
453 0xFFFFFFFF, 0);
454
455 /* cache window 2: context */
456 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
457 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
458 0xFFFFFFFF, 0);
459 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
460 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
461 0xFFFFFFFF, 0);
462 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
463 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
464 0xFFFFFFFF, 0);
465
466 /* VCN global tiling registers */
467 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
468 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
469 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
470 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
471 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
472 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
473 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
474 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
475 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
476 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
477 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
478 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
479 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
480 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
481 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
482 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
483 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
484 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
485 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
486 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
487 }
488
489 /**
490 * vcn_v1_0_disable_clock_gating - disable VCN clock gating
491 *
492 * @vinst: VCN instance
493 *
494 * Disable clock gating for VCN block
495 */
vcn_v1_0_disable_clock_gating(struct amdgpu_vcn_inst * vinst)496 static void vcn_v1_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
497 {
498 struct amdgpu_device *adev = vinst->adev;
499 uint32_t data;
500
501 /* JPEG disable CGC */
502 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
503
504 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
505 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
506 else
507 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
508
509 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
510 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
511 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
512
513 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
514 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
515 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
516
517 /* UVD disable CGC */
518 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
519 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
520 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
521 else
522 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
523
524 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
525 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
526 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
527
528 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
529 data &= ~(UVD_CGC_GATE__SYS_MASK
530 | UVD_CGC_GATE__UDEC_MASK
531 | UVD_CGC_GATE__MPEG2_MASK
532 | UVD_CGC_GATE__REGS_MASK
533 | UVD_CGC_GATE__RBC_MASK
534 | UVD_CGC_GATE__LMI_MC_MASK
535 | UVD_CGC_GATE__LMI_UMC_MASK
536 | UVD_CGC_GATE__IDCT_MASK
537 | UVD_CGC_GATE__MPRD_MASK
538 | UVD_CGC_GATE__MPC_MASK
539 | UVD_CGC_GATE__LBSI_MASK
540 | UVD_CGC_GATE__LRBBM_MASK
541 | UVD_CGC_GATE__UDEC_RE_MASK
542 | UVD_CGC_GATE__UDEC_CM_MASK
543 | UVD_CGC_GATE__UDEC_IT_MASK
544 | UVD_CGC_GATE__UDEC_DB_MASK
545 | UVD_CGC_GATE__UDEC_MP_MASK
546 | UVD_CGC_GATE__WCB_MASK
547 | UVD_CGC_GATE__VCPU_MASK
548 | UVD_CGC_GATE__SCPU_MASK);
549 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
550
551 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
552 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
553 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
554 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
555 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
556 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
557 | UVD_CGC_CTRL__SYS_MODE_MASK
558 | UVD_CGC_CTRL__UDEC_MODE_MASK
559 | UVD_CGC_CTRL__MPEG2_MODE_MASK
560 | UVD_CGC_CTRL__REGS_MODE_MASK
561 | UVD_CGC_CTRL__RBC_MODE_MASK
562 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
563 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
564 | UVD_CGC_CTRL__IDCT_MODE_MASK
565 | UVD_CGC_CTRL__MPRD_MODE_MASK
566 | UVD_CGC_CTRL__MPC_MODE_MASK
567 | UVD_CGC_CTRL__LBSI_MODE_MASK
568 | UVD_CGC_CTRL__LRBBM_MODE_MASK
569 | UVD_CGC_CTRL__WCB_MODE_MASK
570 | UVD_CGC_CTRL__VCPU_MODE_MASK
571 | UVD_CGC_CTRL__SCPU_MODE_MASK);
572 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
573
574 /* turn on */
575 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
576 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
577 | UVD_SUVD_CGC_GATE__SIT_MASK
578 | UVD_SUVD_CGC_GATE__SMP_MASK
579 | UVD_SUVD_CGC_GATE__SCM_MASK
580 | UVD_SUVD_CGC_GATE__SDB_MASK
581 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
582 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
583 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
584 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
585 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
586 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
587 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
588 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
589 | UVD_SUVD_CGC_GATE__SCLR_MASK
590 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
591 | UVD_SUVD_CGC_GATE__ENT_MASK
592 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
593 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
594 | UVD_SUVD_CGC_GATE__SITE_MASK
595 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
596 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
597 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
598 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
599 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
600 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
601
602 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
603 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
604 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
605 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
606 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
607 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
608 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
609 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
610 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
611 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
612 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
613 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
614 }
615
616 /**
617 * vcn_v1_0_enable_clock_gating - enable VCN clock gating
618 *
619 * @vinst: Pointer to the VCN instance structure
620 *
621 * Enable clock gating for VCN block
622 */
vcn_v1_0_enable_clock_gating(struct amdgpu_vcn_inst * vinst)623 static void vcn_v1_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
624 {
625 struct amdgpu_device *adev = vinst->adev;
626 uint32_t data = 0;
627
628 /* enable JPEG CGC */
629 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
630 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
631 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
632 else
633 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
634 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
635 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
636 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
637
638 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
639 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
640 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
641
642 /* enable UVD CGC */
643 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
644 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
645 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
646 else
647 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
648 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
649 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
650 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
651
652 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
653 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
654 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
655 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
656 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
657 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
658 | UVD_CGC_CTRL__SYS_MODE_MASK
659 | UVD_CGC_CTRL__UDEC_MODE_MASK
660 | UVD_CGC_CTRL__MPEG2_MODE_MASK
661 | UVD_CGC_CTRL__REGS_MODE_MASK
662 | UVD_CGC_CTRL__RBC_MODE_MASK
663 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
664 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
665 | UVD_CGC_CTRL__IDCT_MODE_MASK
666 | UVD_CGC_CTRL__MPRD_MODE_MASK
667 | UVD_CGC_CTRL__MPC_MODE_MASK
668 | UVD_CGC_CTRL__LBSI_MODE_MASK
669 | UVD_CGC_CTRL__LRBBM_MODE_MASK
670 | UVD_CGC_CTRL__WCB_MODE_MASK
671 | UVD_CGC_CTRL__VCPU_MODE_MASK
672 | UVD_CGC_CTRL__SCPU_MODE_MASK);
673 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
674
675 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
676 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
677 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
678 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
679 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
680 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
681 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
682 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
683 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
684 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
685 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
686 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
687 }
688
vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst * vinst,uint8_t sram_sel)689 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
690 uint8_t sram_sel)
691 {
692 struct amdgpu_device *adev = vinst->adev;
693 uint32_t reg_data = 0;
694
695 /* disable JPEG CGC */
696 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
697 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
698 else
699 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
700 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
701 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
702 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
703
704 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
705
706 /* enable sw clock gating control */
707 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
708 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
709 else
710 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
711 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
712 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
713 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
714 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
715 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
716 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
717 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
718 UVD_CGC_CTRL__SYS_MODE_MASK |
719 UVD_CGC_CTRL__UDEC_MODE_MASK |
720 UVD_CGC_CTRL__MPEG2_MODE_MASK |
721 UVD_CGC_CTRL__REGS_MODE_MASK |
722 UVD_CGC_CTRL__RBC_MODE_MASK |
723 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
724 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
725 UVD_CGC_CTRL__IDCT_MODE_MASK |
726 UVD_CGC_CTRL__MPRD_MODE_MASK |
727 UVD_CGC_CTRL__MPC_MODE_MASK |
728 UVD_CGC_CTRL__LBSI_MODE_MASK |
729 UVD_CGC_CTRL__LRBBM_MODE_MASK |
730 UVD_CGC_CTRL__WCB_MODE_MASK |
731 UVD_CGC_CTRL__VCPU_MODE_MASK |
732 UVD_CGC_CTRL__SCPU_MODE_MASK);
733 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
734
735 /* turn off clock gating */
736 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
737
738 /* turn on SUVD clock gating */
739 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
740
741 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
742 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
743 }
744
vcn_1_0_disable_static_power_gating(struct amdgpu_vcn_inst * vinst)745 static void vcn_1_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
746 {
747 struct amdgpu_device *adev = vinst->adev;
748 uint32_t data = 0;
749
750 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
751 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
752 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
753 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
754 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
755 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
756 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
757 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
758 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
759 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
760 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
761 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
762
763 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
764 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
765 } else {
766 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
767 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
768 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
769 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
770 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
771 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
772 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
773 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
774 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
775 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
776 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
777 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
778 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
779 }
780
781 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
782
783 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
784 data &= ~0x103;
785 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
786 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
787
788 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
789 }
790
vcn_1_0_enable_static_power_gating(struct amdgpu_vcn_inst * vinst)791 static void vcn_1_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
792 {
793 struct amdgpu_device *adev = vinst->adev;
794 uint32_t data = 0;
795
796 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
797 /* Before power off, this indicator has to be turned on */
798 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
799 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
800 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
801 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
802
803
804 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
805 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
806 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
807 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
808 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
809 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
810 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
811 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
812 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
813 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
814 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
815
816 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
817
818 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
819 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
820 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
821 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
822 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
823 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
824 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
825 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
826 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
827 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
828 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
829 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
830 }
831 }
832
833 /**
834 * vcn_v1_0_start_spg_mode - start VCN block
835 *
836 * @vinst: VCN instance
837 *
838 * Setup and start the VCN block
839 */
vcn_v1_0_start_spg_mode(struct amdgpu_vcn_inst * vinst)840 static int vcn_v1_0_start_spg_mode(struct amdgpu_vcn_inst *vinst)
841 {
842 struct amdgpu_device *adev = vinst->adev;
843 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
844 uint32_t rb_bufsz, tmp;
845 uint32_t lmi_swap_cntl;
846 int i, j, r;
847
848 /* disable byte swapping */
849 lmi_swap_cntl = 0;
850
851 vcn_1_0_disable_static_power_gating(vinst);
852
853 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
854 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
855
856 /* disable clock gating */
857 vcn_v1_0_disable_clock_gating(vinst);
858
859 /* disable interupt */
860 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
861 ~UVD_MASTINT_EN__VCPU_EN_MASK);
862
863 /* initialize VCN memory controller */
864 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
865 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
866 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
867 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
868 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
869 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
870
871 #ifdef __BIG_ENDIAN
872 /* swap (8 in 32) RB and IB */
873 lmi_swap_cntl = 0xa;
874 #endif
875 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
876
877 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
878 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
879 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
880 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
881
882 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
883 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
884 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
885 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
886 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
887
888 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
889 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
890 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
891 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
892 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
893
894 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
895 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
896 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
897 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
898
899 vcn_v1_0_mc_resume_spg_mode(vinst);
900
901 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
902 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
903 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
904
905 /* enable VCPU clock */
906 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
907
908 /* boot up the VCPU */
909 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
910 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
911
912 /* enable UMC */
913 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
914 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
915
916 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
917 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
918 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
919 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
920
921 for (i = 0; i < 10; ++i) {
922 uint32_t status;
923
924 for (j = 0; j < 100; ++j) {
925 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
926 if (status & UVD_STATUS__IDLE)
927 break;
928 mdelay(10);
929 }
930 r = 0;
931 if (status & UVD_STATUS__IDLE)
932 break;
933
934 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
935 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
936 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
937 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
938 mdelay(10);
939 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
940 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
941 mdelay(10);
942 r = -1;
943 }
944
945 if (r) {
946 DRM_ERROR("VCN decode not responding, giving up!!!\n");
947 return r;
948 }
949 /* enable master interrupt */
950 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
951 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
952
953 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
954 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
955 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
956 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
957
958 /* clear the busy bit of UVD_STATUS */
959 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
960 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
961
962 /* force RBC into idle state */
963 rb_bufsz = order_base_2(ring->ring_size);
964 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
965 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
966 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
967 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
968 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
969 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
970
971 /* set the write pointer delay */
972 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
973
974 /* set the wb address */
975 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
976 (upper_32_bits(ring->gpu_addr) >> 2));
977
978 /* program the RB_BASE for ring buffer */
979 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
980 lower_32_bits(ring->gpu_addr));
981 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
982 upper_32_bits(ring->gpu_addr));
983
984 /* Initialize the ring buffer's read and write pointers */
985 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
986
987 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
988
989 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
990 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
991 lower_32_bits(ring->wptr));
992
993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
994 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
995
996 ring = &adev->vcn.inst->ring_enc[0];
997 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
998 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
999 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1000 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1001 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1002
1003 ring = &adev->vcn.inst->ring_enc[1];
1004 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1005 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1006 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1007 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1008 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1009
1010 jpeg_v1_0_start(adev, 0);
1011
1012 return 0;
1013 }
1014
vcn_v1_0_start_dpg_mode(struct amdgpu_vcn_inst * vinst)1015 static int vcn_v1_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst)
1016 {
1017 struct amdgpu_device *adev = vinst->adev;
1018 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
1019 uint32_t rb_bufsz, tmp;
1020 uint32_t lmi_swap_cntl;
1021
1022 /* disable byte swapping */
1023 lmi_swap_cntl = 0;
1024
1025 vcn_1_0_enable_static_power_gating(vinst);
1026
1027 /* enable dynamic power gating mode */
1028 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1029 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
1030 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
1031 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
1032
1033 /* enable clock gating */
1034 vcn_v1_0_clock_gating_dpg_mode(vinst, 0);
1035
1036 /* enable VCPU clock */
1037 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1038 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1039 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
1040 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
1041
1042 /* disable interupt */
1043 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1044 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1045
1046 /* initialize VCN memory controller */
1047 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1048 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1049 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1050 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1051 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1052 UVD_LMI_CTRL__REQ_MODE_MASK |
1053 UVD_LMI_CTRL__CRC_RESET_MASK |
1054 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1055 0x00100000L, 0xFFFFFFFF, 0);
1056
1057 #ifdef __BIG_ENDIAN
1058 /* swap (8 in 32) RB and IB */
1059 lmi_swap_cntl = 0xa;
1060 #endif
1061 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
1062
1063 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
1064 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1065
1066 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1067 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1068 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1069 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1070 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1071
1072 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1073 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1074 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1075 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1076 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1077
1078 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1079 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1080 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1081 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1082
1083 vcn_v1_0_mc_resume_dpg_mode(vinst);
1084
1085 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1086 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1087
1088 /* boot up the VCPU */
1089 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1090
1091 /* enable UMC */
1092 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1093 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1094 0xFFFFFFFF, 0);
1095
1096 /* enable master interrupt */
1097 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1098 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1099
1100 vcn_v1_0_clock_gating_dpg_mode(vinst, 1);
1101 /* setup mmUVD_LMI_CTRL */
1102 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1103 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1104 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1105 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1106 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1107 UVD_LMI_CTRL__REQ_MODE_MASK |
1108 UVD_LMI_CTRL__CRC_RESET_MASK |
1109 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1110 0x00100000L, 0xFFFFFFFF, 1);
1111
1112 tmp = adev->gfx.config.gb_addr_config;
1113 /* setup VCN global tiling registers */
1114 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1115 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1116
1117 /* enable System Interrupt for JRBC */
1118 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1119 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1120
1121 /* force RBC into idle state */
1122 rb_bufsz = order_base_2(ring->ring_size);
1123 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1124 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1125 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1126 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1127 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1128 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1129
1130 /* set the write pointer delay */
1131 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1132
1133 /* set the wb address */
1134 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1135 (upper_32_bits(ring->gpu_addr) >> 2));
1136
1137 /* program the RB_BASE for ring buffer */
1138 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1139 lower_32_bits(ring->gpu_addr));
1140 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1141 upper_32_bits(ring->gpu_addr));
1142
1143 /* Initialize the ring buffer's read and write pointers */
1144 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1145
1146 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1147
1148 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1149 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1150 lower_32_bits(ring->wptr));
1151
1152 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1153 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1154
1155 jpeg_v1_0_start(adev, 1);
1156
1157 return 0;
1158 }
1159
vcn_v1_0_start(struct amdgpu_vcn_inst * vinst)1160 static int vcn_v1_0_start(struct amdgpu_vcn_inst *vinst)
1161 {
1162 struct amdgpu_device *adev = vinst->adev;
1163
1164 return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ?
1165 vcn_v1_0_start_dpg_mode(vinst) : vcn_v1_0_start_spg_mode(vinst);
1166 }
1167
1168 /**
1169 * vcn_v1_0_stop_spg_mode - stop VCN block
1170 *
1171 * @vinst: VCN instance
1172 *
1173 * stop the VCN block
1174 */
vcn_v1_0_stop_spg_mode(struct amdgpu_vcn_inst * vinst)1175 static int vcn_v1_0_stop_spg_mode(struct amdgpu_vcn_inst *vinst)
1176 {
1177 struct amdgpu_device *adev = vinst->adev;
1178 int tmp;
1179
1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1181
1182 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1183 UVD_LMI_STATUS__READ_CLEAN_MASK |
1184 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1185 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1187
1188 /* stall UMC channel */
1189 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1190 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1191 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1192
1193 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1194 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1195 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1196
1197 /* disable VCPU clock */
1198 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1199 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1200
1201 /* reset LMI UMC/LMI */
1202 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1203 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1204 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1205
1206 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1207 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1208 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1209
1210 /* put VCPU into reset */
1211 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1212 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1213 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1214
1215 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1216
1217 vcn_v1_0_enable_clock_gating(vinst);
1218 vcn_1_0_enable_static_power_gating(vinst);
1219 return 0;
1220 }
1221
vcn_v1_0_stop_dpg_mode(struct amdgpu_vcn_inst * vinst)1222 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
1223 {
1224 struct amdgpu_device *adev = vinst->adev;
1225 uint32_t tmp;
1226
1227 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1228 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1229 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1230 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1231
1232 /* wait for read ptr to be equal to write ptr */
1233 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1234 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1235
1236 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1237 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1238
1239 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1240 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1241
1242 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1243 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1244
1245 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1246 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1247 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1248
1249 /* disable dynamic power gating mode */
1250 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1251 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1252
1253 return 0;
1254 }
1255
vcn_v1_0_stop(struct amdgpu_vcn_inst * vinst)1256 static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst)
1257 {
1258 struct amdgpu_device *adev = vinst->adev;
1259 int r;
1260
1261 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1262 r = vcn_v1_0_stop_dpg_mode(vinst);
1263 else
1264 r = vcn_v1_0_stop_spg_mode(vinst);
1265
1266 return r;
1267 }
1268
vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst * vinst,struct dpg_pause_state * new_state)1269 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
1270 struct dpg_pause_state *new_state)
1271 {
1272 struct amdgpu_device *adev = vinst->adev;
1273 int inst_idx = vinst->inst;
1274 int ret_code;
1275 uint32_t reg_data = 0;
1276 uint32_t reg_data2 = 0;
1277 struct amdgpu_ring *ring;
1278
1279 /* pause/unpause if state is changed */
1280 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1281 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1282 adev->vcn.inst[inst_idx].pause_state.fw_based,
1283 adev->vcn.inst[inst_idx].pause_state.jpeg,
1284 new_state->fw_based, new_state->jpeg);
1285
1286 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1287 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1288
1289 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1290 ret_code = 0;
1291
1292 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1293 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1294 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1295 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1296
1297 if (!ret_code) {
1298 /* pause DPG non-jpeg */
1299 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1300 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1301 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1302 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1303 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1304
1305 /* Restore */
1306 ring = &adev->vcn.inst->ring_enc[0];
1307 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1308 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1309 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1310 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1311 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1312
1313 ring = &adev->vcn.inst->ring_enc[1];
1314 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1315 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1316 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1317 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1318 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1319
1320 ring = &adev->vcn.inst->ring_dec;
1321 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1322 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1323 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1324 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1325 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1326 }
1327 } else {
1328 /* unpause dpg non-jpeg, no need to wait */
1329 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1330 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1331 }
1332 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1333 }
1334
1335 /* pause/unpause if state is changed */
1336 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1337 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1338 adev->vcn.inst[inst_idx].pause_state.fw_based,
1339 adev->vcn.inst[inst_idx].pause_state.jpeg,
1340 new_state->fw_based, new_state->jpeg);
1341
1342 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1343 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1344
1345 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1346 ret_code = 0;
1347
1348 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1349 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1350 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1351 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1352
1353 if (!ret_code) {
1354 /* Make sure JPRG Snoop is disabled before sending the pause */
1355 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1356 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1357 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1358
1359 /* pause DPG jpeg */
1360 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1361 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1362 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1363 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1364 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1365
1366 /* Restore */
1367 ring = adev->jpeg.inst->ring_dec;
1368 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1369 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1370 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1371 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1372 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1373 lower_32_bits(ring->gpu_addr));
1374 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1375 upper_32_bits(ring->gpu_addr));
1376 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1377 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1378 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1379 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1380
1381 ring = &adev->vcn.inst->ring_dec;
1382 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1383 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1384 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1385 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1386 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1387 }
1388 } else {
1389 /* unpause dpg jpeg, no need to wait */
1390 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1391 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1392 }
1393 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1394 }
1395
1396 return 0;
1397 }
1398
vcn_v1_0_is_idle(struct amdgpu_ip_block * ip_block)1399 static bool vcn_v1_0_is_idle(struct amdgpu_ip_block *ip_block)
1400 {
1401 struct amdgpu_device *adev = ip_block->adev;
1402
1403 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1404 }
1405
vcn_v1_0_wait_for_idle(struct amdgpu_ip_block * ip_block)1406 static int vcn_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1407 {
1408 struct amdgpu_device *adev = ip_block->adev;
1409 int ret;
1410
1411 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1412 UVD_STATUS__IDLE);
1413
1414 return ret;
1415 }
1416
vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1417 static int vcn_v1_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1418 enum amd_clockgating_state state)
1419 {
1420 struct amdgpu_device *adev = ip_block->adev;
1421 struct amdgpu_vcn_inst *vinst = adev->vcn.inst;
1422 bool enable = (state == AMD_CG_STATE_GATE);
1423
1424 if (enable) {
1425 /* wait for STATUS to clear */
1426 if (!vcn_v1_0_is_idle(ip_block))
1427 return -EBUSY;
1428 vcn_v1_0_enable_clock_gating(vinst);
1429 } else {
1430 /* disable HW gating and enable Sw gating */
1431 vcn_v1_0_disable_clock_gating(vinst);
1432 }
1433 return 0;
1434 }
1435
1436 /**
1437 * vcn_v1_0_dec_ring_get_rptr - get read pointer
1438 *
1439 * @ring: amdgpu_ring pointer
1440 *
1441 * Returns the current hardware read pointer
1442 */
vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1443 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1444 {
1445 struct amdgpu_device *adev = ring->adev;
1446
1447 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1448 }
1449
1450 /**
1451 * vcn_v1_0_dec_ring_get_wptr - get write pointer
1452 *
1453 * @ring: amdgpu_ring pointer
1454 *
1455 * Returns the current hardware write pointer
1456 */
vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1457 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1458 {
1459 struct amdgpu_device *adev = ring->adev;
1460
1461 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1462 }
1463
1464 /**
1465 * vcn_v1_0_dec_ring_set_wptr - set write pointer
1466 *
1467 * @ring: amdgpu_ring pointer
1468 *
1469 * Commits the write pointer to the hardware
1470 */
vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1471 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1472 {
1473 struct amdgpu_device *adev = ring->adev;
1474
1475 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1476 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1477 lower_32_bits(ring->wptr) | 0x80000000);
1478
1479 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1480 }
1481
1482 /**
1483 * vcn_v1_0_dec_ring_insert_start - insert a start command
1484 *
1485 * @ring: amdgpu_ring pointer
1486 *
1487 * Write a start command to the ring.
1488 */
vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring * ring)1489 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1490 {
1491 struct amdgpu_device *adev = ring->adev;
1492
1493 amdgpu_ring_write(ring,
1494 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1495 amdgpu_ring_write(ring, 0);
1496 amdgpu_ring_write(ring,
1497 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1498 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1499 }
1500
1501 /**
1502 * vcn_v1_0_dec_ring_insert_end - insert a end command
1503 *
1504 * @ring: amdgpu_ring pointer
1505 *
1506 * Write a end command to the ring.
1507 */
vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring * ring)1508 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1509 {
1510 struct amdgpu_device *adev = ring->adev;
1511
1512 amdgpu_ring_write(ring,
1513 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1514 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1515 }
1516
1517 /**
1518 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1519 *
1520 * @ring: amdgpu_ring pointer
1521 * @addr: address
1522 * @seq: sequence number
1523 * @flags: fence related flags
1524 *
1525 * Write a fence and a trap command to the ring.
1526 */
vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1527 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1528 unsigned flags)
1529 {
1530 struct amdgpu_device *adev = ring->adev;
1531
1532 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1533
1534 amdgpu_ring_write(ring,
1535 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1536 amdgpu_ring_write(ring, seq);
1537 amdgpu_ring_write(ring,
1538 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1539 amdgpu_ring_write(ring, addr & 0xffffffff);
1540 amdgpu_ring_write(ring,
1541 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1542 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1543 amdgpu_ring_write(ring,
1544 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1545 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1546
1547 amdgpu_ring_write(ring,
1548 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1549 amdgpu_ring_write(ring, 0);
1550 amdgpu_ring_write(ring,
1551 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1552 amdgpu_ring_write(ring, 0);
1553 amdgpu_ring_write(ring,
1554 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1555 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1556 }
1557
1558 /**
1559 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1560 *
1561 * @ring: amdgpu_ring pointer
1562 * @job: job to retrieve vmid from
1563 * @ib: indirect buffer to execute
1564 * @flags: unused
1565 *
1566 * Write ring commands to execute the indirect buffer
1567 */
vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1568 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1569 struct amdgpu_job *job,
1570 struct amdgpu_ib *ib,
1571 uint32_t flags)
1572 {
1573 struct amdgpu_device *adev = ring->adev;
1574 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1575
1576 amdgpu_ring_write(ring,
1577 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1578 amdgpu_ring_write(ring, vmid);
1579
1580 amdgpu_ring_write(ring,
1581 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1582 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1583 amdgpu_ring_write(ring,
1584 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1585 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1586 amdgpu_ring_write(ring,
1587 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1588 amdgpu_ring_write(ring, ib->length_dw);
1589 }
1590
vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1591 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1592 uint32_t reg, uint32_t val,
1593 uint32_t mask)
1594 {
1595 struct amdgpu_device *adev = ring->adev;
1596
1597 amdgpu_ring_write(ring,
1598 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1599 amdgpu_ring_write(ring, reg << 2);
1600 amdgpu_ring_write(ring,
1601 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1602 amdgpu_ring_write(ring, val);
1603 amdgpu_ring_write(ring,
1604 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1605 amdgpu_ring_write(ring, mask);
1606 amdgpu_ring_write(ring,
1607 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1608 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1609 }
1610
vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1611 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1612 unsigned vmid, uint64_t pd_addr)
1613 {
1614 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1615 uint32_t data0, data1, mask;
1616
1617 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1618
1619 /* wait for register write */
1620 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1621 data1 = lower_32_bits(pd_addr);
1622 mask = 0xffffffff;
1623 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1624 }
1625
vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1626 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1627 uint32_t reg, uint32_t val)
1628 {
1629 struct amdgpu_device *adev = ring->adev;
1630
1631 amdgpu_ring_write(ring,
1632 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1633 amdgpu_ring_write(ring, reg << 2);
1634 amdgpu_ring_write(ring,
1635 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1636 amdgpu_ring_write(ring, val);
1637 amdgpu_ring_write(ring,
1638 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1639 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1640 }
1641
1642 /**
1643 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1644 *
1645 * @ring: amdgpu_ring pointer
1646 *
1647 * Returns the current hardware enc read pointer
1648 */
vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1649 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1650 {
1651 struct amdgpu_device *adev = ring->adev;
1652
1653 if (ring == &adev->vcn.inst->ring_enc[0])
1654 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1655 else
1656 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1657 }
1658
1659 /**
1660 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1661 *
1662 * @ring: amdgpu_ring pointer
1663 *
1664 * Returns the current hardware enc write pointer
1665 */
vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1666 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1667 {
1668 struct amdgpu_device *adev = ring->adev;
1669
1670 if (ring == &adev->vcn.inst->ring_enc[0])
1671 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1672 else
1673 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1674 }
1675
1676 /**
1677 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1678 *
1679 * @ring: amdgpu_ring pointer
1680 *
1681 * Commits the enc write pointer to the hardware
1682 */
vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1683 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1684 {
1685 struct amdgpu_device *adev = ring->adev;
1686
1687 if (ring == &adev->vcn.inst->ring_enc[0])
1688 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1689 lower_32_bits(ring->wptr));
1690 else
1691 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1692 lower_32_bits(ring->wptr));
1693 }
1694
1695 /**
1696 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1697 *
1698 * @ring: amdgpu_ring pointer
1699 * @addr: address
1700 * @seq: sequence number
1701 * @flags: fence related flags
1702 *
1703 * Write enc a fence and a trap command to the ring.
1704 */
vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1705 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1706 u64 seq, unsigned flags)
1707 {
1708 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1709
1710 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1711 amdgpu_ring_write(ring, addr);
1712 amdgpu_ring_write(ring, upper_32_bits(addr));
1713 amdgpu_ring_write(ring, seq);
1714 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1715 }
1716
vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring * ring)1717 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1718 {
1719 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1720 }
1721
1722 /**
1723 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1724 *
1725 * @ring: amdgpu_ring pointer
1726 * @job: job to retrive vmid from
1727 * @ib: indirect buffer to execute
1728 * @flags: unused
1729 *
1730 * Write enc ring commands to execute the indirect buffer
1731 */
vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1732 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1733 struct amdgpu_job *job,
1734 struct amdgpu_ib *ib,
1735 uint32_t flags)
1736 {
1737 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1738
1739 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1740 amdgpu_ring_write(ring, vmid);
1741 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1742 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1743 amdgpu_ring_write(ring, ib->length_dw);
1744 }
1745
vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1746 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1747 uint32_t reg, uint32_t val,
1748 uint32_t mask)
1749 {
1750 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1751 amdgpu_ring_write(ring, reg << 2);
1752 amdgpu_ring_write(ring, mask);
1753 amdgpu_ring_write(ring, val);
1754 }
1755
vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1756 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1757 unsigned int vmid, uint64_t pd_addr)
1758 {
1759 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1760
1761 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1762
1763 /* wait for reg writes */
1764 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1765 vmid * hub->ctx_addr_distance,
1766 lower_32_bits(pd_addr), 0xffffffff);
1767 }
1768
vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1769 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1770 uint32_t reg, uint32_t val)
1771 {
1772 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1773 amdgpu_ring_write(ring, reg << 2);
1774 amdgpu_ring_write(ring, val);
1775 }
1776
vcn_v1_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1777 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1778 struct amdgpu_irq_src *source,
1779 unsigned type,
1780 enum amdgpu_interrupt_state state)
1781 {
1782 return 0;
1783 }
1784
vcn_v1_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1785 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1786 struct amdgpu_irq_src *source,
1787 struct amdgpu_iv_entry *entry)
1788 {
1789 DRM_DEBUG("IH: VCN TRAP\n");
1790
1791 switch (entry->src_id) {
1792 case 124:
1793 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1794 break;
1795 case 119:
1796 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1797 break;
1798 case 120:
1799 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1800 break;
1801 default:
1802 DRM_ERROR("Unhandled interrupt: %d %d\n",
1803 entry->src_id, entry->src_data[0]);
1804 break;
1805 }
1806
1807 return 0;
1808 }
1809
vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1810 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1811 {
1812 struct amdgpu_device *adev = ring->adev;
1813 int i;
1814
1815 WARN_ON(ring->wptr % 2 || count % 2);
1816
1817 for (i = 0; i < count / 2; i++) {
1818 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1819 amdgpu_ring_write(ring, 0);
1820 }
1821 }
1822
vcn_v1_0_set_pg_state(struct amdgpu_vcn_inst * vinst,enum amd_powergating_state state)1823 static int vcn_v1_0_set_pg_state(struct amdgpu_vcn_inst *vinst,
1824 enum amd_powergating_state state)
1825 {
1826 /* This doesn't actually powergate the VCN block.
1827 * That's done in the dpm code via the SMC. This
1828 * just re-inits the block as necessary. The actual
1829 * gating still happens in the dpm code. We should
1830 * revisit this when there is a cleaner line between
1831 * the smc and the hw blocks
1832 */
1833 int ret;
1834
1835 if (state == vinst->cur_state)
1836 return 0;
1837
1838 if (state == AMD_PG_STATE_GATE)
1839 ret = vcn_v1_0_stop(vinst);
1840 else
1841 ret = vcn_v1_0_start(vinst);
1842
1843 if (!ret)
1844 vinst->cur_state = state;
1845
1846 return ret;
1847 }
1848
vcn_v1_0_idle_work_handler(struct work_struct * work)1849 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1850 {
1851 struct amdgpu_vcn_inst *vcn_inst =
1852 container_of(work, struct amdgpu_vcn_inst, idle_work.work);
1853 struct amdgpu_device *adev = vcn_inst->adev;
1854 unsigned int fences = 0, i;
1855
1856 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
1857 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1858
1859 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1860 struct dpg_pause_state new_state;
1861
1862 if (fences)
1863 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1864 else
1865 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1866
1867 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
1868 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1869 else
1870 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1871
1872 adev->vcn.inst->pause_dpg_mode(vcn_inst, &new_state);
1873 }
1874
1875 fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec);
1876 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1877
1878 if (fences == 0) {
1879 amdgpu_gfx_off_ctrl(adev, true);
1880 if (adev->pm.dpm_enabled)
1881 amdgpu_dpm_enable_vcn(adev, false, 0);
1882 else
1883 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1884 AMD_PG_STATE_GATE);
1885 } else {
1886 schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
1887 }
1888 }
1889
vcn_v1_0_ring_begin_use(struct amdgpu_ring * ring)1890 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1891 {
1892 struct amdgpu_device *adev = ring->adev;
1893 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
1894
1895 mutex_lock(&adev->vcn.inst[0].vcn1_jpeg1_workaround);
1896
1897 if (amdgpu_fence_wait_empty(ring->adev->jpeg.inst->ring_dec))
1898 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1899
1900 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1901
1902 }
1903
vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring * ring,bool set_clocks)1904 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1905 {
1906 struct amdgpu_device *adev = ring->adev;
1907
1908 if (set_clocks) {
1909 amdgpu_gfx_off_ctrl(adev, false);
1910 if (adev->pm.dpm_enabled)
1911 amdgpu_dpm_enable_vcn(adev, true, 0);
1912 else
1913 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1914 AMD_PG_STATE_UNGATE);
1915 }
1916
1917 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1918 struct dpg_pause_state new_state;
1919 unsigned int fences = 0, i;
1920
1921 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
1922 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1923
1924 if (fences)
1925 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1926 else
1927 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1928
1929 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec))
1930 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1931 else
1932 new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1933
1934 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1935 new_state.fw_based = VCN_DPG_STATE__PAUSE;
1936 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1937 new_state.jpeg = VCN_DPG_STATE__PAUSE;
1938
1939 adev->vcn.inst->pause_dpg_mode(adev->vcn.inst, &new_state);
1940 }
1941 }
1942
vcn_v1_0_ring_end_use(struct amdgpu_ring * ring)1943 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1944 {
1945 schedule_delayed_work(&ring->adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
1946 mutex_unlock(&ring->adev->vcn.inst[0].vcn1_jpeg1_workaround);
1947 }
1948
vcn_v1_0_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)1949 static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1950 {
1951 struct amdgpu_device *adev = ip_block->adev;
1952 int i, j;
1953 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
1954 uint32_t inst_off, is_powered;
1955
1956 if (!adev->vcn.ip_dump)
1957 return;
1958
1959 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1960 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1961 if (adev->vcn.harvest_config & (1 << i)) {
1962 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1963 continue;
1964 }
1965
1966 inst_off = i * reg_count;
1967 is_powered = (adev->vcn.ip_dump[inst_off] &
1968 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1969
1970 if (is_powered) {
1971 drm_printf(p, "\nActive Instance:VCN%d\n", i);
1972 for (j = 0; j < reg_count; j++)
1973 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
1974 adev->vcn.ip_dump[inst_off + j]);
1975 } else {
1976 drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1977 }
1978 }
1979 }
1980
vcn_v1_0_dump_ip_state(struct amdgpu_ip_block * ip_block)1981 static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
1982 {
1983 struct amdgpu_device *adev = ip_block->adev;
1984 int i, j;
1985 bool is_powered;
1986 uint32_t inst_off;
1987 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
1988
1989 if (!adev->vcn.ip_dump)
1990 return;
1991
1992 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1993 if (adev->vcn.harvest_config & (1 << i))
1994 continue;
1995
1996 inst_off = i * reg_count;
1997 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1998 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
1999 is_powered = (adev->vcn.ip_dump[inst_off] &
2000 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
2001
2002 if (is_powered)
2003 for (j = 1; j < reg_count; j++)
2004 adev->vcn.ip_dump[inst_off + j] =
2005 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
2006 }
2007 }
2008
2009 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
2010 .name = "vcn_v1_0",
2011 .early_init = vcn_v1_0_early_init,
2012 .sw_init = vcn_v1_0_sw_init,
2013 .sw_fini = vcn_v1_0_sw_fini,
2014 .hw_init = vcn_v1_0_hw_init,
2015 .hw_fini = vcn_v1_0_hw_fini,
2016 .suspend = vcn_v1_0_suspend,
2017 .resume = vcn_v1_0_resume,
2018 .is_idle = vcn_v1_0_is_idle,
2019 .wait_for_idle = vcn_v1_0_wait_for_idle,
2020 .set_clockgating_state = vcn_v1_0_set_clockgating_state,
2021 .set_powergating_state = vcn_set_powergating_state,
2022 .dump_ip_state = vcn_v1_0_dump_ip_state,
2023 .print_ip_state = vcn_v1_0_print_ip_state,
2024 };
2025
2026 /*
2027 * It is a hardware issue that VCN can't handle a GTT TMZ buffer on
2028 * CHIP_RAVEN series ASIC. Move such a GTT TMZ buffer to VRAM domain
2029 * before command submission as a workaround.
2030 */
vcn_v1_0_validate_bo(struct amdgpu_cs_parser * parser,struct amdgpu_job * job,uint64_t addr)2031 static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser,
2032 struct amdgpu_job *job,
2033 uint64_t addr)
2034 {
2035 struct ttm_operation_ctx ctx = { false, false };
2036 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
2037 struct amdgpu_vm *vm = &fpriv->vm;
2038 struct amdgpu_bo_va_mapping *mapping;
2039 struct amdgpu_bo *bo;
2040 int r;
2041
2042 addr &= AMDGPU_GMC_HOLE_MASK;
2043 if (addr & 0x7) {
2044 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
2045 return -EINVAL;
2046 }
2047
2048 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr/AMDGPU_GPU_PAGE_SIZE);
2049 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
2050 return -EINVAL;
2051
2052 bo = mapping->bo_va->base.bo;
2053 if (!(bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED))
2054 return 0;
2055
2056 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
2057 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2058 if (r) {
2059 DRM_ERROR("Failed to validate the VCN message BO (%d)!\n", r);
2060 return r;
2061 }
2062
2063 return r;
2064 }
2065
vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser * p,struct amdgpu_job * job,struct amdgpu_ib * ib)2066 static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
2067 struct amdgpu_job *job,
2068 struct amdgpu_ib *ib)
2069 {
2070 uint32_t msg_lo = 0, msg_hi = 0;
2071 int i, r;
2072
2073 if (!(ib->flags & AMDGPU_IB_FLAGS_SECURE))
2074 return 0;
2075
2076 for (i = 0; i < ib->length_dw; i += 2) {
2077 uint32_t reg = amdgpu_ib_get_value(ib, i);
2078 uint32_t val = amdgpu_ib_get_value(ib, i + 1);
2079
2080 if (reg == PACKET0(p->adev->vcn.inst[0].internal.data0, 0)) {
2081 msg_lo = val;
2082 } else if (reg == PACKET0(p->adev->vcn.inst[0].internal.data1, 0)) {
2083 msg_hi = val;
2084 } else if (reg == PACKET0(p->adev->vcn.inst[0].internal.cmd, 0)) {
2085 r = vcn_v1_0_validate_bo(p, job,
2086 ((u64)msg_hi) << 32 | msg_lo);
2087 if (r)
2088 return r;
2089 }
2090 }
2091
2092 return 0;
2093 }
2094
2095 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
2096 .type = AMDGPU_RING_TYPE_VCN_DEC,
2097 .align_mask = 0xf,
2098 .support_64bit_ptrs = false,
2099 .no_user_fence = true,
2100 .secure_submission_supported = true,
2101 .get_rptr = vcn_v1_0_dec_ring_get_rptr,
2102 .get_wptr = vcn_v1_0_dec_ring_get_wptr,
2103 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2104 .patch_cs_in_place = vcn_v1_0_ring_patch_cs_in_place,
2105 .emit_frame_size =
2106 6 + 6 + /* hdp invalidate / flush */
2107 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2108 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2109 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
2110 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
2111 6,
2112 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
2113 .emit_ib = vcn_v1_0_dec_ring_emit_ib,
2114 .emit_fence = vcn_v1_0_dec_ring_emit_fence,
2115 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
2116 .test_ring = amdgpu_vcn_dec_ring_test_ring,
2117 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2118 .insert_nop = vcn_v1_0_dec_ring_insert_nop,
2119 .insert_start = vcn_v1_0_dec_ring_insert_start,
2120 .insert_end = vcn_v1_0_dec_ring_insert_end,
2121 .pad_ib = amdgpu_ring_generic_pad_ib,
2122 .begin_use = vcn_v1_0_ring_begin_use,
2123 .end_use = vcn_v1_0_ring_end_use,
2124 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
2125 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
2126 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2127 };
2128
2129 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
2130 .type = AMDGPU_RING_TYPE_VCN_ENC,
2131 .align_mask = 0x3f,
2132 .nop = VCN_ENC_CMD_NO_OP,
2133 .support_64bit_ptrs = false,
2134 .no_user_fence = true,
2135 .get_rptr = vcn_v1_0_enc_ring_get_rptr,
2136 .get_wptr = vcn_v1_0_enc_ring_get_wptr,
2137 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
2138 .emit_frame_size =
2139 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2140 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2141 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
2142 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
2143 1, /* vcn_v1_0_enc_ring_insert_end */
2144 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
2145 .emit_ib = vcn_v1_0_enc_ring_emit_ib,
2146 .emit_fence = vcn_v1_0_enc_ring_emit_fence,
2147 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
2148 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2149 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2150 .insert_nop = amdgpu_ring_insert_nop,
2151 .insert_end = vcn_v1_0_enc_ring_insert_end,
2152 .pad_ib = amdgpu_ring_generic_pad_ib,
2153 .begin_use = vcn_v1_0_ring_begin_use,
2154 .end_use = vcn_v1_0_ring_end_use,
2155 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
2156 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
2157 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2158 };
2159
vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device * adev)2160 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2161 {
2162 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
2163 }
2164
vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device * adev)2165 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2166 {
2167 int i;
2168
2169 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i)
2170 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
2171 }
2172
2173 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
2174 .set = vcn_v1_0_set_interrupt_state,
2175 .process = vcn_v1_0_process_interrupt,
2176 };
2177
vcn_v1_0_set_irq_funcs(struct amdgpu_device * adev)2178 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
2179 {
2180 adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 2;
2181 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
2182 }
2183
2184 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = {
2185 .type = AMD_IP_BLOCK_TYPE_VCN,
2186 .major = 1,
2187 .minor = 0,
2188 .rev = 0,
2189 .funcs = &vcn_v1_0_ip_funcs,
2190 };
2191