1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_11_0_0_offset.h"
34 #include "gc/gc_11_0_0_sh_mask.h"
35 #include "gc/gc_11_0_0_default.h"
36 #include "hdp/hdp_6_0_0_offset.h"
37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
38
39 #include "soc15_common.h"
40 #include "soc15.h"
41 #include "sdma_v6_0_0_pkt_open.h"
42 #include "nbio_v4_3.h"
43 #include "sdma_common.h"
44 #include "sdma_v6_0.h"
45 #include "v11_structs.h"
46
47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
51 MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
52 MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin");
53 MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");
54 MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin");
55
56 #define SDMA1_REG_OFFSET 0x600
57 #define SDMA0_HYP_DEC_REG_START 0x5880
58 #define SDMA0_HYP_DEC_REG_END 0x589a
59 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
60
61 static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = {
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),
75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),
76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),
78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),
81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),
82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),
83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),
84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),
85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),
86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),
87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),
88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),
89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),
90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),
91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),
92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),
93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),
94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),
96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),
97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),
98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),
99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),
100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),
101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),
102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),
103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),
105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),
107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),
108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),
109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),
110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),
111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),
112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),
113 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
115 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),
116 };
117
118 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
119 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
120 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
121 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
122 static int sdma_v6_0_start(struct amdgpu_device *adev);
123
sdma_v6_0_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)124 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
125 {
126 u32 base;
127
128 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
129 internal_offset <= SDMA0_HYP_DEC_REG_END) {
130 base = adev->reg_offset[GC_HWIP][0][1];
131 if (instance != 0)
132 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
133 } else {
134 base = adev->reg_offset[GC_HWIP][0][0];
135 if (instance == 1)
136 internal_offset += SDMA1_REG_OFFSET;
137 }
138
139 return base + internal_offset;
140 }
141
sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)142 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring,
143 uint64_t addr)
144 {
145 unsigned ret;
146
147 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
148 amdgpu_ring_write(ring, lower_32_bits(addr));
149 amdgpu_ring_write(ring, upper_32_bits(addr));
150 amdgpu_ring_write(ring, 1);
151 /* this is the offset we need patch later */
152 ret = ring->wptr & ring->buf_mask;
153 /* insert dummy here and patch it later */
154 amdgpu_ring_write(ring, 0);
155
156 return ret;
157 }
158
159 /**
160 * sdma_v6_0_ring_get_rptr - get the current read pointer
161 *
162 * @ring: amdgpu ring pointer
163 *
164 * Get the current rptr from the hardware.
165 */
sdma_v6_0_ring_get_rptr(struct amdgpu_ring * ring)166 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
167 {
168 u64 *rptr;
169
170 /* XXX check if swapping is necessary on BE */
171 rptr = (u64 *)ring->rptr_cpu_addr;
172
173 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
174 return ((*rptr) >> 2);
175 }
176
177 /**
178 * sdma_v6_0_ring_get_wptr - get the current write pointer
179 *
180 * @ring: amdgpu ring pointer
181 *
182 * Get the current wptr from the hardware.
183 */
sdma_v6_0_ring_get_wptr(struct amdgpu_ring * ring)184 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
185 {
186 u64 wptr = 0;
187
188 if (ring->use_doorbell) {
189 /* XXX check if swapping is necessary on BE */
190 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
191 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
192 }
193
194 return wptr >> 2;
195 }
196
197 /**
198 * sdma_v6_0_ring_set_wptr - commit the write pointer
199 *
200 * @ring: amdgpu ring pointer
201 *
202 * Write the wptr back to the hardware.
203 */
sdma_v6_0_ring_set_wptr(struct amdgpu_ring * ring)204 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
205 {
206 struct amdgpu_device *adev = ring->adev;
207
208 if (ring->use_doorbell) {
209 DRM_DEBUG("Using doorbell -- "
210 "wptr_offs == 0x%08x "
211 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
212 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
213 ring->wptr_offs,
214 lower_32_bits(ring->wptr << 2),
215 upper_32_bits(ring->wptr << 2));
216 /* XXX check if swapping is necessary on BE */
217 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
218 ring->wptr << 2);
219 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
220 ring->doorbell_index, ring->wptr << 2);
221 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
222 } else {
223 DRM_DEBUG("Not using doorbell -- "
224 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
225 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
226 ring->me,
227 lower_32_bits(ring->wptr << 2),
228 ring->me,
229 upper_32_bits(ring->wptr << 2));
230 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
231 ring->me, regSDMA0_QUEUE0_RB_WPTR),
232 lower_32_bits(ring->wptr << 2));
233 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
234 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
235 upper_32_bits(ring->wptr << 2));
236 }
237 }
238
sdma_v6_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)239 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
240 {
241 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
242 int i;
243
244 for (i = 0; i < count; i++)
245 if (sdma && sdma->burst_nop && (i == 0))
246 amdgpu_ring_write(ring, ring->funcs->nop |
247 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
248 else
249 amdgpu_ring_write(ring, ring->funcs->nop);
250 }
251
252 /*
253 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
254 *
255 * @ring: amdgpu ring pointer
256 * @ib: IB object to schedule
257 * @flags: unused
258 * @job: job to retrieve vmid from
259 *
260 * Schedule an IB in the DMA ring.
261 */
sdma_v6_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)262 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
263 struct amdgpu_job *job,
264 struct amdgpu_ib *ib,
265 uint32_t flags)
266 {
267 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
268 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
269
270 /* An IB packet must end on a 8 DW boundary--the next dword
271 * must be on a 8-dword boundary. Our IB packet below is 6
272 * dwords long, thus add x number of NOPs, such that, in
273 * modular arithmetic,
274 * wptr + 6 + x = 8k, k >= 0, which in C is,
275 * (wptr + 6 + x) % 8 = 0.
276 * The expression below, is a solution of x.
277 */
278 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
279
280 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
281 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
282 /* base must be 32 byte aligned */
283 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
284 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
285 amdgpu_ring_write(ring, ib->length_dw);
286 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
287 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
288 }
289
290 /**
291 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
292 *
293 * @ring: amdgpu ring pointer
294 *
295 * flush the IB by graphics cache rinse.
296 */
sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring * ring)297 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
298 {
299 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
300 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
301 SDMA_GCR_GLI_INV(1);
302
303 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
304 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
305 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
306 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
307 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
308 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
309 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
310 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
311 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
312 }
313
314
315 /**
316 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
317 *
318 * @ring: amdgpu ring pointer
319 *
320 * Emit an hdp flush packet on the requested DMA ring.
321 */
sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)322 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
323 {
324 struct amdgpu_device *adev = ring->adev;
325 u32 ref_and_mask = 0;
326 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
327
328 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
329
330 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
331 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
332 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
333 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
334 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
335 amdgpu_ring_write(ring, ref_and_mask); /* reference */
336 amdgpu_ring_write(ring, ref_and_mask); /* mask */
337 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
338 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
339 }
340
341 /**
342 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
343 *
344 * @ring: amdgpu ring pointer
345 * @addr: address
346 * @seq: fence seq number
347 * @flags: fence flags
348 *
349 * Add a DMA fence packet to the ring to write
350 * the fence seq number and DMA trap packet to generate
351 * an interrupt if needed.
352 */
sdma_v6_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)353 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
354 unsigned flags)
355 {
356 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
357 /* write the fence */
358 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
359 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
360 /* zero in first two bits */
361 BUG_ON(addr & 0x3);
362 amdgpu_ring_write(ring, lower_32_bits(addr));
363 amdgpu_ring_write(ring, upper_32_bits(addr));
364 amdgpu_ring_write(ring, lower_32_bits(seq));
365
366 /* optionally write high bits as well */
367 if (write64bit) {
368 addr += 4;
369 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
370 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
371 /* zero in first two bits */
372 BUG_ON(addr & 0x3);
373 amdgpu_ring_write(ring, lower_32_bits(addr));
374 amdgpu_ring_write(ring, upper_32_bits(addr));
375 amdgpu_ring_write(ring, upper_32_bits(seq));
376 }
377
378 if (flags & AMDGPU_FENCE_FLAG_INT) {
379 uint32_t ctx = ring->is_mes_queue ?
380 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
381 /* generate an interrupt */
382 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
383 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
384 }
385 }
386
387 /**
388 * sdma_v6_0_gfx_stop - stop the gfx async dma engines
389 *
390 * @adev: amdgpu_device pointer
391 *
392 * Stop the gfx async dma ring buffers.
393 */
sdma_v6_0_gfx_stop(struct amdgpu_device * adev)394 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
395 {
396 u32 rb_cntl, ib_cntl;
397 int i;
398
399 for (i = 0; i < adev->sdma.num_instances; i++) {
400 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
401 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
402 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
403 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
404 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
405 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
406 }
407 }
408
409 /**
410 * sdma_v6_0_rlc_stop - stop the compute async dma engines
411 *
412 * @adev: amdgpu_device pointer
413 *
414 * Stop the compute async dma queues.
415 */
sdma_v6_0_rlc_stop(struct amdgpu_device * adev)416 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
417 {
418 /* XXX todo */
419 }
420
421 /**
422 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
423 *
424 * @adev: amdgpu_device pointer
425 * @enable: enable/disable context switching due to queue empty conditions
426 *
427 * Enable or disable the async dma engines queue empty context switch.
428 */
sdma_v6_0_ctxempty_int_enable(struct amdgpu_device * adev,bool enable)429 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
430 {
431 u32 f32_cntl;
432 int i;
433
434 if (!amdgpu_sriov_vf(adev)) {
435 for (i = 0; i < adev->sdma.num_instances; i++) {
436 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
437 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
438 CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
439 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
440 }
441 }
442 }
443
444 /**
445 * sdma_v6_0_enable - stop the async dma engines
446 *
447 * @adev: amdgpu_device pointer
448 * @enable: enable/disable the DMA MEs.
449 *
450 * Halt or unhalt the async dma engines.
451 */
sdma_v6_0_enable(struct amdgpu_device * adev,bool enable)452 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
453 {
454 u32 f32_cntl;
455 int i;
456
457 if (!enable) {
458 sdma_v6_0_gfx_stop(adev);
459 sdma_v6_0_rlc_stop(adev);
460 }
461
462 if (amdgpu_sriov_vf(adev))
463 return;
464
465 for (i = 0; i < adev->sdma.num_instances; i++) {
466 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
467 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
468 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
469 }
470 }
471
472 /**
473 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine
474 *
475 * @adev: amdgpu_device pointer
476 * @i: instance
477 * @restore: used to restore wptr when restart
478 *
479 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
480 * Return 0 for success.
481 */
sdma_v6_0_gfx_resume_instance(struct amdgpu_device * adev,int i,bool restore)482 static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
483 {
484 struct amdgpu_ring *ring;
485 u32 rb_cntl, ib_cntl;
486 u32 rb_bufsz;
487 u32 doorbell;
488 u32 doorbell_offset;
489 u32 temp;
490 u64 wptr_gpu_addr;
491
492 ring = &adev->sdma.instance[i].ring;
493 if (!amdgpu_sriov_vf(adev))
494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
495
496 /* Set ring buffer size in dwords */
497 rb_bufsz = order_base_2(ring->ring_size / 4);
498 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
500 #ifdef __BIG_ENDIAN
501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
503 RPTR_WRITEBACK_SWAP_ENABLE, 1);
504 #endif
505 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
506 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
507
508 /* Initialize the ring buffer's read and write pointers */
509 if (restore) {
510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
513 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
514 } else {
515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
516 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
518 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
519 }
520 /* setup the wptr shadow polling */
521 wptr_gpu_addr = ring->wptr_gpu_addr;
522 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
523 lower_32_bits(wptr_gpu_addr));
524 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
525 upper_32_bits(wptr_gpu_addr));
526
527 /* set the wb address whether it's enabled or not */
528 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
529 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
530 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
531 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
532
533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
536
537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
538 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
539
540 if (!restore)
541 ring->wptr = 0;
542
543 /* before programing wptr to a less value, need set minor_ptr_update first */
544 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
545
546 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
547 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
548 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
549 }
550
551 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
552 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
553
554 if (ring->use_doorbell) {
555 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
556 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
557 OFFSET, ring->doorbell_index);
558 } else {
559 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
560 }
561 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
562 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
563
564 if (i == 0)
565 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
566 ring->doorbell_index,
567 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
568
569 if (amdgpu_sriov_vf(adev))
570 sdma_v6_0_ring_set_wptr(ring);
571
572 /* set minor_ptr_update to 0 after wptr programed */
573 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
574
575 /* Set up sdma hang watchdog */
576 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
577 /* 100ms per unit */
578 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
579 max(adev->usec_timeout/100000, 1));
580 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);
581
582 /* Set up RESP_MODE to non-copy addresses */
583 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
584 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
585 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
586 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
587
588 /* program default cache read and write policy */
589 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
590 /* clean read policy and write policy bits */
591 temp &= 0xFF0FFF;
592 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
593 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
594 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
595 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
596
597 if (!amdgpu_sriov_vf(adev)) {
598 /* unhalt engine */
599 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
600 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
601 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
602 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
603 }
604
605 /* enable DMA RB */
606 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
607 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
608
609 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
610 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
611 #ifdef __BIG_ENDIAN
612 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
613 #endif
614 /* enable DMA IBs */
615 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
616
617 if (amdgpu_sriov_vf(adev))
618 sdma_v6_0_enable(adev, true);
619
620 return amdgpu_ring_test_helper(ring);
621 }
622
623 /**
624 * sdma_v6_0_gfx_resume - setup and start the async dma engines
625 *
626 * @adev: amdgpu_device pointer
627 *
628 * Set up the gfx DMA ring buffers and enable them.
629 * Returns 0 for success, error for failure.
630 */
sdma_v6_0_gfx_resume(struct amdgpu_device * adev)631 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
632 {
633 int i, r;
634
635 for (i = 0; i < adev->sdma.num_instances; i++) {
636 r = sdma_v6_0_gfx_resume_instance(adev, i, false);
637 if (r)
638 return r;
639 }
640
641 return 0;
642 }
643
644 /**
645 * sdma_v6_0_rlc_resume - setup and start the async dma engines
646 *
647 * @adev: amdgpu_device pointer
648 *
649 * Set up the compute DMA queues and enable them.
650 * Returns 0 for success, error for failure.
651 */
sdma_v6_0_rlc_resume(struct amdgpu_device * adev)652 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
653 {
654 return 0;
655 }
656
657 /**
658 * sdma_v6_0_load_microcode - load the sDMA ME ucode
659 *
660 * @adev: amdgpu_device pointer
661 *
662 * Loads the sDMA0/1 ucode.
663 * Returns 0 for success, -EINVAL if the ucode is not available.
664 */
sdma_v6_0_load_microcode(struct amdgpu_device * adev)665 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
666 {
667 const struct sdma_firmware_header_v2_0 *hdr;
668 const __le32 *fw_data;
669 u32 fw_size;
670 int i, j;
671 bool use_broadcast;
672
673 /* halt the MEs */
674 sdma_v6_0_enable(adev, false);
675
676 if (!adev->sdma.instance[0].fw)
677 return -EINVAL;
678
679 /* use broadcast mode to load SDMA microcode by default */
680 use_broadcast = true;
681
682 if (use_broadcast) {
683 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
684 /* load Control Thread microcode */
685 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
686 amdgpu_ucode_print_sdma_hdr(&hdr->header);
687 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
688
689 fw_data = (const __le32 *)
690 (adev->sdma.instance[0].fw->data +
691 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
692
693 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
694
695 for (j = 0; j < fw_size; j++) {
696 if (amdgpu_emu_mode == 1 && j % 500 == 0)
697 msleep(1);
698 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
699 }
700
701 /* load Context Switch microcode */
702 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
703
704 fw_data = (const __le32 *)
705 (adev->sdma.instance[0].fw->data +
706 le32_to_cpu(hdr->ctl_ucode_offset));
707
708 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
709
710 for (j = 0; j < fw_size; j++) {
711 if (amdgpu_emu_mode == 1 && j % 500 == 0)
712 msleep(1);
713 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
714 }
715 } else {
716 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
717 for (i = 0; i < adev->sdma.num_instances; i++) {
718 /* load Control Thread microcode */
719 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
720 amdgpu_ucode_print_sdma_hdr(&hdr->header);
721 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
722
723 fw_data = (const __le32 *)
724 (adev->sdma.instance[0].fw->data +
725 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
726
727 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
728
729 for (j = 0; j < fw_size; j++) {
730 if (amdgpu_emu_mode == 1 && j % 500 == 0)
731 msleep(1);
732 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
733 }
734
735 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
736
737 /* load Context Switch microcode */
738 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
739
740 fw_data = (const __le32 *)
741 (adev->sdma.instance[0].fw->data +
742 le32_to_cpu(hdr->ctl_ucode_offset));
743
744 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
745
746 for (j = 0; j < fw_size; j++) {
747 if (amdgpu_emu_mode == 1 && j % 500 == 0)
748 msleep(1);
749 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
750 }
751
752 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
753 }
754 }
755
756 return 0;
757 }
758
sdma_v6_0_soft_reset(struct amdgpu_ip_block * ip_block)759 static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
760 {
761 struct amdgpu_device *adev = ip_block->adev;
762 u32 tmp;
763 int i;
764
765 sdma_v6_0_gfx_stop(adev);
766
767 for (i = 0; i < adev->sdma.num_instances; i++) {
768 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
769 tmp |= SDMA0_FREEZE__FREEZE_MASK;
770 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
771 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
772 tmp |= SDMA0_F32_CNTL__HALT_MASK;
773 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
774 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
775
776 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
777
778 udelay(100);
779
780 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
781 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
782 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
783
784 udelay(100);
785
786 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
787 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
788
789 udelay(100);
790 }
791
792 return sdma_v6_0_start(adev);
793 }
794
sdma_v6_0_check_soft_reset(struct amdgpu_ip_block * ip_block)795 static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
796 {
797 struct amdgpu_device *adev = ip_block->adev;
798 struct amdgpu_ring *ring;
799 int i, r;
800 long tmo = msecs_to_jiffies(1000);
801
802 for (i = 0; i < adev->sdma.num_instances; i++) {
803 ring = &adev->sdma.instance[i].ring;
804 r = amdgpu_ring_test_ib(ring, tmo);
805 if (r)
806 return true;
807 }
808
809 return false;
810 }
811
812 /**
813 * sdma_v6_0_start - setup and start the async dma engines
814 *
815 * @adev: amdgpu_device pointer
816 *
817 * Set up the DMA engines and enable them.
818 * Returns 0 for success, error for failure.
819 */
sdma_v6_0_start(struct amdgpu_device * adev)820 static int sdma_v6_0_start(struct amdgpu_device *adev)
821 {
822 int r = 0;
823
824 if (amdgpu_sriov_vf(adev)) {
825 sdma_v6_0_enable(adev, false);
826
827 /* set RB registers */
828 r = sdma_v6_0_gfx_resume(adev);
829 return r;
830 }
831
832 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
833 r = sdma_v6_0_load_microcode(adev);
834 if (r)
835 return r;
836
837 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
838 if (amdgpu_emu_mode == 1)
839 msleep(1000);
840 }
841
842 /* unhalt the MEs */
843 sdma_v6_0_enable(adev, true);
844 /* enable sdma ring preemption */
845 sdma_v6_0_ctxempty_int_enable(adev, true);
846
847 /* start the gfx rings and rlc compute queues */
848 r = sdma_v6_0_gfx_resume(adev);
849 if (r)
850 return r;
851 r = sdma_v6_0_rlc_resume(adev);
852
853 return r;
854 }
855
sdma_v6_0_mqd_init(struct amdgpu_device * adev,void * mqd,struct amdgpu_mqd_prop * prop)856 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
857 struct amdgpu_mqd_prop *prop)
858 {
859 struct v11_sdma_mqd *m = mqd;
860 uint64_t wb_gpu_addr;
861
862 m->sdmax_rlcx_rb_cntl =
863 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
864 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
865 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
866 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
867
868 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
869 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
870
871 wb_gpu_addr = prop->wptr_gpu_addr;
872 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
873 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
874
875 wb_gpu_addr = prop->rptr_gpu_addr;
876 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
877 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
878
879 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
880 regSDMA0_QUEUE0_IB_CNTL));
881
882 m->sdmax_rlcx_doorbell_offset =
883 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
884
885 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
886
887 m->sdmax_rlcx_skip_cntl = 0;
888 m->sdmax_rlcx_context_status = 0;
889 m->sdmax_rlcx_doorbell_log = 0;
890
891 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
892 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
893
894 return 0;
895 }
896
sdma_v6_0_set_mqd_funcs(struct amdgpu_device * adev)897 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
898 {
899 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
900 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
901 }
902
903 /**
904 * sdma_v6_0_ring_test_ring - simple async dma engine test
905 *
906 * @ring: amdgpu_ring structure holding ring information
907 *
908 * Test the DMA engine by writing using it to write an
909 * value to memory.
910 * Returns 0 for success, error for failure.
911 */
sdma_v6_0_ring_test_ring(struct amdgpu_ring * ring)912 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
913 {
914 struct amdgpu_device *adev = ring->adev;
915 unsigned i;
916 unsigned index;
917 int r;
918 u32 tmp;
919 u64 gpu_addr;
920 volatile uint32_t *cpu_ptr = NULL;
921
922 tmp = 0xCAFEDEAD;
923
924 if (ring->is_mes_queue) {
925 uint32_t offset = 0;
926 offset = amdgpu_mes_ctx_get_offs(ring,
927 AMDGPU_MES_CTX_PADDING_OFFS);
928 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
929 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
930 *cpu_ptr = tmp;
931 } else {
932 r = amdgpu_device_wb_get(adev, &index);
933 if (r) {
934 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
935 return r;
936 }
937
938 gpu_addr = adev->wb.gpu_addr + (index * 4);
939 adev->wb.wb[index] = cpu_to_le32(tmp);
940 }
941
942 r = amdgpu_ring_alloc(ring, 5);
943 if (r) {
944 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
945 if (!ring->is_mes_queue)
946 amdgpu_device_wb_free(adev, index);
947 return r;
948 }
949
950 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
951 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
952 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
953 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
954 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
955 amdgpu_ring_write(ring, 0xDEADBEEF);
956 amdgpu_ring_commit(ring);
957
958 for (i = 0; i < adev->usec_timeout; i++) {
959 if (ring->is_mes_queue)
960 tmp = le32_to_cpu(*cpu_ptr);
961 else
962 tmp = le32_to_cpu(adev->wb.wb[index]);
963 if (tmp == 0xDEADBEEF)
964 break;
965 if (amdgpu_emu_mode == 1)
966 msleep(1);
967 else
968 udelay(1);
969 }
970
971 if (i >= adev->usec_timeout)
972 r = -ETIMEDOUT;
973
974 if (!ring->is_mes_queue)
975 amdgpu_device_wb_free(adev, index);
976
977 return r;
978 }
979
980 /*
981 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
982 *
983 * @ring: amdgpu_ring structure holding ring information
984 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
985 *
986 * Test a simple IB in the DMA ring.
987 * Returns 0 on success, error on failure.
988 */
sdma_v6_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)989 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
990 {
991 struct amdgpu_device *adev = ring->adev;
992 struct amdgpu_ib ib;
993 struct dma_fence *f = NULL;
994 unsigned index;
995 long r;
996 u32 tmp = 0;
997 u64 gpu_addr;
998 volatile uint32_t *cpu_ptr = NULL;
999
1000 tmp = 0xCAFEDEAD;
1001 memset(&ib, 0, sizeof(ib));
1002
1003 if (ring->is_mes_queue) {
1004 uint32_t offset = 0;
1005 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1006 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1007 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1008
1009 offset = amdgpu_mes_ctx_get_offs(ring,
1010 AMDGPU_MES_CTX_PADDING_OFFS);
1011 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1012 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1013 *cpu_ptr = tmp;
1014 } else {
1015 r = amdgpu_device_wb_get(adev, &index);
1016 if (r) {
1017 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1018 return r;
1019 }
1020
1021 gpu_addr = adev->wb.gpu_addr + (index * 4);
1022 adev->wb.wb[index] = cpu_to_le32(tmp);
1023
1024 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1025 if (r) {
1026 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1027 goto err0;
1028 }
1029 }
1030
1031 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1032 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1033 ib.ptr[1] = lower_32_bits(gpu_addr);
1034 ib.ptr[2] = upper_32_bits(gpu_addr);
1035 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1036 ib.ptr[4] = 0xDEADBEEF;
1037 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1038 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1039 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1040 ib.length_dw = 8;
1041
1042 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1043 if (r)
1044 goto err1;
1045
1046 r = dma_fence_wait_timeout(f, false, timeout);
1047 if (r == 0) {
1048 DRM_ERROR("amdgpu: IB test timed out\n");
1049 r = -ETIMEDOUT;
1050 goto err1;
1051 } else if (r < 0) {
1052 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1053 goto err1;
1054 }
1055
1056 if (ring->is_mes_queue)
1057 tmp = le32_to_cpu(*cpu_ptr);
1058 else
1059 tmp = le32_to_cpu(adev->wb.wb[index]);
1060
1061 if (tmp == 0xDEADBEEF)
1062 r = 0;
1063 else
1064 r = -EINVAL;
1065
1066 err1:
1067 amdgpu_ib_free(&ib, NULL);
1068 dma_fence_put(f);
1069 err0:
1070 if (!ring->is_mes_queue)
1071 amdgpu_device_wb_free(adev, index);
1072 return r;
1073 }
1074
1075
1076 /**
1077 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1078 *
1079 * @ib: indirect buffer to fill with commands
1080 * @pe: addr of the page entry
1081 * @src: src addr to copy from
1082 * @count: number of page entries to update
1083 *
1084 * Update PTEs by copying them from the GART using sDMA.
1085 */
sdma_v6_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1086 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1087 uint64_t pe, uint64_t src,
1088 unsigned count)
1089 {
1090 unsigned bytes = count * 8;
1091
1092 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1093 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1094 ib->ptr[ib->length_dw++] = bytes - 1;
1095 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1096 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1097 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1098 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1099 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1100
1101 }
1102
1103 /**
1104 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1105 *
1106 * @ib: indirect buffer to fill with commands
1107 * @pe: addr of the page entry
1108 * @value: dst addr to write into pe
1109 * @count: number of page entries to update
1110 * @incr: increase next addr by incr bytes
1111 *
1112 * Update PTEs by writing them manually using sDMA.
1113 */
sdma_v6_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1114 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1115 uint64_t value, unsigned count,
1116 uint32_t incr)
1117 {
1118 unsigned ndw = count * 2;
1119
1120 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1121 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1122 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1123 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1124 ib->ptr[ib->length_dw++] = ndw - 1;
1125 for (; ndw > 0; ndw -= 2) {
1126 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1127 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1128 value += incr;
1129 }
1130 }
1131
1132 /**
1133 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1134 *
1135 * @ib: indirect buffer to fill with commands
1136 * @pe: addr of the page entry
1137 * @addr: dst addr to write into pe
1138 * @count: number of page entries to update
1139 * @incr: increase next addr by incr bytes
1140 * @flags: access flags
1141 *
1142 * Update the page tables using sDMA.
1143 */
sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1144 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1145 uint64_t pe,
1146 uint64_t addr, unsigned count,
1147 uint32_t incr, uint64_t flags)
1148 {
1149 /* for physically contiguous pages (vram) */
1150 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1151 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1152 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1153 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1154 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1155 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1156 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1157 ib->ptr[ib->length_dw++] = incr; /* increment size */
1158 ib->ptr[ib->length_dw++] = 0;
1159 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1160 }
1161
1162 /*
1163 * sdma_v6_0_ring_pad_ib - pad the IB
1164 * @ib: indirect buffer to fill with padding
1165 * @ring: amdgpu ring pointer
1166 *
1167 * Pad the IB with NOPs to a boundary multiple of 8.
1168 */
sdma_v6_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1169 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1170 {
1171 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1172 u32 pad_count;
1173 int i;
1174
1175 pad_count = (-ib->length_dw) & 0x7;
1176 for (i = 0; i < pad_count; i++)
1177 if (sdma && sdma->burst_nop && (i == 0))
1178 ib->ptr[ib->length_dw++] =
1179 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1180 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1181 else
1182 ib->ptr[ib->length_dw++] =
1183 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1184 }
1185
1186 /**
1187 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1188 *
1189 * @ring: amdgpu_ring pointer
1190 *
1191 * Make sure all previous operations are completed (CIK).
1192 */
sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1193 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1194 {
1195 uint32_t seq = ring->fence_drv.sync_seq;
1196 uint64_t addr = ring->fence_drv.gpu_addr;
1197
1198 /* wait for idle */
1199 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1200 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1201 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1202 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1203 amdgpu_ring_write(ring, addr & 0xfffffffc);
1204 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1205 amdgpu_ring_write(ring, seq); /* reference */
1206 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1207 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1208 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1209 }
1210
1211 /*
1212 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1213 *
1214 * @ring: amdgpu_ring pointer
1215 * @vmid: vmid number to use
1216 * @pd_addr: address
1217 *
1218 * Update the page table base and flush the VM TLB
1219 * using sDMA.
1220 */
sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1221 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1222 unsigned vmid, uint64_t pd_addr)
1223 {
1224 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1225 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1226
1227 /* Update the PD address for this VMID. */
1228 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1229 (hub->ctx_addr_distance * vmid),
1230 lower_32_bits(pd_addr));
1231 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1232 (hub->ctx_addr_distance * vmid),
1233 upper_32_bits(pd_addr));
1234
1235 /* Trigger invalidation. */
1236 amdgpu_ring_write(ring,
1237 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1238 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1239 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1240 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1241 amdgpu_ring_write(ring, req);
1242 amdgpu_ring_write(ring, 0xFFFFFFFF);
1243 amdgpu_ring_write(ring,
1244 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1245 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1246 }
1247
sdma_v6_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1248 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1249 uint32_t reg, uint32_t val)
1250 {
1251 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1252 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1253 amdgpu_ring_write(ring, reg);
1254 amdgpu_ring_write(ring, val);
1255 }
1256
sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1257 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1258 uint32_t val, uint32_t mask)
1259 {
1260 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1261 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1262 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1263 amdgpu_ring_write(ring, reg << 2);
1264 amdgpu_ring_write(ring, 0);
1265 amdgpu_ring_write(ring, val); /* reference */
1266 amdgpu_ring_write(ring, mask); /* mask */
1267 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1268 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1269 }
1270
sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1271 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1272 uint32_t reg0, uint32_t reg1,
1273 uint32_t ref, uint32_t mask)
1274 {
1275 amdgpu_ring_emit_wreg(ring, reg0, ref);
1276 /* wait for a cycle to reset vm_inv_eng*_ack */
1277 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1278 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1279 }
1280
1281 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1282 .ras_block = {
1283 .ras_late_init = amdgpu_ras_block_late_init,
1284 },
1285 };
1286
sdma_v6_0_set_ras_funcs(struct amdgpu_device * adev)1287 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1288 {
1289 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1290 case IP_VERSION(6, 0, 3):
1291 adev->sdma.ras = &sdma_v6_0_3_ras;
1292 break;
1293 default:
1294 break;
1295 }
1296 }
1297
sdma_v6_0_early_init(struct amdgpu_ip_block * ip_block)1298 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
1299 {
1300 struct amdgpu_device *adev = ip_block->adev;
1301 int r;
1302
1303 r = amdgpu_sdma_init_microcode(adev, 0, true);
1304 if (r)
1305 return r;
1306
1307 sdma_v6_0_set_ring_funcs(adev);
1308 sdma_v6_0_set_buffer_funcs(adev);
1309 sdma_v6_0_set_vm_pte_funcs(adev);
1310 sdma_v6_0_set_irq_funcs(adev);
1311 sdma_v6_0_set_mqd_funcs(adev);
1312 sdma_v6_0_set_ras_funcs(adev);
1313
1314 return 0;
1315 }
1316
sdma_v6_0_sw_init(struct amdgpu_ip_block * ip_block)1317 static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
1318 {
1319 struct amdgpu_ring *ring;
1320 int r, i;
1321 struct amdgpu_device *adev = ip_block->adev;
1322 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1323 uint32_t *ptr;
1324
1325 /* SDMA trap event */
1326 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1327 GFX_11_0_0__SRCID__SDMA_TRAP,
1328 &adev->sdma.trap_irq);
1329 if (r)
1330 return r;
1331
1332 for (i = 0; i < adev->sdma.num_instances; i++) {
1333 ring = &adev->sdma.instance[i].ring;
1334 ring->ring_obj = NULL;
1335 ring->use_doorbell = true;
1336 ring->me = i;
1337
1338 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1339 ring->use_doorbell?"true":"false");
1340
1341 ring->doorbell_index =
1342 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1343
1344 ring->vm_hub = AMDGPU_GFXHUB(0);
1345 sprintf(ring->name, "sdma%d", i);
1346 r = amdgpu_ring_init(adev, ring, 1024,
1347 &adev->sdma.trap_irq,
1348 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1349 AMDGPU_RING_PRIO_DEFAULT, NULL);
1350 if (r)
1351 return r;
1352 }
1353
1354 adev->sdma.supported_reset =
1355 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
1356 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1357 case IP_VERSION(6, 0, 0):
1358 case IP_VERSION(6, 0, 2):
1359 case IP_VERSION(6, 0, 3):
1360 if (adev->sdma.instance[0].fw_version >= 21)
1361 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1362 break;
1363 default:
1364 break;
1365 }
1366
1367 if (amdgpu_sdma_ras_sw_init(adev)) {
1368 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1369 return -EINVAL;
1370 }
1371
1372 /* Allocate memory for SDMA IP Dump buffer */
1373 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1374 if (ptr)
1375 adev->sdma.ip_dump = ptr;
1376 else
1377 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1378
1379 r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1380 if (r)
1381 return r;
1382
1383 return r;
1384 }
1385
sdma_v6_0_sw_fini(struct amdgpu_ip_block * ip_block)1386 static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
1387 {
1388 struct amdgpu_device *adev = ip_block->adev;
1389 int i;
1390
1391 for (i = 0; i < adev->sdma.num_instances; i++)
1392 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1393
1394 amdgpu_sdma_sysfs_reset_mask_fini(adev);
1395 amdgpu_sdma_destroy_inst_ctx(adev, true);
1396
1397 kfree(adev->sdma.ip_dump);
1398
1399 return 0;
1400 }
1401
sdma_v6_0_hw_init(struct amdgpu_ip_block * ip_block)1402 static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
1403 {
1404 struct amdgpu_device *adev = ip_block->adev;
1405
1406 return sdma_v6_0_start(adev);
1407 }
1408
sdma_v6_0_hw_fini(struct amdgpu_ip_block * ip_block)1409 static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
1410 {
1411 struct amdgpu_device *adev = ip_block->adev;
1412
1413 if (amdgpu_sriov_vf(adev))
1414 return 0;
1415
1416 sdma_v6_0_ctxempty_int_enable(adev, false);
1417 sdma_v6_0_enable(adev, false);
1418
1419 return 0;
1420 }
1421
sdma_v6_0_suspend(struct amdgpu_ip_block * ip_block)1422 static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block)
1423 {
1424 return sdma_v6_0_hw_fini(ip_block);
1425 }
1426
sdma_v6_0_resume(struct amdgpu_ip_block * ip_block)1427 static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)
1428 {
1429 return sdma_v6_0_hw_init(ip_block);
1430 }
1431
sdma_v6_0_is_idle(struct amdgpu_ip_block * ip_block)1432 static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
1433 {
1434 struct amdgpu_device *adev = ip_block->adev;
1435 u32 i;
1436
1437 for (i = 0; i < adev->sdma.num_instances; i++) {
1438 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1439
1440 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1441 return false;
1442 }
1443
1444 return true;
1445 }
1446
sdma_v6_0_wait_for_idle(struct amdgpu_ip_block * ip_block)1447 static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1448 {
1449 unsigned i;
1450 u32 sdma0, sdma1;
1451 struct amdgpu_device *adev = ip_block->adev;
1452
1453 for (i = 0; i < adev->usec_timeout; i++) {
1454 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1455 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1456
1457 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1458 return 0;
1459 udelay(1);
1460 }
1461 return -ETIMEDOUT;
1462 }
1463
sdma_v6_0_ring_preempt_ib(struct amdgpu_ring * ring)1464 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1465 {
1466 int i, r = 0;
1467 struct amdgpu_device *adev = ring->adev;
1468 u32 index = 0;
1469 u64 sdma_gfx_preempt;
1470
1471 amdgpu_sdma_get_index_from_ring(ring, &index);
1472 sdma_gfx_preempt =
1473 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1474
1475 /* assert preemption condition */
1476 amdgpu_ring_set_preempt_cond_exec(ring, false);
1477
1478 /* emit the trailing fence */
1479 ring->trail_seq += 1;
1480 amdgpu_ring_alloc(ring, 10);
1481 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1482 ring->trail_seq, 0);
1483 amdgpu_ring_commit(ring);
1484
1485 /* assert IB preemption */
1486 WREG32(sdma_gfx_preempt, 1);
1487
1488 /* poll the trailing fence */
1489 for (i = 0; i < adev->usec_timeout; i++) {
1490 if (ring->trail_seq ==
1491 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1492 break;
1493 udelay(1);
1494 }
1495
1496 if (i >= adev->usec_timeout) {
1497 r = -EINVAL;
1498 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1499 }
1500
1501 /* deassert IB preemption */
1502 WREG32(sdma_gfx_preempt, 0);
1503
1504 /* deassert the preemption condition */
1505 amdgpu_ring_set_preempt_cond_exec(ring, true);
1506 return r;
1507 }
1508
sdma_v6_0_reset_queue(struct amdgpu_ring * ring,unsigned int vmid)1509 static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
1510 {
1511 struct amdgpu_device *adev = ring->adev;
1512 int i, r;
1513
1514 if (amdgpu_sriov_vf(adev))
1515 return -EINVAL;
1516
1517 for (i = 0; i < adev->sdma.num_instances; i++) {
1518 if (ring == &adev->sdma.instance[i].ring)
1519 break;
1520 }
1521
1522 if (i == adev->sdma.num_instances) {
1523 DRM_ERROR("sdma instance not found\n");
1524 return -EINVAL;
1525 }
1526
1527 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);
1528 if (r)
1529 return r;
1530
1531 return sdma_v6_0_gfx_resume_instance(adev, i, true);
1532 }
1533
sdma_v6_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1534 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1535 struct amdgpu_irq_src *source,
1536 unsigned type,
1537 enum amdgpu_interrupt_state state)
1538 {
1539 u32 sdma_cntl;
1540
1541 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1542
1543 if (!amdgpu_sriov_vf(adev)) {
1544 sdma_cntl = RREG32(reg_offset);
1545 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1546 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1547 WREG32(reg_offset, sdma_cntl);
1548 }
1549
1550 return 0;
1551 }
1552
sdma_v6_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1553 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1554 struct amdgpu_irq_src *source,
1555 struct amdgpu_iv_entry *entry)
1556 {
1557 int instances, queue;
1558 uint32_t mes_queue_id = entry->src_data[0];
1559
1560 DRM_DEBUG("IH: SDMA trap\n");
1561
1562 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1563 struct amdgpu_mes_queue *queue;
1564
1565 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1566
1567 spin_lock(&adev->mes.queue_id_lock);
1568 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1569 if (queue) {
1570 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1571 amdgpu_fence_process(queue->ring);
1572 }
1573 spin_unlock(&adev->mes.queue_id_lock);
1574 return 0;
1575 }
1576
1577 queue = entry->ring_id & 0xf;
1578 instances = (entry->ring_id & 0xf0) >> 4;
1579 if (instances > 1) {
1580 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1581 return -EINVAL;
1582 }
1583
1584 switch (entry->client_id) {
1585 case SOC21_IH_CLIENTID_GFX:
1586 switch (queue) {
1587 case 0:
1588 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1589 break;
1590 default:
1591 break;
1592 }
1593 break;
1594 }
1595 return 0;
1596 }
1597
sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1598 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1599 struct amdgpu_irq_src *source,
1600 struct amdgpu_iv_entry *entry)
1601 {
1602 return 0;
1603 }
1604
sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)1605 static int sdma_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1606 enum amd_clockgating_state state)
1607 {
1608 return 0;
1609 }
1610
sdma_v6_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)1611 static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
1612 enum amd_powergating_state state)
1613 {
1614 return 0;
1615 }
1616
sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)1617 static void sdma_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1618 {
1619 }
1620
sdma_v6_0_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)1621 static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1622 {
1623 struct amdgpu_device *adev = ip_block->adev;
1624 int i, j;
1625 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1626 uint32_t instance_offset;
1627
1628 if (!adev->sdma.ip_dump)
1629 return;
1630
1631 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1632 for (i = 0; i < adev->sdma.num_instances; i++) {
1633 instance_offset = i * reg_count;
1634 drm_printf(p, "\nInstance:%d\n", i);
1635
1636 for (j = 0; j < reg_count; j++)
1637 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name,
1638 adev->sdma.ip_dump[instance_offset + j]);
1639 }
1640 }
1641
sdma_v6_0_dump_ip_state(struct amdgpu_ip_block * ip_block)1642 static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
1643 {
1644 struct amdgpu_device *adev = ip_block->adev;
1645 int i, j;
1646 uint32_t instance_offset;
1647 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1648
1649 if (!adev->sdma.ip_dump)
1650 return;
1651
1652 amdgpu_gfx_off_ctrl(adev, false);
1653 for (i = 0; i < adev->sdma.num_instances; i++) {
1654 instance_offset = i * reg_count;
1655 for (j = 0; j < reg_count; j++)
1656 adev->sdma.ip_dump[instance_offset + j] =
1657 RREG32(sdma_v6_0_get_reg_offset(adev, i,
1658 sdma_reg_list_6_0[j].reg_offset));
1659 }
1660 amdgpu_gfx_off_ctrl(adev, true);
1661 }
1662
1663 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1664 .name = "sdma_v6_0",
1665 .early_init = sdma_v6_0_early_init,
1666 .sw_init = sdma_v6_0_sw_init,
1667 .sw_fini = sdma_v6_0_sw_fini,
1668 .hw_init = sdma_v6_0_hw_init,
1669 .hw_fini = sdma_v6_0_hw_fini,
1670 .suspend = sdma_v6_0_suspend,
1671 .resume = sdma_v6_0_resume,
1672 .is_idle = sdma_v6_0_is_idle,
1673 .wait_for_idle = sdma_v6_0_wait_for_idle,
1674 .soft_reset = sdma_v6_0_soft_reset,
1675 .check_soft_reset = sdma_v6_0_check_soft_reset,
1676 .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1677 .set_powergating_state = sdma_v6_0_set_powergating_state,
1678 .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1679 .dump_ip_state = sdma_v6_0_dump_ip_state,
1680 .print_ip_state = sdma_v6_0_print_ip_state,
1681 };
1682
1683 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1684 .type = AMDGPU_RING_TYPE_SDMA,
1685 .align_mask = 0xf,
1686 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1687 .support_64bit_ptrs = true,
1688 .secure_submission_supported = true,
1689 .get_rptr = sdma_v6_0_ring_get_rptr,
1690 .get_wptr = sdma_v6_0_ring_get_wptr,
1691 .set_wptr = sdma_v6_0_ring_set_wptr,
1692 .emit_frame_size =
1693 5 + /* sdma_v6_0_ring_init_cond_exec */
1694 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1695 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1696 /* sdma_v6_0_ring_emit_vm_flush */
1697 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1698 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1699 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1700 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1701 .emit_ib = sdma_v6_0_ring_emit_ib,
1702 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1703 .emit_fence = sdma_v6_0_ring_emit_fence,
1704 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1705 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1706 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1707 .test_ring = sdma_v6_0_ring_test_ring,
1708 .test_ib = sdma_v6_0_ring_test_ib,
1709 .insert_nop = sdma_v6_0_ring_insert_nop,
1710 .pad_ib = sdma_v6_0_ring_pad_ib,
1711 .emit_wreg = sdma_v6_0_ring_emit_wreg,
1712 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1713 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1714 .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1715 .preempt_ib = sdma_v6_0_ring_preempt_ib,
1716 .reset = sdma_v6_0_reset_queue,
1717 };
1718
sdma_v6_0_set_ring_funcs(struct amdgpu_device * adev)1719 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1720 {
1721 int i;
1722
1723 for (i = 0; i < adev->sdma.num_instances; i++) {
1724 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1725 adev->sdma.instance[i].ring.me = i;
1726 }
1727 }
1728
1729 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1730 .set = sdma_v6_0_set_trap_irq_state,
1731 .process = sdma_v6_0_process_trap_irq,
1732 };
1733
1734 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1735 .process = sdma_v6_0_process_illegal_inst_irq,
1736 };
1737
sdma_v6_0_set_irq_funcs(struct amdgpu_device * adev)1738 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1739 {
1740 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1741 adev->sdma.num_instances;
1742 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1743 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1744 }
1745
1746 /**
1747 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1748 *
1749 * @ib: indirect buffer to fill with commands
1750 * @src_offset: src GPU address
1751 * @dst_offset: dst GPU address
1752 * @byte_count: number of bytes to xfer
1753 * @copy_flags: copy flags for the buffers
1754 *
1755 * Copy GPU buffers using the DMA engine.
1756 * Used by the amdgpu ttm implementation to move pages if
1757 * registered as the asic copy callback.
1758 */
sdma_v6_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)1759 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1760 uint64_t src_offset,
1761 uint64_t dst_offset,
1762 uint32_t byte_count,
1763 uint32_t copy_flags)
1764 {
1765 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1766 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1767 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1768 ib->ptr[ib->length_dw++] = byte_count - 1;
1769 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1770 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1771 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1772 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1773 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1774 }
1775
1776 /**
1777 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1778 *
1779 * @ib: indirect buffer to fill
1780 * @src_data: value to write to buffer
1781 * @dst_offset: dst GPU address
1782 * @byte_count: number of bytes to xfer
1783 *
1784 * Fill GPU buffers using the DMA engine.
1785 */
sdma_v6_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1786 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1787 uint32_t src_data,
1788 uint64_t dst_offset,
1789 uint32_t byte_count)
1790 {
1791 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL);
1792 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1793 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1794 ib->ptr[ib->length_dw++] = src_data;
1795 ib->ptr[ib->length_dw++] = byte_count - 1;
1796 }
1797
1798 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1799 .copy_max_bytes = 0x400000,
1800 .copy_num_dw = 7,
1801 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1802
1803 .fill_max_bytes = 0x400000,
1804 .fill_num_dw = 5,
1805 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1806 };
1807
sdma_v6_0_set_buffer_funcs(struct amdgpu_device * adev)1808 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1809 {
1810 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1811 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1812 }
1813
1814 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1815 .copy_pte_num_dw = 7,
1816 .copy_pte = sdma_v6_0_vm_copy_pte,
1817 .write_pte = sdma_v6_0_vm_write_pte,
1818 .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1819 };
1820
sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device * adev)1821 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1822 {
1823 unsigned i;
1824
1825 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1826 for (i = 0; i < adev->sdma.num_instances; i++) {
1827 adev->vm_manager.vm_pte_scheds[i] =
1828 &adev->sdma.instance[i].ring.sched;
1829 }
1830 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1831 }
1832
1833 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1834 .type = AMD_IP_BLOCK_TYPE_SDMA,
1835 .major = 6,
1836 .minor = 0,
1837 .rev = 0,
1838 .funcs = &sdma_v6_0_ip_funcs,
1839 };
1840