1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_xcp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_trace.h"
33 #include "amdgpu_reset.h"
34 
35 #include "sdma/sdma_4_4_2_offset.h"
36 #include "sdma/sdma_4_4_2_sh_mask.h"
37 
38 #include "soc15_common.h"
39 #include "soc15.h"
40 #include "vega10_sdma_pkt_open.h"
41 
42 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
43 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
44 
45 #include "amdgpu_ras.h"
46 
47 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
48 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin");
49 
50 static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = {
51 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS_REG),
52 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS1_REG),
53 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS2_REG),
54 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_STATUS3_REG),
55 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UCODE_CHECKSUM),
56 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH_HI),
57 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RB_RPTR_FETCH),
58 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_STATUS),
59 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_STATUS),
60 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK0),
61 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_RD_XNACK1),
62 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK0),
63 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_UTCL1_WR_XNACK1),
64 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_CNTL),
65 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR),
66 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_RPTR_HI),
67 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR),
68 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_RB_WPTR_HI),
69 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_OFFSET),
70 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_LO),
71 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_BASE_HI),
72 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_CNTL),
73 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_RPTR),
74 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_IB_SUB_REMAIN),
75 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_GFX_DUMMY_REG),
76 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_CNTL),
77 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR),
78 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_RPTR_HI),
79 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR),
80 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_RB_WPTR_HI),
81 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_OFFSET),
82 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_LO),
83 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_IB_BASE_HI),
84 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_PAGE_DUMMY_REG),
85 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_CNTL),
86 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR),
87 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_RPTR_HI),
88 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR),
89 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_RB_WPTR_HI),
90 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_OFFSET),
91 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_LO),
92 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_IB_BASE_HI),
93 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_RLC0_DUMMY_REG),
94 	SOC15_REG_ENTRY_STR(GC, 0, regSDMA_VM_CNTL)
95 };
96 
97 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
98 
99 #define WREG32_SDMA(instance, offset, value) \
100 	WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
101 #define RREG32_SDMA(instance, offset) \
102 	RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
103 
104 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
105 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
106 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
107 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
108 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
109 static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev);
110 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev);
111 
sdma_v4_4_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 offset)112 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
113 		u32 instance, u32 offset)
114 {
115 	u32 dev_inst = GET_INST(SDMA0, instance);
116 
117 	return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
118 }
119 
sdma_v4_4_2_seq_to_irq_id(int seq_num)120 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
121 {
122 	switch (seq_num) {
123 	case 0:
124 		return SOC15_IH_CLIENTID_SDMA0;
125 	case 1:
126 		return SOC15_IH_CLIENTID_SDMA1;
127 	case 2:
128 		return SOC15_IH_CLIENTID_SDMA2;
129 	case 3:
130 		return SOC15_IH_CLIENTID_SDMA3;
131 	default:
132 		return -EINVAL;
133 	}
134 }
135 
sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device * adev,unsigned client_id)136 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id)
137 {
138 	switch (client_id) {
139 	case SOC15_IH_CLIENTID_SDMA0:
140 		return 0;
141 	case SOC15_IH_CLIENTID_SDMA1:
142 		return 1;
143 	case SOC15_IH_CLIENTID_SDMA2:
144 		if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
145 			return 0;
146 		else
147 			return 2;
148 	case SOC15_IH_CLIENTID_SDMA3:
149 		if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
150 			return 1;
151 		else
152 			return 3;
153 	default:
154 		return -EINVAL;
155 	}
156 }
157 
sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device * adev,uint32_t inst_mask)158 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
159 						   uint32_t inst_mask)
160 {
161 	u32 val;
162 	int i;
163 
164 	for (i = 0; i < adev->sdma.num_instances; i++) {
165 		val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
166 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
167 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
168 				    PIPE_INTERLEAVE_SIZE, 0);
169 		WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
170 
171 		val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
172 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
173 				    4);
174 		val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
175 				    PIPE_INTERLEAVE_SIZE, 0);
176 		WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
177 	}
178 }
179 
180 /**
181  * sdma_v4_4_2_init_microcode - load ucode images from disk
182  *
183  * @adev: amdgpu_device pointer
184  *
185  * Use the firmware interface to load the ucode images into
186  * the driver (not loaded into hw).
187  * Returns 0 on success, error on failure.
188  */
sdma_v4_4_2_init_microcode(struct amdgpu_device * adev)189 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
190 {
191 	int ret, i;
192 
193 	for (i = 0; i < adev->sdma.num_instances; i++) {
194 		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
195 		    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) ||
196 		    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
197 			ret = amdgpu_sdma_init_microcode(adev, 0, true);
198 			break;
199 		} else {
200 			ret = amdgpu_sdma_init_microcode(adev, i, false);
201 			if (ret)
202 				return ret;
203 		}
204 	}
205 
206 	return ret;
207 }
208 
209 /**
210  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
211  *
212  * @ring: amdgpu ring pointer
213  *
214  * Get the current rptr from the hardware.
215  */
sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring * ring)216 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
217 {
218 	u64 rptr;
219 
220 	/* XXX check if swapping is necessary on BE */
221 	rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
222 
223 	DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
224 	return rptr >> 2;
225 }
226 
227 /**
228  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
229  *
230  * @ring: amdgpu ring pointer
231  *
232  * Get the current wptr from the hardware.
233  */
sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring * ring)234 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
235 {
236 	struct amdgpu_device *adev = ring->adev;
237 	u64 wptr;
238 
239 	if (ring->use_doorbell) {
240 		/* XXX check if swapping is necessary on BE */
241 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
242 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
243 	} else {
244 		wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
245 		wptr = wptr << 32;
246 		wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
247 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
248 				ring->me, wptr);
249 	}
250 
251 	return wptr >> 2;
252 }
253 
254 /**
255  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
256  *
257  * @ring: amdgpu ring pointer
258  *
259  * Write the wptr back to the hardware.
260  */
sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring * ring)261 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
262 {
263 	struct amdgpu_device *adev = ring->adev;
264 
265 	DRM_DEBUG("Setting write pointer\n");
266 	if (ring->use_doorbell) {
267 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
268 
269 		DRM_DEBUG("Using doorbell -- "
270 				"wptr_offs == 0x%08x "
271 				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
272 				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
273 				ring->wptr_offs,
274 				lower_32_bits(ring->wptr << 2),
275 				upper_32_bits(ring->wptr << 2));
276 		/* XXX check if swapping is necessary on BE */
277 		WRITE_ONCE(*wb, (ring->wptr << 2));
278 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
279 				ring->doorbell_index, ring->wptr << 2);
280 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
281 	} else {
282 		DRM_DEBUG("Not using doorbell -- "
283 				"regSDMA%i_GFX_RB_WPTR == 0x%08x "
284 				"regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
285 				ring->me,
286 				lower_32_bits(ring->wptr << 2),
287 				ring->me,
288 				upper_32_bits(ring->wptr << 2));
289 		WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
290 			    lower_32_bits(ring->wptr << 2));
291 		WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
292 			    upper_32_bits(ring->wptr << 2));
293 	}
294 }
295 
296 /**
297  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
298  *
299  * @ring: amdgpu ring pointer
300  *
301  * Get the current wptr from the hardware.
302  */
sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring * ring)303 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
304 {
305 	struct amdgpu_device *adev = ring->adev;
306 	u64 wptr;
307 
308 	if (ring->use_doorbell) {
309 		/* XXX check if swapping is necessary on BE */
310 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
311 	} else {
312 		wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
313 		wptr = wptr << 32;
314 		wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
315 	}
316 
317 	return wptr >> 2;
318 }
319 
320 /**
321  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
322  *
323  * @ring: amdgpu ring pointer
324  *
325  * Write the wptr back to the hardware.
326  */
sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring * ring)327 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
328 {
329 	struct amdgpu_device *adev = ring->adev;
330 
331 	if (ring->use_doorbell) {
332 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
333 
334 		/* XXX check if swapping is necessary on BE */
335 		WRITE_ONCE(*wb, (ring->wptr << 2));
336 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
337 	} else {
338 		uint64_t wptr = ring->wptr << 2;
339 
340 		WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
341 			    lower_32_bits(wptr));
342 		WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
343 			    upper_32_bits(wptr));
344 	}
345 }
346 
sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)347 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
348 {
349 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
350 	int i;
351 
352 	for (i = 0; i < count; i++)
353 		if (sdma && sdma->burst_nop && (i == 0))
354 			amdgpu_ring_write(ring, ring->funcs->nop |
355 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
356 		else
357 			amdgpu_ring_write(ring, ring->funcs->nop);
358 }
359 
360 /**
361  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
362  *
363  * @ring: amdgpu ring pointer
364  * @job: job to retrieve vmid from
365  * @ib: IB object to schedule
366  * @flags: unused
367  *
368  * Schedule an IB in the DMA ring.
369  */
sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)370 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
371 				   struct amdgpu_job *job,
372 				   struct amdgpu_ib *ib,
373 				   uint32_t flags)
374 {
375 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
376 
377 	/* IB packet must end on a 8 DW boundary */
378 	sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
379 
380 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
381 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
382 	/* base must be 32 byte aligned */
383 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
384 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
385 	amdgpu_ring_write(ring, ib->length_dw);
386 	amdgpu_ring_write(ring, 0);
387 	amdgpu_ring_write(ring, 0);
388 
389 }
390 
sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring * ring,int mem_space,int hdp,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)391 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
392 				   int mem_space, int hdp,
393 				   uint32_t addr0, uint32_t addr1,
394 				   uint32_t ref, uint32_t mask,
395 				   uint32_t inv)
396 {
397 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
398 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
399 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
400 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
401 	if (mem_space) {
402 		/* memory */
403 		amdgpu_ring_write(ring, addr0);
404 		amdgpu_ring_write(ring, addr1);
405 	} else {
406 		/* registers */
407 		amdgpu_ring_write(ring, addr0 << 2);
408 		amdgpu_ring_write(ring, addr1 << 2);
409 	}
410 	amdgpu_ring_write(ring, ref); /* reference */
411 	amdgpu_ring_write(ring, mask); /* mask */
412 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
413 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
414 }
415 
416 /**
417  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
418  *
419  * @ring: amdgpu ring pointer
420  *
421  * Emit an hdp flush packet on the requested DMA ring.
422  */
sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)423 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
424 {
425 	struct amdgpu_device *adev = ring->adev;
426 	u32 ref_and_mask = 0;
427 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
428 
429 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
430 		       << (ring->me % adev->sdma.num_inst_per_aid);
431 
432 	sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
433 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
434 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
435 			       ref_and_mask, ref_and_mask, 10);
436 }
437 
438 /**
439  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
440  *
441  * @ring: amdgpu ring pointer
442  * @addr: address
443  * @seq: sequence number
444  * @flags: fence related flags
445  *
446  * Add a DMA fence packet to the ring to write
447  * the fence seq number and DMA trap packet to generate
448  * an interrupt if needed.
449  */
sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)450 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
451 				      unsigned flags)
452 {
453 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
454 	/* write the fence */
455 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
456 	/* zero in first two bits */
457 	BUG_ON(addr & 0x3);
458 	amdgpu_ring_write(ring, lower_32_bits(addr));
459 	amdgpu_ring_write(ring, upper_32_bits(addr));
460 	amdgpu_ring_write(ring, lower_32_bits(seq));
461 
462 	/* optionally write high bits as well */
463 	if (write64bit) {
464 		addr += 4;
465 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
466 		/* zero in first two bits */
467 		BUG_ON(addr & 0x3);
468 		amdgpu_ring_write(ring, lower_32_bits(addr));
469 		amdgpu_ring_write(ring, upper_32_bits(addr));
470 		amdgpu_ring_write(ring, upper_32_bits(seq));
471 	}
472 
473 	/* generate an interrupt */
474 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
475 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
476 }
477 
478 
479 /**
480  * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
481  *
482  * @adev: amdgpu_device pointer
483  * @inst_mask: mask of dma engine instances to be disabled
484  *
485  * Stop the gfx async dma ring buffers.
486  */
sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device * adev,uint32_t inst_mask)487 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
488 				      uint32_t inst_mask)
489 {
490 	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
491 	u32 doorbell_offset, doorbell;
492 	u32 rb_cntl, ib_cntl;
493 	int i;
494 
495 	for_each_inst(i, inst_mask) {
496 		sdma[i] = &adev->sdma.instance[i].ring;
497 
498 		rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
499 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
500 		WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
501 		ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
502 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
503 		WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
504 
505 		if (sdma[i]->use_doorbell) {
506 			doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
507 			doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
508 
509 			doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
510 			doorbell_offset = REG_SET_FIELD(doorbell_offset,
511 					SDMA_GFX_DOORBELL_OFFSET,
512 					OFFSET, 0);
513 			WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
514 			WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
515 		}
516 	}
517 }
518 
519 /**
520  * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
521  *
522  * @adev: amdgpu_device pointer
523  * @inst_mask: mask of dma engine instances to be disabled
524  *
525  * Stop the compute async dma queues.
526  */
sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device * adev,uint32_t inst_mask)527 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
528 				      uint32_t inst_mask)
529 {
530 	/* XXX todo */
531 }
532 
533 /**
534  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
535  *
536  * @adev: amdgpu_device pointer
537  * @inst_mask: mask of dma engine instances to be disabled
538  *
539  * Stop the page async dma ring buffers.
540  */
sdma_v4_4_2_inst_page_stop(struct amdgpu_device * adev,uint32_t inst_mask)541 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
542 				       uint32_t inst_mask)
543 {
544 	u32 rb_cntl, ib_cntl;
545 	int i;
546 
547 	for_each_inst(i, inst_mask) {
548 		rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
549 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
550 					RB_ENABLE, 0);
551 		WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
552 		ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
553 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
554 					IB_ENABLE, 0);
555 		WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
556 	}
557 }
558 
559 /**
560  * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
561  *
562  * @adev: amdgpu_device pointer
563  * @enable: enable/disable the DMA MEs context switch.
564  * @inst_mask: mask of dma engine instances to be enabled
565  *
566  * Halt or unhalt the async dma engines context switch.
567  */
sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)568 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
569 					       bool enable, uint32_t inst_mask)
570 {
571 	u32 f32_cntl, phase_quantum = 0;
572 	int i;
573 
574 	if (amdgpu_sdma_phase_quantum) {
575 		unsigned value = amdgpu_sdma_phase_quantum;
576 		unsigned unit = 0;
577 
578 		while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
579 				SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
580 			value = (value + 1) >> 1;
581 			unit++;
582 		}
583 		if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
584 			    SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
585 			value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
586 				 SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
587 			unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
588 				SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
589 			WARN_ONCE(1,
590 			"clamping sdma_phase_quantum to %uK clock cycles\n",
591 				  value << unit);
592 		}
593 		phase_quantum =
594 			value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
595 			unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
596 	}
597 
598 	for_each_inst(i, inst_mask) {
599 		f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
600 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
601 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
602 		if (enable && amdgpu_sdma_phase_quantum) {
603 			WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
604 			WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
605 			WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
606 		}
607 		WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
608 
609 		/* Extend page fault timeout to avoid interrupt storm */
610 		WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
611 	}
612 }
613 
614 /**
615  * sdma_v4_4_2_inst_enable - stop the async dma engines
616  *
617  * @adev: amdgpu_device pointer
618  * @enable: enable/disable the DMA MEs.
619  * @inst_mask: mask of dma engine instances to be enabled
620  *
621  * Halt or unhalt the async dma engines.
622  */
sdma_v4_4_2_inst_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)623 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
624 				    uint32_t inst_mask)
625 {
626 	u32 f32_cntl;
627 	int i;
628 
629 	if (!enable) {
630 		sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
631 		sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
632 		if (adev->sdma.has_page_queue)
633 			sdma_v4_4_2_inst_page_stop(adev, inst_mask);
634 
635 		/* SDMA FW needs to respond to FREEZE requests during reset.
636 		 * Keep it running during reset */
637 		if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
638 			return;
639 	}
640 
641 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
642 		return;
643 
644 	for_each_inst(i, inst_mask) {
645 		f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
646 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
647 		WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
648 	}
649 }
650 
651 /*
652  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
653  */
sdma_v4_4_2_rb_cntl(struct amdgpu_ring * ring,uint32_t rb_cntl)654 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
655 {
656 	/* Set ring buffer size in dwords */
657 	uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
658 
659 	barrier(); /* work around https://llvm.org/pr42576 */
660 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
661 #ifdef __BIG_ENDIAN
662 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
663 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
664 				RPTR_WRITEBACK_SWAP_ENABLE, 1);
665 #endif
666 	return rb_cntl;
667 }
668 
669 /**
670  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
671  *
672  * @adev: amdgpu_device pointer
673  * @i: instance to resume
674  * @restore: used to restore wptr when restart
675  *
676  * Set up the gfx DMA ring buffers and enable them.
677  * Returns 0 for success, error for failure.
678  */
sdma_v4_4_2_gfx_resume(struct amdgpu_device * adev,unsigned int i,bool restore)679 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
680 {
681 	struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
682 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
683 	u32 wb_offset;
684 	u32 doorbell;
685 	u32 doorbell_offset;
686 	u64 wptr_gpu_addr;
687 	u64 rwptr;
688 
689 	wb_offset = (ring->rptr_offs * 4);
690 
691 	rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
692 	rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
693 	WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
694 
695 	/* set the wb address whether it's enabled or not */
696 	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
697 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
698 	WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
699 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
700 
701 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
702 				RPTR_WRITEBACK_ENABLE, 1);
703 
704 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
705 	WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
706 
707 	if (!restore)
708 		ring->wptr = 0;
709 
710 	/* before programing wptr to a less value, need set minor_ptr_update first */
711 	WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
712 
713 	/* For the guilty queue, set RPTR to the current wptr to skip bad commands,
714 	 * It is not a guilty queue, restore cache_rptr and continue execution.
715 	 */
716 	if (adev->sdma.instance[i].gfx_guilty)
717 		rwptr = ring->wptr;
718 	else
719 		rwptr = ring->cached_rptr;
720 
721 	/* Initialize the ring buffer's read and write pointers */
722 	if (restore) {
723 		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, lower_32_bits(rwptr << 2));
724 		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, upper_32_bits(rwptr << 2));
725 		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, lower_32_bits(rwptr << 2));
726 		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, upper_32_bits(rwptr << 2));
727 	} else {
728 		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
729 		WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
730 		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
731 		WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
732 	}
733 
734 	doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
735 	doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
736 
737 	doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
738 				 ring->use_doorbell);
739 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
740 					SDMA_GFX_DOORBELL_OFFSET,
741 					OFFSET, ring->doorbell_index);
742 	WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
743 	WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
744 
745 	sdma_v4_4_2_ring_set_wptr(ring);
746 
747 	/* set minor_ptr_update to 0 after wptr programed */
748 	WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
749 
750 	/* setup the wptr shadow polling */
751 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
752 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
753 		    lower_32_bits(wptr_gpu_addr));
754 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
755 		    upper_32_bits(wptr_gpu_addr));
756 	wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
757 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
758 				       SDMA_GFX_RB_WPTR_POLL_CNTL,
759 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
760 	WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
761 
762 	/* enable DMA RB */
763 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
764 	WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
765 
766 	ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
767 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
768 #ifdef __BIG_ENDIAN
769 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
770 #endif
771 	/* enable DMA IBs */
772 	WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
773 }
774 
775 /**
776  * sdma_v4_4_2_page_resume - setup and start the async dma engines
777  *
778  * @adev: amdgpu_device pointer
779  * @i: instance to resume
780  * @restore: boolean to say restore needed or not
781  *
782  * Set up the page DMA ring buffers and enable them.
783  * Returns 0 for success, error for failure.
784  */
sdma_v4_4_2_page_resume(struct amdgpu_device * adev,unsigned int i,bool restore)785 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i, bool restore)
786 {
787 	struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
788 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
789 	u32 wb_offset;
790 	u32 doorbell;
791 	u32 doorbell_offset;
792 	u64 wptr_gpu_addr;
793 	u64 rwptr;
794 
795 	wb_offset = (ring->rptr_offs * 4);
796 
797 	rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
798 	rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
799 	WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
800 
801 	/* For the guilty queue, set RPTR to the current wptr to skip bad commands,
802 	 * It is not a guilty queue, restore cache_rptr and continue execution.
803 	 */
804 	if (adev->sdma.instance[i].page_guilty)
805 		rwptr = ring->wptr;
806 	else
807 		rwptr = ring->cached_rptr;
808 
809 	/* Initialize the ring buffer's read and write pointers */
810 	if (restore) {
811 		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, lower_32_bits(rwptr << 2));
812 		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, upper_32_bits(rwptr << 2));
813 		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, lower_32_bits(rwptr << 2));
814 		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, upper_32_bits(rwptr << 2));
815 	} else {
816 		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
817 		WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
818 		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
819 		WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
820 	}
821 
822 	/* set the wb address whether it's enabled or not */
823 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
824 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
825 	WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
826 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
827 
828 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
829 				RPTR_WRITEBACK_ENABLE, 1);
830 
831 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
832 	WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
833 
834 	if (!restore)
835 		ring->wptr = 0;
836 
837 	/* before programing wptr to a less value, need set minor_ptr_update first */
838 	WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
839 
840 	doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
841 	doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
842 
843 	doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
844 				 ring->use_doorbell);
845 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
846 					SDMA_PAGE_DOORBELL_OFFSET,
847 					OFFSET, ring->doorbell_index);
848 	WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
849 	WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
850 
851 	/* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
852 	sdma_v4_4_2_page_ring_set_wptr(ring);
853 
854 	/* set minor_ptr_update to 0 after wptr programed */
855 	WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
856 
857 	/* setup the wptr shadow polling */
858 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
859 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
860 		    lower_32_bits(wptr_gpu_addr));
861 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
862 		    upper_32_bits(wptr_gpu_addr));
863 	wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
864 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
865 				       SDMA_PAGE_RB_WPTR_POLL_CNTL,
866 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
867 	WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
868 
869 	/* enable DMA RB */
870 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
871 	WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
872 
873 	ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
874 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
875 #ifdef __BIG_ENDIAN
876 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
877 #endif
878 	/* enable DMA IBs */
879 	WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
880 }
881 
sdma_v4_4_2_init_pg(struct amdgpu_device * adev)882 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
883 {
884 
885 }
886 
887 /**
888  * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
889  *
890  * @adev: amdgpu_device pointer
891  * @inst_mask: mask of dma engine instances to be enabled
892  *
893  * Set up the compute DMA queues and enable them.
894  * Returns 0 for success, error for failure.
895  */
sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device * adev,uint32_t inst_mask)896 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
897 				       uint32_t inst_mask)
898 {
899 	sdma_v4_4_2_init_pg(adev);
900 
901 	return 0;
902 }
903 
904 /**
905  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
906  *
907  * @adev: amdgpu_device pointer
908  * @inst_mask: mask of dma engine instances to be enabled
909  *
910  * Loads the sDMA0/1 ucode.
911  * Returns 0 for success, -EINVAL if the ucode is not available.
912  */
sdma_v4_4_2_inst_load_microcode(struct amdgpu_device * adev,uint32_t inst_mask)913 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
914 					   uint32_t inst_mask)
915 {
916 	const struct sdma_firmware_header_v1_0 *hdr;
917 	const __le32 *fw_data;
918 	u32 fw_size;
919 	int i, j;
920 
921 	/* halt the MEs */
922 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
923 
924 	for_each_inst(i, inst_mask) {
925 		if (!adev->sdma.instance[i].fw)
926 			return -EINVAL;
927 
928 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
929 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
930 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
931 
932 		fw_data = (const __le32 *)
933 			(adev->sdma.instance[i].fw->data +
934 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
935 
936 		WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
937 
938 		for (j = 0; j < fw_size; j++)
939 			WREG32_SDMA(i, regSDMA_UCODE_DATA,
940 				    le32_to_cpup(fw_data++));
941 
942 		WREG32_SDMA(i, regSDMA_UCODE_ADDR,
943 			    adev->sdma.instance[i].fw_version);
944 	}
945 
946 	return 0;
947 }
948 
949 /**
950  * sdma_v4_4_2_inst_start - setup and start the async dma engines
951  *
952  * @adev: amdgpu_device pointer
953  * @inst_mask: mask of dma engine instances to be enabled
954  * @restore: boolean to say restore needed or not
955  *
956  * Set up the DMA engines and enable them.
957  * Returns 0 for success, error for failure.
958  */
sdma_v4_4_2_inst_start(struct amdgpu_device * adev,uint32_t inst_mask,bool restore)959 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
960 				  uint32_t inst_mask, bool restore)
961 {
962 	struct amdgpu_ring *ring;
963 	uint32_t tmp_mask;
964 	int i, r = 0;
965 
966 	if (amdgpu_sriov_vf(adev)) {
967 		sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
968 		sdma_v4_4_2_inst_enable(adev, false, inst_mask);
969 	} else {
970 		/* bypass sdma microcode loading on Gopher */
971 		if (!restore && adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
972 		    adev->sdma.instance[0].fw) {
973 			r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
974 			if (r)
975 				return r;
976 		}
977 
978 		/* unhalt the MEs */
979 		sdma_v4_4_2_inst_enable(adev, true, inst_mask);
980 		/* enable sdma ring preemption */
981 		sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
982 	}
983 
984 	/* start the gfx rings and rlc compute queues */
985 	tmp_mask = inst_mask;
986 	for_each_inst(i, tmp_mask) {
987 		uint32_t temp;
988 
989 		WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
990 		sdma_v4_4_2_gfx_resume(adev, i, restore);
991 		if (adev->sdma.has_page_queue)
992 			sdma_v4_4_2_page_resume(adev, i, restore);
993 
994 		/* set utc l1 enable flag always to 1 */
995 		temp = RREG32_SDMA(i, regSDMA_CNTL);
996 		temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
997 
998 		if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(4, 4, 5)) {
999 			/* enable context empty interrupt during initialization */
1000 			temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
1001 			WREG32_SDMA(i, regSDMA_CNTL, temp);
1002 		}
1003 		if (!amdgpu_sriov_vf(adev)) {
1004 			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1005 				/* unhalt engine */
1006 				temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
1007 				temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
1008 				WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
1009 			}
1010 		}
1011 	}
1012 
1013 	if (amdgpu_sriov_vf(adev)) {
1014 		sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
1015 		sdma_v4_4_2_inst_enable(adev, true, inst_mask);
1016 	} else {
1017 		r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
1018 		if (r)
1019 			return r;
1020 	}
1021 
1022 	tmp_mask = inst_mask;
1023 	for_each_inst(i, tmp_mask) {
1024 		ring = &adev->sdma.instance[i].ring;
1025 
1026 		r = amdgpu_ring_test_helper(ring);
1027 		if (r)
1028 			return r;
1029 
1030 		if (adev->sdma.has_page_queue) {
1031 			struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1032 
1033 			r = amdgpu_ring_test_helper(page);
1034 			if (r)
1035 				return r;
1036 		}
1037 	}
1038 
1039 	return r;
1040 }
1041 
1042 /**
1043  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
1044  *
1045  * @ring: amdgpu_ring structure holding ring information
1046  *
1047  * Test the DMA engine by writing using it to write an
1048  * value to memory.
1049  * Returns 0 for success, error for failure.
1050  */
sdma_v4_4_2_ring_test_ring(struct amdgpu_ring * ring)1051 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
1052 {
1053 	struct amdgpu_device *adev = ring->adev;
1054 	unsigned i;
1055 	unsigned index;
1056 	int r;
1057 	u32 tmp;
1058 	u64 gpu_addr;
1059 
1060 	r = amdgpu_device_wb_get(adev, &index);
1061 	if (r)
1062 		return r;
1063 
1064 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1065 	tmp = 0xCAFEDEAD;
1066 	adev->wb.wb[index] = cpu_to_le32(tmp);
1067 
1068 	r = amdgpu_ring_alloc(ring, 5);
1069 	if (r)
1070 		goto error_free_wb;
1071 
1072 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1073 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1074 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1075 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1076 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1077 	amdgpu_ring_write(ring, 0xDEADBEEF);
1078 	amdgpu_ring_commit(ring);
1079 
1080 	for (i = 0; i < adev->usec_timeout; i++) {
1081 		tmp = le32_to_cpu(adev->wb.wb[index]);
1082 		if (tmp == 0xDEADBEEF)
1083 			break;
1084 		udelay(1);
1085 	}
1086 
1087 	if (i >= adev->usec_timeout)
1088 		r = -ETIMEDOUT;
1089 
1090 error_free_wb:
1091 	amdgpu_device_wb_free(adev, index);
1092 	return r;
1093 }
1094 
1095 /**
1096  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1097  *
1098  * @ring: amdgpu_ring structure holding ring information
1099  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1100  *
1101  * Test a simple IB in the DMA ring.
1102  * Returns 0 on success, error on failure.
1103  */
sdma_v4_4_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)1104 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1105 {
1106 	struct amdgpu_device *adev = ring->adev;
1107 	struct amdgpu_ib ib;
1108 	struct dma_fence *f = NULL;
1109 	unsigned index;
1110 	long r;
1111 	u32 tmp = 0;
1112 	u64 gpu_addr;
1113 
1114 	r = amdgpu_device_wb_get(adev, &index);
1115 	if (r)
1116 		return r;
1117 
1118 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1119 	tmp = 0xCAFEDEAD;
1120 	adev->wb.wb[index] = cpu_to_le32(tmp);
1121 	memset(&ib, 0, sizeof(ib));
1122 	r = amdgpu_ib_get(adev, NULL, 256,
1123 					AMDGPU_IB_POOL_DIRECT, &ib);
1124 	if (r)
1125 		goto err0;
1126 
1127 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1128 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1129 	ib.ptr[1] = lower_32_bits(gpu_addr);
1130 	ib.ptr[2] = upper_32_bits(gpu_addr);
1131 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1132 	ib.ptr[4] = 0xDEADBEEF;
1133 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1134 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1135 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1136 	ib.length_dw = 8;
1137 
1138 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1139 	if (r)
1140 		goto err1;
1141 
1142 	r = dma_fence_wait_timeout(f, false, timeout);
1143 	if (r == 0) {
1144 		r = -ETIMEDOUT;
1145 		goto err1;
1146 	} else if (r < 0) {
1147 		goto err1;
1148 	}
1149 	tmp = le32_to_cpu(adev->wb.wb[index]);
1150 	if (tmp == 0xDEADBEEF)
1151 		r = 0;
1152 	else
1153 		r = -EINVAL;
1154 
1155 err1:
1156 	amdgpu_ib_free(&ib, NULL);
1157 	dma_fence_put(f);
1158 err0:
1159 	amdgpu_device_wb_free(adev, index);
1160 	return r;
1161 }
1162 
1163 
1164 /**
1165  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1166  *
1167  * @ib: indirect buffer to fill with commands
1168  * @pe: addr of the page entry
1169  * @src: src addr to copy from
1170  * @count: number of page entries to update
1171  *
1172  * Update PTEs by copying them from the GART using sDMA.
1173  */
sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1174 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1175 				  uint64_t pe, uint64_t src,
1176 				  unsigned count)
1177 {
1178 	unsigned bytes = count * 8;
1179 
1180 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1181 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1182 	ib->ptr[ib->length_dw++] = bytes - 1;
1183 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1184 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1185 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1186 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1187 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1188 
1189 }
1190 
1191 /**
1192  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1193  *
1194  * @ib: indirect buffer to fill with commands
1195  * @pe: addr of the page entry
1196  * @value: dst addr to write into pe
1197  * @count: number of page entries to update
1198  * @incr: increase next addr by incr bytes
1199  *
1200  * Update PTEs by writing them manually using sDMA.
1201  */
sdma_v4_4_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1202 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1203 				   uint64_t value, unsigned count,
1204 				   uint32_t incr)
1205 {
1206 	unsigned ndw = count * 2;
1207 
1208 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1209 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1210 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1211 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1212 	ib->ptr[ib->length_dw++] = ndw - 1;
1213 	for (; ndw > 0; ndw -= 2) {
1214 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1215 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1216 		value += incr;
1217 	}
1218 }
1219 
1220 /**
1221  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1222  *
1223  * @ib: indirect buffer to fill with commands
1224  * @pe: addr of the page entry
1225  * @addr: dst addr to write into pe
1226  * @count: number of page entries to update
1227  * @incr: increase next addr by incr bytes
1228  * @flags: access flags
1229  *
1230  * Update the page tables using sDMA.
1231  */
sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1232 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1233 				     uint64_t pe,
1234 				     uint64_t addr, unsigned count,
1235 				     uint32_t incr, uint64_t flags)
1236 {
1237 	/* for physically contiguous pages (vram) */
1238 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1239 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1240 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1241 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1242 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1243 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1244 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1245 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1246 	ib->ptr[ib->length_dw++] = 0;
1247 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1248 }
1249 
1250 /**
1251  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1252  *
1253  * @ring: amdgpu_ring structure holding ring information
1254  * @ib: indirect buffer to fill with padding
1255  */
sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1256 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1257 {
1258 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1259 	u32 pad_count;
1260 	int i;
1261 
1262 	pad_count = (-ib->length_dw) & 7;
1263 	for (i = 0; i < pad_count; i++)
1264 		if (sdma && sdma->burst_nop && (i == 0))
1265 			ib->ptr[ib->length_dw++] =
1266 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1267 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1268 		else
1269 			ib->ptr[ib->length_dw++] =
1270 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1271 }
1272 
1273 
1274 /**
1275  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1276  *
1277  * @ring: amdgpu_ring pointer
1278  *
1279  * Make sure all previous operations are completed (CIK).
1280  */
sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1281 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1282 {
1283 	uint32_t seq = ring->fence_drv.sync_seq;
1284 	uint64_t addr = ring->fence_drv.gpu_addr;
1285 
1286 	/* wait for idle */
1287 	sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1288 			       addr & 0xfffffffc,
1289 			       upper_32_bits(addr) & 0xffffffff,
1290 			       seq, 0xffffffff, 4);
1291 }
1292 
1293 
1294 /**
1295  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1296  *
1297  * @ring: amdgpu_ring pointer
1298  * @vmid: vmid number to use
1299  * @pd_addr: address
1300  *
1301  * Update the page table base and flush the VM TLB
1302  * using sDMA.
1303  */
sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1304 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1305 					 unsigned vmid, uint64_t pd_addr)
1306 {
1307 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1308 }
1309 
sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1310 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1311 				     uint32_t reg, uint32_t val)
1312 {
1313 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1314 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1315 	amdgpu_ring_write(ring, reg);
1316 	amdgpu_ring_write(ring, val);
1317 }
1318 
sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1319 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1320 					 uint32_t val, uint32_t mask)
1321 {
1322 	sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1323 }
1324 
sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device * adev)1325 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1326 {
1327 	switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1328 	case IP_VERSION(4, 4, 2):
1329 	case IP_VERSION(4, 4, 5):
1330 		return false;
1331 	default:
1332 		return false;
1333 	}
1334 }
1335 
sdma_v4_4_2_early_init(struct amdgpu_ip_block * ip_block)1336 static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
1337 {
1338 	struct amdgpu_device *adev = ip_block->adev;
1339 	int r;
1340 
1341 	r = sdma_v4_4_2_init_microcode(adev);
1342 	if (r)
1343 		return r;
1344 
1345 	/* TODO: Page queue breaks driver reload under SRIOV */
1346 	if (sdma_v4_4_2_fw_support_paging_queue(adev))
1347 		adev->sdma.has_page_queue = true;
1348 
1349 	sdma_v4_4_2_set_ring_funcs(adev);
1350 	sdma_v4_4_2_set_buffer_funcs(adev);
1351 	sdma_v4_4_2_set_vm_pte_funcs(adev);
1352 	sdma_v4_4_2_set_irq_funcs(adev);
1353 	sdma_v4_4_2_set_ras_funcs(adev);
1354 	sdma_v4_4_2_set_engine_reset_funcs(adev);
1355 
1356 	return 0;
1357 }
1358 
1359 #if 0
1360 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1361 		void *err_data,
1362 		struct amdgpu_iv_entry *entry);
1363 #endif
1364 
sdma_v4_4_2_late_init(struct amdgpu_ip_block * ip_block)1365 static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block)
1366 {
1367 	struct amdgpu_device *adev = ip_block->adev;
1368 #if 0
1369 	struct ras_ih_if ih_info = {
1370 		.cb = sdma_v4_4_2_process_ras_data_cb,
1371 	};
1372 #endif
1373 	if (!amdgpu_persistent_edc_harvesting_supported(adev))
1374 		amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1375 
1376 	/* The initialization is done in the late_init stage to ensure that the SMU
1377 	 * initialization and capability setup are completed before we check the SDMA
1378 	 * reset capability
1379 	 */
1380 	sdma_v4_4_2_update_reset_mask(adev);
1381 
1382 	return 0;
1383 }
1384 
sdma_v4_4_2_sw_init(struct amdgpu_ip_block * ip_block)1385 static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block)
1386 {
1387 	struct amdgpu_ring *ring;
1388 	int r, i;
1389 	struct amdgpu_device *adev = ip_block->adev;
1390 	u32 aid_id;
1391 	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
1392 	uint32_t *ptr;
1393 
1394 	/* SDMA trap event */
1395 	for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1396 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1397 				      SDMA0_4_0__SRCID__SDMA_TRAP,
1398 				      &adev->sdma.trap_irq);
1399 		if (r)
1400 			return r;
1401 	}
1402 
1403 	/* SDMA SRAM ECC event */
1404 	for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1405 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1406 				      SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1407 				      &adev->sdma.ecc_irq);
1408 		if (r)
1409 			return r;
1410 	}
1411 
1412 	/* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1413 	for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1414 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1415 				      SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1416 				      &adev->sdma.vm_hole_irq);
1417 		if (r)
1418 			return r;
1419 
1420 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1421 				      SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1422 				      &adev->sdma.doorbell_invalid_irq);
1423 		if (r)
1424 			return r;
1425 
1426 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1427 				      SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1428 				      &adev->sdma.pool_timeout_irq);
1429 		if (r)
1430 			return r;
1431 
1432 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1433 				      SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1434 				      &adev->sdma.srbm_write_irq);
1435 		if (r)
1436 			return r;
1437 
1438 		r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1439 				      SDMA0_4_0__SRCID__SDMA_CTXEMPTY,
1440 				      &adev->sdma.ctxt_empty_irq);
1441 		if (r)
1442 			return r;
1443 	}
1444 
1445 	for (i = 0; i < adev->sdma.num_instances; i++) {
1446 		mutex_init(&adev->sdma.instance[i].engine_reset_mutex);
1447 		/* Initialize guilty flags for GFX and PAGE queues */
1448 		adev->sdma.instance[i].gfx_guilty = false;
1449 		adev->sdma.instance[i].page_guilty = false;
1450 
1451 		ring = &adev->sdma.instance[i].ring;
1452 		ring->ring_obj = NULL;
1453 		ring->use_doorbell = true;
1454 		aid_id = adev->sdma.instance[i].aid_id;
1455 
1456 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1457 				ring->use_doorbell?"true":"false");
1458 
1459 		/* doorbell size is 2 dwords, get DWORD offset */
1460 		ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1461 		ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1462 
1463 		sprintf(ring->name, "sdma%d.%d", aid_id,
1464 				i % adev->sdma.num_inst_per_aid);
1465 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1466 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1467 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1468 		if (r)
1469 			return r;
1470 
1471 		if (adev->sdma.has_page_queue) {
1472 			ring = &adev->sdma.instance[i].page;
1473 			ring->ring_obj = NULL;
1474 			ring->use_doorbell = true;
1475 
1476 			/* doorbell index of page queue is assigned right after
1477 			 * gfx queue on the same instance
1478 			 */
1479 			ring->doorbell_index =
1480 				(adev->doorbell_index.sdma_engine[i] + 1) << 1;
1481 			ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1482 
1483 			sprintf(ring->name, "page%d.%d", aid_id,
1484 					i % adev->sdma.num_inst_per_aid);
1485 			r = amdgpu_ring_init(adev, ring, 1024,
1486 					     &adev->sdma.trap_irq,
1487 					     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1488 					     AMDGPU_RING_PRIO_DEFAULT, NULL);
1489 			if (r)
1490 				return r;
1491 		}
1492 	}
1493 
1494 	adev->sdma.supported_reset =
1495 		amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
1496 
1497 	if (amdgpu_sdma_ras_sw_init(adev)) {
1498 		dev_err(adev->dev, "fail to initialize sdma ras block\n");
1499 		return -EINVAL;
1500 	}
1501 
1502 	/* Allocate memory for SDMA IP Dump buffer */
1503 	ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1504 	if (ptr)
1505 		adev->sdma.ip_dump = ptr;
1506 	else
1507 		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1508 
1509 	r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1510 	if (r)
1511 		return r;
1512 
1513 	return r;
1514 }
1515 
sdma_v4_4_2_sw_fini(struct amdgpu_ip_block * ip_block)1516 static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block)
1517 {
1518 	struct amdgpu_device *adev = ip_block->adev;
1519 	int i;
1520 
1521 	for (i = 0; i < adev->sdma.num_instances; i++) {
1522 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1523 		if (adev->sdma.has_page_queue)
1524 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
1525 	}
1526 
1527 	amdgpu_sdma_sysfs_reset_mask_fini(adev);
1528 	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
1529 	    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 4) ||
1530 	    amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5))
1531 		amdgpu_sdma_destroy_inst_ctx(adev, true);
1532 	else
1533 		amdgpu_sdma_destroy_inst_ctx(adev, false);
1534 
1535 	kfree(adev->sdma.ip_dump);
1536 
1537 	return 0;
1538 }
1539 
sdma_v4_4_2_hw_init(struct amdgpu_ip_block * ip_block)1540 static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block)
1541 {
1542 	int r;
1543 	struct amdgpu_device *adev = ip_block->adev;
1544 	uint32_t inst_mask;
1545 
1546 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1547 	if (!amdgpu_sriov_vf(adev))
1548 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1549 
1550 	r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
1551 
1552 	return r;
1553 }
1554 
sdma_v4_4_2_hw_fini(struct amdgpu_ip_block * ip_block)1555 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
1556 {
1557 	struct amdgpu_device *adev = ip_block->adev;
1558 	uint32_t inst_mask;
1559 	int i;
1560 
1561 	if (amdgpu_sriov_vf(adev))
1562 		return 0;
1563 
1564 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1565 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1566 		for (i = 0; i < adev->sdma.num_instances; i++) {
1567 			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1568 				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1569 		}
1570 	}
1571 
1572 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1573 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1574 
1575 	return 0;
1576 }
1577 
1578 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1579 					     enum amd_clockgating_state state);
1580 
sdma_v4_4_2_suspend(struct amdgpu_ip_block * ip_block)1581 static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block)
1582 {
1583 	struct amdgpu_device *adev = ip_block->adev;
1584 
1585 	if (amdgpu_in_reset(adev))
1586 		sdma_v4_4_2_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE);
1587 
1588 	return sdma_v4_4_2_hw_fini(ip_block);
1589 }
1590 
sdma_v4_4_2_resume(struct amdgpu_ip_block * ip_block)1591 static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)
1592 {
1593 	return sdma_v4_4_2_hw_init(ip_block);
1594 }
1595 
sdma_v4_4_2_is_idle(struct amdgpu_ip_block * ip_block)1596 static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
1597 {
1598 	struct amdgpu_device *adev = ip_block->adev;
1599 	u32 i;
1600 
1601 	for (i = 0; i < adev->sdma.num_instances; i++) {
1602 		u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1603 
1604 		if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1605 			return false;
1606 	}
1607 
1608 	return true;
1609 }
1610 
sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block * ip_block)1611 static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
1612 {
1613 	unsigned i, j;
1614 	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1615 	struct amdgpu_device *adev = ip_block->adev;
1616 
1617 	for (i = 0; i < adev->usec_timeout; i++) {
1618 		for (j = 0; j < adev->sdma.num_instances; j++) {
1619 			sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1620 			if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1621 				break;
1622 		}
1623 		if (j == adev->sdma.num_instances)
1624 			return 0;
1625 		udelay(1);
1626 	}
1627 	return -ETIMEDOUT;
1628 }
1629 
sdma_v4_4_2_soft_reset(struct amdgpu_ip_block * ip_block)1630 static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block)
1631 {
1632 	/* todo */
1633 
1634 	return 0;
1635 }
1636 
sdma_v4_4_2_is_queue_selected(struct amdgpu_device * adev,uint32_t instance_id,bool is_page_queue)1637 static bool sdma_v4_4_2_is_queue_selected(struct amdgpu_device *adev, uint32_t instance_id, bool is_page_queue)
1638 {
1639 	uint32_t reg_offset = is_page_queue ? regSDMA_PAGE_CONTEXT_STATUS : regSDMA_GFX_CONTEXT_STATUS;
1640 	uint32_t context_status = RREG32(sdma_v4_4_2_get_reg_offset(adev, instance_id, reg_offset));
1641 
1642 	/* Check if the SELECTED bit is set */
1643 	return (context_status & SDMA_GFX_CONTEXT_STATUS__SELECTED_MASK) != 0;
1644 }
1645 
sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring * ring)1646 static bool sdma_v4_4_2_ring_is_guilty(struct amdgpu_ring *ring)
1647 {
1648 	struct amdgpu_device *adev = ring->adev;
1649 	uint32_t instance_id = ring->me;
1650 
1651 	return sdma_v4_4_2_is_queue_selected(adev, instance_id, false);
1652 }
1653 
sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring * ring)1654 static bool sdma_v4_4_2_page_ring_is_guilty(struct amdgpu_ring *ring)
1655 {
1656 	struct amdgpu_device *adev = ring->adev;
1657 	uint32_t instance_id = ring->me;
1658 
1659 	if (!adev->sdma.has_page_queue)
1660 		return false;
1661 
1662 	return sdma_v4_4_2_is_queue_selected(adev, instance_id, true);
1663 }
1664 
sdma_v4_4_2_reset_queue(struct amdgpu_ring * ring,unsigned int vmid)1665 static int sdma_v4_4_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
1666 {
1667 	struct amdgpu_device *adev = ring->adev;
1668 	u32 id = GET_INST(SDMA0, ring->me);
1669 	int r;
1670 
1671 	if (!(adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
1672 		return -EOPNOTSUPP;
1673 
1674 	amdgpu_amdkfd_suspend(adev, false);
1675 	r = amdgpu_sdma_reset_engine(adev, id);
1676 	amdgpu_amdkfd_resume(adev, false);
1677 
1678 	return r;
1679 }
1680 
sdma_v4_4_2_stop_queue(struct amdgpu_device * adev,uint32_t instance_id)1681 static int sdma_v4_4_2_stop_queue(struct amdgpu_device *adev, uint32_t instance_id)
1682 {
1683 	u32 inst_mask;
1684 	uint64_t rptr;
1685 	struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring;
1686 
1687 	if (amdgpu_sriov_vf(adev))
1688 		return -EINVAL;
1689 
1690 	/* Check if this queue is the guilty one */
1691 	adev->sdma.instance[instance_id].gfx_guilty =
1692 		sdma_v4_4_2_is_queue_selected(adev, instance_id, false);
1693 	if (adev->sdma.has_page_queue)
1694 		adev->sdma.instance[instance_id].page_guilty =
1695 			sdma_v4_4_2_is_queue_selected(adev, instance_id, true);
1696 
1697 	/* Cache the rptr before reset, after the reset,
1698 	* all of the registers will be reset to 0
1699 	*/
1700 	rptr = amdgpu_ring_get_rptr(ring);
1701 	ring->cached_rptr = rptr;
1702 	/* Cache the rptr for the page queue if it exists */
1703 	if (adev->sdma.has_page_queue) {
1704 		struct amdgpu_ring *page_ring = &adev->sdma.instance[instance_id].page;
1705 		rptr = amdgpu_ring_get_rptr(page_ring);
1706 		page_ring->cached_rptr = rptr;
1707 	}
1708 
1709 	/* stop queue */
1710 	inst_mask = 1 << ring->me;
1711 	sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
1712 	if (adev->sdma.has_page_queue)
1713 		sdma_v4_4_2_inst_page_stop(adev, inst_mask);
1714 
1715 	return 0;
1716 }
1717 
sdma_v4_4_2_restore_queue(struct amdgpu_device * adev,uint32_t instance_id)1718 static int sdma_v4_4_2_restore_queue(struct amdgpu_device *adev, uint32_t instance_id)
1719 {
1720 	int i;
1721 	u32 inst_mask;
1722 	struct amdgpu_ring *ring = &adev->sdma.instance[instance_id].ring;
1723 
1724 	inst_mask = 1 << ring->me;
1725 	udelay(50);
1726 
1727 	for (i = 0; i < adev->usec_timeout; i++) {
1728 		if (!REG_GET_FIELD(RREG32_SDMA(ring->me, regSDMA_F32_CNTL), SDMA_F32_CNTL, HALT))
1729 			break;
1730 		udelay(1);
1731 	}
1732 
1733 	if (i == adev->usec_timeout) {
1734 		dev_err(adev->dev, "timed out waiting for SDMA%d unhalt after reset\n",
1735 			ring->me);
1736 		return -ETIMEDOUT;
1737 	}
1738 
1739 	return sdma_v4_4_2_inst_start(adev, inst_mask, true);
1740 }
1741 
1742 static struct sdma_on_reset_funcs sdma_v4_4_2_engine_reset_funcs = {
1743 	.pre_reset = sdma_v4_4_2_stop_queue,
1744 	.post_reset = sdma_v4_4_2_restore_queue,
1745 };
1746 
sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device * adev)1747 static void sdma_v4_4_2_set_engine_reset_funcs(struct amdgpu_device *adev)
1748 {
1749 	amdgpu_sdma_register_on_reset_callbacks(adev, &sdma_v4_4_2_engine_reset_funcs);
1750 }
1751 
sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1752 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1753 					struct amdgpu_irq_src *source,
1754 					unsigned type,
1755 					enum amdgpu_interrupt_state state)
1756 {
1757 	u32 sdma_cntl;
1758 
1759 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1760 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1761 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1762 	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1763 
1764 	return 0;
1765 }
1766 
sdma_v4_4_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1767 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1768 				      struct amdgpu_irq_src *source,
1769 				      struct amdgpu_iv_entry *entry)
1770 {
1771 	uint32_t instance, i;
1772 
1773 	DRM_DEBUG("IH: SDMA trap\n");
1774 	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1775 
1776 	/* Client id gives the SDMA instance in AID. To know the exact SDMA
1777 	 * instance, interrupt entry gives the node id which corresponds to the AID instance.
1778 	 * Match node id with the AID id associated with the SDMA instance. */
1779 	for (i = instance; i < adev->sdma.num_instances;
1780 	     i += adev->sdma.num_inst_per_aid) {
1781 		if (adev->sdma.instance[i].aid_id ==
1782 		    node_id_to_phys_map[entry->node_id])
1783 			break;
1784 	}
1785 
1786 	if (i >= adev->sdma.num_instances) {
1787 		dev_WARN_ONCE(
1788 			adev->dev, 1,
1789 			"Couldn't find the right sdma instance in trap handler");
1790 		return 0;
1791 	}
1792 
1793 	switch (entry->ring_id) {
1794 	case 0:
1795 		amdgpu_fence_process(&adev->sdma.instance[i].ring);
1796 		break;
1797 	case 1:
1798 		amdgpu_fence_process(&adev->sdma.instance[i].page);
1799 		break;
1800 	default:
1801 		break;
1802 	}
1803 	return 0;
1804 }
1805 
1806 #if 0
1807 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1808 		void *err_data,
1809 		struct amdgpu_iv_entry *entry)
1810 {
1811 	int instance;
1812 
1813 	/* When “Full RAS” is enabled, the per-IP interrupt sources should
1814 	 * be disabled and the driver should only look for the aggregated
1815 	 * interrupt via sync flood
1816 	 */
1817 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1818 		goto out;
1819 
1820 	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1821 	if (instance < 0)
1822 		goto out;
1823 
1824 	amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1825 
1826 out:
1827 	return AMDGPU_RAS_SUCCESS;
1828 }
1829 #endif
1830 
sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1831 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1832 					      struct amdgpu_irq_src *source,
1833 					      struct amdgpu_iv_entry *entry)
1834 {
1835 	int instance;
1836 
1837 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
1838 
1839 	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1840 	if (instance < 0)
1841 		return 0;
1842 
1843 	switch (entry->ring_id) {
1844 	case 0:
1845 		drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1846 		break;
1847 	}
1848 	return 0;
1849 }
1850 
sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1851 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1852 					struct amdgpu_irq_src *source,
1853 					unsigned type,
1854 					enum amdgpu_interrupt_state state)
1855 {
1856 	u32 sdma_cntl;
1857 
1858 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1859 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1860 					state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1861 	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1862 
1863 	return 0;
1864 }
1865 
sdma_v4_4_2_print_iv_entry(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)1866 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1867 					      struct amdgpu_iv_entry *entry)
1868 {
1869 	int instance;
1870 	struct amdgpu_task_info *task_info;
1871 	u64 addr;
1872 
1873 	instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1874 	if (instance < 0 || instance >= adev->sdma.num_instances) {
1875 		dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1876 		return -EINVAL;
1877 	}
1878 
1879 	addr = (u64)entry->src_data[0] << 12;
1880 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1881 
1882 	dev_dbg_ratelimited(adev->dev,
1883 			    "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1884 			    instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1885 			    entry->pasid);
1886 
1887 	task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1888 	if (task_info) {
1889 		dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1890 				    task_info->process_name, task_info->tgid,
1891 				    task_info->task_name, task_info->pid);
1892 		amdgpu_vm_put_task_info(task_info);
1893 	}
1894 
1895 	return 0;
1896 }
1897 
sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1898 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1899 					      struct amdgpu_irq_src *source,
1900 					      struct amdgpu_iv_entry *entry)
1901 {
1902 	dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1903 	sdma_v4_4_2_print_iv_entry(adev, entry);
1904 	return 0;
1905 }
1906 
sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1907 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1908 					      struct amdgpu_irq_src *source,
1909 					      struct amdgpu_iv_entry *entry)
1910 {
1911 
1912 	dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1913 	sdma_v4_4_2_print_iv_entry(adev, entry);
1914 	return 0;
1915 }
1916 
sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1917 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1918 					      struct amdgpu_irq_src *source,
1919 					      struct amdgpu_iv_entry *entry)
1920 {
1921 	dev_dbg_ratelimited(adev->dev,
1922 		"Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1923 	sdma_v4_4_2_print_iv_entry(adev, entry);
1924 	return 0;
1925 }
1926 
sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1927 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1928 					      struct amdgpu_irq_src *source,
1929 					      struct amdgpu_iv_entry *entry)
1930 {
1931 	dev_dbg_ratelimited(adev->dev,
1932 		"SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1933 	sdma_v4_4_2_print_iv_entry(adev, entry);
1934 	return 0;
1935 }
1936 
sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1937 static int sdma_v4_4_2_process_ctxt_empty_irq(struct amdgpu_device *adev,
1938 					      struct amdgpu_irq_src *source,
1939 					      struct amdgpu_iv_entry *entry)
1940 {
1941 	/* There is nothing useful to be done here, only kept for debug */
1942 	dev_dbg_ratelimited(adev->dev, "SDMA context empty interrupt");
1943 	sdma_v4_4_2_print_iv_entry(adev, entry);
1944 	return 0;
1945 }
1946 
sdma_v4_4_2_inst_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)1947 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1948 	struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1949 {
1950 	uint32_t data, def;
1951 	int i;
1952 
1953 	/* leave as default if it is not driver controlled */
1954 	if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1955 		return;
1956 
1957 	if (enable) {
1958 		for_each_inst(i, inst_mask) {
1959 			/* 1-not override: enable sdma mem light sleep */
1960 			def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1961 			data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1962 			if (def != data)
1963 				WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1964 		}
1965 	} else {
1966 		for_each_inst(i, inst_mask) {
1967 			/* 0-override:disable sdma mem light sleep */
1968 			def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1969 			data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1970 			if (def != data)
1971 				WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1972 		}
1973 	}
1974 }
1975 
sdma_v4_4_2_inst_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable,uint32_t inst_mask)1976 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1977 	struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1978 {
1979 	uint32_t data, def;
1980 	int i;
1981 
1982 	/* leave as default if it is not driver controlled */
1983 	if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1984 		return;
1985 
1986 	if (enable) {
1987 		for_each_inst(i, inst_mask) {
1988 			def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1989 			data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1990 				  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1991 				  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1992 				  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1993 				  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1994 				  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1995 			if (def != data)
1996 				WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1997 		}
1998 	} else {
1999 		for_each_inst(i, inst_mask) {
2000 			def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
2001 			data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2002 				 SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2003 				 SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2004 				 SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2005 				 SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2006 				 SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2007 			if (def != data)
2008 				WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
2009 		}
2010 	}
2011 }
2012 
sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2013 static int sdma_v4_4_2_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2014 					  enum amd_clockgating_state state)
2015 {
2016 	struct amdgpu_device *adev = ip_block->adev;
2017 	uint32_t inst_mask;
2018 
2019 	if (amdgpu_sriov_vf(adev))
2020 		return 0;
2021 
2022 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2023 
2024 	sdma_v4_4_2_inst_update_medium_grain_clock_gating(
2025 		adev, state == AMD_CG_STATE_GATE, inst_mask);
2026 	sdma_v4_4_2_inst_update_medium_grain_light_sleep(
2027 		adev, state == AMD_CG_STATE_GATE, inst_mask);
2028 	return 0;
2029 }
2030 
sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2031 static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
2032 					  enum amd_powergating_state state)
2033 {
2034 	return 0;
2035 }
2036 
sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)2037 static void sdma_v4_4_2_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
2038 {
2039 	struct amdgpu_device *adev = ip_block->adev;
2040 	int data;
2041 
2042 	if (amdgpu_sriov_vf(adev))
2043 		*flags = 0;
2044 
2045 	/* AMD_CG_SUPPORT_SDMA_MGCG */
2046 	data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
2047 	if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
2048 		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2049 
2050 	/* AMD_CG_SUPPORT_SDMA_LS */
2051 	data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
2052 	if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2053 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
2054 }
2055 
sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block * ip_block,struct drm_printer * p)2056 static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
2057 {
2058 	struct amdgpu_device *adev = ip_block->adev;
2059 	int i, j;
2060 	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
2061 	uint32_t instance_offset;
2062 
2063 	if (!adev->sdma.ip_dump)
2064 		return;
2065 
2066 	drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
2067 	for (i = 0; i < adev->sdma.num_instances; i++) {
2068 		instance_offset = i * reg_count;
2069 		drm_printf(p, "\nInstance:%d\n", i);
2070 
2071 		for (j = 0; j < reg_count; j++)
2072 			drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_4_4_2[j].reg_name,
2073 				   adev->sdma.ip_dump[instance_offset + j]);
2074 	}
2075 }
2076 
sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block * ip_block)2077 static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block)
2078 {
2079 	struct amdgpu_device *adev = ip_block->adev;
2080 	int i, j;
2081 	uint32_t instance_offset;
2082 	uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2);
2083 
2084 	if (!adev->sdma.ip_dump)
2085 		return;
2086 
2087 	for (i = 0; i < adev->sdma.num_instances; i++) {
2088 		instance_offset = i * reg_count;
2089 		for (j = 0; j < reg_count; j++)
2090 			adev->sdma.ip_dump[instance_offset + j] =
2091 				RREG32(sdma_v4_4_2_get_reg_offset(adev, i,
2092 				       sdma_reg_list_4_4_2[j].reg_offset));
2093 	}
2094 }
2095 
2096 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
2097 	.name = "sdma_v4_4_2",
2098 	.early_init = sdma_v4_4_2_early_init,
2099 	.late_init = sdma_v4_4_2_late_init,
2100 	.sw_init = sdma_v4_4_2_sw_init,
2101 	.sw_fini = sdma_v4_4_2_sw_fini,
2102 	.hw_init = sdma_v4_4_2_hw_init,
2103 	.hw_fini = sdma_v4_4_2_hw_fini,
2104 	.suspend = sdma_v4_4_2_suspend,
2105 	.resume = sdma_v4_4_2_resume,
2106 	.is_idle = sdma_v4_4_2_is_idle,
2107 	.wait_for_idle = sdma_v4_4_2_wait_for_idle,
2108 	.soft_reset = sdma_v4_4_2_soft_reset,
2109 	.set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
2110 	.set_powergating_state = sdma_v4_4_2_set_powergating_state,
2111 	.get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
2112 	.dump_ip_state = sdma_v4_4_2_dump_ip_state,
2113 	.print_ip_state = sdma_v4_4_2_print_ip_state,
2114 };
2115 
2116 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
2117 	.type = AMDGPU_RING_TYPE_SDMA,
2118 	.align_mask = 0xff,
2119 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2120 	.support_64bit_ptrs = true,
2121 	.get_rptr = sdma_v4_4_2_ring_get_rptr,
2122 	.get_wptr = sdma_v4_4_2_ring_get_wptr,
2123 	.set_wptr = sdma_v4_4_2_ring_set_wptr,
2124 	.emit_frame_size =
2125 		6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
2126 		3 + /* hdp invalidate */
2127 		6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
2128 		/* sdma_v4_4_2_ring_emit_vm_flush */
2129 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2130 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2131 		10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
2132 	.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
2133 	.emit_ib = sdma_v4_4_2_ring_emit_ib,
2134 	.emit_fence = sdma_v4_4_2_ring_emit_fence,
2135 	.emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
2136 	.emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
2137 	.emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
2138 	.test_ring = sdma_v4_4_2_ring_test_ring,
2139 	.test_ib = sdma_v4_4_2_ring_test_ib,
2140 	.insert_nop = sdma_v4_4_2_ring_insert_nop,
2141 	.pad_ib = sdma_v4_4_2_ring_pad_ib,
2142 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,
2143 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
2144 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2145 	.reset = sdma_v4_4_2_reset_queue,
2146 	.is_guilty = sdma_v4_4_2_ring_is_guilty,
2147 };
2148 
2149 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
2150 	.type = AMDGPU_RING_TYPE_SDMA,
2151 	.align_mask = 0xff,
2152 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2153 	.support_64bit_ptrs = true,
2154 	.get_rptr = sdma_v4_4_2_ring_get_rptr,
2155 	.get_wptr = sdma_v4_4_2_page_ring_get_wptr,
2156 	.set_wptr = sdma_v4_4_2_page_ring_set_wptr,
2157 	.emit_frame_size =
2158 		6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
2159 		3 + /* hdp invalidate */
2160 		6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
2161 		/* sdma_v4_4_2_ring_emit_vm_flush */
2162 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2163 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2164 		10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
2165 	.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
2166 	.emit_ib = sdma_v4_4_2_ring_emit_ib,
2167 	.emit_fence = sdma_v4_4_2_ring_emit_fence,
2168 	.emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
2169 	.emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
2170 	.emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
2171 	.test_ring = sdma_v4_4_2_ring_test_ring,
2172 	.test_ib = sdma_v4_4_2_ring_test_ib,
2173 	.insert_nop = sdma_v4_4_2_ring_insert_nop,
2174 	.pad_ib = sdma_v4_4_2_ring_pad_ib,
2175 	.emit_wreg = sdma_v4_4_2_ring_emit_wreg,
2176 	.emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
2177 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2178 	.reset = sdma_v4_4_2_reset_queue,
2179 	.is_guilty = sdma_v4_4_2_page_ring_is_guilty,
2180 };
2181 
sdma_v4_4_2_set_ring_funcs(struct amdgpu_device * adev)2182 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
2183 {
2184 	int i, dev_inst;
2185 
2186 	for (i = 0; i < adev->sdma.num_instances; i++) {
2187 		adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
2188 		adev->sdma.instance[i].ring.me = i;
2189 		if (adev->sdma.has_page_queue) {
2190 			adev->sdma.instance[i].page.funcs =
2191 				&sdma_v4_4_2_page_ring_funcs;
2192 			adev->sdma.instance[i].page.me = i;
2193 		}
2194 
2195 		dev_inst = GET_INST(SDMA0, i);
2196 		/* AID to which SDMA belongs depends on physical instance */
2197 		adev->sdma.instance[i].aid_id =
2198 			dev_inst / adev->sdma.num_inst_per_aid;
2199 	}
2200 }
2201 
2202 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
2203 	.set = sdma_v4_4_2_set_trap_irq_state,
2204 	.process = sdma_v4_4_2_process_trap_irq,
2205 };
2206 
2207 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
2208 	.process = sdma_v4_4_2_process_illegal_inst_irq,
2209 };
2210 
2211 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
2212 	.set = sdma_v4_4_2_set_ecc_irq_state,
2213 	.process = amdgpu_sdma_process_ecc_irq,
2214 };
2215 
2216 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
2217 	.process = sdma_v4_4_2_process_vm_hole_irq,
2218 };
2219 
2220 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
2221 	.process = sdma_v4_4_2_process_doorbell_invalid_irq,
2222 };
2223 
2224 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
2225 	.process = sdma_v4_4_2_process_pool_timeout_irq,
2226 };
2227 
2228 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
2229 	.process = sdma_v4_4_2_process_srbm_write_irq,
2230 };
2231 
2232 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ctxt_empty_irq_funcs = {
2233 	.process = sdma_v4_4_2_process_ctxt_empty_irq,
2234 };
2235 
sdma_v4_4_2_set_irq_funcs(struct amdgpu_device * adev)2236 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
2237 {
2238 	adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2239 	adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2240 	adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2241 	adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2242 	adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2243 	adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2244 	adev->sdma.ctxt_empty_irq.num_types = adev->sdma.num_instances;
2245 
2246 	adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
2247 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
2248 	adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
2249 	adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
2250 	adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
2251 	adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
2252 	adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
2253 	adev->sdma.ctxt_empty_irq.funcs = &sdma_v4_4_2_ctxt_empty_irq_funcs;
2254 }
2255 
2256 /**
2257  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
2258  *
2259  * @ib: indirect buffer to copy to
2260  * @src_offset: src GPU address
2261  * @dst_offset: dst GPU address
2262  * @byte_count: number of bytes to xfer
2263  * @copy_flags: copy flags for the buffers
2264  *
2265  * Copy GPU buffers using the DMA engine.
2266  * Used by the amdgpu ttm implementation to move pages if
2267  * registered as the asic copy callback.
2268  */
sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,uint32_t copy_flags)2269 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
2270 				       uint64_t src_offset,
2271 				       uint64_t dst_offset,
2272 				       uint32_t byte_count,
2273 				       uint32_t copy_flags)
2274 {
2275 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2276 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2277 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
2278 	ib->ptr[ib->length_dw++] = byte_count - 1;
2279 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2280 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2281 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2282 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2283 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2284 }
2285 
2286 /**
2287  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
2288  *
2289  * @ib: indirect buffer to copy to
2290  * @src_data: value to write to buffer
2291  * @dst_offset: dst GPU address
2292  * @byte_count: number of bytes to xfer
2293  *
2294  * Fill GPU buffers using the DMA engine.
2295  */
sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)2296 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
2297 				       uint32_t src_data,
2298 				       uint64_t dst_offset,
2299 				       uint32_t byte_count)
2300 {
2301 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2302 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2303 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2304 	ib->ptr[ib->length_dw++] = src_data;
2305 	ib->ptr[ib->length_dw++] = byte_count - 1;
2306 }
2307 
2308 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2309 	.copy_max_bytes = 0x400000,
2310 	.copy_num_dw = 7,
2311 	.emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2312 
2313 	.fill_max_bytes = 0x400000,
2314 	.fill_num_dw = 5,
2315 	.emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2316 };
2317 
sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device * adev)2318 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2319 {
2320 	adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2321 	if (adev->sdma.has_page_queue)
2322 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2323 	else
2324 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2325 }
2326 
2327 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2328 	.copy_pte_num_dw = 7,
2329 	.copy_pte = sdma_v4_4_2_vm_copy_pte,
2330 
2331 	.write_pte = sdma_v4_4_2_vm_write_pte,
2332 	.set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2333 };
2334 
sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device * adev)2335 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2336 {
2337 	struct drm_gpu_scheduler *sched;
2338 	unsigned i;
2339 
2340 	adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2341 	for (i = 0; i < adev->sdma.num_instances; i++) {
2342 		if (adev->sdma.has_page_queue)
2343 			sched = &adev->sdma.instance[i].page.sched;
2344 		else
2345 			sched = &adev->sdma.instance[i].ring.sched;
2346 		adev->vm_manager.vm_pte_scheds[i] = sched;
2347 	}
2348 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2349 }
2350 
2351 /**
2352  * sdma_v4_4_2_update_reset_mask - update  reset mask for SDMA
2353  * @adev: Pointer to the AMDGPU device structure
2354  *
2355  * This function update reset mask for SDMA and sets the supported
2356  * reset types based on the IP version and firmware versions.
2357  *
2358  */
sdma_v4_4_2_update_reset_mask(struct amdgpu_device * adev)2359 static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev)
2360 {
2361 	/* per queue reset not supported for SRIOV */
2362 	if (amdgpu_sriov_vf(adev))
2363 		return;
2364 
2365 	/*
2366 	 * the user queue relies on MEC fw and pmfw when the sdma queue do reset.
2367 	 * it needs to check both of them at here to skip old mec and pmfw.
2368 	 */
2369 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2370 	case IP_VERSION(9, 4, 3):
2371 	case IP_VERSION(9, 4, 4):
2372 		if ((adev->gfx.mec_fw_version >= 0xb0) && amdgpu_dpm_reset_sdma_is_supported(adev))
2373 			adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
2374 		break;
2375 	case IP_VERSION(9, 5, 0):
2376 		/*TODO: enable the queue reset flag until fw supported */
2377 	default:
2378 		break;
2379 	}
2380 
2381 }
2382 
2383 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2384 	.type = AMD_IP_BLOCK_TYPE_SDMA,
2385 	.major = 4,
2386 	.minor = 4,
2387 	.rev = 2,
2388 	.funcs = &sdma_v4_4_2_ip_funcs,
2389 };
2390 
sdma_v4_4_2_xcp_resume(void * handle,uint32_t inst_mask)2391 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2392 {
2393 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2394 	int r;
2395 
2396 	if (!amdgpu_sriov_vf(adev))
2397 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2398 
2399 	r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
2400 
2401 	return r;
2402 }
2403 
sdma_v4_4_2_xcp_suspend(void * handle,uint32_t inst_mask)2404 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2405 {
2406 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2407 	uint32_t tmp_mask = inst_mask;
2408 	int i;
2409 
2410 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2411 		for_each_inst(i, tmp_mask) {
2412 			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2413 				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2414 		}
2415 	}
2416 
2417 	sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2418 	sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2419 
2420 	return 0;
2421 }
2422 
2423 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2424 	.suspend = &sdma_v4_4_2_xcp_suspend,
2425 	.resume = &sdma_v4_4_2_xcp_resume
2426 };
2427 
2428 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2429 	{AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2430 	1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2431 };
2432 
2433 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2434 	{AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2435 	{AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2436 	{AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2437 	{AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2438 	{AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2439 	{AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2440 	{AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2441 	{AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2442 	{AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2443 	{AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2444 	{AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2445 	{AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2446 	{AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2447 	{AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2448 	{AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2449 	{AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2450 	{AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2451 	{AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2452 	{AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2453 	{AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2454 	{AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2455 	{AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2456 	{AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2457 	{AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2458 };
2459 
sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device * adev,uint32_t sdma_inst,void * ras_err_status)2460 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2461 						   uint32_t sdma_inst,
2462 						   void *ras_err_status)
2463 {
2464 	struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2465 	uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2466 	unsigned long ue_count = 0;
2467 	struct amdgpu_smuio_mcm_config_info mcm_info = {
2468 		.socket_id = adev->smuio.funcs->get_socket_id(adev),
2469 		.die_id = adev->sdma.instance[sdma_inst].aid_id,
2470 	};
2471 
2472 	/* sdma v4_4_2 doesn't support query ce counts */
2473 	amdgpu_ras_inst_query_ras_error_count(adev,
2474 					sdma_v4_2_2_ue_reg_list,
2475 					ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2476 					sdma_v4_4_2_ras_memory_list,
2477 					ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2478 					sdma_dev_inst,
2479 					AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2480 					&ue_count);
2481 
2482 	amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count);
2483 }
2484 
sdma_v4_4_2_query_ras_error_count(struct amdgpu_device * adev,void * ras_err_status)2485 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2486 					      void *ras_err_status)
2487 {
2488 	uint32_t inst_mask;
2489 	int i = 0;
2490 
2491 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2492 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2493 		for_each_inst(i, inst_mask)
2494 			sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2495 	} else {
2496 		dev_warn(adev->dev, "SDMA RAS is not supported\n");
2497 	}
2498 }
2499 
sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device * adev,uint32_t sdma_inst)2500 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2501 						   uint32_t sdma_inst)
2502 {
2503 	uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2504 
2505 	amdgpu_ras_inst_reset_ras_error_count(adev,
2506 					sdma_v4_2_2_ue_reg_list,
2507 					ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2508 					sdma_dev_inst);
2509 }
2510 
sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device * adev)2511 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2512 {
2513 	uint32_t inst_mask;
2514 	int i = 0;
2515 
2516 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2517 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2518 		for_each_inst(i, inst_mask)
2519 			sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2520 	} else {
2521 		dev_warn(adev->dev, "SDMA RAS is not supported\n");
2522 	}
2523 }
2524 
2525 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2526 	.query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2527 	.reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2528 };
2529 
sdma_v4_4_2_aca_bank_parser(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)2530 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
2531 				       enum aca_smu_type type, void *data)
2532 {
2533 	struct aca_bank_info info;
2534 	u64 misc0;
2535 	int ret;
2536 
2537 	ret = aca_bank_info_decode(bank, &info);
2538 	if (ret)
2539 		return ret;
2540 
2541 	misc0 = bank->regs[ACA_REG_IDX_MISC0];
2542 	switch (type) {
2543 	case ACA_SMU_TYPE_UE:
2544 		bank->aca_err_type = ACA_ERROR_TYPE_UE;
2545 		ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
2546 						     1ULL);
2547 		break;
2548 	case ACA_SMU_TYPE_CE:
2549 		bank->aca_err_type = ACA_ERROR_TYPE_CE;
2550 		ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,
2551 						     ACA_REG__MISC0__ERRCNT(misc0));
2552 		break;
2553 	default:
2554 		return -EINVAL;
2555 	}
2556 
2557 	return ret;
2558 }
2559 
2560 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2561 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2562 
sdma_v4_4_2_aca_bank_is_valid(struct aca_handle * handle,struct aca_bank * bank,enum aca_smu_type type,void * data)2563 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2564 					  enum aca_smu_type type, void *data)
2565 {
2566 	u32 instlo;
2567 
2568 	instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2569 	instlo &= GENMASK(31, 1);
2570 
2571 	if (instlo != mmSMNAID_AID0_MCA_SMU)
2572 		return false;
2573 
2574 	if (aca_bank_check_error_codes(handle->adev, bank,
2575 				       sdma_v4_4_2_err_codes,
2576 				       ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2577 		return false;
2578 
2579 	return true;
2580 }
2581 
2582 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2583 	.aca_bank_parser = sdma_v4_4_2_aca_bank_parser,
2584 	.aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2585 };
2586 
2587 static const struct aca_info sdma_v4_4_2_aca_info = {
2588 	.hwip = ACA_HWIP_TYPE_SMU,
2589 	.mask = ACA_ERROR_UE_MASK,
2590 	.bank_ops = &sdma_v4_4_2_aca_bank_ops,
2591 };
2592 
sdma_v4_4_2_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)2593 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2594 {
2595 	int r;
2596 
2597 	r = amdgpu_sdma_ras_late_init(adev, ras_block);
2598 	if (r)
2599 		return r;
2600 
2601 	return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2602 				   &sdma_v4_4_2_aca_info, NULL);
2603 }
2604 
2605 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2606 	.ras_block = {
2607 		.hw_ops = &sdma_v4_4_2_ras_hw_ops,
2608 		.ras_late_init = sdma_v4_4_2_ras_late_init,
2609 	},
2610 };
2611 
sdma_v4_4_2_set_ras_funcs(struct amdgpu_device * adev)2612 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2613 {
2614 	adev->sdma.ras = &sdma_v4_4_2_ras;
2615 }
2616