1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/vmalloc.h>
26 #include <drm/drm_drv.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ras.h"
31 #include "amdgpu_ucode.h"
32 #include "soc15_common.h"
33 #include "psp_v11_0.h"
34
35 #include "mp/mp_11_0_offset.h"
36 #include "mp/mp_11_0_sh_mask.h"
37 #include "gc/gc_9_0_offset.h"
38 #include "sdma0/sdma0_4_0_offset.h"
39 #include "nbio/nbio_7_4_offset.h"
40
41 #include "oss/osssys_4_0_offset.h"
42 #include "oss/osssys_4_0_sh_mask.h"
43
44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin");
57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");
63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
71
72 /* address block */
73 #define smnMP1_FIRMWARE_FLAGS 0x3010024
74 /* navi10 reg offset define */
75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880
78 #define mmSDMA0_UCODE_DATA_NV10 0x5881
79 /* memory training timeout define */
80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
81
82 /* For large FW files the time to complete can be very long */
83 #define USBC_PD_POLLING_LIMIT_S 240
84
85 /* Read USB-PD from LFB */
86 #define GFX_CMD_USB_PD_USE_LFB 0x480
87
psp_v11_0_init_microcode(struct psp_context * psp)88 static int psp_v11_0_init_microcode(struct psp_context *psp)
89 {
90 struct amdgpu_device *adev = psp->adev;
91 char ucode_prefix[30];
92 int err = 0;
93
94 DRM_DEBUG("\n");
95
96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
97
98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
99 case IP_VERSION(11, 0, 2):
100 case IP_VERSION(11, 0, 4):
101 err = psp_init_sos_microcode(psp, ucode_prefix);
102 if (err)
103 return err;
104 err = psp_init_asd_microcode(psp, ucode_prefix);
105 if (err)
106 return err;
107 err = psp_init_ta_microcode(psp, ucode_prefix);
108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
109 break;
110 case IP_VERSION(11, 0, 0):
111 case IP_VERSION(11, 0, 5):
112 case IP_VERSION(11, 0, 9):
113 err = psp_init_sos_microcode(psp, ucode_prefix);
114 if (err)
115 return err;
116 err = psp_init_asd_microcode(psp, ucode_prefix);
117 if (err)
118 return err;
119 err = psp_init_ta_microcode(psp, ucode_prefix);
120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
121 break;
122 case IP_VERSION(11, 0, 7):
123 case IP_VERSION(11, 0, 11):
124 case IP_VERSION(11, 0, 12):
125 case IP_VERSION(11, 0, 13):
126 err = psp_init_sos_microcode(psp, ucode_prefix);
127 if (err)
128 return err;
129 err = psp_init_ta_microcode(psp, ucode_prefix);
130 break;
131 case IP_VERSION(11, 5, 0):
132 case IP_VERSION(11, 5, 2):
133 err = psp_init_asd_microcode(psp, ucode_prefix);
134 if (err)
135 return err;
136 err = psp_init_toc_microcode(psp, ucode_prefix);
137 break;
138 default:
139 BUG();
140 }
141
142 return err;
143 }
144
psp_v11_0_wait_for_bootloader(struct psp_context * psp)145 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
146 {
147 struct amdgpu_device *adev = psp->adev;
148
149 int ret;
150 int retry_loop;
151
152 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
153 /* Wait for bootloader to signify that is
154 ready having bit 31 of C2PMSG_35 set to 1 */
155 ret = psp_wait_for(psp,
156 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
157 0x80000000,
158 0x80000000,
159 false);
160
161 if (ret == 0)
162 return 0;
163 }
164
165 return ret;
166 }
167
psp_v11_0_is_sos_alive(struct psp_context * psp)168 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
169 {
170 struct amdgpu_device *adev = psp->adev;
171 uint32_t sol_reg;
172
173 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
174
175 return sol_reg != 0x0;
176 }
177
psp_v11_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)178 static int psp_v11_0_bootloader_load_component(struct psp_context *psp,
179 struct psp_bin_desc *bin_desc,
180 enum psp_bootloader_cmd bl_cmd)
181 {
182 int ret;
183 uint32_t psp_gfxdrv_command_reg = 0;
184 struct amdgpu_device *adev = psp->adev;
185
186 /* Check sOS sign of life register to confirm sys driver and sOS
187 * are already been loaded.
188 */
189 if (psp_v11_0_is_sos_alive(psp))
190 return 0;
191
192 ret = psp_v11_0_wait_for_bootloader(psp);
193 if (ret)
194 return ret;
195
196 /* Copy PSP System Driver binary to memory */
197 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
198
199 /* Provide the sys driver to bootloader */
200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
201 (uint32_t)(psp->fw_pri_mc_addr >> 20));
202 psp_gfxdrv_command_reg = bl_cmd;
203 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
204 psp_gfxdrv_command_reg);
205
206 ret = psp_v11_0_wait_for_bootloader(psp);
207
208 return ret;
209 }
210
psp_v11_0_bootloader_load_kdb(struct psp_context * psp)211 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
212 {
213 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
214 }
215
psp_v11_0_bootloader_load_spl(struct psp_context * psp)216 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
217 {
218 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
219 }
220
psp_v11_0_bootloader_load_sysdrv(struct psp_context * psp)221 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
222 {
223 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
224 }
225
psp_v11_0_bootloader_load_sos(struct psp_context * psp)226 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
227 {
228 int ret;
229 unsigned int psp_gfxdrv_command_reg = 0;
230 struct amdgpu_device *adev = psp->adev;
231
232 /* Check sOS sign of life register to confirm sys driver and sOS
233 * are already been loaded.
234 */
235 if (psp_v11_0_is_sos_alive(psp))
236 return 0;
237
238 ret = psp_v11_0_wait_for_bootloader(psp);
239 if (ret)
240 return ret;
241
242 /* Copy Secure OS binary to PSP memory */
243 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
244
245 /* Provide the PSP secure OS to bootloader */
246 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
247 (uint32_t)(psp->fw_pri_mc_addr >> 20));
248 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
249 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
250 psp_gfxdrv_command_reg);
251
252 /* there might be handshake issue with hardware which needs delay */
253 mdelay(20);
254 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
255 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
256 0, true);
257
258 return ret;
259 }
260
psp_v11_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)261 static int psp_v11_0_ring_stop(struct psp_context *psp,
262 enum psp_ring_type ring_type)
263 {
264 int ret = 0;
265 struct amdgpu_device *adev = psp->adev;
266
267 /* Write the ring destroy command*/
268 if (amdgpu_sriov_vf(adev))
269 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
270 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
271 else
272 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
273 GFX_CTRL_CMD_ID_DESTROY_RINGS);
274
275 /* there might be handshake issue with hardware which needs delay */
276 mdelay(20);
277
278 /* Wait for response flag (bit 31) */
279 if (amdgpu_sriov_vf(adev))
280 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
281 0x80000000, 0x80000000, false);
282 else
283 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
284 0x80000000, 0x80000000, false);
285
286 return ret;
287 }
288
psp_v11_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)289 static int psp_v11_0_ring_create(struct psp_context *psp,
290 enum psp_ring_type ring_type)
291 {
292 int ret = 0;
293 unsigned int psp_ring_reg = 0;
294 struct psp_ring *ring = &psp->km_ring;
295 struct amdgpu_device *adev = psp->adev;
296
297 if (amdgpu_sriov_vf(adev)) {
298 ring->ring_wptr = 0;
299 ret = psp_v11_0_ring_stop(psp, ring_type);
300 if (ret) {
301 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
302 return ret;
303 }
304
305 /* Write low address of the ring to C2PMSG_102 */
306 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
308 /* Write high address of the ring to C2PMSG_103 */
309 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
310 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
311
312 /* Write the ring initialization command to C2PMSG_101 */
313 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
314 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
315
316 /* there might be handshake issue with hardware which needs delay */
317 mdelay(20);
318
319 /* Wait for response flag (bit 31) in C2PMSG_101 */
320 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
321 0x80000000, 0x8000FFFF, false);
322
323 } else {
324 /* Wait for sOS ready for ring creation */
325 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
326 0x80000000, 0x80000000, false);
327 if (ret) {
328 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
329 return ret;
330 }
331
332 /* Write low address of the ring to C2PMSG_69 */
333 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
334 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
335 /* Write high address of the ring to C2PMSG_70 */
336 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
337 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
338 /* Write size of ring to C2PMSG_71 */
339 psp_ring_reg = ring->ring_size;
340 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
341 /* Write the ring initialization command to C2PMSG_64 */
342 psp_ring_reg = ring_type;
343 psp_ring_reg = psp_ring_reg << 16;
344 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
345
346 /* there might be handshake issue with hardware which needs delay */
347 mdelay(20);
348
349 /* Wait for response flag (bit 31) in C2PMSG_64 */
350 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
351 0x80000000, 0x8000FFFF, false);
352 }
353
354 return ret;
355 }
356
357
psp_v11_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)358 static int psp_v11_0_ring_destroy(struct psp_context *psp,
359 enum psp_ring_type ring_type)
360 {
361 int ret = 0;
362 struct psp_ring *ring = &psp->km_ring;
363 struct amdgpu_device *adev = psp->adev;
364
365 ret = psp_v11_0_ring_stop(psp, ring_type);
366 if (ret)
367 DRM_ERROR("Fail to stop psp ring\n");
368
369 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
370 &ring->ring_mem_mc_addr,
371 (void **)&ring->ring_mem);
372
373 return ret;
374 }
375
psp_v11_0_mode1_reset(struct psp_context * psp)376 static int psp_v11_0_mode1_reset(struct psp_context *psp)
377 {
378 int ret;
379 uint32_t offset;
380 struct amdgpu_device *adev = psp->adev;
381
382 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
383
384 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
385
386 if (ret) {
387 DRM_INFO("psp is not working correctly before mode1 reset!\n");
388 return -EINVAL;
389 }
390
391 /*send the mode 1 reset command*/
392 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
393
394 msleep(500);
395
396 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
397
398 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
399
400 if (ret) {
401 DRM_INFO("psp mode 1 reset failed!\n");
402 return -EINVAL;
403 }
404
405 DRM_INFO("psp mode1 reset succeed \n");
406
407 return 0;
408 }
409
psp_v11_0_memory_training_send_msg(struct psp_context * psp,int msg)410 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
411 {
412 int ret;
413 int i;
414 uint32_t data_32;
415 int max_wait;
416 struct amdgpu_device *adev = psp->adev;
417
418 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
419 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
420 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
421
422 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
423 for (i = 0; i < max_wait; i++) {
424 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
425 0x80000000, 0x80000000, false);
426 if (ret == 0)
427 break;
428 }
429 if (i < max_wait)
430 ret = 0;
431 else
432 ret = -ETIME;
433
434 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
435 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
436 (ret == 0) ? "succeed" : "failed",
437 i, adev->usec_timeout/1000);
438 return ret;
439 }
440
441 /*
442 * save and restore process
443 */
psp_v11_0_memory_training(struct psp_context * psp,uint32_t ops)444 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
445 {
446 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
447 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
448 struct amdgpu_device *adev = psp->adev;
449 uint32_t p2c_header[4];
450 uint32_t sz;
451 void *buf;
452 int ret, idx;
453
454 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
455 DRM_DEBUG("Memory training is not supported.\n");
456 return 0;
457 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
458 DRM_ERROR("Memory training initialization failure.\n");
459 return -EINVAL;
460 }
461
462 if (psp_v11_0_is_sos_alive(psp)) {
463 DRM_DEBUG("SOS is alive, skip memory training.\n");
464 return 0;
465 }
466
467 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
468 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
469 pcache[0], pcache[1], pcache[2], pcache[3],
470 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
471
472 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
473 DRM_DEBUG("Short training depends on restore.\n");
474 ops |= PSP_MEM_TRAIN_RESTORE;
475 }
476
477 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
478 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
479 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
480 ops |= PSP_MEM_TRAIN_SAVE;
481 }
482
483 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
484 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
485 pcache[3] == p2c_header[3])) {
486 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
487 ops |= PSP_MEM_TRAIN_SAVE;
488 }
489
490 if ((ops & PSP_MEM_TRAIN_SAVE) &&
491 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
492 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
493 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
494 }
495
496 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
497 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
498 ops |= PSP_MEM_TRAIN_SAVE;
499 }
500
501 DRM_DEBUG("Memory training ops:%x.\n", ops);
502
503 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
504 /*
505 * Long training will encroach a certain amount on the bottom of VRAM;
506 * save the content from the bottom of VRAM to system memory
507 * before training, and restore it after training to avoid
508 * VRAM corruption.
509 */
510 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
511
512 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
513 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
514 adev->gmc.visible_vram_size,
515 adev->mman.aper_base_kaddr);
516 return -EINVAL;
517 }
518
519 buf = vmalloc(sz);
520 if (!buf) {
521 DRM_ERROR("failed to allocate system memory.\n");
522 return -ENOMEM;
523 }
524
525 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
526 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
527 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
528 if (ret) {
529 DRM_ERROR("Send long training msg failed.\n");
530 vfree(buf);
531 drm_dev_exit(idx);
532 return ret;
533 }
534
535 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
536 amdgpu_device_flush_hdp(adev, NULL);
537 vfree(buf);
538 drm_dev_exit(idx);
539 } else {
540 vfree(buf);
541 return -ENODEV;
542 }
543 }
544
545 if (ops & PSP_MEM_TRAIN_SAVE) {
546 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
547 }
548
549 if (ops & PSP_MEM_TRAIN_RESTORE) {
550 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
551 }
552
553 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
554 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
555 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
556 if (ret) {
557 DRM_ERROR("send training msg failed.\n");
558 return ret;
559 }
560 }
561 ctx->training_cnt++;
562 return 0;
563 }
564
psp_v11_0_ring_get_wptr(struct psp_context * psp)565 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
566 {
567 uint32_t data;
568 struct amdgpu_device *adev = psp->adev;
569
570 if (amdgpu_sriov_vf(adev))
571 data = psp->km_ring.ring_wptr;
572 else
573 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
574
575 return data;
576 }
577
psp_v11_0_ring_set_wptr(struct psp_context * psp,uint32_t value)578 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
579 {
580 struct amdgpu_device *adev = psp->adev;
581
582 if (amdgpu_sriov_vf(adev)) {
583 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
584 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
585 psp->km_ring.ring_wptr = value;
586 } else
587 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
588 }
589
psp_v11_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)590 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
591 {
592 struct amdgpu_device *adev = psp->adev;
593 uint32_t reg_status;
594 int ret, i = 0;
595
596 /*
597 * LFB address which is aligned to 1MB address and has to be
598 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
599 * register
600 */
601 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
602
603 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
604 0x80000000, 0x80000000, false);
605 if (ret)
606 return ret;
607
608 /* Fireup interrupt so PSP can pick up the address */
609 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
610
611 /* FW load takes very long time */
612 do {
613 msleep(1000);
614 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
615
616 if (reg_status & 0x80000000)
617 goto done;
618
619 } while (++i < USBC_PD_POLLING_LIMIT_S);
620
621 return -ETIME;
622 done:
623
624 if ((reg_status & 0xFFFF) != 0) {
625 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",
626 reg_status & 0xFFFF);
627 return -EIO;
628 }
629
630 return 0;
631 }
632
psp_v11_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)633 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
634 {
635 struct amdgpu_device *adev = psp->adev;
636 int ret;
637
638 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
639
640 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
641 0x80000000, 0x80000000, false);
642 if (!ret)
643 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
644
645 return ret;
646 }
647
648 static const struct psp_funcs psp_v11_0_funcs = {
649 .init_microcode = psp_v11_0_init_microcode,
650 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
651 .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
652 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
653 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
654 .ring_create = psp_v11_0_ring_create,
655 .ring_stop = psp_v11_0_ring_stop,
656 .ring_destroy = psp_v11_0_ring_destroy,
657 .mode1_reset = psp_v11_0_mode1_reset,
658 .mem_training = psp_v11_0_memory_training,
659 .ring_get_wptr = psp_v11_0_ring_get_wptr,
660 .ring_set_wptr = psp_v11_0_ring_set_wptr,
661 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
662 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw
663 };
664
psp_v11_0_set_psp_funcs(struct psp_context * psp)665 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
666 {
667 psp->funcs = &psp_v11_0_funcs;
668 }
669