1 /*
2  * Copyright 2024 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __JPEG_V5_0_1_H__
25 #define __JPEG_V5_0_1_H__
26 
27 extern const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block;
28 
29 #define regUVD_JRBC0_UVD_JRBC_RB_WPTR                                                         0x0640
30 #define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX                                                1
31 #define regUVD_JRBC0_UVD_JRBC_STATUS                                                          0x0649
32 #define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX                                                 1
33 #define regUVD_JRBC0_UVD_JRBC_RB_RPTR                                                         0x064a
34 #define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX                                                1
35 #define regUVD_JRBC1_UVD_JRBC_RB_WPTR                                                         0x0000
36 #define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
37 #define regUVD_JRBC1_UVD_JRBC_STATUS                                                          0x0009
38 #define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX                                                 0
39 #define regUVD_JRBC1_UVD_JRBC_RB_RPTR                                                         0x000a
40 #define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
41 #define regUVD_JRBC2_UVD_JRBC_RB_WPTR                                                         0x0040
42 #define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
43 #define regUVD_JRBC2_UVD_JRBC_STATUS                                                          0x0049
44 #define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX                                                 0
45 #define regUVD_JRBC2_UVD_JRBC_RB_RPTR                                                         0x004a
46 #define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
47 #define regUVD_JRBC3_UVD_JRBC_RB_WPTR                                                         0x0080
48 #define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
49 #define regUVD_JRBC3_UVD_JRBC_STATUS                                                          0x0089
50 #define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX                                                 0
51 #define regUVD_JRBC3_UVD_JRBC_RB_RPTR                                                         0x008a
52 #define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
53 #define regUVD_JRBC4_UVD_JRBC_RB_WPTR                                                         0x00c0
54 #define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
55 #define regUVD_JRBC4_UVD_JRBC_STATUS                                                          0x00c9
56 #define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX                                                 0
57 #define regUVD_JRBC4_UVD_JRBC_RB_RPTR                                                         0x00ca
58 #define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
59 #define regUVD_JRBC5_UVD_JRBC_RB_WPTR                                                         0x0100
60 #define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
61 #define regUVD_JRBC5_UVD_JRBC_STATUS                                                          0x0109
62 #define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX                                                 0
63 #define regUVD_JRBC5_UVD_JRBC_RB_RPTR                                                         0x010a
64 #define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
65 #define regUVD_JRBC6_UVD_JRBC_RB_WPTR                                                         0x0140
66 #define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
67 #define regUVD_JRBC6_UVD_JRBC_STATUS                                                          0x0149
68 #define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX                                                 0
69 #define regUVD_JRBC6_UVD_JRBC_RB_RPTR                                                         0x014a
70 #define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
71 #define regUVD_JRBC7_UVD_JRBC_RB_WPTR                                                         0x0180
72 #define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
73 #define regUVD_JRBC7_UVD_JRBC_STATUS                                                          0x0189
74 #define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX                                                 0
75 #define regUVD_JRBC7_UVD_JRBC_RB_RPTR                                                         0x018a
76 #define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
77 #define regUVD_JRBC8_UVD_JRBC_RB_WPTR                                                         0x01c0
78 #define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX                                                0
79 #define regUVD_JRBC8_UVD_JRBC_STATUS                                                          0x01c9
80 #define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX                                                 0
81 #define regUVD_JRBC8_UVD_JRBC_RB_RPTR                                                         0x01ca
82 #define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX                                                0
83 #define regUVD_JRBC9_UVD_JRBC_RB_WPTR                                                         0x0440
84 #define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX                                                1
85 #define regUVD_JRBC9_UVD_JRBC_STATUS                                                          0x0449
86 #define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX                                                 1
87 #define regUVD_JRBC9_UVD_JRBC_RB_RPTR                                                         0x044a
88 #define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX                                                1
89 #define regUVD_JMI0_JPEG_LMI_DROP                                                             0x0663
90 #define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX                                                    1
91 #define regUVD_JMI0_UVD_JMI_CLIENT_STALL                                                      0x067a
92 #define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX                                             1
93 #define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS                                               0x067b
94 #define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX                                      1
95 #define regJPEG_CORE_RST_CTRL                                                                 0x072e
96 #define regJPEG_CORE_RST_CTRL_BASE_IDX                                                        1
97 
98 #define regVCN_RRMT_CNTL                          0x0940
99 #define regVCN_RRMT_CNTL_BASE_IDX                 1
100 
101 #endif /* __JPEG_V5_0_1_H__ */
102