1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu.h"
25 #include "amdgpu_jpeg.h"
26 #include "amdgpu_cs.h"
27 #include "amdgpu_pm.h"
28 #include "soc15.h"
29 #include "soc15d.h"
30 #include "jpeg_v2_0.h"
31
32 #include "vcn/vcn_2_0_0_offset.h"
33 #include "vcn/vcn_2_0_0_sh_mask.h"
34 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
35
36 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = {
37 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
49 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),
50 };
51
52 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
53 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
54 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
55 enum amd_powergating_state state);
56
57 /**
58 * jpeg_v2_0_early_init - set function pointers
59 *
60 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
61 *
62 * Set ring and irq function pointers
63 */
jpeg_v2_0_early_init(struct amdgpu_ip_block * ip_block)64 static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block)
65 {
66 struct amdgpu_device *adev = ip_block->adev;
67
68 adev->jpeg.num_jpeg_inst = 1;
69 adev->jpeg.num_jpeg_rings = 1;
70
71 jpeg_v2_0_set_dec_ring_funcs(adev);
72 jpeg_v2_0_set_irq_funcs(adev);
73
74 return 0;
75 }
76
77 /**
78 * jpeg_v2_0_sw_init - sw init for JPEG block
79 *
80 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
81 *
82 * Load firmware and sw initialization
83 */
jpeg_v2_0_sw_init(struct amdgpu_ip_block * ip_block)84 static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block)
85 {
86 struct amdgpu_device *adev = ip_block->adev;
87 struct amdgpu_ring *ring;
88 int r;
89
90 /* JPEG TRAP */
91 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
92 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
93 if (r)
94 return r;
95
96 r = amdgpu_jpeg_sw_init(adev);
97 if (r)
98 return r;
99
100 r = amdgpu_jpeg_resume(adev);
101 if (r)
102 return r;
103
104 ring = adev->jpeg.inst->ring_dec;
105 ring->use_doorbell = true;
106 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
107 ring->vm_hub = AMDGPU_MMHUB0(0);
108 sprintf(ring->name, "jpeg_dec");
109 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
110 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
111 if (r)
112 return r;
113
114 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
115 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
116
117 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0));
118 if (r)
119 return r;
120
121 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
122 r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
123
124 return r;
125 }
126
127 /**
128 * jpeg_v2_0_sw_fini - sw fini for JPEG block
129 *
130 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
131 *
132 * JPEG suspend and free up sw allocation
133 */
jpeg_v2_0_sw_fini(struct amdgpu_ip_block * ip_block)134 static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block)
135 {
136 int r;
137 struct amdgpu_device *adev = ip_block->adev;
138
139 r = amdgpu_jpeg_suspend(adev);
140 if (r)
141 return r;
142
143 amdgpu_jpeg_sysfs_reset_mask_fini(adev);
144
145 r = amdgpu_jpeg_sw_fini(adev);
146
147 return r;
148 }
149
150 /**
151 * jpeg_v2_0_hw_init - start and test JPEG block
152 *
153 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
154 *
155 */
jpeg_v2_0_hw_init(struct amdgpu_ip_block * ip_block)156 static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block)
157 {
158 struct amdgpu_device *adev = ip_block->adev;
159 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
160
161 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
162 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
163
164 return amdgpu_ring_test_helper(ring);
165 }
166
167 /**
168 * jpeg_v2_0_hw_fini - stop the hardware block
169 *
170 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
171 *
172 * Stop the JPEG block, mark ring as not ready any more
173 */
jpeg_v2_0_hw_fini(struct amdgpu_ip_block * ip_block)174 static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block)
175 {
176 struct amdgpu_device *adev = ip_block->adev;
177
178 cancel_delayed_work_sync(&adev->jpeg.idle_work);
179
180 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
181 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
182 jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
183
184 return 0;
185 }
186
187 /**
188 * jpeg_v2_0_suspend - suspend JPEG block
189 *
190 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
191 *
192 * HW fini and suspend JPEG block
193 */
jpeg_v2_0_suspend(struct amdgpu_ip_block * ip_block)194 static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block)
195 {
196 int r;
197
198 r = jpeg_v2_0_hw_fini(ip_block);
199 if (r)
200 return r;
201
202 r = amdgpu_jpeg_suspend(ip_block->adev);
203
204 return r;
205 }
206
207 /**
208 * jpeg_v2_0_resume - resume JPEG block
209 *
210 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
211 *
212 * Resume firmware and hw init JPEG block
213 */
jpeg_v2_0_resume(struct amdgpu_ip_block * ip_block)214 static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block)
215 {
216 int r;
217
218 r = amdgpu_jpeg_resume(ip_block->adev);
219 if (r)
220 return r;
221
222 r = jpeg_v2_0_hw_init(ip_block);
223
224 return r;
225 }
226
jpeg_v2_0_disable_power_gating(struct amdgpu_device * adev)227 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
228 {
229 uint32_t data;
230 int r = 0;
231
232 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
233 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
234 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
235
236 r = SOC15_WAIT_ON_RREG(JPEG, 0,
237 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
238 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
239
240 if (r) {
241 DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
242 return r;
243 }
244 }
245
246 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
247 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
248 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
249
250 return 0;
251 }
252
jpeg_v2_0_enable_power_gating(struct amdgpu_device * adev)253 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
254 {
255 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
256 uint32_t data;
257 int r = 0;
258
259 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
260 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
261 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
262 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
263
264 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
265 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
266
267 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
268 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
269 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
270
271 if (r) {
272 DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
273 return r;
274 }
275 }
276
277 return 0;
278 }
279
jpeg_v2_0_disable_clock_gating(struct amdgpu_device * adev)280 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
281 {
282 uint32_t data;
283
284 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
285 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
286 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
287 else
288 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
289
290 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
291 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
292 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
293
294 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
295 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
296 | JPEG_CGC_GATE__JPEG2_DEC_MASK
297 | JPEG_CGC_GATE__JPEG_ENC_MASK
298 | JPEG_CGC_GATE__JMCIF_MASK
299 | JPEG_CGC_GATE__JRBBM_MASK);
300 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
301 }
302
jpeg_v2_0_enable_clock_gating(struct amdgpu_device * adev)303 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
304 {
305 uint32_t data;
306
307 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
308 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
309 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
310 else
311 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
312
313 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
314 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
315 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
316
317 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
318 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
319 |JPEG_CGC_GATE__JPEG2_DEC_MASK
320 |JPEG_CGC_GATE__JPEG_ENC_MASK
321 |JPEG_CGC_GATE__JMCIF_MASK
322 |JPEG_CGC_GATE__JRBBM_MASK);
323 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
324 }
325
326 /**
327 * jpeg_v2_0_start - start JPEG block
328 *
329 * @adev: amdgpu_device pointer
330 *
331 * Setup and start the JPEG block
332 */
jpeg_v2_0_start(struct amdgpu_device * adev)333 static int jpeg_v2_0_start(struct amdgpu_device *adev)
334 {
335 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
336 int r;
337
338 if (adev->pm.dpm_enabled)
339 amdgpu_dpm_enable_jpeg(adev, true);
340
341 /* disable power gating */
342 r = jpeg_v2_0_disable_power_gating(adev);
343 if (r)
344 return r;
345
346 /* JPEG disable CGC */
347 jpeg_v2_0_disable_clock_gating(adev);
348
349 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
350
351 /* enable JMI channel */
352 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
353 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
354
355 /* enable System Interrupt for JRBC */
356 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
357 JPEG_SYS_INT_EN__DJRBC_MASK,
358 ~JPEG_SYS_INT_EN__DJRBC_MASK);
359
360 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
361 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
362 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
363 lower_32_bits(ring->gpu_addr));
364 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
365 upper_32_bits(ring->gpu_addr));
366 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
367 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
368 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
369 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
370 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
371
372 return 0;
373 }
374
375 /**
376 * jpeg_v2_0_stop - stop JPEG block
377 *
378 * @adev: amdgpu_device pointer
379 *
380 * stop the JPEG block
381 */
jpeg_v2_0_stop(struct amdgpu_device * adev)382 static int jpeg_v2_0_stop(struct amdgpu_device *adev)
383 {
384 int r;
385
386 /* reset JMI */
387 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
388 UVD_JMI_CNTL__SOFT_RESET_MASK,
389 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
390
391 /* enable JPEG CGC */
392 jpeg_v2_0_enable_clock_gating(adev);
393
394 /* enable power gating */
395 r = jpeg_v2_0_enable_power_gating(adev);
396 if (r)
397 return r;
398
399 if (adev->pm.dpm_enabled)
400 amdgpu_dpm_enable_jpeg(adev, false);
401
402 return 0;
403 }
404
405 /**
406 * jpeg_v2_0_dec_ring_get_rptr - get read pointer
407 *
408 * @ring: amdgpu_ring pointer
409 *
410 * Returns the current hardware read pointer
411 */
jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)412 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
413 {
414 struct amdgpu_device *adev = ring->adev;
415
416 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
417 }
418
419 /**
420 * jpeg_v2_0_dec_ring_get_wptr - get write pointer
421 *
422 * @ring: amdgpu_ring pointer
423 *
424 * Returns the current hardware write pointer
425 */
jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)426 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
427 {
428 struct amdgpu_device *adev = ring->adev;
429
430 if (ring->use_doorbell)
431 return *ring->wptr_cpu_addr;
432 else
433 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
434 }
435
436 /**
437 * jpeg_v2_0_dec_ring_set_wptr - set write pointer
438 *
439 * @ring: amdgpu_ring pointer
440 *
441 * Commits the write pointer to the hardware
442 */
jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)443 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
444 {
445 struct amdgpu_device *adev = ring->adev;
446
447 if (ring->use_doorbell) {
448 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
449 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
450 } else {
451 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
452 }
453 }
454
455 /**
456 * jpeg_v2_0_dec_ring_insert_start - insert a start command
457 *
458 * @ring: amdgpu_ring pointer
459 *
460 * Write a start command to the ring.
461 */
jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)462 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
463 {
464 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
465 0, 0, PACKETJ_TYPE0));
466 amdgpu_ring_write(ring, 0x68e04);
467
468 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
469 0, 0, PACKETJ_TYPE0));
470 amdgpu_ring_write(ring, 0x80010000);
471 }
472
473 /**
474 * jpeg_v2_0_dec_ring_insert_end - insert a end command
475 *
476 * @ring: amdgpu_ring pointer
477 *
478 * Write a end command to the ring.
479 */
jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)480 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
481 {
482 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
483 0, 0, PACKETJ_TYPE0));
484 amdgpu_ring_write(ring, 0x68e04);
485
486 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
487 0, 0, PACKETJ_TYPE0));
488 amdgpu_ring_write(ring, 0x00010000);
489 }
490
491 /**
492 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
493 *
494 * @ring: amdgpu_ring pointer
495 * @addr: address
496 * @seq: sequence number
497 * @flags: fence related flags
498 *
499 * Write a fence and a trap command to the ring.
500 */
jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)501 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
502 unsigned flags)
503 {
504 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
505
506 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
507 0, 0, PACKETJ_TYPE0));
508 amdgpu_ring_write(ring, seq);
509
510 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
511 0, 0, PACKETJ_TYPE0));
512 amdgpu_ring_write(ring, seq);
513
514 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
515 0, 0, PACKETJ_TYPE0));
516 amdgpu_ring_write(ring, lower_32_bits(addr));
517
518 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
519 0, 0, PACKETJ_TYPE0));
520 amdgpu_ring_write(ring, upper_32_bits(addr));
521
522 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
523 0, 0, PACKETJ_TYPE0));
524 amdgpu_ring_write(ring, 0x8);
525
526 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
527 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
528 amdgpu_ring_write(ring, 0);
529
530 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
531 0, 0, PACKETJ_TYPE0));
532 amdgpu_ring_write(ring, 0x3fbc);
533
534 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
535 0, 0, PACKETJ_TYPE0));
536 amdgpu_ring_write(ring, 0x1);
537
538 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
539 amdgpu_ring_write(ring, 0);
540 }
541
542 /**
543 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
544 *
545 * @ring: amdgpu_ring pointer
546 * @job: job to retrieve vmid from
547 * @ib: indirect buffer to execute
548 * @flags: unused
549 *
550 * Write ring commands to execute the indirect buffer.
551 */
jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)552 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
553 struct amdgpu_job *job,
554 struct amdgpu_ib *ib,
555 uint32_t flags)
556 {
557 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
558
559 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,
560 0, 0, PACKETJ_TYPE0));
561 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));
562
563 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
564 0, 0, PACKETJ_TYPE0));
565
566 if (ring->funcs->parse_cs)
567 amdgpu_ring_write(ring, 0);
568 else
569 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
570
571 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
572 0, 0, PACKETJ_TYPE0));
573 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
574
575 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
576 0, 0, PACKETJ_TYPE0));
577 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
578
579 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
580 0, 0, PACKETJ_TYPE0));
581 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
582
583 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
584 0, 0, PACKETJ_TYPE0));
585 amdgpu_ring_write(ring, ib->length_dw);
586
587 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
588 0, 0, PACKETJ_TYPE0));
589 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
590
591 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
592 0, 0, PACKETJ_TYPE0));
593 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
594
595 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
596 amdgpu_ring_write(ring, 0);
597
598 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
599 0, 0, PACKETJ_TYPE0));
600 amdgpu_ring_write(ring, 0x01400200);
601
602 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
603 0, 0, PACKETJ_TYPE0));
604 amdgpu_ring_write(ring, 0x2);
605
606 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
607 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
608 amdgpu_ring_write(ring, 0x2);
609 }
610
jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)611 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
612 uint32_t val, uint32_t mask)
613 {
614 uint32_t reg_offset = (reg << 2);
615
616 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
617 0, 0, PACKETJ_TYPE0));
618 amdgpu_ring_write(ring, 0x01400200);
619
620 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
621 0, 0, PACKETJ_TYPE0));
622 amdgpu_ring_write(ring, val);
623
624 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
625 0, 0, PACKETJ_TYPE0));
626 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
627 amdgpu_ring_write(ring, 0);
628 amdgpu_ring_write(ring,
629 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
630 } else {
631 amdgpu_ring_write(ring, reg_offset);
632 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
633 0, 0, PACKETJ_TYPE3));
634 }
635 amdgpu_ring_write(ring, mask);
636 }
637
jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)638 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
639 unsigned vmid, uint64_t pd_addr)
640 {
641 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
642 uint32_t data0, data1, mask;
643
644 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
645
646 /* wait for register write */
647 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
648 data1 = lower_32_bits(pd_addr);
649 mask = 0xffffffff;
650 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
651 }
652
jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)653 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
654 {
655 uint32_t reg_offset = (reg << 2);
656
657 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
658 0, 0, PACKETJ_TYPE0));
659 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
660 amdgpu_ring_write(ring, 0);
661 amdgpu_ring_write(ring,
662 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
663 } else {
664 amdgpu_ring_write(ring, reg_offset);
665 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
666 0, 0, PACKETJ_TYPE0));
667 }
668 amdgpu_ring_write(ring, val);
669 }
670
jpeg_v2_0_dec_ring_nop(struct amdgpu_ring * ring,uint32_t count)671 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
672 {
673 int i;
674
675 WARN_ON(ring->wptr % 2 || count % 2);
676
677 for (i = 0; i < count / 2; i++) {
678 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
679 amdgpu_ring_write(ring, 0);
680 }
681 }
682
jpeg_v2_0_is_idle(struct amdgpu_ip_block * ip_block)683 static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block)
684 {
685 struct amdgpu_device *adev = ip_block->adev;
686
687 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
688 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
689 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
690 }
691
jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block * ip_block)692 static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
693 {
694 struct amdgpu_device *adev = ip_block->adev;
695 int ret;
696
697 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
698 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
699
700 return ret;
701 }
702
jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)703 static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
704 enum amd_clockgating_state state)
705 {
706 struct amdgpu_device *adev = ip_block->adev;
707 bool enable = (state == AMD_CG_STATE_GATE);
708
709 if (enable) {
710 if (!jpeg_v2_0_is_idle(ip_block))
711 return -EBUSY;
712 jpeg_v2_0_enable_clock_gating(adev);
713 } else {
714 jpeg_v2_0_disable_clock_gating(adev);
715 }
716
717 return 0;
718 }
719
jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)720 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
721 enum amd_powergating_state state)
722 {
723 struct amdgpu_device *adev = ip_block->adev;
724 int ret;
725
726 if (state == adev->jpeg.cur_state)
727 return 0;
728
729 if (state == AMD_PG_STATE_GATE)
730 ret = jpeg_v2_0_stop(adev);
731 else
732 ret = jpeg_v2_0_start(adev);
733
734 if (!ret)
735 adev->jpeg.cur_state = state;
736
737 return ret;
738 }
739
jpeg_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)740 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
741 struct amdgpu_irq_src *source,
742 unsigned type,
743 enum amdgpu_interrupt_state state)
744 {
745 return 0;
746 }
747
jpeg_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)748 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
749 struct amdgpu_irq_src *source,
750 struct amdgpu_iv_entry *entry)
751 {
752 DRM_DEBUG("IH: JPEG TRAP\n");
753
754 switch (entry->src_id) {
755 case VCN_2_0__SRCID__JPEG_DECODE:
756 amdgpu_fence_process(adev->jpeg.inst->ring_dec);
757 break;
758 default:
759 DRM_ERROR("Unhandled interrupt: %d %d\n",
760 entry->src_id, entry->src_data[0]);
761 break;
762 }
763
764 return 0;
765 }
766
jpeg_v2_0_ring_reset(struct amdgpu_ring * ring,unsigned int vmid)767 static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
768 {
769 jpeg_v2_0_stop(ring->adev);
770 jpeg_v2_0_start(ring->adev);
771 return amdgpu_ring_test_helper(ring);
772 }
773
774 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
775 .name = "jpeg_v2_0",
776 .early_init = jpeg_v2_0_early_init,
777 .sw_init = jpeg_v2_0_sw_init,
778 .sw_fini = jpeg_v2_0_sw_fini,
779 .hw_init = jpeg_v2_0_hw_init,
780 .hw_fini = jpeg_v2_0_hw_fini,
781 .suspend = jpeg_v2_0_suspend,
782 .resume = jpeg_v2_0_resume,
783 .is_idle = jpeg_v2_0_is_idle,
784 .wait_for_idle = jpeg_v2_0_wait_for_idle,
785 .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
786 .set_powergating_state = jpeg_v2_0_set_powergating_state,
787 .dump_ip_state = amdgpu_jpeg_dump_ip_state,
788 .print_ip_state = amdgpu_jpeg_print_ip_state,
789 };
790
791 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
792 .type = AMDGPU_RING_TYPE_VCN_JPEG,
793 .align_mask = 0xf,
794 .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
795 .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
796 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
797 .parse_cs = jpeg_v2_dec_ring_parse_cs,
798 .emit_frame_size =
799 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
800 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
801 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
802 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
803 8 + 16,
804 .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */
805 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
806 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
807 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
808 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
809 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
810 .insert_nop = jpeg_v2_0_dec_ring_nop,
811 .insert_start = jpeg_v2_0_dec_ring_insert_start,
812 .insert_end = jpeg_v2_0_dec_ring_insert_end,
813 .pad_ib = amdgpu_ring_generic_pad_ib,
814 .begin_use = amdgpu_jpeg_ring_begin_use,
815 .end_use = amdgpu_jpeg_ring_end_use,
816 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
817 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
818 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
819 .reset = jpeg_v2_0_ring_reset,
820 };
821
jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)822 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
823 {
824 adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;
825 }
826
827 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
828 .set = jpeg_v2_0_set_interrupt_state,
829 .process = jpeg_v2_0_process_interrupt,
830 };
831
jpeg_v2_0_set_irq_funcs(struct amdgpu_device * adev)832 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
833 {
834 adev->jpeg.inst->irq.num_types = 1;
835 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
836 }
837
838 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {
839 .type = AMD_IP_BLOCK_TYPE_JPEG,
840 .major = 2,
841 .minor = 0,
842 .rev = 0,
843 .funcs = &jpeg_v2_0_ip_funcs,
844 };
845
846 /**
847 * jpeg_v2_dec_ring_parse_cs - command submission parser
848 *
849 * @parser: Command submission parser context
850 * @job: the job to parse
851 * @ib: the IB to parse
852 *
853 * Parse the command stream, return -EINVAL for invalid packet,
854 * 0 otherwise
855 */
jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser * parser,struct amdgpu_job * job,struct amdgpu_ib * ib)856 int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
857 struct amdgpu_job *job,
858 struct amdgpu_ib *ib)
859 {
860 u32 i, reg, res, cond, type;
861 struct amdgpu_device *adev = parser->adev;
862
863 for (i = 0; i < ib->length_dw ; i += 2) {
864 reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
865 res = CP_PACKETJ_GET_RES(ib->ptr[i]);
866 cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
867 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
868
869 if (res) /* only support 0 at the moment */
870 return -EINVAL;
871
872 switch (type) {
873 case PACKETJ_TYPE0:
874 if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||
875 reg > JPEG_REG_RANGE_END) {
876 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
877 return -EINVAL;
878 }
879 break;
880 case PACKETJ_TYPE3:
881 if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||
882 reg > JPEG_REG_RANGE_END) {
883 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
884 return -EINVAL;
885 }
886 break;
887 case PACKETJ_TYPE6:
888 if (ib->ptr[i] == CP_PACKETJ_NOP)
889 continue;
890 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
891 return -EINVAL;
892 default:
893 dev_err(adev->dev, "Unknown packet type %d !\n", type);
894 return -EINVAL;
895 }
896 }
897
898 return 0;
899 }
900