1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "hdp_v6_0.h"
25
26 #include "hdp/hdp_6_0_0_offset.h"
27 #include "hdp/hdp_6_0_0_sh_mask.h"
28 #include <uapi/linux/kfd_ioctl.h>
29
30 #define regHDP_CLK_CNTL_V6_1 0xd5
31 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0
32
hdp_v6_0_flush_hdp(struct amdgpu_device * adev,struct amdgpu_ring * ring)33 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
34 struct amdgpu_ring *ring)
35 {
36 if (!ring || !ring->funcs->emit_wreg) {
37 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
38 /* We just need to read back a register to post the write.
39 * Reading back the remapped register causes problems on
40 * some platforms so just read back the memory size register.
41 */
42 if (adev->nbio.funcs->get_memsize)
43 adev->nbio.funcs->get_memsize(adev);
44 } else {
45 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
46 }
47 }
48
hdp_v6_0_update_clock_gating(struct amdgpu_device * adev,bool enable)49 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
50 bool enable)
51 {
52 uint32_t hdp_clk_cntl;
53 uint32_t hdp_mem_pwr_cntl;
54
55 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
56 AMD_CG_SUPPORT_HDP_DS |
57 AMD_CG_SUPPORT_HDP_SD)))
58 return;
59
60 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
61 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1);
62 else
63 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
64 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
65
66 /* Before doing clock/power mode switch,
67 * forced on IPH & RC clock */
68 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
69 RC_MEM_CLK_SOFT_OVERRIDE, 1);
70 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
71 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
72 else
73 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
74
75 /* disable clock and power gating before any changing */
76 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
77 ATOMIC_MEM_POWER_CTRL_EN, 0);
78 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
79 ATOMIC_MEM_POWER_LS_EN, 0);
80 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
81 ATOMIC_MEM_POWER_DS_EN, 0);
82 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
83 ATOMIC_MEM_POWER_SD_EN, 0);
84 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
85 RC_MEM_POWER_CTRL_EN, 0);
86 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
87 RC_MEM_POWER_LS_EN, 0);
88 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
89 RC_MEM_POWER_DS_EN, 0);
90 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
91 RC_MEM_POWER_SD_EN, 0);
92 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
93
94 /* Already disabled above. The actions below are for "enabled" only */
95 if (enable) {
96 /* only one clock gating mode (LS/DS/SD) can be enabled */
97 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
98 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
99 HDP_MEM_POWER_CTRL,
100 ATOMIC_MEM_POWER_SD_EN, 1);
101 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
102 HDP_MEM_POWER_CTRL,
103 RC_MEM_POWER_SD_EN, 1);
104 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
105 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
106 HDP_MEM_POWER_CTRL,
107 ATOMIC_MEM_POWER_LS_EN, 1);
108 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
109 HDP_MEM_POWER_CTRL,
110 RC_MEM_POWER_LS_EN, 1);
111 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
112 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
113 HDP_MEM_POWER_CTRL,
114 ATOMIC_MEM_POWER_DS_EN, 1);
115 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
116 HDP_MEM_POWER_CTRL,
117 RC_MEM_POWER_DS_EN, 1);
118 }
119
120 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
121 * be set for SRAM LS/DS/SD */
122 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
123 AMD_CG_SUPPORT_HDP_SD)) {
124 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
125 ATOMIC_MEM_POWER_CTRL_EN, 1);
126 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
127 RC_MEM_POWER_CTRL_EN, 1);
128 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
129 }
130 }
131
132 /* disable IPH & RC clock override after clock/power mode changing */
133 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
134 RC_MEM_CLK_SOFT_OVERRIDE, 0);
135 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0))
136 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl);
137 else
138 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
139 }
140
hdp_v6_0_get_clockgating_state(struct amdgpu_device * adev,u64 * flags)141 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
142 u64 *flags)
143 {
144 uint32_t tmp;
145
146 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
147 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
148 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
149 *flags |= AMD_CG_SUPPORT_HDP_LS;
150 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
151 *flags |= AMD_CG_SUPPORT_HDP_DS;
152 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
153 *flags |= AMD_CG_SUPPORT_HDP_SD;
154 }
155
156 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
157 .flush_hdp = hdp_v6_0_flush_hdp,
158 .update_clock_gating = hdp_v6_0_update_clock_gating,
159 .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
160 };
161