1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/kernel.h>
25 
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include "soc15.h"
29 #include "soc15d.h"
30 #include "amdgpu_pm.h"
31 
32 #include "gc/gc_9_4_1_offset.h"
33 #include "gc/gc_9_4_1_sh_mask.h"
34 #include "soc15_common.h"
35 
36 #include "gfx_v9_4.h"
37 #include "amdgpu_ras.h"
38 
39 static const struct soc15_reg_entry gfx_v9_4_edc_counter_regs[] = {
40 	/* CPC */
41 	{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
42 	{ SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
43 	/* DC */
44 	{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
45 	{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
46 	{ SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
47 	/* CPF */
48 	{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
49 	{ SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
50 	/* GDS */
51 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
52 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 },
53 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 },
54 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
55 	{ SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
56 	/* SPI */
57 	{ SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
58 	/* SQ */
59 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 8, 16 },
60 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 8, 16 },
61 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 8, 16 },
62 	{ SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 8, 16 },
63 	/* SQC */
64 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6 },
65 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6 },
66 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6 },
67 	{ SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 0, 4, 6 },
68 	/* TA */
69 	{ SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16 },
70 	/* TCA */
71 	{ SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2 },
72 	/* TCC */
73 	{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16 },
74 	{ SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16 },
75 	/* TCI */
76 	{ SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72 },
77 	/* TCP */
78 	{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16 },
79 	{ SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16 },
80 	{ SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16 },
81 	/* TD */
82 	{ SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16 },
83 	/* GCEA */
84 	{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32 },
85 	{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32 },
86 	{ SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 1, 32 },
87 	/* RLC */
88 	{ SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT), 0, 1, 1 },
89 	{ SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2), 0, 1, 1 },
90 };
91 
gfx_v9_4_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)92 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,
93 				  u32 sh_num, u32 instance)
94 {
95 	u32 data;
96 
97 	if (instance == 0xffffffff)
98 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
99 				     INSTANCE_BROADCAST_WRITES, 1);
100 	else
101 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
102 				     instance);
103 
104 	if (se_num == 0xffffffff)
105 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
106 				     1);
107 	else
108 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
109 
110 	if (sh_num == 0xffffffff)
111 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
112 				     1);
113 	else
114 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
115 
116 	WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
117 }
118 
119 static const struct soc15_ras_field_entry gfx_v9_4_ras_fields[] = {
120 	/* CPC */
121 	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
122 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
123 	  SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
124 	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
125 	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
126 	  SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
127 	{ "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
128 	  SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
129 	  SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
130 	{ "CPC_DC_CSINVOC_RAM_ME1",
131 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
132 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
133 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
134 	{ "CPC_DC_RESTORE_RAM_ME1",
135 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
136 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
137 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
138 	{ "CPC_DC_CSINVOC_RAM1_ME1",
139 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
140 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
141 	  SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
142 	{ "CPC_DC_RESTORE_RAM1_ME1",
143 	  SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
144 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
145 	  SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
146 
147 	/* CPF */
148 	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
149 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
150 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
151 	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
152 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
153 	  SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
154 	{ "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
155 	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
156 	  SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
157 
158 	/* GDS */
159 	{ "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT),
160 	  SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
161 	  SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
162 	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
163 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
164 	  SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
165 	{ "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
166 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
167 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
168 	{ "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
169 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
170 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
171 	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
172 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
173 	  SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
174 	{ "GDS_ME1_PIPE0_PIPE_MEM",
175 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
176 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
177 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
178 	{ "GDS_ME1_PIPE1_PIPE_MEM",
179 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
180 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
181 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
182 	{ "GDS_ME1_PIPE2_PIPE_MEM",
183 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
184 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
185 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
186 	{ "GDS_ME1_PIPE3_PIPE_MEM",
187 	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
188 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
189 	  SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
190 
191 	/* SPI */
192 	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
193 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
194 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
195 	{ "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
196 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
197 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
198 	{ "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
199 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
200 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
201 	{ "SPI_WB_GRANT_61", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
202 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_SEC_COUNT),
203 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_DED_COUNT) },
204 	{ "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
205 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
206 	  SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
207 
208 	/* SQ */
209 	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
210 	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
211 	  SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
212 	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
213 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
214 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
215 	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
216 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
217 	  SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
218 	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
219 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
220 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
221 	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
222 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
223 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
224 	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
225 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
226 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
227 	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
228 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
229 	  SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
230 
231 	/* SQC */
232 	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
233 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
234 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
235 	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
236 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
237 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
238 	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
239 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
240 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
241 	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
242 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
243 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
244 	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
245 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
246 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
247 	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
248 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
249 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
250 	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
251 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
252 	  SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
253 	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
254 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
255 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
256 	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO",
257 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
258 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
259 			  INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
260 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
261 			  INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
262 	{ "SQC_INST_BANKA_MISS_FIFO",
263 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
264 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
265 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
266 			  INST_BANKA_MISS_FIFO_DED_COUNT) },
267 	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
268 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
269 	  SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
270 	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
271 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
272 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
273 	{ "SQC_DATA_BANKA_HIT_FIFO",
274 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
275 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
276 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
277 	{ "SQC_DATA_BANKA_MISS_FIFO",
278 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
279 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
280 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
281 			  DATA_BANKA_MISS_FIFO_DED_COUNT) },
282 	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
283 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
284 	  SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
285 	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
286 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
287 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
288 	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO",
289 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
290 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
291 			  INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
292 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
293 			  INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
294 	{ "SQC_INST_BANKB_MISS_FIFO",
295 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
296 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
297 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
298 			  INST_BANKB_MISS_FIFO_DED_COUNT) },
299 	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
300 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
301 	  SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
302 	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
303 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
304 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
305 	{ "SQC_DATA_BANKB_HIT_FIFO",
306 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
307 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
308 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
309 	{ "SQC_DATA_BANKB_MISS_FIFO",
310 	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
311 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
312 	  SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
313 			  DATA_BANKB_MISS_FIFO_DED_COUNT) },
314 	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
315 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
316 	  SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
317 
318 	/* TA */
319 	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
320 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
321 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
322 	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
323 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SEC_COUNT),
324 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_DED_COUNT) },
325 	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
326 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
327 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
328 	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
329 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
330 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
331 	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
332 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
333 	  SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
334 
335 	/* TCA */
336 	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
337 	  SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
338 	  SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
339 	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
340 	  SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
341 	  SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
342 
343 	/* TCC */
344 	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
345 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
346 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
347 	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
348 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
349 	  SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
350 	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
351 	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
352 	  SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
353 	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
354 	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
355 	  SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
356 	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
357 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
358 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
359 	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
360 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
361 	  SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
362 	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
363 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
364 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
365 	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
366 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
367 	  SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
368 	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
369 	  SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
370 	  SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
371 	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
372 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
373 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
374 	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
375 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
376 	  SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
377 	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
378 	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
379 	  SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
380 	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
381 	  SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
382 	  SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
383 	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
384 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
385 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
386 	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
387 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
388 	  SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
389 
390 	/* TCI */
391 	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
392 	  SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
393 	  SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
394 
395 	/* TCP */
396 	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
397 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
398 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
399 	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
400 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
401 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
402 	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
403 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
404 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
405 	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
406 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
407 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
408 	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
409 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0, 0 },
410 	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
411 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
412 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
413 	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
414 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
415 	  SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
416 
417 	/* TD */
418 	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
419 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
420 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
421 	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
422 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
423 	  SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
424 	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
425 	  SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
426 	  SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
427 
428 	/* EA */
429 	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
430 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
431 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
432 	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
433 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
434 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
435 	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
436 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
437 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
438 	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
439 	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
440 	  SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
441 	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
442 	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
443 	  SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
444 	{ "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
445 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
446 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
447 	{ "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
448 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
449 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
450 	{ "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
451 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
452 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
453 	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
454 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
455 	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
456 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
457 	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
458 	  SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 },
459 	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
460 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
461 	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
462 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
463 	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
464 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
465 	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
466 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 },
467 	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
468 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
469 	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
470 	  SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0, 0 },
471 	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
472 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_DATAMEM_DED_COUNT) },
473 	{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
474 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 },
475 	{ "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
476 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
477 	{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
478 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
479 	{ "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
480 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
481 	{ "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
482 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
483 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
484 	{ "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
485 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
486 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
487 	{ "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
488 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
489 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
490 	{ "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
491 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
492 	  SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
493 	{ "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
494 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
495 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
496 	{ "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
497 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
498 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
499 	{ "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
500 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
501 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
502 	{ "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
503 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
504 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
505 	{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
506 	  SOC15_REG_FIELD(GCEA_EDC_CNT, MAM_AFMEM_SEC_COUNT), 0, 0 },
507 	{ "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
508 	  SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
509 
510 	/* RLC */
511 	{ "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
512 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
513 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
514 	{ "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
515 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
516 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
517 	{ "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
518 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
519 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
520 	{ "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
521 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
522 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
523 	{ "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
524 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
525 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
526 	{ "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
527 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
528 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
529 	{ "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
530 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
531 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
532 	{ "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
533 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
534 	  SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
535 	{ "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
536 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
537 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
538 	{ "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
539 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
540 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
541 	{ "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
542 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
543 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
544 	{ "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
545 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
546 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
547 	{ "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
548 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
549 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
550 	{ "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
551 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
552 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
553 	{ "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
554 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
555 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
556 	{ "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
557 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
558 	  SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
559 };
560 
561 static const char * const vml2_mems[] = {
562 	"UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
563 	"UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
564 	"UTC_VML2_BANK_CACHE_0_4K_MEM0",
565 	"UTC_VML2_BANK_CACHE_0_4K_MEM1",
566 	"UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
567 	"UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
568 	"UTC_VML2_BANK_CACHE_1_4K_MEM0",
569 	"UTC_VML2_BANK_CACHE_1_4K_MEM1",
570 	"UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
571 	"UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
572 	"UTC_VML2_BANK_CACHE_2_4K_MEM0",
573 	"UTC_VML2_BANK_CACHE_2_4K_MEM1",
574 	"UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
575 	"UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
576 	"UTC_VML2_BANK_CACHE_3_4K_MEM0",
577 	"UTC_VML2_BANK_CACHE_3_4K_MEM1",
578 	"UTC_VML2_IFIFO_GROUP0",
579 	"UTC_VML2_IFIFO_GROUP1",
580 	"UTC_VML2_IFIFO_GROUP2",
581 	"UTC_VML2_IFIFO_GROUP3",
582 	"UTC_VML2_IFIFO_GROUP4",
583 	"UTC_VML2_IFIFO_GROUP5",
584 	"UTC_VML2_IFIFO_GROUP6",
585 	"UTC_VML2_IFIFO_GROUP7",
586 	"UTC_VML2_IFIFO_GROUP8",
587 	"UTC_VML2_IFIFO_GROUP9",
588 	"UTC_VML2_IFIFO_GROUP10",
589 	"UTC_VML2_IFIFO_GROUP11",
590 	"UTC_VML2_IFIFO_GROUP12",
591 	"UTC_VML2_IFIFO_GROUP13",
592 	"UTC_VML2_IFIFO_GROUP14",
593 	"UTC_VML2_IFIFO_GROUP15",
594 	"UTC_VML2_IFIFO_GROUP16",
595 	"UTC_VML2_IFIFO_GROUP17",
596 	"UTC_VML2_IFIFO_GROUP18",
597 	"UTC_VML2_IFIFO_GROUP19",
598 	"UTC_VML2_IFIFO_GROUP20",
599 	"UTC_VML2_IFIFO_GROUP21",
600 	"UTC_VML2_IFIFO_GROUP22",
601 	"UTC_VML2_IFIFO_GROUP23",
602 	"UTC_VML2_IFIFO_GROUP24",
603 };
604 
605 static const char * const vml2_walker_mems[] = {
606 	"UTC_VML2_CACHE_PDE0_MEM0",
607 	"UTC_VML2_CACHE_PDE0_MEM1",
608 	"UTC_VML2_CACHE_PDE1_MEM0",
609 	"UTC_VML2_CACHE_PDE1_MEM1",
610 	"UTC_VML2_CACHE_PDE2_MEM0",
611 	"UTC_VML2_CACHE_PDE2_MEM1",
612 	"UTC_VML2_RDIF_ARADDRS",
613 	"UTC_VML2_RDIF_LOG_FIFO",
614 	"UTC_VML2_QUEUE_REQ",
615 	"UTC_VML2_QUEUE_RET",
616 };
617 
618 static const char * const utcl2_router_mems[] = {
619 	"UTCL2_ROUTER_GROUP0_VML2_REQ_FIFO0",
620 	"UTCL2_ROUTER_GROUP1_VML2_REQ_FIFO1",
621 	"UTCL2_ROUTER_GROUP2_VML2_REQ_FIFO2",
622 	"UTCL2_ROUTER_GROUP3_VML2_REQ_FIFO3",
623 	"UTCL2_ROUTER_GROUP4_VML2_REQ_FIFO4",
624 	"UTCL2_ROUTER_GROUP5_VML2_REQ_FIFO5",
625 	"UTCL2_ROUTER_GROUP6_VML2_REQ_FIFO6",
626 	"UTCL2_ROUTER_GROUP7_VML2_REQ_FIFO7",
627 	"UTCL2_ROUTER_GROUP8_VML2_REQ_FIFO8",
628 	"UTCL2_ROUTER_GROUP9_VML2_REQ_FIFO9",
629 	"UTCL2_ROUTER_GROUP10_VML2_REQ_FIFO10",
630 	"UTCL2_ROUTER_GROUP11_VML2_REQ_FIFO11",
631 	"UTCL2_ROUTER_GROUP12_VML2_REQ_FIFO12",
632 	"UTCL2_ROUTER_GROUP13_VML2_REQ_FIFO13",
633 	"UTCL2_ROUTER_GROUP14_VML2_REQ_FIFO14",
634 	"UTCL2_ROUTER_GROUP15_VML2_REQ_FIFO15",
635 	"UTCL2_ROUTER_GROUP16_VML2_REQ_FIFO16",
636 	"UTCL2_ROUTER_GROUP17_VML2_REQ_FIFO17",
637 	"UTCL2_ROUTER_GROUP18_VML2_REQ_FIFO18",
638 	"UTCL2_ROUTER_GROUP19_VML2_REQ_FIFO19",
639 	"UTCL2_ROUTER_GROUP20_VML2_REQ_FIFO20",
640 	"UTCL2_ROUTER_GROUP21_VML2_REQ_FIFO21",
641 	"UTCL2_ROUTER_GROUP22_VML2_REQ_FIFO22",
642 	"UTCL2_ROUTER_GROUP23_VML2_REQ_FIFO23",
643 	"UTCL2_ROUTER_GROUP24_VML2_REQ_FIFO24",
644 };
645 
646 static const char * const atc_l2_cache_2m_mems[] = {
647 	"UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
648 	"UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
649 	"UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
650 	"UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
651 };
652 
653 static const char * const atc_l2_cache_4k_mems[] = {
654 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
655 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
656 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
657 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
658 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
659 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
660 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
661 	"UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
662 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
663 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
664 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
665 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
666 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
667 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
668 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
669 	"UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
670 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
671 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
672 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
673 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
674 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
675 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
676 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
677 	"UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
678 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
679 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
680 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
681 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
682 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
683 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
684 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
685 	"UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
686 };
687 
gfx_v9_4_query_utc_edc_status(struct amdgpu_device * adev,struct ras_err_data * err_data)688 static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
689 					 struct ras_err_data *err_data)
690 {
691 	uint32_t i, data;
692 	uint32_t sec_count, ded_count;
693 
694 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
695 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
696 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
697 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
698 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
699 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
700 
701 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
702 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
703 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
704 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
705 
706 	for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
707 		WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
708 		data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
709 
710 		sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
711 		if (sec_count) {
712 			dev_info(adev->dev,
713 				 "Instance[%d]: SubBlock %s, SEC %d\n", i,
714 				 vml2_mems[i], sec_count);
715 			err_data->ce_count += sec_count;
716 		}
717 
718 		ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
719 		if (ded_count) {
720 			dev_info(adev->dev,
721 				 "Instance[%d]: SubBlock %s, DED %d\n", i,
722 				 vml2_mems[i], ded_count);
723 			err_data->ue_count += ded_count;
724 		}
725 	}
726 
727 	for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
728 		WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
729 		data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
730 
731 		sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
732 					  SEC_COUNT);
733 		if (sec_count) {
734 			dev_info(adev->dev,
735 				 "Instance[%d]: SubBlock %s, SEC %d\n", i,
736 				 vml2_walker_mems[i], sec_count);
737 			err_data->ce_count += sec_count;
738 		}
739 
740 		ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
741 					  DED_COUNT);
742 		if (ded_count) {
743 			dev_info(adev->dev,
744 				 "Instance[%d]: SubBlock %s, DED %d\n", i,
745 				 vml2_walker_mems[i], ded_count);
746 			err_data->ue_count += ded_count;
747 		}
748 	}
749 
750 	for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
751 		WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
752 		data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
753 
754 		sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);
755 		if (sec_count) {
756 			dev_info(adev->dev,
757 				 "Instance[%d]: SubBlock %s, SEC %d\n", i,
758 				 utcl2_router_mems[i], sec_count);
759 			err_data->ce_count += sec_count;
760 		}
761 
762 		ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);
763 		if (ded_count) {
764 			dev_info(adev->dev,
765 				 "Instance[%d]: SubBlock %s, DED %d\n", i,
766 				 utcl2_router_mems[i], ded_count);
767 			err_data->ue_count += ded_count;
768 		}
769 	}
770 
771 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
772 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
773 		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
774 
775 		sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
776 					  SEC_COUNT);
777 		if (sec_count) {
778 			dev_info(adev->dev,
779 				 "Instance[%d]: SubBlock %s, SEC %d\n", i,
780 				 atc_l2_cache_2m_mems[i], sec_count);
781 			err_data->ce_count += sec_count;
782 		}
783 
784 		ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
785 					  DED_COUNT);
786 		if (ded_count) {
787 			dev_info(adev->dev,
788 				 "Instance[%d]: SubBlock %s, DED %d\n", i,
789 				 atc_l2_cache_2m_mems[i], ded_count);
790 			err_data->ue_count += ded_count;
791 		}
792 	}
793 
794 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
795 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
796 		data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
797 
798 		sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
799 					  SEC_COUNT);
800 		if (sec_count) {
801 			dev_info(adev->dev,
802 				 "Instance[%d]: SubBlock %s, SEC %d\n", i,
803 				 atc_l2_cache_4k_mems[i], sec_count);
804 			err_data->ce_count += sec_count;
805 		}
806 
807 		ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
808 					  DED_COUNT);
809 		if (ded_count) {
810 			dev_info(adev->dev,
811 				 "Instance[%d]: SubBlock %s, DED %d\n", i,
812 				 atc_l2_cache_4k_mems[i], ded_count);
813 			err_data->ue_count += ded_count;
814 		}
815 	}
816 
817 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
818 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
819 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
820 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
821 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
822 
823 	return 0;
824 }
825 
gfx_v9_4_ras_error_count(struct amdgpu_device * adev,const struct soc15_reg_entry * reg,uint32_t se_id,uint32_t inst_id,uint32_t value,uint32_t * sec_count,uint32_t * ded_count)826 static int gfx_v9_4_ras_error_count(struct amdgpu_device *adev,
827 				    const struct soc15_reg_entry *reg,
828 				    uint32_t se_id, uint32_t inst_id,
829 				    uint32_t value, uint32_t *sec_count,
830 				    uint32_t *ded_count)
831 {
832 	uint32_t i;
833 	uint32_t sec_cnt, ded_cnt;
834 
835 	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_ras_fields); i++) {
836 		if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||
837 		    gfx_v9_4_ras_fields[i].seg != reg->seg ||
838 		    gfx_v9_4_ras_fields[i].inst != reg->inst)
839 			continue;
840 
841 		sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >>
842 			  gfx_v9_4_ras_fields[i].sec_count_shift;
843 		if (sec_cnt) {
844 			dev_info(adev->dev,
845 				 "GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
846 				 gfx_v9_4_ras_fields[i].name, se_id, inst_id,
847 				 sec_cnt);
848 			*sec_count += sec_cnt;
849 		}
850 
851 		ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >>
852 			  gfx_v9_4_ras_fields[i].ded_count_shift;
853 		if (ded_cnt) {
854 			dev_info(adev->dev,
855 				 "GFX SubBlock %s, Instance[%d][%d], DED %d\n",
856 				 gfx_v9_4_ras_fields[i].name, se_id, inst_id,
857 				 ded_cnt);
858 			*ded_count += ded_cnt;
859 		}
860 	}
861 
862 	return 0;
863 }
864 
gfx_v9_4_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)865 static void gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
866 					  void *ras_error_status)
867 {
868 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
869 	uint32_t sec_count = 0, ded_count = 0;
870 	uint32_t i, j, k;
871 	uint32_t reg_value;
872 
873 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
874 		return;
875 
876 	err_data->ue_count = 0;
877 	err_data->ce_count = 0;
878 
879 	mutex_lock(&adev->grbm_idx_mutex);
880 
881 	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
882 		for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
883 			for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
884 			     k++) {
885 				gfx_v9_4_select_se_sh(adev, j, 0, k);
886 				reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
887 					gfx_v9_4_edc_counter_regs[i]));
888 				if (reg_value)
889 					gfx_v9_4_ras_error_count(adev,
890 						&gfx_v9_4_edc_counter_regs[i],
891 						j, k, reg_value, &sec_count,
892 						&ded_count);
893 			}
894 		}
895 	}
896 
897 	err_data->ce_count += sec_count;
898 	err_data->ue_count += ded_count;
899 
900 	gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
901 	mutex_unlock(&adev->grbm_idx_mutex);
902 
903 	gfx_v9_4_query_utc_edc_status(adev, err_data);
904 
905 }
906 
gfx_v9_4_reset_ras_error_count(struct amdgpu_device * adev)907 static void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
908 {
909 	int i, j, k;
910 
911 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
912 		return;
913 
914 	mutex_lock(&adev->grbm_idx_mutex);
915 	for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
916 		for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
917 			for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
918 			     k++) {
919 				gfx_v9_4_select_se_sh(adev, j, 0x0, k);
920 				RREG32(SOC15_REG_ENTRY_OFFSET(
921 					gfx_v9_4_edc_counter_regs[i]));
922 			}
923 		}
924 	}
925 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
926 	mutex_unlock(&adev->grbm_idx_mutex);
927 
928 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
929 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
930 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
931 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
932 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
933 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
934 
935 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
936 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
937 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
938 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
939 
940 	for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
941 		WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
942 		RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
943 	}
944 
945 	for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
946 		WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
947 		RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
948 	}
949 
950 	for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
951 		WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
952 		RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
953 	}
954 
955 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
956 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
957 		RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
958 	}
959 
960 	for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
961 		WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
962 		RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
963 	}
964 
965 	WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
966 	WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
967 	WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
968 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
969 	WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
970 }
971 
972 static const struct soc15_reg_entry gfx_v9_4_ea_err_status_regs = {
973 	SOC15_REG_ENTRY(GC, 0, mmGCEA_ERR_STATUS), 0, 1, 32
974 };
975 
gfx_v9_4_query_ras_error_status(struct amdgpu_device * adev)976 static void gfx_v9_4_query_ras_error_status(struct amdgpu_device *adev)
977 {
978 	uint32_t i, j;
979 	uint32_t reg_value;
980 
981 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
982 		return;
983 
984 	mutex_lock(&adev->grbm_idx_mutex);
985 
986 	for (i = 0; i < gfx_v9_4_ea_err_status_regs.se_num; i++) {
987 		for (j = 0; j < gfx_v9_4_ea_err_status_regs.instance;
988 		     j++) {
989 			gfx_v9_4_select_se_sh(adev, i, 0, j);
990 			reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
991 				gfx_v9_4_ea_err_status_regs));
992 			if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
993 			    REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
994 			    REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
995 				/* SDP read/write error/parity error in FUE_IS_FATAL mode
996 				 * can cause system fatal error in arcturas. Harvest the error
997 				 * status before GPU reset */
998 				dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
999 						j, reg_value);
1000 			}
1001 		}
1002 	}
1003 
1004 	gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1005 	mutex_unlock(&adev->grbm_idx_mutex);
1006 }
1007 
1008 
1009 const struct amdgpu_ras_block_hw_ops  gfx_v9_4_ras_ops = {
1010 	.query_ras_error_count = &gfx_v9_4_query_ras_error_count,
1011 	.reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
1012 	.query_ras_error_status = &gfx_v9_4_query_ras_error_status,
1013 };
1014 
1015 struct amdgpu_gfx_ras gfx_v9_4_ras = {
1016 	.ras_block = {
1017 		.hw_ops = &gfx_v9_4_ras_ops,
1018 	},
1019 };
1020