1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_smu.h"
32 #include "imu_v12_0.h"
33 #include "soc24.h"
34 #include "nvd.h"
35
36 #include "gc/gc_12_0_0_offset.h"
37 #include "gc/gc_12_0_0_sh_mask.h"
38 #include "soc24_enum.h"
39 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
40
41 #include "soc15.h"
42 #include "clearstate_gfx12.h"
43 #include "v12_structs.h"
44 #include "gfx_v12_0.h"
45 #include "nbif_v6_3_1.h"
46 #include "mes_v12_0.h"
47
48 #define GFX12_NUM_GFX_RINGS 1
49 #define GFX12_MEC_HPD_SIZE 2048
50
51 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
52
53 #define regCP_GFX_MQD_CONTROL_DEFAULT 0x00000100
54 #define regCP_GFX_HQD_VMID_DEFAULT 0x00000000
55 #define regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT 0x00000000
56 #define regCP_GFX_HQD_QUANTUM_DEFAULT 0x00000a01
57 #define regCP_GFX_HQD_CNTL_DEFAULT 0x00f00000
58 #define regCP_RB_DOORBELL_CONTROL_DEFAULT 0x00000000
59 #define regCP_GFX_HQD_RPTR_DEFAULT 0x00000000
60
61 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000006
62 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
63 #define regCP_MQD_CONTROL_DEFAULT 0x00000100
64 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509
65 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000
66 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000
67 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0be05501
68 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00300000
69
70
71 MODULE_FIRMWARE("amdgpu/gc_12_0_0_pfp.bin");
72 MODULE_FIRMWARE("amdgpu/gc_12_0_0_me.bin");
73 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mec.bin");
74 MODULE_FIRMWARE("amdgpu/gc_12_0_0_rlc.bin");
75 MODULE_FIRMWARE("amdgpu/gc_12_0_0_toc.bin");
76 MODULE_FIRMWARE("amdgpu/gc_12_0_1_pfp.bin");
77 MODULE_FIRMWARE("amdgpu/gc_12_0_1_me.bin");
78 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mec.bin");
79 MODULE_FIRMWARE("amdgpu/gc_12_0_1_rlc.bin");
80 MODULE_FIRMWARE("amdgpu/gc_12_0_1_toc.bin");
81
82 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_0[] = {
83 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
84 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
85 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
86 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
87 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
88 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
114 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
115 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
116 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
118 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
121 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
124 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
125 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
126 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
127 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
128 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
136
137 /* cp header registers */
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
139 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 /* SE status registers */
143 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
144 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
145 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
146 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
147 };
148
149 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12[] = {
150 /* compute registers */
151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
190 };
191
192 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = {
193 /* gfx queue registers */
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
196 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
205 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
206 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
207 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
208 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
219 };
220
221 static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = {
222 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
223 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
224 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
225 };
226
227 static const struct soc15_reg_golden golden_settings_gc_12_0[] = {
228 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
229 };
230
231 #define DEFAULT_SH_MEM_CONFIG \
232 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
233 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
234 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
235
236 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev);
237 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev);
238 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev);
239 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev);
240 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev);
241 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev);
242 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
243 struct amdgpu_cu_info *cu_info);
244 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev);
245 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
246 u32 sh_num, u32 instance, int xcc_id);
247 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
248
249 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
250 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
251 uint32_t val);
252 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
253 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
254 uint16_t pasid, uint32_t flush_type,
255 bool all_hub, uint8_t dst_sel);
256 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
257 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
258 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
259 bool enable);
260
gfx_v12_0_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)261 static void gfx_v12_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
262 uint64_t queue_mask)
263 {
264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
265 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
266 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
267 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
268 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
269 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
270 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
271 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
272 amdgpu_ring_write(kiq_ring, 0);
273 }
274
gfx_v12_0_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)275 static void gfx_v12_0_kiq_map_queues(struct amdgpu_ring *kiq_ring,
276 struct amdgpu_ring *ring)
277 {
278 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
279 uint64_t wptr_addr = ring->wptr_gpu_addr;
280 uint32_t me = 0, eng_sel = 0;
281
282 switch (ring->funcs->type) {
283 case AMDGPU_RING_TYPE_COMPUTE:
284 me = 1;
285 eng_sel = 0;
286 break;
287 case AMDGPU_RING_TYPE_GFX:
288 me = 0;
289 eng_sel = 4;
290 break;
291 case AMDGPU_RING_TYPE_MES:
292 me = 2;
293 eng_sel = 5;
294 break;
295 default:
296 WARN_ON(1);
297 }
298
299 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
300 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
301 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
302 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
303 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
304 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
305 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
306 PACKET3_MAP_QUEUES_ME((me)) |
307 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
308 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
309 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
310 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
311 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
312 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
313 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
314 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
315 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
316 }
317
gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)318 static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
319 struct amdgpu_ring *ring,
320 enum amdgpu_unmap_queues_action action,
321 u64 gpu_addr, u64 seq)
322 {
323 struct amdgpu_device *adev = kiq_ring->adev;
324 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
325
326 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
327 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
328 return;
329 }
330
331 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
332 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
333 PACKET3_UNMAP_QUEUES_ACTION(action) |
334 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
335 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
336 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
337 amdgpu_ring_write(kiq_ring,
338 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
339
340 if (action == PREEMPT_QUEUES_NO_UNMAP) {
341 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
342 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
343 amdgpu_ring_write(kiq_ring, seq);
344 } else {
345 amdgpu_ring_write(kiq_ring, 0);
346 amdgpu_ring_write(kiq_ring, 0);
347 amdgpu_ring_write(kiq_ring, 0);
348 }
349 }
350
gfx_v12_0_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)351 static void gfx_v12_0_kiq_query_status(struct amdgpu_ring *kiq_ring,
352 struct amdgpu_ring *ring,
353 u64 addr, u64 seq)
354 {
355 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
356
357 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
358 amdgpu_ring_write(kiq_ring,
359 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
360 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
361 PACKET3_QUERY_STATUS_COMMAND(2));
362 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
363 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
364 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
365 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
366 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
367 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
368 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
369 }
370
gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)371 static void gfx_v12_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
372 uint16_t pasid,
373 uint32_t flush_type,
374 bool all_hub)
375 {
376 gfx_v12_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
377 }
378
379 static const struct kiq_pm4_funcs gfx_v12_0_kiq_pm4_funcs = {
380 .kiq_set_resources = gfx_v12_0_kiq_set_resources,
381 .kiq_map_queues = gfx_v12_0_kiq_map_queues,
382 .kiq_unmap_queues = gfx_v12_0_kiq_unmap_queues,
383 .kiq_query_status = gfx_v12_0_kiq_query_status,
384 .kiq_invalidate_tlbs = gfx_v12_0_kiq_invalidate_tlbs,
385 .set_resources_size = 8,
386 .map_queues_size = 7,
387 .unmap_queues_size = 6,
388 .query_status_size = 7,
389 .invalidate_tlbs_size = 2,
390 };
391
gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)392 static void gfx_v12_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
393 {
394 adev->gfx.kiq[0].pmf = &gfx_v12_0_kiq_pm4_funcs;
395 }
396
gfx_v12_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)397 static void gfx_v12_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
398 int mem_space, int opt, uint32_t addr0,
399 uint32_t addr1, uint32_t ref,
400 uint32_t mask, uint32_t inv)
401 {
402 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
403 amdgpu_ring_write(ring,
404 /* memory (1) or register (0) */
405 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
406 WAIT_REG_MEM_OPERATION(opt) | /* wait */
407 WAIT_REG_MEM_FUNCTION(3) | /* equal */
408 WAIT_REG_MEM_ENGINE(eng_sel)));
409
410 if (mem_space)
411 BUG_ON(addr0 & 0x3); /* Dword align */
412 amdgpu_ring_write(ring, addr0);
413 amdgpu_ring_write(ring, addr1);
414 amdgpu_ring_write(ring, ref);
415 amdgpu_ring_write(ring, mask);
416 amdgpu_ring_write(ring, inv); /* poll interval */
417 }
418
gfx_v12_0_ring_test_ring(struct amdgpu_ring * ring)419 static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring)
420 {
421 struct amdgpu_device *adev = ring->adev;
422 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
423 uint32_t tmp = 0;
424 unsigned i;
425 int r;
426
427 WREG32(scratch, 0xCAFEDEAD);
428 r = amdgpu_ring_alloc(ring, 5);
429 if (r) {
430 dev_err(adev->dev,
431 "amdgpu: cp failed to lock ring %d (%d).\n",
432 ring->idx, r);
433 return r;
434 }
435
436 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
437 gfx_v12_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
438 } else {
439 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
440 amdgpu_ring_write(ring, scratch -
441 PACKET3_SET_UCONFIG_REG_START);
442 amdgpu_ring_write(ring, 0xDEADBEEF);
443 }
444 amdgpu_ring_commit(ring);
445
446 for (i = 0; i < adev->usec_timeout; i++) {
447 tmp = RREG32(scratch);
448 if (tmp == 0xDEADBEEF)
449 break;
450 if (amdgpu_emu_mode == 1)
451 msleep(1);
452 else
453 udelay(1);
454 }
455
456 if (i >= adev->usec_timeout)
457 r = -ETIMEDOUT;
458 return r;
459 }
460
gfx_v12_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)461 static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
462 {
463 struct amdgpu_device *adev = ring->adev;
464 struct amdgpu_ib ib;
465 struct dma_fence *f = NULL;
466 unsigned index;
467 uint64_t gpu_addr;
468 volatile uint32_t *cpu_ptr;
469 long r;
470
471 /* MES KIQ fw hasn't indirect buffer support for now */
472 if (adev->enable_mes_kiq &&
473 ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
474 return 0;
475
476 memset(&ib, 0, sizeof(ib));
477
478 if (ring->is_mes_queue) {
479 uint32_t padding, offset;
480
481 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
482 padding = amdgpu_mes_ctx_get_offs(ring,
483 AMDGPU_MES_CTX_PADDING_OFFS);
484
485 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
486 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
487
488 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
489 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
490 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
491 } else {
492 r = amdgpu_device_wb_get(adev, &index);
493 if (r)
494 return r;
495
496 gpu_addr = adev->wb.gpu_addr + (index * 4);
497 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
498 cpu_ptr = &adev->wb.wb[index];
499
500 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
501 if (r) {
502 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r);
503 goto err1;
504 }
505 }
506
507 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
508 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
509 ib.ptr[2] = lower_32_bits(gpu_addr);
510 ib.ptr[3] = upper_32_bits(gpu_addr);
511 ib.ptr[4] = 0xDEADBEEF;
512 ib.length_dw = 5;
513
514 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
515 if (r)
516 goto err2;
517
518 r = dma_fence_wait_timeout(f, false, timeout);
519 if (r == 0) {
520 r = -ETIMEDOUT;
521 goto err2;
522 } else if (r < 0) {
523 goto err2;
524 }
525
526 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
527 r = 0;
528 else
529 r = -EINVAL;
530 err2:
531 if (!ring->is_mes_queue)
532 amdgpu_ib_free(&ib, NULL);
533 dma_fence_put(f);
534 err1:
535 if (!ring->is_mes_queue)
536 amdgpu_device_wb_free(adev, index);
537 return r;
538 }
539
gfx_v12_0_free_microcode(struct amdgpu_device * adev)540 static void gfx_v12_0_free_microcode(struct amdgpu_device *adev)
541 {
542 amdgpu_ucode_release(&adev->gfx.pfp_fw);
543 amdgpu_ucode_release(&adev->gfx.me_fw);
544 amdgpu_ucode_release(&adev->gfx.rlc_fw);
545 amdgpu_ucode_release(&adev->gfx.mec_fw);
546
547 kfree(adev->gfx.rlc.register_list_format);
548 }
549
gfx_v12_0_init_toc_microcode(struct amdgpu_device * adev,const char * ucode_prefix)550 static int gfx_v12_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
551 {
552 const struct psp_firmware_header_v1_0 *toc_hdr;
553 int err = 0;
554
555 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw,
556 AMDGPU_UCODE_REQUIRED,
557 "amdgpu/%s_toc.bin", ucode_prefix);
558 if (err)
559 goto out;
560
561 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
562 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
563 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
564 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
565 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
566 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
567 return 0;
568 out:
569 amdgpu_ucode_release(&adev->psp.toc_fw);
570 return err;
571 }
572
gfx_v12_0_init_microcode(struct amdgpu_device * adev)573 static int gfx_v12_0_init_microcode(struct amdgpu_device *adev)
574 {
575 char ucode_prefix[15];
576 int err;
577 const struct rlc_firmware_header_v2_0 *rlc_hdr;
578 uint16_t version_major;
579 uint16_t version_minor;
580
581 DRM_DEBUG("\n");
582
583 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
584
585 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
586 AMDGPU_UCODE_REQUIRED,
587 "amdgpu/%s_pfp.bin", ucode_prefix);
588 if (err)
589 goto out;
590 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
591 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
592
593 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
594 AMDGPU_UCODE_REQUIRED,
595 "amdgpu/%s_me.bin", ucode_prefix);
596 if (err)
597 goto out;
598 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
599 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
600
601 if (!amdgpu_sriov_vf(adev)) {
602 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
603 AMDGPU_UCODE_REQUIRED,
604 "amdgpu/%s_rlc.bin", ucode_prefix);
605 if (err)
606 goto out;
607 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
608 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
609 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
610 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
611 if (err)
612 goto out;
613 }
614
615 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
616 AMDGPU_UCODE_REQUIRED,
617 "amdgpu/%s_mec.bin", ucode_prefix);
618 if (err)
619 goto out;
620 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
621 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
622 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
623
624 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
625 err = gfx_v12_0_init_toc_microcode(adev, ucode_prefix);
626
627 /* only one MEC for gfx 12 */
628 adev->gfx.mec2_fw = NULL;
629
630 if (adev->gfx.imu.funcs) {
631 if (adev->gfx.imu.funcs->init_microcode) {
632 err = adev->gfx.imu.funcs->init_microcode(adev);
633 if (err)
634 dev_err(adev->dev, "Failed to load imu firmware!\n");
635 }
636 }
637
638 out:
639 if (err) {
640 amdgpu_ucode_release(&adev->gfx.pfp_fw);
641 amdgpu_ucode_release(&adev->gfx.me_fw);
642 amdgpu_ucode_release(&adev->gfx.rlc_fw);
643 amdgpu_ucode_release(&adev->gfx.mec_fw);
644 }
645
646 return err;
647 }
648
gfx_v12_0_get_csb_size(struct amdgpu_device * adev)649 static u32 gfx_v12_0_get_csb_size(struct amdgpu_device *adev)
650 {
651 u32 count = 0;
652 const struct cs_section_def *sect = NULL;
653 const struct cs_extent_def *ext = NULL;
654
655 count += 1;
656
657 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) {
658 if (sect->id == SECT_CONTEXT) {
659 for (ext = sect->section; ext->extent != NULL; ++ext)
660 count += 2 + ext->reg_count;
661 } else
662 return 0;
663 }
664
665 return count;
666 }
667
gfx_v12_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)668 static void gfx_v12_0_get_csb_buffer(struct amdgpu_device *adev,
669 volatile u32 *buffer)
670 {
671 u32 count = 0, clustercount = 0, i;
672 const struct cs_section_def *sect = NULL;
673 const struct cs_extent_def *ext = NULL;
674
675 if (adev->gfx.rlc.cs_data == NULL)
676 return;
677 if (buffer == NULL)
678 return;
679
680 count += 1;
681
682 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
683 if (sect->id == SECT_CONTEXT) {
684 for (ext = sect->section; ext->extent != NULL; ++ext) {
685 clustercount++;
686 buffer[count++] = ext->reg_count;
687 buffer[count++] = ext->reg_index;
688
689 for (i = 0; i < ext->reg_count; i++)
690 buffer[count++] = cpu_to_le32(ext->extent[i]);
691 }
692 } else
693 return;
694 }
695
696 buffer[0] = clustercount;
697 }
698
gfx_v12_0_rlc_fini(struct amdgpu_device * adev)699 static void gfx_v12_0_rlc_fini(struct amdgpu_device *adev)
700 {
701 /* clear state block */
702 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
703 &adev->gfx.rlc.clear_state_gpu_addr,
704 (void **)&adev->gfx.rlc.cs_ptr);
705
706 /* jump table block */
707 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
708 &adev->gfx.rlc.cp_table_gpu_addr,
709 (void **)&adev->gfx.rlc.cp_table_ptr);
710 }
711
gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)712 static void gfx_v12_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
713 {
714 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
715
716 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
717 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
718 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
719 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
720 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
721 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
722 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
723 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
724 adev->gfx.rlc.rlcg_reg_access_supported = true;
725 }
726
gfx_v12_0_rlc_init(struct amdgpu_device * adev)727 static int gfx_v12_0_rlc_init(struct amdgpu_device *adev)
728 {
729 const struct cs_section_def *cs_data;
730 int r;
731
732 adev->gfx.rlc.cs_data = gfx12_cs_data;
733
734 cs_data = adev->gfx.rlc.cs_data;
735
736 if (cs_data) {
737 /* init clear state block */
738 r = amdgpu_gfx_rlc_init_csb(adev);
739 if (r)
740 return r;
741 }
742
743 /* init spm vmid with 0xf */
744 if (adev->gfx.rlc.funcs->update_spm_vmid)
745 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
746
747 return 0;
748 }
749
gfx_v12_0_mec_fini(struct amdgpu_device * adev)750 static void gfx_v12_0_mec_fini(struct amdgpu_device *adev)
751 {
752 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
753 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
754 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
755 }
756
gfx_v12_0_me_init(struct amdgpu_device * adev)757 static void gfx_v12_0_me_init(struct amdgpu_device *adev)
758 {
759 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
760
761 amdgpu_gfx_graphics_queue_acquire(adev);
762 }
763
gfx_v12_0_mec_init(struct amdgpu_device * adev)764 static int gfx_v12_0_mec_init(struct amdgpu_device *adev)
765 {
766 int r;
767 u32 *hpd;
768 size_t mec_hpd_size;
769
770 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
771
772 /* take ownership of the relevant compute queues */
773 amdgpu_gfx_compute_queue_acquire(adev);
774 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE;
775
776 if (mec_hpd_size) {
777 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
778 AMDGPU_GEM_DOMAIN_GTT,
779 &adev->gfx.mec.hpd_eop_obj,
780 &adev->gfx.mec.hpd_eop_gpu_addr,
781 (void **)&hpd);
782 if (r) {
783 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
784 gfx_v12_0_mec_fini(adev);
785 return r;
786 }
787
788 memset(hpd, 0, mec_hpd_size);
789
790 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
791 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
792 }
793
794 return 0;
795 }
796
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)797 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
798 {
799 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
800 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
801 (address << SQ_IND_INDEX__INDEX__SHIFT));
802 return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
803 }
804
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)805 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
806 uint32_t thread, uint32_t regno,
807 uint32_t num, uint32_t *out)
808 {
809 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
810 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
811 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
812 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
813 (SQ_IND_INDEX__AUTO_INCR_MASK));
814 while (num--)
815 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
816 }
817
gfx_v12_0_read_wave_data(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)818 static void gfx_v12_0_read_wave_data(struct amdgpu_device *adev,
819 uint32_t xcc_id,
820 uint32_t simd, uint32_t wave,
821 uint32_t *dst, int *no_fields)
822 {
823 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE
824 * field when performing a select_se_sh so it should be
825 * zero here */
826 WARN_ON(simd != 0);
827
828 /* type 4 wave data */
829 dst[(*no_fields)++] = 4;
830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
832 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
833 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
834 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
835 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
836 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
837 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
838 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
839 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
840 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
841 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
842 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
843 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
844 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV);
845 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV);
846 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER);
847 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL);
848 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE);
849 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE);
850 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO);
851 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI);
852 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE);
853 }
854
gfx_v12_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)855 static void gfx_v12_0_read_wave_sgprs(struct amdgpu_device *adev,
856 uint32_t xcc_id, uint32_t simd,
857 uint32_t wave, uint32_t start,
858 uint32_t size, uint32_t *dst)
859 {
860 WARN_ON(simd != 0);
861
862 wave_read_regs(
863 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
864 dst);
865 }
866
gfx_v12_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t xcc_id,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)867 static void gfx_v12_0_read_wave_vgprs(struct amdgpu_device *adev,
868 uint32_t xcc_id, uint32_t simd,
869 uint32_t wave, uint32_t thread,
870 uint32_t start, uint32_t size,
871 uint32_t *dst)
872 {
873 wave_read_regs(
874 adev, wave, thread,
875 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
876 }
877
gfx_v12_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm,u32 xcc_id)878 static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev,
879 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
880 {
881 soc24_grbm_select(adev, me, pipe, q, vm);
882 }
883
884 static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
885 .get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter,
886 .select_se_sh = &gfx_v12_0_select_se_sh,
887 .read_wave_data = &gfx_v12_0_read_wave_data,
888 .read_wave_sgprs = &gfx_v12_0_read_wave_sgprs,
889 .read_wave_vgprs = &gfx_v12_0_read_wave_vgprs,
890 .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q,
891 .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk,
892 };
893
gfx_v12_0_gpu_early_init(struct amdgpu_device * adev)894 static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)
895 {
896
897 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
898 case IP_VERSION(12, 0, 0):
899 case IP_VERSION(12, 0, 1):
900 adev->gfx.config.max_hw_contexts = 8;
901 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
902 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
903 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
904 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
905 break;
906 default:
907 BUG();
908 break;
909 }
910
911 return 0;
912 }
913
gfx_v12_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)914 static int gfx_v12_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
915 int me, int pipe, int queue)
916 {
917 int r;
918 struct amdgpu_ring *ring;
919 unsigned int irq_type;
920
921 ring = &adev->gfx.gfx_ring[ring_id];
922
923 ring->me = me;
924 ring->pipe = pipe;
925 ring->queue = queue;
926
927 ring->ring_obj = NULL;
928 ring->use_doorbell = true;
929
930 if (!ring_id)
931 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
932 else
933 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
934 ring->vm_hub = AMDGPU_GFXHUB(0);
935 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
936
937 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
938 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
939 AMDGPU_RING_PRIO_DEFAULT, NULL);
940 if (r)
941 return r;
942 return 0;
943 }
944
gfx_v12_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)945 static int gfx_v12_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
946 int mec, int pipe, int queue)
947 {
948 int r;
949 unsigned irq_type;
950 struct amdgpu_ring *ring;
951 unsigned int hw_prio;
952
953 ring = &adev->gfx.compute_ring[ring_id];
954
955 /* mec0 is me1 */
956 ring->me = mec + 1;
957 ring->pipe = pipe;
958 ring->queue = queue;
959
960 ring->ring_obj = NULL;
961 ring->use_doorbell = true;
962 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
963 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
964 + (ring_id * GFX12_MEC_HPD_SIZE);
965 ring->vm_hub = AMDGPU_GFXHUB(0);
966 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
967
968 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
969 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
970 + ring->pipe;
971 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
972 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
973 /* type-2 packets are deprecated on MEC, use type-3 instead */
974 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
975 hw_prio, NULL);
976 if (r)
977 return r;
978
979 return 0;
980 }
981
982 static struct {
983 SOC24_FIRMWARE_ID id;
984 unsigned int offset;
985 unsigned int size;
986 unsigned int size_x16;
987 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX];
988
989 #define RLC_TOC_OFFSET_DWUNIT 8
990 #define RLC_SIZE_MULTIPLE 1024
991 #define RLC_TOC_UMF_SIZE_inM 23ULL
992 #define RLC_TOC_FORMAT_API 165ULL
993
gfx_v12_0_parse_rlc_toc(struct amdgpu_device * adev,void * rlc_toc)994 static void gfx_v12_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
995 {
996 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc;
997
998 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) {
999 rlc_autoload_info[ucode->id].id = ucode->id;
1000 rlc_autoload_info[ucode->id].offset =
1001 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4;
1002 rlc_autoload_info[ucode->id].size =
1003 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 :
1004 ucode->size * 4;
1005 ucode++;
1006 }
1007 }
1008
gfx_v12_0_calc_toc_total_size(struct amdgpu_device * adev)1009 static uint32_t gfx_v12_0_calc_toc_total_size(struct amdgpu_device *adev)
1010 {
1011 uint32_t total_size = 0;
1012 SOC24_FIRMWARE_ID id;
1013
1014 gfx_v12_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1015
1016 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++)
1017 total_size += rlc_autoload_info[id].size;
1018
1019 /* In case the offset in rlc toc ucode is aligned */
1020 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset)
1021 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset +
1022 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size;
1023 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20))
1024 total_size = RLC_TOC_UMF_SIZE_inM << 20;
1025
1026 return total_size;
1027 }
1028
gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device * adev)1029 static int gfx_v12_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1030 {
1031 int r;
1032 uint32_t total_size;
1033
1034 total_size = gfx_v12_0_calc_toc_total_size(adev);
1035
1036 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1037 AMDGPU_GEM_DOMAIN_VRAM,
1038 &adev->gfx.rlc.rlc_autoload_bo,
1039 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1040 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1041
1042 if (r) {
1043 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1044 return r;
1045 }
1046
1047 return 0;
1048 }
1049
gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,SOC24_FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)1050 static void gfx_v12_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1051 SOC24_FIRMWARE_ID id,
1052 const void *fw_data,
1053 uint32_t fw_size)
1054 {
1055 uint32_t toc_offset;
1056 uint32_t toc_fw_size;
1057 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1058
1059 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX)
1060 return;
1061
1062 toc_offset = rlc_autoload_info[id].offset;
1063 toc_fw_size = rlc_autoload_info[id].size;
1064
1065 if (fw_size == 0)
1066 fw_size = toc_fw_size;
1067
1068 if (fw_size > toc_fw_size)
1069 fw_size = toc_fw_size;
1070
1071 memcpy(ptr + toc_offset, fw_data, fw_size);
1072
1073 if (fw_size < toc_fw_size)
1074 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1075 }
1076
1077 static void
gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)1078 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
1079 {
1080 void *data;
1081 uint32_t size;
1082 uint32_t *toc_ptr;
1083
1084 data = adev->psp.toc.start_addr;
1085 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size;
1086
1087 toc_ptr = (uint32_t *)data + size / 4 - 2;
1088 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1;
1089
1090 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC,
1091 data, size);
1092 }
1093
1094 static void
gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)1095 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
1096 {
1097 const __le32 *fw_data;
1098 uint32_t fw_size;
1099 const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1100 const struct rlc_firmware_header_v2_0 *rlc_hdr;
1101 const struct rlc_firmware_header_v2_1 *rlcv21_hdr;
1102 const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1103 uint16_t version_major, version_minor;
1104
1105 /* pfp ucode */
1106 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1107 adev->gfx.pfp_fw->data;
1108 /* instruction */
1109 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1110 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1111 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1112 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP,
1113 fw_data, fw_size);
1114 /* data */
1115 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1116 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1117 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1118 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P0_STACK,
1119 fw_data, fw_size);
1120 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_PFP_P1_STACK,
1121 fw_data, fw_size);
1122 /* me ucode */
1123 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1124 adev->gfx.me_fw->data;
1125 /* instruction */
1126 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1127 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1128 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1129 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME,
1130 fw_data, fw_size);
1131 /* data */
1132 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1133 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1134 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1135 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P0_STACK,
1136 fw_data, fw_size);
1137 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_ME_P1_STACK,
1138 fw_data, fw_size);
1139 /* mec ucode */
1140 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1141 adev->gfx.mec_fw->data;
1142 /* instruction */
1143 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1144 le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1145 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1146 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC,
1147 fw_data, fw_size);
1148 /* data */
1149 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1150 le32_to_cpu(cpv2_hdr->data_offset_bytes));
1151 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1152 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK,
1153 fw_data, fw_size);
1154 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK,
1155 fw_data, fw_size);
1156 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK,
1157 fw_data, fw_size);
1158 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK,
1159 fw_data, fw_size);
1160
1161 /* rlc ucode */
1162 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1163 adev->gfx.rlc_fw->data;
1164 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1165 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1166 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1167 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE,
1168 fw_data, fw_size);
1169
1170 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1171 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1172 if (version_major == 2) {
1173 if (version_minor >= 1) {
1174 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
1175
1176 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1177 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes));
1178 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes);
1179 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH,
1180 fw_data, fw_size);
1181
1182 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1183 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes));
1184 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes);
1185 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM,
1186 fw_data, fw_size);
1187 }
1188 if (version_minor >= 2) {
1189 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1190
1191 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1192 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1193 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1194 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE,
1195 fw_data, fw_size);
1196
1197 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1198 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1199 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1200 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT,
1201 fw_data, fw_size);
1202 }
1203 }
1204 }
1205
1206 static void
gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)1207 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
1208 {
1209 const __le32 *fw_data;
1210 uint32_t fw_size;
1211 const struct sdma_firmware_header_v3_0 *sdma_hdr;
1212
1213 sdma_hdr = (const struct sdma_firmware_header_v3_0 *)
1214 adev->sdma.instance[0].fw->data;
1215 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1216 le32_to_cpu(sdma_hdr->ucode_offset_bytes));
1217 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes);
1218
1219 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0,
1220 fw_data, fw_size);
1221 }
1222
1223 static void
gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device * adev)1224 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev)
1225 {
1226 const __le32 *fw_data;
1227 unsigned fw_size;
1228 const struct mes_firmware_header_v1_0 *mes_hdr;
1229 int pipe, ucode_id, data_id;
1230
1231 for (pipe = 0; pipe < 2; pipe++) {
1232 if (pipe == 0) {
1233 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0;
1234 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK;
1235 } else {
1236 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1;
1237 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK;
1238 }
1239
1240 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1241 adev->mes.fw[pipe]->data;
1242
1243 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1244 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1245 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1246
1247 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size);
1248
1249 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1250 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1251 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1252
1253 gfx_v12_0_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size);
1254 }
1255 }
1256
gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)1257 static int gfx_v12_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1258 {
1259 uint32_t rlc_g_offset, rlc_g_size;
1260 uint64_t gpu_addr;
1261 uint32_t data;
1262
1263 /* RLC autoload sequence 2: copy ucode */
1264 gfx_v12_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
1265 gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
1266 gfx_v12_0_rlc_backdoor_autoload_copy_mes_ucode(adev);
1267 gfx_v12_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
1268
1269 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset;
1270 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size;
1271 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start;
1272
1273 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1275
1276 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1277
1278 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
1279 /* RLC autoload sequence 3: load IMU fw */
1280 if (adev->gfx.imu.funcs->load_microcode)
1281 adev->gfx.imu.funcs->load_microcode(adev);
1282 /* RLC autoload sequence 4 init IMU fw */
1283 if (adev->gfx.imu.funcs->setup_imu)
1284 adev->gfx.imu.funcs->setup_imu(adev);
1285 if (adev->gfx.imu.funcs->start_imu)
1286 adev->gfx.imu.funcs->start_imu(adev);
1287
1288 /* RLC autoload sequence 5 disable gpa mode */
1289 gfx_v12_0_disable_gpa_mode(adev);
1290 } else {
1291 /* unhalt rlc to start autoload without imu */
1292 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1293 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1);
1294 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1295 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);
1296 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1297 }
1298
1299 return 0;
1300 }
1301
gfx_v12_0_alloc_ip_dump(struct amdgpu_device * adev)1302 static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev)
1303 {
1304 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
1305 uint32_t *ptr;
1306 uint32_t inst;
1307
1308 ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
1309 if (!ptr) {
1310 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
1311 adev->gfx.ip_dump_core = NULL;
1312 } else {
1313 adev->gfx.ip_dump_core = ptr;
1314 }
1315
1316 /* Allocate memory for compute queue registers for all the instances */
1317 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
1318 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
1319 adev->gfx.mec.num_queue_per_pipe;
1320
1321 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1322 if (!ptr) {
1323 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
1324 adev->gfx.ip_dump_compute_queues = NULL;
1325 } else {
1326 adev->gfx.ip_dump_compute_queues = ptr;
1327 }
1328
1329 /* Allocate memory for gfx queue registers for all the instances */
1330 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
1331 inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
1332 adev->gfx.me.num_queue_per_pipe;
1333
1334 ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
1335 if (!ptr) {
1336 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
1337 adev->gfx.ip_dump_gfx_queues = NULL;
1338 } else {
1339 adev->gfx.ip_dump_gfx_queues = ptr;
1340 }
1341 }
1342
gfx_v12_0_sw_init(struct amdgpu_ip_block * ip_block)1343 static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
1344 {
1345 int i, j, k, r, ring_id = 0;
1346 unsigned num_compute_rings;
1347 int xcc_id = 0;
1348 struct amdgpu_device *adev = ip_block->adev;
1349
1350 INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
1351
1352 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1353 case IP_VERSION(12, 0, 0):
1354 case IP_VERSION(12, 0, 1):
1355 adev->gfx.me.num_me = 1;
1356 adev->gfx.me.num_pipe_per_me = 1;
1357 adev->gfx.me.num_queue_per_pipe = 1;
1358 adev->gfx.mec.num_mec = 1;
1359 adev->gfx.mec.num_pipe_per_mec = 2;
1360 adev->gfx.mec.num_queue_per_pipe = 4;
1361 break;
1362 default:
1363 adev->gfx.me.num_me = 1;
1364 adev->gfx.me.num_pipe_per_me = 1;
1365 adev->gfx.me.num_queue_per_pipe = 1;
1366 adev->gfx.mec.num_mec = 1;
1367 adev->gfx.mec.num_pipe_per_mec = 4;
1368 adev->gfx.mec.num_queue_per_pipe = 8;
1369 break;
1370 }
1371
1372 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1373 case IP_VERSION(12, 0, 0):
1374 case IP_VERSION(12, 0, 1):
1375 if (adev->gfx.me_fw_version >= 2480 &&
1376 adev->gfx.pfp_fw_version >= 2530 &&
1377 adev->gfx.mec_fw_version >= 2680 &&
1378 adev->mes.fw_version[0] >= 100)
1379 adev->gfx.enable_cleaner_shader = true;
1380 break;
1381 default:
1382 adev->gfx.enable_cleaner_shader = false;
1383 break;
1384 }
1385
1386 /* recalculate compute rings to use based on hardware configuration */
1387 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec *
1388 adev->gfx.mec.num_queue_per_pipe) / 2;
1389 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings,
1390 num_compute_rings);
1391
1392 /* EOP Event */
1393 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1394 GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1395 &adev->gfx.eop_irq);
1396 if (r)
1397 return r;
1398
1399 /* Bad opcode Event */
1400 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1401 GFX_11_0_0__SRCID__CP_BAD_OPCODE_ERROR,
1402 &adev->gfx.bad_op_irq);
1403 if (r)
1404 return r;
1405
1406 /* Privileged reg */
1407 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1408 GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1409 &adev->gfx.priv_reg_irq);
1410 if (r)
1411 return r;
1412
1413 /* Privileged inst */
1414 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1415 GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1416 &adev->gfx.priv_inst_irq);
1417 if (r)
1418 return r;
1419
1420 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1421
1422 gfx_v12_0_me_init(adev);
1423
1424 r = gfx_v12_0_rlc_init(adev);
1425 if (r) {
1426 dev_err(adev->dev, "Failed to init rlc BOs!\n");
1427 return r;
1428 }
1429
1430 r = gfx_v12_0_mec_init(adev);
1431 if (r) {
1432 dev_err(adev->dev, "Failed to init MEC BOs!\n");
1433 return r;
1434 }
1435
1436 /* set up the gfx ring */
1437 for (i = 0; i < adev->gfx.me.num_me; i++) {
1438 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1439 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1440 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1441 continue;
1442
1443 r = gfx_v12_0_gfx_ring_init(adev, ring_id,
1444 i, k, j);
1445 if (r)
1446 return r;
1447 ring_id++;
1448 }
1449 }
1450 }
1451
1452 ring_id = 0;
1453 /* set up the compute queues - allocate horizontally across pipes */
1454 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1455 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1456 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1457 if (!amdgpu_gfx_is_mec_queue_enabled(adev,
1458 0, i, k, j))
1459 continue;
1460
1461 r = gfx_v12_0_compute_ring_init(adev, ring_id,
1462 i, k, j);
1463 if (r)
1464 return r;
1465
1466 ring_id++;
1467 }
1468 }
1469 }
1470
1471 adev->gfx.gfx_supported_reset =
1472 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
1473 adev->gfx.compute_supported_reset =
1474 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
1475 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1476 case IP_VERSION(12, 0, 0):
1477 case IP_VERSION(12, 0, 1):
1478 if ((adev->gfx.me_fw_version >= 2660) &&
1479 (adev->gfx.mec_fw_version >= 2920)) {
1480 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1481 adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1482 }
1483 }
1484
1485 if (!adev->enable_mes_kiq) {
1486 r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, 0);
1487 if (r) {
1488 dev_err(adev->dev, "Failed to init KIQ BOs!\n");
1489 return r;
1490 }
1491
1492 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
1493 if (r)
1494 return r;
1495 }
1496
1497 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_compute_mqd), 0);
1498 if (r)
1499 return r;
1500
1501 /* allocate visible FB for rlc auto-loading fw */
1502 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1503 r = gfx_v12_0_rlc_autoload_buffer_init(adev);
1504 if (r)
1505 return r;
1506 }
1507
1508 r = gfx_v12_0_gpu_early_init(adev);
1509 if (r)
1510 return r;
1511
1512 gfx_v12_0_alloc_ip_dump(adev);
1513
1514 r = amdgpu_gfx_sysfs_init(adev);
1515 if (r)
1516 return r;
1517
1518 return 0;
1519 }
1520
gfx_v12_0_pfp_fini(struct amdgpu_device * adev)1521 static void gfx_v12_0_pfp_fini(struct amdgpu_device *adev)
1522 {
1523 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1524 &adev->gfx.pfp.pfp_fw_gpu_addr,
1525 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1526
1527 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1528 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1529 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1530 }
1531
gfx_v12_0_me_fini(struct amdgpu_device * adev)1532 static void gfx_v12_0_me_fini(struct amdgpu_device *adev)
1533 {
1534 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1535 &adev->gfx.me.me_fw_gpu_addr,
1536 (void **)&adev->gfx.me.me_fw_ptr);
1537
1538 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1539 &adev->gfx.me.me_fw_data_gpu_addr,
1540 (void **)&adev->gfx.me.me_fw_data_ptr);
1541 }
1542
gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device * adev)1543 static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1544 {
1545 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1546 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1547 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1548 }
1549
gfx_v12_0_sw_fini(struct amdgpu_ip_block * ip_block)1550 static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block)
1551 {
1552 int i;
1553 struct amdgpu_device *adev = ip_block->adev;
1554
1555 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1556 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1557 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1558 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1559
1560 amdgpu_gfx_mqd_sw_fini(adev, 0);
1561
1562 if (!adev->enable_mes_kiq) {
1563 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1564 amdgpu_gfx_kiq_fini(adev, 0);
1565 }
1566
1567 gfx_v12_0_pfp_fini(adev);
1568 gfx_v12_0_me_fini(adev);
1569 gfx_v12_0_rlc_fini(adev);
1570 gfx_v12_0_mec_fini(adev);
1571
1572 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1573 gfx_v12_0_rlc_autoload_buffer_fini(adev);
1574
1575 gfx_v12_0_free_microcode(adev);
1576
1577 amdgpu_gfx_sysfs_fini(adev);
1578
1579 kfree(adev->gfx.ip_dump_core);
1580 kfree(adev->gfx.ip_dump_compute_queues);
1581 kfree(adev->gfx.ip_dump_gfx_queues);
1582
1583 return 0;
1584 }
1585
gfx_v12_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance,int xcc_id)1586 static void gfx_v12_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1587 u32 sh_num, u32 instance, int xcc_id)
1588 {
1589 u32 data;
1590
1591 if (instance == 0xffffffff)
1592 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1593 INSTANCE_BROADCAST_WRITES, 1);
1594 else
1595 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1596 instance);
1597
1598 if (se_num == 0xffffffff)
1599 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1600 1);
1601 else
1602 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1603
1604 if (sh_num == 0xffffffff)
1605 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1606 1);
1607 else
1608 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1609
1610 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1611 }
1612
gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device * adev)1613 static u32 gfx_v12_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1614 {
1615 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1616
1617 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);
1618 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1619 GRBM_CC_GC_SA_UNIT_DISABLE,
1620 SA_DISABLE);
1621 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);
1622 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1623 GRBM_GC_USER_SA_UNIT_DISABLE,
1624 SA_DISABLE);
1625 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1626 adev->gfx.config.max_shader_engines);
1627
1628 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1629 }
1630
gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device * adev)1631 static u32 gfx_v12_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1632 {
1633 u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1634 u32 rb_mask;
1635
1636 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1637 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1638 CC_RB_BACKEND_DISABLE,
1639 BACKEND_DISABLE);
1640 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1641 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1642 GC_USER_RB_BACKEND_DISABLE,
1643 BACKEND_DISABLE);
1644 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1645 adev->gfx.config.max_shader_engines);
1646
1647 return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1648 }
1649
gfx_v12_0_setup_rb(struct amdgpu_device * adev)1650 static void gfx_v12_0_setup_rb(struct amdgpu_device *adev)
1651 {
1652 u32 rb_bitmap_per_sa;
1653 u32 rb_bitmap_width_per_sa;
1654 u32 max_sa;
1655 u32 active_sa_bitmap;
1656 u32 global_active_rb_bitmap;
1657 u32 active_rb_bitmap = 0;
1658 u32 i;
1659
1660 /* query sa bitmap from SA_UNIT_DISABLE registers */
1661 active_sa_bitmap = gfx_v12_0_get_sa_active_bitmap(adev);
1662 /* query rb bitmap from RB_BACKEND_DISABLE registers */
1663 global_active_rb_bitmap = gfx_v12_0_get_rb_active_bitmap(adev);
1664
1665 /* generate active rb bitmap according to active sa bitmap */
1666 max_sa = adev->gfx.config.max_shader_engines *
1667 adev->gfx.config.max_sh_per_se;
1668 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1669 adev->gfx.config.max_sh_per_se;
1670 rb_bitmap_per_sa = amdgpu_gfx_create_bitmask(rb_bitmap_width_per_sa);
1671
1672 for (i = 0; i < max_sa; i++) {
1673 if (active_sa_bitmap & (1 << i))
1674 active_rb_bitmap |= (rb_bitmap_per_sa << (i * rb_bitmap_width_per_sa));
1675 }
1676
1677 active_rb_bitmap &= global_active_rb_bitmap;
1678 adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1679 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1680 }
1681
1682 #define LDS_APP_BASE 0x1
1683 #define SCRATCH_APP_BASE 0x2
1684
gfx_v12_0_init_compute_vmid(struct amdgpu_device * adev)1685 static void gfx_v12_0_init_compute_vmid(struct amdgpu_device *adev)
1686 {
1687 int i;
1688 uint32_t sh_mem_bases;
1689 uint32_t data;
1690
1691 /*
1692 * Configure apertures:
1693 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1694 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1695 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1696 */
1697 sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1698 SCRATCH_APP_BASE;
1699
1700 mutex_lock(&adev->srbm_mutex);
1701 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1702 soc24_grbm_select(adev, 0, 0, 0, i);
1703 /* CP and shaders */
1704 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1705 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1706
1707 /* Enable trap for each kfd vmid. */
1708 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1709 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1710 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1711 }
1712 soc24_grbm_select(adev, 0, 0, 0, 0);
1713 mutex_unlock(&adev->srbm_mutex);
1714 }
1715
gfx_v12_0_tcp_harvest(struct amdgpu_device * adev)1716 static void gfx_v12_0_tcp_harvest(struct amdgpu_device *adev)
1717 {
1718 /* TODO: harvest feature to be added later. */
1719 }
1720
gfx_v12_0_get_tcc_info(struct amdgpu_device * adev)1721 static void gfx_v12_0_get_tcc_info(struct amdgpu_device *adev)
1722 {
1723 }
1724
gfx_v12_0_constants_init(struct amdgpu_device * adev)1725 static void gfx_v12_0_constants_init(struct amdgpu_device *adev)
1726 {
1727 u32 tmp;
1728 int i;
1729
1730 if (!amdgpu_sriov_vf(adev))
1731 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1732
1733 gfx_v12_0_setup_rb(adev);
1734 gfx_v12_0_get_cu_info(adev, &adev->gfx.cu_info);
1735 gfx_v12_0_get_tcc_info(adev);
1736 adev->gfx.config.pa_sc_tile_steering_override = 0;
1737
1738 /* XXX SH_MEM regs */
1739 /* where to put LDS, scratch, GPUVM in FSA64 space */
1740 mutex_lock(&adev->srbm_mutex);
1741 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1742 soc24_grbm_select(adev, 0, 0, 0, i);
1743 /* CP and shaders */
1744 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1745 if (i != 0) {
1746 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1747 (adev->gmc.private_aperture_start >> 48));
1748 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1749 (adev->gmc.shared_aperture_start >> 48));
1750 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1751 }
1752 }
1753 soc24_grbm_select(adev, 0, 0, 0, 0);
1754
1755 mutex_unlock(&adev->srbm_mutex);
1756
1757 gfx_v12_0_init_compute_vmid(adev);
1758 }
1759
gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device * adev,int me,int pipe)1760 static u32 gfx_v12_0_get_cpg_int_cntl(struct amdgpu_device *adev,
1761 int me, int pipe)
1762 {
1763 if (me != 0)
1764 return 0;
1765
1766 switch (pipe) {
1767 case 0:
1768 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
1769 default:
1770 return 0;
1771 }
1772 }
1773
gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device * adev,int me,int pipe)1774 static u32 gfx_v12_0_get_cpc_int_cntl(struct amdgpu_device *adev,
1775 int me, int pipe)
1776 {
1777 /*
1778 * amdgpu controls only the first MEC. That's why this function only
1779 * handles the setting of interrupts for this specific MEC. All other
1780 * pipes' interrupts are set by amdkfd.
1781 */
1782 if (me != 1)
1783 return 0;
1784
1785 switch (pipe) {
1786 case 0:
1787 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1788 case 1:
1789 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1790 default:
1791 return 0;
1792 }
1793 }
1794
gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)1795 static void gfx_v12_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1796 bool enable)
1797 {
1798 u32 tmp, cp_int_cntl_reg;
1799 int i, j;
1800
1801 if (amdgpu_sriov_vf(adev))
1802 return;
1803
1804 for (i = 0; i < adev->gfx.me.num_me; i++) {
1805 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
1806 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
1807
1808 if (cp_int_cntl_reg) {
1809 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
1810 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1811 enable ? 1 : 0);
1812 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1813 enable ? 1 : 0);
1814 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1815 enable ? 1 : 0);
1816 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1817 enable ? 1 : 0);
1818 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
1819 }
1820 }
1821 }
1822 }
1823
gfx_v12_0_init_csb(struct amdgpu_device * adev)1824 static int gfx_v12_0_init_csb(struct amdgpu_device *adev)
1825 {
1826 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1827
1828 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1829 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1830 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1831 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1832 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1833
1834 return 0;
1835 }
1836
gfx_v12_0_rlc_stop(struct amdgpu_device * adev)1837 static void gfx_v12_0_rlc_stop(struct amdgpu_device *adev)
1838 {
1839 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1840
1841 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1842 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1843 }
1844
gfx_v12_0_rlc_reset(struct amdgpu_device * adev)1845 static void gfx_v12_0_rlc_reset(struct amdgpu_device *adev)
1846 {
1847 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1848 udelay(50);
1849 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1850 udelay(50);
1851 }
1852
gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)1853 static void gfx_v12_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1854 bool enable)
1855 {
1856 uint32_t rlc_pg_cntl;
1857
1858 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1859
1860 if (!enable) {
1861 /* RLC_PG_CNTL[23] = 0 (default)
1862 * RLC will wait for handshake acks with SMU
1863 * GFXOFF will be enabled
1864 * RLC_PG_CNTL[23] = 1
1865 * RLC will not issue any message to SMU
1866 * hence no handshake between SMU & RLC
1867 * GFXOFF will be disabled
1868 */
1869 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1870 } else
1871 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1872 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1873 }
1874
gfx_v12_0_rlc_start(struct amdgpu_device * adev)1875 static void gfx_v12_0_rlc_start(struct amdgpu_device *adev)
1876 {
1877 /* TODO: enable rlc & smu handshake until smu
1878 * and gfxoff feature works as expected */
1879 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1880 gfx_v12_0_rlc_smu_handshake_cntl(adev, false);
1881
1882 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1883 udelay(50);
1884 }
1885
gfx_v12_0_rlc_enable_srm(struct amdgpu_device * adev)1886 static void gfx_v12_0_rlc_enable_srm(struct amdgpu_device *adev)
1887 {
1888 uint32_t tmp;
1889
1890 /* enable Save Restore Machine */
1891 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1892 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1893 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1894 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1895 }
1896
gfx_v12_0_load_rlcg_microcode(struct amdgpu_device * adev)1897 static void gfx_v12_0_load_rlcg_microcode(struct amdgpu_device *adev)
1898 {
1899 const struct rlc_firmware_header_v2_0 *hdr;
1900 const __le32 *fw_data;
1901 unsigned i, fw_size;
1902
1903 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1904 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1905 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1906 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1907
1908 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1909 RLCG_UCODE_LOADING_START_ADDRESS);
1910
1911 for (i = 0; i < fw_size; i++)
1912 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1913 le32_to_cpup(fw_data++));
1914
1915 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1916 }
1917
gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device * adev)1918 static void gfx_v12_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1919 {
1920 const struct rlc_firmware_header_v2_2 *hdr;
1921 const __le32 *fw_data;
1922 unsigned i, fw_size;
1923 u32 tmp;
1924
1925 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1926
1927 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1928 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1929 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1930
1931 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1932
1933 for (i = 0; i < fw_size; i++) {
1934 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1935 msleep(1);
1936 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1937 le32_to_cpup(fw_data++));
1938 }
1939
1940 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1941
1942 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1943 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1944 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1945
1946 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1947 for (i = 0; i < fw_size; i++) {
1948 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1949 msleep(1);
1950 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1951 le32_to_cpup(fw_data++));
1952 }
1953
1954 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1955
1956 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1957 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1958 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1959 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1960 }
1961
gfx_v12_0_rlc_load_microcode(struct amdgpu_device * adev)1962 static int gfx_v12_0_rlc_load_microcode(struct amdgpu_device *adev)
1963 {
1964 const struct rlc_firmware_header_v2_0 *hdr;
1965 uint16_t version_major;
1966 uint16_t version_minor;
1967
1968 if (!adev->gfx.rlc_fw)
1969 return -EINVAL;
1970
1971 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1972 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1973
1974 version_major = le16_to_cpu(hdr->header.header_version_major);
1975 version_minor = le16_to_cpu(hdr->header.header_version_minor);
1976
1977 if (version_major == 2) {
1978 gfx_v12_0_load_rlcg_microcode(adev);
1979 if (amdgpu_dpm == 1) {
1980 if (version_minor >= 2)
1981 gfx_v12_0_load_rlc_iram_dram_microcode(adev);
1982 }
1983
1984 return 0;
1985 }
1986
1987 return -EINVAL;
1988 }
1989
gfx_v12_0_rlc_resume(struct amdgpu_device * adev)1990 static int gfx_v12_0_rlc_resume(struct amdgpu_device *adev)
1991 {
1992 int r;
1993
1994 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1995 gfx_v12_0_init_csb(adev);
1996
1997 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1998 gfx_v12_0_rlc_enable_srm(adev);
1999 } else {
2000 if (amdgpu_sriov_vf(adev)) {
2001 gfx_v12_0_init_csb(adev);
2002 return 0;
2003 }
2004
2005 adev->gfx.rlc.funcs->stop(adev);
2006
2007 /* disable CG */
2008 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2009
2010 /* disable PG */
2011 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2012
2013 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2014 /* legacy rlc firmware loading */
2015 r = gfx_v12_0_rlc_load_microcode(adev);
2016 if (r)
2017 return r;
2018 }
2019
2020 gfx_v12_0_init_csb(adev);
2021
2022 adev->gfx.rlc.funcs->start(adev);
2023 }
2024
2025 return 0;
2026 }
2027
gfx_v12_0_config_gfx_rs64(struct amdgpu_device * adev)2028 static void gfx_v12_0_config_gfx_rs64(struct amdgpu_device *adev)
2029 {
2030 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2031 const struct gfx_firmware_header_v2_0 *me_hdr;
2032 const struct gfx_firmware_header_v2_0 *mec_hdr;
2033 uint32_t pipe_id, tmp;
2034
2035 mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2036 adev->gfx.mec_fw->data;
2037 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2038 adev->gfx.me_fw->data;
2039 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2040 adev->gfx.pfp_fw->data;
2041
2042 /* config pfp program start addr */
2043 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2044 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2045 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2046 (pfp_hdr->ucode_start_addr_hi << 30) |
2047 (pfp_hdr->ucode_start_addr_lo >> 2));
2048 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2049 pfp_hdr->ucode_start_addr_hi >> 2);
2050 }
2051 soc24_grbm_select(adev, 0, 0, 0, 0);
2052
2053 /* reset pfp pipe */
2054 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2055 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2056 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2057 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2058
2059 /* clear pfp pipe reset */
2060 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2061 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2062 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2063
2064 /* config me program start addr */
2065 for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2066 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2067 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2068 (me_hdr->ucode_start_addr_hi << 30) |
2069 (me_hdr->ucode_start_addr_lo >> 2));
2070 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2071 me_hdr->ucode_start_addr_hi>>2);
2072 }
2073 soc24_grbm_select(adev, 0, 0, 0, 0);
2074
2075 /* reset me pipe */
2076 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2077 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2078 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2079 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2080
2081 /* clear me pipe reset */
2082 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2083 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2084 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2085
2086 /* config mec program start addr */
2087 for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2088 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2089 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2090 mec_hdr->ucode_start_addr_lo >> 2 |
2091 mec_hdr->ucode_start_addr_hi << 30);
2092 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2093 mec_hdr->ucode_start_addr_hi >> 2);
2094 }
2095 soc24_grbm_select(adev, 0, 0, 0, 0);
2096
2097 /* reset mec pipe */
2098 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2099 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2100 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2101 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2102 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2103 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2104
2105 /* clear mec pipe reset */
2106 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2107 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2108 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2109 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2110 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2111 }
2112
gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device * adev)2113 static void gfx_v12_0_set_pfp_ucode_start_addr(struct amdgpu_device *adev)
2114 {
2115 const struct gfx_firmware_header_v2_0 *cp_hdr;
2116 unsigned pipe_id, tmp;
2117
2118 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2119 adev->gfx.pfp_fw->data;
2120 mutex_lock(&adev->srbm_mutex);
2121 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2122 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2123 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2124 (cp_hdr->ucode_start_addr_hi << 30) |
2125 (cp_hdr->ucode_start_addr_lo >> 2));
2126 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2127 cp_hdr->ucode_start_addr_hi>>2);
2128
2129 /*
2130 * Program CP_ME_CNTL to reset given PIPE to take
2131 * effect of CP_PFP_PRGRM_CNTR_START.
2132 */
2133 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2134 if (pipe_id == 0)
2135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2136 PFP_PIPE0_RESET, 1);
2137 else
2138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2139 PFP_PIPE1_RESET, 1);
2140 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2141
2142 /* Clear pfp pipe0 reset bit. */
2143 if (pipe_id == 0)
2144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2145 PFP_PIPE0_RESET, 0);
2146 else
2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2148 PFP_PIPE1_RESET, 0);
2149 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2150 }
2151 soc24_grbm_select(adev, 0, 0, 0, 0);
2152 mutex_unlock(&adev->srbm_mutex);
2153 }
2154
gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device * adev)2155 static void gfx_v12_0_set_me_ucode_start_addr(struct amdgpu_device *adev)
2156 {
2157 const struct gfx_firmware_header_v2_0 *cp_hdr;
2158 unsigned pipe_id, tmp;
2159
2160 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2161 adev->gfx.me_fw->data;
2162 mutex_lock(&adev->srbm_mutex);
2163 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2164 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2165 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2166 (cp_hdr->ucode_start_addr_hi << 30) |
2167 (cp_hdr->ucode_start_addr_lo >> 2) );
2168 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2169 cp_hdr->ucode_start_addr_hi>>2);
2170
2171 /*
2172 * Program CP_ME_CNTL to reset given PIPE to take
2173 * effect of CP_ME_PRGRM_CNTR_START.
2174 */
2175 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2176 if (pipe_id == 0)
2177 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2178 ME_PIPE0_RESET, 1);
2179 else
2180 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2181 ME_PIPE1_RESET, 1);
2182 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2183
2184 /* Clear pfp pipe0 reset bit. */
2185 if (pipe_id == 0)
2186 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2187 ME_PIPE0_RESET, 0);
2188 else
2189 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2190 ME_PIPE1_RESET, 0);
2191 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2192 }
2193 soc24_grbm_select(adev, 0, 0, 0, 0);
2194 mutex_unlock(&adev->srbm_mutex);
2195 }
2196
gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device * adev)2197 static void gfx_v12_0_set_mec_ucode_start_addr(struct amdgpu_device *adev)
2198 {
2199 const struct gfx_firmware_header_v2_0 *cp_hdr;
2200 unsigned pipe_id;
2201
2202 cp_hdr = (const struct gfx_firmware_header_v2_0 *)
2203 adev->gfx.mec_fw->data;
2204 mutex_lock(&adev->srbm_mutex);
2205 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) {
2206 soc24_grbm_select(adev, 1, pipe_id, 0, 0);
2207 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2208 cp_hdr->ucode_start_addr_lo >> 2 |
2209 cp_hdr->ucode_start_addr_hi << 30);
2210 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2211 cp_hdr->ucode_start_addr_hi >> 2);
2212 }
2213 soc24_grbm_select(adev, 0, 0, 0, 0);
2214 mutex_unlock(&adev->srbm_mutex);
2215 }
2216
gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)2217 static int gfx_v12_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2218 {
2219 uint32_t cp_status;
2220 uint32_t bootload_status;
2221 int i;
2222
2223 for (i = 0; i < adev->usec_timeout; i++) {
2224 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2225 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2226
2227 if ((cp_status == 0) &&
2228 (REG_GET_FIELD(bootload_status,
2229 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2230 break;
2231 }
2232 udelay(1);
2233 if (amdgpu_emu_mode)
2234 msleep(10);
2235 }
2236
2237 if (i >= adev->usec_timeout) {
2238 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2239 return -ETIMEDOUT;
2240 }
2241
2242 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2243 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2244 gfx_v12_0_set_me_ucode_start_addr(adev);
2245 gfx_v12_0_set_mec_ucode_start_addr(adev);
2246 }
2247
2248 return 0;
2249 }
2250
gfx_v12_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)2251 static int gfx_v12_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2252 {
2253 int i;
2254 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2255
2256 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2257 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2258 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2259
2260 for (i = 0; i < adev->usec_timeout; i++) {
2261 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2262 break;
2263 udelay(1);
2264 }
2265
2266 if (i >= adev->usec_timeout)
2267 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2268
2269 return 0;
2270 }
2271
gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device * adev)2272 static int gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2273 {
2274 int r;
2275 const struct gfx_firmware_header_v2_0 *pfp_hdr;
2276 const __le32 *fw_ucode, *fw_data;
2277 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2278 uint32_t tmp;
2279 uint32_t usec_timeout = 50000; /* wait for 50ms */
2280
2281 pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2282 adev->gfx.pfp_fw->data;
2283
2284 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2285
2286 /* instruction */
2287 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2288 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2289 fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2290 /* data */
2291 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2292 le32_to_cpu(pfp_hdr->data_offset_bytes));
2293 fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2294
2295 /* 64kb align */
2296 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2297 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2298 &adev->gfx.pfp.pfp_fw_obj,
2299 &adev->gfx.pfp.pfp_fw_gpu_addr,
2300 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2301 if (r) {
2302 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2303 gfx_v12_0_pfp_fini(adev);
2304 return r;
2305 }
2306
2307 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2308 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2309 &adev->gfx.pfp.pfp_fw_data_obj,
2310 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2311 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2312 if (r) {
2313 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2314 gfx_v12_0_pfp_fini(adev);
2315 return r;
2316 }
2317
2318 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2319 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2320
2321 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2322 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2323 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2324 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2325
2326 if (amdgpu_emu_mode == 1)
2327 amdgpu_device_flush_hdp(adev, NULL);
2328
2329 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2330 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2331 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2332 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2333
2334 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2335 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2336 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2337 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2338 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2339
2340 /*
2341 * Programming any of the CP_PFP_IC_BASE registers
2342 * forces invalidation of the ME L1 I$. Wait for the
2343 * invalidation complete
2344 */
2345 for (i = 0; i < usec_timeout; i++) {
2346 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2347 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2348 INVALIDATE_CACHE_COMPLETE))
2349 break;
2350 udelay(1);
2351 }
2352
2353 if (i >= usec_timeout) {
2354 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2355 return -EINVAL;
2356 }
2357
2358 /* Prime the L1 instruction caches */
2359 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2360 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2361 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2362 /* Waiting for cache primed*/
2363 for (i = 0; i < usec_timeout; i++) {
2364 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2365 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2366 ICACHE_PRIMED))
2367 break;
2368 udelay(1);
2369 }
2370
2371 if (i >= usec_timeout) {
2372 dev_err(adev->dev, "failed to prime instruction cache\n");
2373 return -EINVAL;
2374 }
2375
2376 mutex_lock(&adev->srbm_mutex);
2377 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2378 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2379
2380 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2381 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2382 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2383 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2384 }
2385 soc24_grbm_select(adev, 0, 0, 0, 0);
2386 mutex_unlock(&adev->srbm_mutex);
2387
2388 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2389 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2390 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2391 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2392
2393 /* Invalidate the data caches */
2394 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2395 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2396 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2397
2398 for (i = 0; i < usec_timeout; i++) {
2399 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2400 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2401 INVALIDATE_DCACHE_COMPLETE))
2402 break;
2403 udelay(1);
2404 }
2405
2406 if (i >= usec_timeout) {
2407 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2408 return -EINVAL;
2409 }
2410
2411 gfx_v12_0_set_pfp_ucode_start_addr(adev);
2412
2413 return 0;
2414 }
2415
gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device * adev)2416 static int gfx_v12_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2417 {
2418 int r;
2419 const struct gfx_firmware_header_v2_0 *me_hdr;
2420 const __le32 *fw_ucode, *fw_data;
2421 unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2422 uint32_t tmp;
2423 uint32_t usec_timeout = 50000; /* wait for 50ms */
2424
2425 me_hdr = (const struct gfx_firmware_header_v2_0 *)
2426 adev->gfx.me_fw->data;
2427
2428 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2429
2430 /* instruction */
2431 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2432 le32_to_cpu(me_hdr->ucode_offset_bytes));
2433 fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2434 /* data */
2435 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2436 le32_to_cpu(me_hdr->data_offset_bytes));
2437 fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2438
2439 /* 64kb align*/
2440 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2441 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2442 &adev->gfx.me.me_fw_obj,
2443 &adev->gfx.me.me_fw_gpu_addr,
2444 (void **)&adev->gfx.me.me_fw_ptr);
2445 if (r) {
2446 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2447 gfx_v12_0_me_fini(adev);
2448 return r;
2449 }
2450
2451 r = amdgpu_bo_create_reserved(adev, fw_data_size,
2452 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2453 &adev->gfx.me.me_fw_data_obj,
2454 &adev->gfx.me.me_fw_data_gpu_addr,
2455 (void **)&adev->gfx.me.me_fw_data_ptr);
2456 if (r) {
2457 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2458 gfx_v12_0_me_fini(adev);
2459 return r;
2460 }
2461
2462 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2463 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2464
2465 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2466 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2467 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2468 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2469
2470 if (amdgpu_emu_mode == 1)
2471 amdgpu_device_flush_hdp(adev, NULL);
2472
2473 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2474 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2475 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2476 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2477
2478 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2479 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2480 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2481 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2482 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2483
2484 /*
2485 * Programming any of the CP_ME_IC_BASE registers
2486 * forces invalidation of the ME L1 I$. Wait for the
2487 * invalidation complete
2488 */
2489 for (i = 0; i < usec_timeout; i++) {
2490 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2491 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2492 INVALIDATE_CACHE_COMPLETE))
2493 break;
2494 udelay(1);
2495 }
2496
2497 if (i >= usec_timeout) {
2498 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2499 return -EINVAL;
2500 }
2501
2502 /* Prime the instruction caches */
2503 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2504 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2505 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2506
2507 /* Waiting for instruction cache primed*/
2508 for (i = 0; i < usec_timeout; i++) {
2509 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2510 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2511 ICACHE_PRIMED))
2512 break;
2513 udelay(1);
2514 }
2515
2516 if (i >= usec_timeout) {
2517 dev_err(adev->dev, "failed to prime instruction cache\n");
2518 return -EINVAL;
2519 }
2520
2521 mutex_lock(&adev->srbm_mutex);
2522 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2523 soc24_grbm_select(adev, 0, pipe_id, 0, 0);
2524
2525 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2526 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2527 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2528 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2529 }
2530 soc24_grbm_select(adev, 0, 0, 0, 0);
2531 mutex_unlock(&adev->srbm_mutex);
2532
2533 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2534 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2535 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2536 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2537
2538 /* Invalidate the data caches */
2539 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2540 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2541 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2542
2543 for (i = 0; i < usec_timeout; i++) {
2544 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2545 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2546 INVALIDATE_DCACHE_COMPLETE))
2547 break;
2548 udelay(1);
2549 }
2550
2551 if (i >= usec_timeout) {
2552 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2553 return -EINVAL;
2554 }
2555
2556 gfx_v12_0_set_me_ucode_start_addr(adev);
2557
2558 return 0;
2559 }
2560
gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device * adev)2561 static int gfx_v12_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2562 {
2563 int r;
2564
2565 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
2566 return -EINVAL;
2567
2568 gfx_v12_0_cp_gfx_enable(adev, false);
2569
2570 r = gfx_v12_0_cp_gfx_load_pfp_microcode_rs64(adev);
2571 if (r) {
2572 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2573 return r;
2574 }
2575
2576 r = gfx_v12_0_cp_gfx_load_me_microcode_rs64(adev);
2577 if (r) {
2578 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2579 return r;
2580 }
2581
2582 return 0;
2583 }
2584
gfx_v12_0_cp_gfx_start(struct amdgpu_device * adev)2585 static int gfx_v12_0_cp_gfx_start(struct amdgpu_device *adev)
2586 {
2587 /* init the CP */
2588 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
2589 adev->gfx.config.max_hw_contexts - 1);
2590 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
2591
2592 if (!amdgpu_async_gfx_ring)
2593 gfx_v12_0_cp_gfx_enable(adev, true);
2594
2595 return 0;
2596 }
2597
gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)2598 static void gfx_v12_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2599 CP_PIPE_ID pipe)
2600 {
2601 u32 tmp;
2602
2603 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
2604 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2605
2606 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
2607 }
2608
gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)2609 static void gfx_v12_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2610 struct amdgpu_ring *ring)
2611 {
2612 u32 tmp;
2613
2614 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2615 if (ring->use_doorbell) {
2616 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2617 DOORBELL_OFFSET, ring->doorbell_index);
2618 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2619 DOORBELL_EN, 1);
2620 } else {
2621 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2622 DOORBELL_EN, 0);
2623 }
2624 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
2625
2626 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2627 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2628 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
2629
2630 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2631 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2632 }
2633
gfx_v12_0_cp_gfx_resume(struct amdgpu_device * adev)2634 static int gfx_v12_0_cp_gfx_resume(struct amdgpu_device *adev)
2635 {
2636 struct amdgpu_ring *ring;
2637 u32 tmp;
2638 u32 rb_bufsz;
2639 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2640
2641 /* Set the write pointer delay */
2642 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
2643
2644 /* set the RB to use vmid 0 */
2645 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
2646
2647 /* Init gfx ring 0 for pipe 0 */
2648 mutex_lock(&adev->srbm_mutex);
2649 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2650
2651 /* Set ring buffer size */
2652 ring = &adev->gfx.gfx_ring[0];
2653 rb_bufsz = order_base_2(ring->ring_size / 8);
2654 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2655 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2656 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2657
2658 /* Initialize the ring buffer's write pointers */
2659 ring->wptr = 0;
2660 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
2661 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2662
2663 /* set the wb address whether it's enabled or not */
2664 rptr_addr = ring->rptr_gpu_addr;
2665 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2666 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2667 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2668
2669 wptr_gpu_addr = ring->wptr_gpu_addr;
2670 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
2671 lower_32_bits(wptr_gpu_addr));
2672 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
2673 upper_32_bits(wptr_gpu_addr));
2674
2675 mdelay(1);
2676 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2677
2678 rb_addr = ring->gpu_addr >> 8;
2679 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
2680 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2681
2682 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
2683
2684 gfx_v12_0_cp_gfx_set_doorbell(adev, ring);
2685 mutex_unlock(&adev->srbm_mutex);
2686
2687 /* Switch to pipe 0 */
2688 mutex_lock(&adev->srbm_mutex);
2689 gfx_v12_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2690 mutex_unlock(&adev->srbm_mutex);
2691
2692 /* start the ring */
2693 gfx_v12_0_cp_gfx_start(adev);
2694 return 0;
2695 }
2696
gfx_v12_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)2697 static void gfx_v12_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2698 {
2699 u32 data;
2700
2701 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2702 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
2703 enable ? 0 : 1);
2704 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
2705 enable ? 0 : 1);
2706 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
2707 enable ? 0 : 1);
2708 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
2709 enable ? 0 : 1);
2710 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
2711 enable ? 0 : 1);
2712 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
2713 enable ? 1 : 0);
2714 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
2715 enable ? 1 : 0);
2716 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
2717 enable ? 1 : 0);
2718 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
2719 enable ? 1 : 0);
2720 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
2721 enable ? 0 : 1);
2722 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
2723
2724 adev->gfx.kiq[0].ring.sched.ready = enable;
2725
2726 udelay(50);
2727 }
2728
gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device * adev)2729 static int gfx_v12_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
2730 {
2731 const struct gfx_firmware_header_v2_0 *mec_hdr;
2732 const __le32 *fw_ucode, *fw_data;
2733 u32 tmp, fw_ucode_size, fw_data_size;
2734 u32 i, usec_timeout = 50000; /* Wait for 50 ms */
2735 u32 *fw_ucode_ptr, *fw_data_ptr;
2736 int r;
2737
2738 if (!adev->gfx.mec_fw)
2739 return -EINVAL;
2740
2741 gfx_v12_0_cp_compute_enable(adev, false);
2742
2743 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
2744 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2745
2746 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
2747 le32_to_cpu(mec_hdr->ucode_offset_bytes));
2748 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
2749
2750 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2751 le32_to_cpu(mec_hdr->data_offset_bytes));
2752 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
2753
2754 r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2755 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2756 &adev->gfx.mec.mec_fw_obj,
2757 &adev->gfx.mec.mec_fw_gpu_addr,
2758 (void **)&fw_ucode_ptr);
2759 if (r) {
2760 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2761 gfx_v12_0_mec_fini(adev);
2762 return r;
2763 }
2764
2765 r = amdgpu_bo_create_reserved(adev,
2766 ALIGN(fw_data_size, 64 * 1024) *
2767 adev->gfx.mec.num_pipe_per_mec,
2768 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2769 &adev->gfx.mec.mec_fw_data_obj,
2770 &adev->gfx.mec.mec_fw_data_gpu_addr,
2771 (void **)&fw_data_ptr);
2772 if (r) {
2773 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
2774 gfx_v12_0_mec_fini(adev);
2775 return r;
2776 }
2777
2778 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
2779 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2780 memcpy(fw_data_ptr + i * ALIGN(fw_data_size, 64 * 1024) / 4, fw_data, fw_data_size);
2781 }
2782
2783 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
2784 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
2785 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
2786 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
2787
2788 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2789 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2790 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2791 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2792 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2793
2794 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2795 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2796 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2797 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2798
2799 mutex_lock(&adev->srbm_mutex);
2800 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2801 soc24_grbm_select(adev, 1, i, 0, 0);
2802
2803 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,
2804 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2805 i * ALIGN(fw_data_size, 64 * 1024)));
2806 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2807 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr +
2808 i * ALIGN(fw_data_size, 64 * 1024)));
2809
2810 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2811 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2812 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2813 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2814 }
2815 mutex_unlock(&adev->srbm_mutex);
2816 soc24_grbm_select(adev, 0, 0, 0, 0);
2817
2818 /* Trigger an invalidation of the L1 instruction caches */
2819 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2820 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2821 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2822
2823 /* Wait for invalidation complete */
2824 for (i = 0; i < usec_timeout; i++) {
2825 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2826 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2827 INVALIDATE_DCACHE_COMPLETE))
2828 break;
2829 udelay(1);
2830 }
2831
2832 if (i >= usec_timeout) {
2833 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2834 return -EINVAL;
2835 }
2836
2837 /* Trigger an invalidation of the L1 instruction caches */
2838 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2839 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2840 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2841
2842 /* Wait for invalidation complete */
2843 for (i = 0; i < usec_timeout; i++) {
2844 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2845 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2846 INVALIDATE_CACHE_COMPLETE))
2847 break;
2848 udelay(1);
2849 }
2850
2851 if (i >= usec_timeout) {
2852 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2853 return -EINVAL;
2854 }
2855
2856 gfx_v12_0_set_mec_ucode_start_addr(adev);
2857
2858 return 0;
2859 }
2860
gfx_v12_0_kiq_setting(struct amdgpu_ring * ring)2861 static void gfx_v12_0_kiq_setting(struct amdgpu_ring *ring)
2862 {
2863 uint32_t tmp;
2864 struct amdgpu_device *adev = ring->adev;
2865
2866 /* tell RLC which is KIQ queue */
2867 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
2868 tmp &= 0xffffff00;
2869 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2870 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
2871 }
2872
gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device * adev)2873 static void gfx_v12_0_cp_set_doorbell_range(struct amdgpu_device *adev)
2874 {
2875 /* set graphics engine doorbell range */
2876 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
2877 (adev->doorbell_index.gfx_ring0 * 2) << 2);
2878 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2879 (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
2880
2881 /* set compute engine doorbell range */
2882 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
2883 (adev->doorbell_index.kiq * 2) << 2);
2884 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
2885 (adev->doorbell_index.userqueue_end * 2) << 2);
2886 }
2887
gfx_v12_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)2888 static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
2889 struct amdgpu_mqd_prop *prop)
2890 {
2891 struct v12_gfx_mqd *mqd = m;
2892 uint64_t hqd_gpu_addr, wb_gpu_addr;
2893 uint32_t tmp;
2894 uint32_t rb_bufsz;
2895
2896 /* set up gfx hqd wptr */
2897 mqd->cp_gfx_hqd_wptr = 0;
2898 mqd->cp_gfx_hqd_wptr_hi = 0;
2899
2900 /* set the pointer to the MQD */
2901 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
2902 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
2903
2904 /* set up mqd control */
2905 tmp = regCP_GFX_MQD_CONTROL_DEFAULT;
2906 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2907 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2908 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2909 mqd->cp_gfx_mqd_control = tmp;
2910
2911 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
2912 tmp = regCP_GFX_HQD_VMID_DEFAULT;
2913 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
2914 mqd->cp_gfx_hqd_vmid = 0;
2915
2916 /* set up default queue priority level
2917 * 0x0 = low priority, 0x1 = high priority */
2918 tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT;
2919 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
2920 mqd->cp_gfx_hqd_queue_priority = tmp;
2921
2922 /* set up time quantum */
2923 tmp = regCP_GFX_HQD_QUANTUM_DEFAULT;
2924 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
2925 mqd->cp_gfx_hqd_quantum = tmp;
2926
2927 /* set up gfx hqd base. this is similar as CP_RB_BASE */
2928 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
2929 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
2930 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
2931
2932 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
2933 wb_gpu_addr = prop->rptr_gpu_addr;
2934 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
2935 mqd->cp_gfx_hqd_rptr_addr_hi =
2936 upper_32_bits(wb_gpu_addr) & 0xffff;
2937
2938 /* set up rb_wptr_poll addr */
2939 wb_gpu_addr = prop->wptr_gpu_addr;
2940 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2941 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2942
2943 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
2944 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
2945 tmp = regCP_GFX_HQD_CNTL_DEFAULT;
2946 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
2947 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
2948 #ifdef __BIG_ENDIAN
2949 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
2950 #endif
2951 mqd->cp_gfx_hqd_cntl = tmp;
2952
2953 /* set up cp_doorbell_control */
2954 tmp = regCP_RB_DOORBELL_CONTROL_DEFAULT;
2955 if (prop->use_doorbell) {
2956 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2957 DOORBELL_OFFSET, prop->doorbell_index);
2958 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2959 DOORBELL_EN, 1);
2960 } else
2961 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2962 DOORBELL_EN, 0);
2963 mqd->cp_rb_doorbell_control = tmp;
2964
2965 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2966 mqd->cp_gfx_hqd_rptr = regCP_GFX_HQD_RPTR_DEFAULT;
2967
2968 /* active the queue */
2969 mqd->cp_gfx_hqd_active = 1;
2970
2971 return 0;
2972 }
2973
gfx_v12_0_kgq_init_queue(struct amdgpu_ring * ring,bool reset)2974 static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
2975 {
2976 struct amdgpu_device *adev = ring->adev;
2977 struct v12_gfx_mqd *mqd = ring->mqd_ptr;
2978 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
2979
2980 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
2981 memset((void *)mqd, 0, sizeof(*mqd));
2982 mutex_lock(&adev->srbm_mutex);
2983 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
2984 amdgpu_ring_init_mqd(ring);
2985 soc24_grbm_select(adev, 0, 0, 0, 0);
2986 mutex_unlock(&adev->srbm_mutex);
2987 if (adev->gfx.me.mqd_backup[mqd_idx])
2988 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
2989 } else {
2990 /* restore mqd with the backup copy */
2991 if (adev->gfx.me.mqd_backup[mqd_idx])
2992 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
2993 /* reset the ring */
2994 ring->wptr = 0;
2995 *ring->wptr_cpu_addr = 0;
2996 amdgpu_ring_clear_ring(ring);
2997 }
2998
2999 return 0;
3000 }
3001
gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)3002 static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3003 {
3004 int i, r;
3005
3006 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3007 r = gfx_v12_0_kgq_init_queue(&adev->gfx.gfx_ring[i], false);
3008 if (r)
3009 return r;
3010 }
3011
3012 r = amdgpu_gfx_enable_kgq(adev, 0);
3013 if (r)
3014 return r;
3015
3016 return gfx_v12_0_cp_gfx_start(adev);
3017 }
3018
gfx_v12_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)3019 static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3020 struct amdgpu_mqd_prop *prop)
3021 {
3022 struct v12_compute_mqd *mqd = m;
3023 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3024 uint32_t tmp;
3025
3026 mqd->header = 0xC0310800;
3027 mqd->compute_pipelinestat_enable = 0x00000001;
3028 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3029 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3030 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3031 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3032 mqd->compute_misc_reserved = 0x00000007;
3033
3034 eop_base_addr = prop->eop_gpu_addr >> 8;
3035 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3036 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3037
3038 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3039 tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
3040 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3041 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1));
3042
3043 mqd->cp_hqd_eop_control = tmp;
3044
3045 /* enable doorbell? */
3046 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3047
3048 if (prop->use_doorbell) {
3049 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3050 DOORBELL_OFFSET, prop->doorbell_index);
3051 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3052 DOORBELL_EN, 1);
3053 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3054 DOORBELL_SOURCE, 0);
3055 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3056 DOORBELL_HIT, 0);
3057 } else {
3058 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3059 DOORBELL_EN, 0);
3060 }
3061
3062 mqd->cp_hqd_pq_doorbell_control = tmp;
3063
3064 /* disable the queue if it's active */
3065 mqd->cp_hqd_dequeue_request = 0;
3066 mqd->cp_hqd_pq_rptr = 0;
3067 mqd->cp_hqd_pq_wptr_lo = 0;
3068 mqd->cp_hqd_pq_wptr_hi = 0;
3069
3070 /* set the pointer to the MQD */
3071 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3072 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3073
3074 /* set MQD vmid to 0 */
3075 tmp = regCP_MQD_CONTROL_DEFAULT;
3076 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3077 mqd->cp_mqd_control = tmp;
3078
3079 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3080 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3081 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3082 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3083
3084 /* set up the HQD, this is similar to CP_RB0_CNTL */
3085 tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
3086 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3087 (order_base_2(prop->queue_size / 4) - 1));
3088 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3089 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3090 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
3091 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3092 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3093 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3094 mqd->cp_hqd_pq_control = tmp;
3095
3096 /* set the wb address whether it's enabled or not */
3097 wb_gpu_addr = prop->rptr_gpu_addr;
3098 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3099 mqd->cp_hqd_pq_rptr_report_addr_hi =
3100 upper_32_bits(wb_gpu_addr) & 0xffff;
3101
3102 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3103 wb_gpu_addr = prop->wptr_gpu_addr;
3104 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3105 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3106
3107 tmp = 0;
3108 /* enable the doorbell if requested */
3109 if (prop->use_doorbell) {
3110 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT;
3111 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3112 DOORBELL_OFFSET, prop->doorbell_index);
3113
3114 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3115 DOORBELL_EN, 1);
3116 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3117 DOORBELL_SOURCE, 0);
3118 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3119 DOORBELL_HIT, 0);
3120 }
3121
3122 mqd->cp_hqd_pq_doorbell_control = tmp;
3123
3124 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3125 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT;
3126
3127 /* set the vmid for the queue */
3128 mqd->cp_hqd_vmid = 0;
3129
3130 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
3131 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3132 mqd->cp_hqd_persistent_state = tmp;
3133
3134 /* set MIN_IB_AVAIL_SIZE */
3135 tmp = regCP_HQD_IB_CONTROL_DEFAULT;
3136 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3137 mqd->cp_hqd_ib_control = tmp;
3138
3139 /* set static priority for a compute queue/ring */
3140 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3141 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3142
3143 mqd->cp_hqd_active = prop->hqd_active;
3144
3145 return 0;
3146 }
3147
gfx_v12_0_kiq_init_register(struct amdgpu_ring * ring)3148 static int gfx_v12_0_kiq_init_register(struct amdgpu_ring *ring)
3149 {
3150 struct amdgpu_device *adev = ring->adev;
3151 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3152 int j;
3153
3154 /* inactivate the queue */
3155 if (amdgpu_sriov_vf(adev))
3156 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3157
3158 /* disable wptr polling */
3159 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3160
3161 /* write the EOP addr */
3162 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3163 mqd->cp_hqd_eop_base_addr_lo);
3164 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3165 mqd->cp_hqd_eop_base_addr_hi);
3166
3167 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3168 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3169 mqd->cp_hqd_eop_control);
3170
3171 /* enable doorbell? */
3172 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3173 mqd->cp_hqd_pq_doorbell_control);
3174
3175 /* disable the queue if it's active */
3176 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3177 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3178 for (j = 0; j < adev->usec_timeout; j++) {
3179 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3180 break;
3181 udelay(1);
3182 }
3183 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3184 mqd->cp_hqd_dequeue_request);
3185 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3186 mqd->cp_hqd_pq_rptr);
3187 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3188 mqd->cp_hqd_pq_wptr_lo);
3189 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3190 mqd->cp_hqd_pq_wptr_hi);
3191 }
3192
3193 /* set the pointer to the MQD */
3194 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3195 mqd->cp_mqd_base_addr_lo);
3196 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3197 mqd->cp_mqd_base_addr_hi);
3198
3199 /* set MQD vmid to 0 */
3200 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3201 mqd->cp_mqd_control);
3202
3203 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3204 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3205 mqd->cp_hqd_pq_base_lo);
3206 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3207 mqd->cp_hqd_pq_base_hi);
3208
3209 /* set up the HQD, this is similar to CP_RB0_CNTL */
3210 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3211 mqd->cp_hqd_pq_control);
3212
3213 /* set the wb address whether it's enabled or not */
3214 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3215 mqd->cp_hqd_pq_rptr_report_addr_lo);
3216 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3217 mqd->cp_hqd_pq_rptr_report_addr_hi);
3218
3219 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3220 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3221 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3222 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3223 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3224
3225 /* enable the doorbell if requested */
3226 if (ring->use_doorbell) {
3227 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3228 (adev->doorbell_index.kiq * 2) << 2);
3229 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3230 (adev->doorbell_index.userqueue_end * 2) << 2);
3231 }
3232
3233 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3234 mqd->cp_hqd_pq_doorbell_control);
3235
3236 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3237 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3238 mqd->cp_hqd_pq_wptr_lo);
3239 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3240 mqd->cp_hqd_pq_wptr_hi);
3241
3242 /* set the vmid for the queue */
3243 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3244
3245 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3246 mqd->cp_hqd_persistent_state);
3247
3248 /* activate the queue */
3249 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3250 mqd->cp_hqd_active);
3251
3252 if (ring->use_doorbell)
3253 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3254
3255 return 0;
3256 }
3257
gfx_v12_0_kiq_init_queue(struct amdgpu_ring * ring)3258 static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring)
3259 {
3260 struct amdgpu_device *adev = ring->adev;
3261 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3262 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3263
3264 gfx_v12_0_kiq_setting(ring);
3265
3266 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3267 /* reset MQD to a clean status */
3268 if (adev->gfx.mec.mqd_backup[mqd_idx])
3269 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3270
3271 /* reset ring buffer */
3272 ring->wptr = 0;
3273 amdgpu_ring_clear_ring(ring);
3274
3275 mutex_lock(&adev->srbm_mutex);
3276 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3277 gfx_v12_0_kiq_init_register(ring);
3278 soc24_grbm_select(adev, 0, 0, 0, 0);
3279 mutex_unlock(&adev->srbm_mutex);
3280 } else {
3281 memset((void *)mqd, 0, sizeof(*mqd));
3282 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
3283 amdgpu_ring_clear_ring(ring);
3284 mutex_lock(&adev->srbm_mutex);
3285 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3286 amdgpu_ring_init_mqd(ring);
3287 gfx_v12_0_kiq_init_register(ring);
3288 soc24_grbm_select(adev, 0, 0, 0, 0);
3289 mutex_unlock(&adev->srbm_mutex);
3290
3291 if (adev->gfx.mec.mqd_backup[mqd_idx])
3292 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3293 }
3294
3295 return 0;
3296 }
3297
gfx_v12_0_kcq_init_queue(struct amdgpu_ring * ring,bool reset)3298 static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset)
3299 {
3300 struct amdgpu_device *adev = ring->adev;
3301 struct v12_compute_mqd *mqd = ring->mqd_ptr;
3302 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3303
3304 if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
3305 memset((void *)mqd, 0, sizeof(*mqd));
3306 mutex_lock(&adev->srbm_mutex);
3307 soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3308 amdgpu_ring_init_mqd(ring);
3309 soc24_grbm_select(adev, 0, 0, 0, 0);
3310 mutex_unlock(&adev->srbm_mutex);
3311
3312 if (adev->gfx.mec.mqd_backup[mqd_idx])
3313 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3314 } else {
3315 /* restore MQD to a clean status */
3316 if (adev->gfx.mec.mqd_backup[mqd_idx])
3317 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3318 /* reset ring buffer */
3319 ring->wptr = 0;
3320 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
3321 amdgpu_ring_clear_ring(ring);
3322 }
3323
3324 return 0;
3325 }
3326
gfx_v12_0_kiq_resume(struct amdgpu_device * adev)3327 static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)
3328 {
3329 gfx_v12_0_kiq_init_queue(&adev->gfx.kiq[0].ring);
3330 adev->gfx.kiq[0].ring.sched.ready = true;
3331 return 0;
3332 }
3333
gfx_v12_0_kcq_resume(struct amdgpu_device * adev)3334 static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)
3335 {
3336 int i, r;
3337
3338 if (!amdgpu_async_gfx_ring)
3339 gfx_v12_0_cp_compute_enable(adev, true);
3340
3341 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3342 r = gfx_v12_0_kcq_init_queue(&adev->gfx.compute_ring[i], false);
3343 if (r)
3344 return r;
3345 }
3346
3347 return amdgpu_gfx_enable_kcq(adev, 0);
3348 }
3349
gfx_v12_0_cp_resume(struct amdgpu_device * adev)3350 static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)
3351 {
3352 int r, i;
3353 struct amdgpu_ring *ring;
3354
3355 if (!(adev->flags & AMD_IS_APU))
3356 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3357
3358 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3359 /* legacy firmware loading */
3360 r = gfx_v12_0_cp_gfx_load_microcode(adev);
3361 if (r)
3362 return r;
3363
3364 r = gfx_v12_0_cp_compute_load_microcode_rs64(adev);
3365 if (r)
3366 return r;
3367 }
3368
3369 gfx_v12_0_cp_set_doorbell_range(adev);
3370
3371 if (amdgpu_async_gfx_ring) {
3372 gfx_v12_0_cp_compute_enable(adev, true);
3373 gfx_v12_0_cp_gfx_enable(adev, true);
3374 }
3375
3376 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
3377 r = amdgpu_mes_kiq_hw_init(adev);
3378 else
3379 r = gfx_v12_0_kiq_resume(adev);
3380 if (r)
3381 return r;
3382
3383 r = gfx_v12_0_kcq_resume(adev);
3384 if (r)
3385 return r;
3386
3387 if (!amdgpu_async_gfx_ring) {
3388 r = gfx_v12_0_cp_gfx_resume(adev);
3389 if (r)
3390 return r;
3391 } else {
3392 r = gfx_v12_0_cp_async_gfx_ring_resume(adev);
3393 if (r)
3394 return r;
3395 }
3396
3397 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3398 ring = &adev->gfx.gfx_ring[i];
3399 r = amdgpu_ring_test_helper(ring);
3400 if (r)
3401 return r;
3402 }
3403
3404 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3405 ring = &adev->gfx.compute_ring[i];
3406 r = amdgpu_ring_test_helper(ring);
3407 if (r)
3408 return r;
3409 }
3410
3411 return 0;
3412 }
3413
gfx_v12_0_cp_enable(struct amdgpu_device * adev,bool enable)3414 static void gfx_v12_0_cp_enable(struct amdgpu_device *adev, bool enable)
3415 {
3416 gfx_v12_0_cp_gfx_enable(adev, enable);
3417 gfx_v12_0_cp_compute_enable(adev, enable);
3418 }
3419
gfx_v12_0_gfxhub_enable(struct amdgpu_device * adev)3420 static int gfx_v12_0_gfxhub_enable(struct amdgpu_device *adev)
3421 {
3422 int r;
3423 bool value;
3424
3425 r = adev->gfxhub.funcs->gart_enable(adev);
3426 if (r)
3427 return r;
3428
3429 amdgpu_device_flush_hdp(adev, NULL);
3430
3431 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
3432 false : true;
3433
3434 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
3435 /* TODO investigate why this and the hdp flush above is needed,
3436 * are we missing a flush somewhere else? */
3437 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
3438
3439 return 0;
3440 }
3441
get_gb_addr_config(struct amdgpu_device * adev)3442 static int get_gb_addr_config(struct amdgpu_device *adev)
3443 {
3444 u32 gb_addr_config;
3445
3446 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
3447 if (gb_addr_config == 0)
3448 return -EINVAL;
3449
3450 adev->gfx.config.gb_addr_config_fields.num_pkrs =
3451 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
3452
3453 adev->gfx.config.gb_addr_config = gb_addr_config;
3454
3455 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
3456 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3457 GB_ADDR_CONFIG, NUM_PIPES);
3458
3459 adev->gfx.config.max_tile_pipes =
3460 adev->gfx.config.gb_addr_config_fields.num_pipes;
3461
3462 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
3463 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3464 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
3465 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
3466 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3467 GB_ADDR_CONFIG, NUM_RB_PER_SE);
3468 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
3469 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3470 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
3471 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
3472 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
3473 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
3474
3475 return 0;
3476 }
3477
gfx_v12_0_disable_gpa_mode(struct amdgpu_device * adev)3478 static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev)
3479 {
3480 uint32_t data;
3481
3482 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
3483 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
3484 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
3485
3486 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
3487 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
3488 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
3489 }
3490
gfx_v12_0_init_golden_registers(struct amdgpu_device * adev)3491 static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)
3492 {
3493 if (amdgpu_sriov_vf(adev))
3494 return;
3495
3496 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3497 case IP_VERSION(12, 0, 0):
3498 case IP_VERSION(12, 0, 1):
3499 soc15_program_register_sequence(adev,
3500 golden_settings_gc_12_0,
3501 (const u32)ARRAY_SIZE(golden_settings_gc_12_0));
3502
3503 if (adev->rev_id == 0)
3504 soc15_program_register_sequence(adev,
3505 golden_settings_gc_12_0_rev0,
3506 (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0));
3507 break;
3508 default:
3509 break;
3510 }
3511 }
3512
gfx_v12_0_hw_init(struct amdgpu_ip_block * ip_block)3513 static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block)
3514 {
3515 int r;
3516 struct amdgpu_device *adev = ip_block->adev;
3517
3518 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
3519 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3520 /* RLC autoload sequence 1: Program rlc ram */
3521 if (adev->gfx.imu.funcs->program_rlc_ram)
3522 adev->gfx.imu.funcs->program_rlc_ram(adev);
3523 }
3524 /* rlc autoload firmware */
3525 r = gfx_v12_0_rlc_backdoor_autoload_enable(adev);
3526 if (r)
3527 return r;
3528 } else {
3529 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3530 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
3531 if (adev->gfx.imu.funcs->load_microcode)
3532 adev->gfx.imu.funcs->load_microcode(adev);
3533 if (adev->gfx.imu.funcs->setup_imu)
3534 adev->gfx.imu.funcs->setup_imu(adev);
3535 if (adev->gfx.imu.funcs->start_imu)
3536 adev->gfx.imu.funcs->start_imu(adev);
3537 }
3538
3539 /* disable gpa mode in backdoor loading */
3540 gfx_v12_0_disable_gpa_mode(adev);
3541 }
3542 }
3543
3544 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
3545 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3546 r = gfx_v12_0_wait_for_rlc_autoload_complete(adev);
3547 if (r) {
3548 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
3549 return r;
3550 }
3551 }
3552
3553 if (!amdgpu_emu_mode)
3554 gfx_v12_0_init_golden_registers(adev);
3555
3556 adev->gfx.is_poweron = true;
3557
3558 if (get_gb_addr_config(adev))
3559 DRM_WARN("Invalid gb_addr_config !\n");
3560
3561 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
3562 gfx_v12_0_config_gfx_rs64(adev);
3563
3564 r = gfx_v12_0_gfxhub_enable(adev);
3565 if (r)
3566 return r;
3567
3568 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT ||
3569 adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) &&
3570 (amdgpu_dpm == 1)) {
3571 /**
3572 * For gfx 12, rlc firmware loading relies on smu firmware is
3573 * loaded firstly, so in direct type, it has to load smc ucode
3574 * here before rlc.
3575 */
3576 r = amdgpu_pm_load_smu_firmware(adev, NULL);
3577 if (r)
3578 return r;
3579 }
3580
3581 gfx_v12_0_constants_init(adev);
3582
3583 if (adev->nbio.funcs->gc_doorbell_init)
3584 adev->nbio.funcs->gc_doorbell_init(adev);
3585
3586 r = gfx_v12_0_rlc_resume(adev);
3587 if (r)
3588 return r;
3589
3590 /*
3591 * init golden registers and rlc resume may override some registers,
3592 * reconfig them here
3593 */
3594 gfx_v12_0_tcp_harvest(adev);
3595
3596 r = gfx_v12_0_cp_resume(adev);
3597 if (r)
3598 return r;
3599
3600 return r;
3601 }
3602
gfx_v12_0_hw_fini(struct amdgpu_ip_block * ip_block)3603 static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block)
3604 {
3605 struct amdgpu_device *adev = ip_block->adev;
3606 uint32_t tmp;
3607
3608 cancel_delayed_work_sync(&adev->gfx.idle_work);
3609
3610 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3611 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3612 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
3613
3614 if (!adev->no_hw_access) {
3615 if (amdgpu_async_gfx_ring) {
3616 if (amdgpu_gfx_disable_kgq(adev, 0))
3617 DRM_ERROR("KGQ disable failed\n");
3618 }
3619
3620 if (amdgpu_gfx_disable_kcq(adev, 0))
3621 DRM_ERROR("KCQ disable failed\n");
3622
3623 amdgpu_mes_kiq_hw_fini(adev);
3624 }
3625
3626 if (amdgpu_sriov_vf(adev)) {
3627 gfx_v12_0_cp_gfx_enable(adev, false);
3628 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
3629 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3630 tmp &= 0xffffff00;
3631 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3632
3633 return 0;
3634 }
3635 gfx_v12_0_cp_enable(adev, false);
3636 gfx_v12_0_enable_gui_idle_interrupt(adev, false);
3637
3638 adev->gfxhub.funcs->gart_disable(adev);
3639
3640 adev->gfx.is_poweron = false;
3641
3642 return 0;
3643 }
3644
gfx_v12_0_suspend(struct amdgpu_ip_block * ip_block)3645 static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block)
3646 {
3647 return gfx_v12_0_hw_fini(ip_block);
3648 }
3649
gfx_v12_0_resume(struct amdgpu_ip_block * ip_block)3650 static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
3651 {
3652 return gfx_v12_0_hw_init(ip_block);
3653 }
3654
gfx_v12_0_is_idle(struct amdgpu_ip_block * ip_block)3655 static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
3656 {
3657 struct amdgpu_device *adev = ip_block->adev;
3658
3659 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
3660 GRBM_STATUS, GUI_ACTIVE))
3661 return false;
3662 else
3663 return true;
3664 }
3665
gfx_v12_0_wait_for_idle(struct amdgpu_ip_block * ip_block)3666 static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
3667 {
3668 unsigned i;
3669 u32 tmp;
3670 struct amdgpu_device *adev = ip_block->adev;
3671
3672 for (i = 0; i < adev->usec_timeout; i++) {
3673 /* read MC_STATUS */
3674 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
3675 GRBM_STATUS__GUI_ACTIVE_MASK;
3676
3677 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3678 return 0;
3679 udelay(1);
3680 }
3681 return -ETIMEDOUT;
3682 }
3683
gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device * adev)3684 static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3685 {
3686 uint64_t clock = 0;
3687
3688 if (adev->smuio.funcs &&
3689 adev->smuio.funcs->get_gpu_clock_counter)
3690 clock = adev->smuio.funcs->get_gpu_clock_counter(adev);
3691 else
3692 dev_warn(adev->dev, "query gpu clock counter is not supported\n");
3693
3694 return clock;
3695 }
3696
gfx_v12_0_early_init(struct amdgpu_ip_block * ip_block)3697 static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block)
3698 {
3699 struct amdgpu_device *adev = ip_block->adev;
3700
3701 adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
3702
3703 adev->gfx.num_gfx_rings = GFX12_NUM_GFX_RINGS;
3704 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3705 AMDGPU_MAX_COMPUTE_RINGS);
3706
3707 gfx_v12_0_set_kiq_pm4_funcs(adev);
3708 gfx_v12_0_set_ring_funcs(adev);
3709 gfx_v12_0_set_irq_funcs(adev);
3710 gfx_v12_0_set_rlc_funcs(adev);
3711 gfx_v12_0_set_mqd_funcs(adev);
3712 gfx_v12_0_set_imu_funcs(adev);
3713
3714 gfx_v12_0_init_rlcg_reg_access_ctrl(adev);
3715
3716 return gfx_v12_0_init_microcode(adev);
3717 }
3718
gfx_v12_0_late_init(struct amdgpu_ip_block * ip_block)3719 static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block)
3720 {
3721 struct amdgpu_device *adev = ip_block->adev;
3722 int r;
3723
3724 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3725 if (r)
3726 return r;
3727
3728 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3729 if (r)
3730 return r;
3731
3732 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
3733 if (r)
3734 return r;
3735
3736 return 0;
3737 }
3738
gfx_v12_0_is_rlc_enabled(struct amdgpu_device * adev)3739 static bool gfx_v12_0_is_rlc_enabled(struct amdgpu_device *adev)
3740 {
3741 uint32_t rlc_cntl;
3742
3743 /* if RLC is not enabled, do nothing */
3744 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
3745 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
3746 }
3747
gfx_v12_0_set_safe_mode(struct amdgpu_device * adev,int xcc_id)3748 static void gfx_v12_0_set_safe_mode(struct amdgpu_device *adev,
3749 int xcc_id)
3750 {
3751 uint32_t data;
3752 unsigned i;
3753
3754 data = RLC_SAFE_MODE__CMD_MASK;
3755 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3756
3757 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
3758
3759 /* wait for RLC_SAFE_MODE */
3760 for (i = 0; i < adev->usec_timeout; i++) {
3761 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
3762 RLC_SAFE_MODE, CMD))
3763 break;
3764 udelay(1);
3765 }
3766 }
3767
gfx_v12_0_unset_safe_mode(struct amdgpu_device * adev,int xcc_id)3768 static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,
3769 int xcc_id)
3770 {
3771 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
3772 }
3773
gfx_v12_0_update_perf_clk(struct amdgpu_device * adev,bool enable)3774 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
3775 bool enable)
3776 {
3777 uint32_t def, data;
3778
3779 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
3780 return;
3781
3782 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3783
3784 if (enable)
3785 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3786 else
3787 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
3788
3789 if (def != data)
3790 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
3791 }
3792
gfx_v12_0_update_spm_vmid(struct amdgpu_device * adev,struct amdgpu_ring * ring,unsigned vmid)3793 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
3794 struct amdgpu_ring *ring,
3795 unsigned vmid)
3796 {
3797 u32 reg, data;
3798
3799 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3800 if (amdgpu_sriov_is_pp_one_vf(adev))
3801 data = RREG32_NO_KIQ(reg);
3802 else
3803 data = RREG32(reg);
3804
3805 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
3806 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
3807
3808 if (amdgpu_sriov_is_pp_one_vf(adev))
3809 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
3810 else
3811 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
3812
3813 if (ring
3814 && amdgpu_sriov_is_pp_one_vf(adev)
3815 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX)
3816 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) {
3817 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
3818 amdgpu_ring_emit_wreg(ring, reg, data);
3819 }
3820 }
3821
3822 static const struct amdgpu_rlc_funcs gfx_v12_0_rlc_funcs = {
3823 .is_rlc_enabled = gfx_v12_0_is_rlc_enabled,
3824 .set_safe_mode = gfx_v12_0_set_safe_mode,
3825 .unset_safe_mode = gfx_v12_0_unset_safe_mode,
3826 .init = gfx_v12_0_rlc_init,
3827 .get_csb_size = gfx_v12_0_get_csb_size,
3828 .get_csb_buffer = gfx_v12_0_get_csb_buffer,
3829 .resume = gfx_v12_0_rlc_resume,
3830 .stop = gfx_v12_0_rlc_stop,
3831 .reset = gfx_v12_0_rlc_reset,
3832 .start = gfx_v12_0_rlc_start,
3833 .update_spm_vmid = gfx_v12_0_update_spm_vmid,
3834 };
3835
3836 #if 0
3837 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable)
3838 {
3839 /* TODO */
3840 }
3841
3842 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
3843 {
3844 /* TODO */
3845 }
3846 #endif
3847
gfx_v12_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)3848 static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3849 enum amd_powergating_state state)
3850 {
3851 struct amdgpu_device *adev = ip_block->adev;
3852 bool enable = (state == AMD_PG_STATE_GATE);
3853
3854 if (amdgpu_sriov_vf(adev))
3855 return 0;
3856
3857 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3858 case IP_VERSION(12, 0, 0):
3859 case IP_VERSION(12, 0, 1):
3860 amdgpu_gfx_off_ctrl(adev, enable);
3861 break;
3862 default:
3863 break;
3864 }
3865
3866 return 0;
3867 }
3868
gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)3869 static void gfx_v12_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3870 bool enable)
3871 {
3872 uint32_t def, data;
3873
3874 if (!(adev->cg_flags &
3875 (AMD_CG_SUPPORT_GFX_CGCG |
3876 AMD_CG_SUPPORT_GFX_CGLS |
3877 AMD_CG_SUPPORT_GFX_3D_CGCG |
3878 AMD_CG_SUPPORT_GFX_3D_CGLS)))
3879 return;
3880
3881 if (enable) {
3882 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3883
3884 /* unset CGCG override */
3885 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
3886 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3887 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3888 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3889 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
3890 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3891 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3892
3893 /* update CGCG override bits */
3894 if (def != data)
3895 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
3896
3897 /* enable cgcg FSM(0x0000363F) */
3898 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
3899
3900 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
3901 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
3902 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3903 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3904 }
3905
3906 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
3907 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
3908 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3909 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3910 }
3911
3912 if (def != data)
3913 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
3914
3915 /* Program RLC_CGCG_CGLS_CTRL_3D */
3916 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
3917
3918 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
3919 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
3920 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3921 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3922 }
3923
3924 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
3925 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
3926 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3927 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3928 }
3929
3930 if (def != data)
3931 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
3932
3933 /* set IDLE_POLL_COUNT(0x00900100) */
3934 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
3935
3936 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
3937 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3938 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3939
3940 if (def != data)
3941 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
3942
3943 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
3944 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
3945 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
3946 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
3947 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
3948 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
3949
3950 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
3951 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
3952 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
3953
3954 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
3955 if (adev->sdma.num_instances > 1) {
3956 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
3957 data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
3958 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
3959 }
3960 } else {
3961 /* Program RLC_CGCG_CGLS_CTRL */
3962 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
3963
3964 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
3965 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3966
3967 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3968 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3969
3970 if (def != data)
3971 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
3972
3973 /* Program RLC_CGCG_CGLS_CTRL_3D */
3974 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
3975
3976 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
3977 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3978 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3979 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3980
3981 if (def != data)
3982 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
3983 }
3984 }
3985
gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)3986 static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3987 bool enable)
3988 {
3989 uint32_t data, def;
3990 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
3991 return;
3992
3993 /* It is disabled by HW by default */
3994 if (enable) {
3995 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
3996 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3997 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3998
3999 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4000 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4001 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4002
4003 if (def != data)
4004 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4005 }
4006 } else {
4007 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4008 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4009
4010 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4011 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4012 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4013
4014 if (def != data)
4015 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4016 }
4017 }
4018 }
4019
gfx_v12_0_update_repeater_fgcg(struct amdgpu_device * adev,bool enable)4020 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,
4021 bool enable)
4022 {
4023 uint32_t def, data;
4024
4025 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4026 return;
4027
4028 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4029
4030 if (enable)
4031 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4032 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);
4033 else
4034 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
4035 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;
4036
4037 if (def != data)
4038 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4039 }
4040
gfx_v12_0_update_sram_fgcg(struct amdgpu_device * adev,bool enable)4041 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,
4042 bool enable)
4043 {
4044 uint32_t def, data;
4045
4046 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4047 return;
4048
4049 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4050
4051 if (enable)
4052 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4053 else
4054 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4055
4056 if (def != data)
4057 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4058 }
4059
gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)4060 static int gfx_v12_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4061 bool enable)
4062 {
4063 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4064
4065 gfx_v12_0_update_coarse_grain_clock_gating(adev, enable);
4066
4067 gfx_v12_0_update_medium_grain_clock_gating(adev, enable);
4068
4069 gfx_v12_0_update_repeater_fgcg(adev, enable);
4070
4071 gfx_v12_0_update_sram_fgcg(adev, enable);
4072
4073 gfx_v12_0_update_perf_clk(adev, enable);
4074
4075 if (adev->cg_flags &
4076 (AMD_CG_SUPPORT_GFX_MGCG |
4077 AMD_CG_SUPPORT_GFX_CGLS |
4078 AMD_CG_SUPPORT_GFX_CGCG |
4079 AMD_CG_SUPPORT_GFX_3D_CGCG |
4080 AMD_CG_SUPPORT_GFX_3D_CGLS))
4081 gfx_v12_0_enable_gui_idle_interrupt(adev, enable);
4082
4083 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4084
4085 return 0;
4086 }
4087
gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)4088 static int gfx_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
4089 enum amd_clockgating_state state)
4090 {
4091 struct amdgpu_device *adev = ip_block->adev;
4092
4093 if (amdgpu_sriov_vf(adev))
4094 return 0;
4095
4096 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4097 case IP_VERSION(12, 0, 0):
4098 case IP_VERSION(12, 0, 1):
4099 gfx_v12_0_update_gfx_clock_gating(adev,
4100 state == AMD_CG_STATE_GATE);
4101 break;
4102 default:
4103 break;
4104 }
4105
4106 return 0;
4107 }
4108
gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)4109 static void gfx_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
4110 {
4111 struct amdgpu_device *adev = ip_block->adev;
4112 int data;
4113
4114 /* AMD_CG_SUPPORT_GFX_MGCG */
4115 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4116 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4117 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4118
4119 /* AMD_CG_SUPPORT_REPEATER_FGCG */
4120 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
4121 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
4122
4123 /* AMD_CG_SUPPORT_GFX_FGCG */
4124 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
4125 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
4126
4127 /* AMD_CG_SUPPORT_GFX_PERF_CLK */
4128 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
4129 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
4130
4131 /* AMD_CG_SUPPORT_GFX_CGCG */
4132 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4133 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4134 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4135
4136 /* AMD_CG_SUPPORT_GFX_CGLS */
4137 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4138 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4139
4140 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
4141 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4142 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4143 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4144
4145 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
4146 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4147 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4148 }
4149
gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)4150 static u64 gfx_v12_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4151 {
4152 /* gfx12 is 32bit rptr*/
4153 return *(uint32_t *)ring->rptr_cpu_addr;
4154 }
4155
gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)4156 static u64 gfx_v12_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4157 {
4158 struct amdgpu_device *adev = ring->adev;
4159 u64 wptr;
4160
4161 /* XXX check if swapping is necessary on BE */
4162 if (ring->use_doorbell) {
4163 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4164 } else {
4165 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
4166 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
4167 }
4168
4169 return wptr;
4170 }
4171
gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)4172 static void gfx_v12_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4173 {
4174 struct amdgpu_device *adev = ring->adev;
4175 uint32_t *wptr_saved;
4176 uint32_t *is_queue_unmap;
4177 uint64_t aggregated_db_index;
4178 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
4179 uint64_t wptr_tmp;
4180
4181 if (ring->is_mes_queue) {
4182 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
4183 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
4184 sizeof(uint32_t));
4185 aggregated_db_index =
4186 amdgpu_mes_get_aggregated_doorbell_index(adev,
4187 ring->hw_prio);
4188
4189 wptr_tmp = ring->wptr & ring->buf_mask;
4190 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
4191 *wptr_saved = wptr_tmp;
4192 /* assume doorbell always being used by mes mapped queue */
4193 if (*is_queue_unmap) {
4194 WDOORBELL64(aggregated_db_index, wptr_tmp);
4195 WDOORBELL64(ring->doorbell_index, wptr_tmp);
4196 } else {
4197 WDOORBELL64(ring->doorbell_index, wptr_tmp);
4198
4199 if (*is_queue_unmap)
4200 WDOORBELL64(aggregated_db_index, wptr_tmp);
4201 }
4202 } else {
4203 if (ring->use_doorbell) {
4204 /* XXX check if swapping is necessary on BE */
4205 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4206 ring->wptr);
4207 WDOORBELL64(ring->doorbell_index, ring->wptr);
4208 } else {
4209 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
4210 lower_32_bits(ring->wptr));
4211 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
4212 upper_32_bits(ring->wptr));
4213 }
4214 }
4215 }
4216
gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring * ring)4217 static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4218 {
4219 /* gfx12 hardware is 32bit rptr */
4220 return *(uint32_t *)ring->rptr_cpu_addr;
4221 }
4222
gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring * ring)4223 static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4224 {
4225 u64 wptr;
4226
4227 /* XXX check if swapping is necessary on BE */
4228 if (ring->use_doorbell)
4229 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
4230 else
4231 BUG();
4232 return wptr;
4233 }
4234
gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring * ring)4235 static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4236 {
4237 struct amdgpu_device *adev = ring->adev;
4238 uint32_t *wptr_saved;
4239 uint32_t *is_queue_unmap;
4240 uint64_t aggregated_db_index;
4241 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
4242 uint64_t wptr_tmp;
4243
4244 if (ring->is_mes_queue) {
4245 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
4246 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
4247 sizeof(uint32_t));
4248 aggregated_db_index =
4249 amdgpu_mes_get_aggregated_doorbell_index(adev,
4250 ring->hw_prio);
4251
4252 wptr_tmp = ring->wptr & ring->buf_mask;
4253 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
4254 *wptr_saved = wptr_tmp;
4255 /* assume doorbell always used by mes mapped queue */
4256 if (*is_queue_unmap) {
4257 WDOORBELL64(aggregated_db_index, wptr_tmp);
4258 WDOORBELL64(ring->doorbell_index, wptr_tmp);
4259 } else {
4260 WDOORBELL64(ring->doorbell_index, wptr_tmp);
4261
4262 if (*is_queue_unmap)
4263 WDOORBELL64(aggregated_db_index, wptr_tmp);
4264 }
4265 } else {
4266 /* XXX check if swapping is necessary on BE */
4267 if (ring->use_doorbell) {
4268 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
4269 ring->wptr);
4270 WDOORBELL64(ring->doorbell_index, ring->wptr);
4271 } else {
4272 BUG(); /* only DOORBELL method supported on gfx12 now */
4273 }
4274 }
4275 }
4276
gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)4277 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4278 {
4279 struct amdgpu_device *adev = ring->adev;
4280 u32 ref_and_mask, reg_mem_engine;
4281 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4282
4283 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4284 switch (ring->me) {
4285 case 1:
4286 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4287 break;
4288 case 2:
4289 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4290 break;
4291 default:
4292 return;
4293 }
4294 reg_mem_engine = 0;
4295 } else {
4296 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4297 reg_mem_engine = 1; /* pfp */
4298 }
4299
4300 gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4301 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4302 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4303 ref_and_mask, ref_and_mask, 0x20);
4304 }
4305
gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4306 static void gfx_v12_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4307 struct amdgpu_job *job,
4308 struct amdgpu_ib *ib,
4309 uint32_t flags)
4310 {
4311 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4312 u32 header, control = 0;
4313
4314 BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
4315
4316 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4317
4318 control |= ib->length_dw | (vmid << 24);
4319
4320 if (ring->is_mes_queue)
4321 /* inherit vmid from mqd */
4322 control |= 0x400000;
4323
4324 amdgpu_ring_write(ring, header);
4325 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4326 amdgpu_ring_write(ring,
4327 #ifdef __BIG_ENDIAN
4328 (2 << 0) |
4329 #endif
4330 lower_32_bits(ib->gpu_addr));
4331 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4332 amdgpu_ring_write(ring, control);
4333 }
4334
gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)4335 static void gfx_v12_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4336 struct amdgpu_job *job,
4337 struct amdgpu_ib *ib,
4338 uint32_t flags)
4339 {
4340 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4341 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4342
4343 if (ring->is_mes_queue)
4344 /* inherit vmid from mqd */
4345 control |= 0x40000000;
4346
4347 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4348 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4349 amdgpu_ring_write(ring,
4350 #ifdef __BIG_ENDIAN
4351 (2 << 0) |
4352 #endif
4353 lower_32_bits(ib->gpu_addr));
4354 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4355 amdgpu_ring_write(ring, control);
4356 }
4357
gfx_v12_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)4358 static void gfx_v12_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4359 u64 seq, unsigned flags)
4360 {
4361 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4362 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4363
4364 /* RELEASE_MEM - flush caches, send int */
4365 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4366 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4367 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4368 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4369 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4370 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4371 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4372 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4373
4374 /*
4375 * the address should be Qword aligned if 64bit write, Dword
4376 * aligned if only send 32bit data low (discard data high)
4377 */
4378 if (write64bit)
4379 BUG_ON(addr & 0x7);
4380 else
4381 BUG_ON(addr & 0x3);
4382 amdgpu_ring_write(ring, lower_32_bits(addr));
4383 amdgpu_ring_write(ring, upper_32_bits(addr));
4384 amdgpu_ring_write(ring, lower_32_bits(seq));
4385 amdgpu_ring_write(ring, upper_32_bits(seq));
4386 amdgpu_ring_write(ring, ring->is_mes_queue ?
4387 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
4388 }
4389
gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)4390 static void gfx_v12_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4391 {
4392 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4393 uint32_t seq = ring->fence_drv.sync_seq;
4394 uint64_t addr = ring->fence_drv.gpu_addr;
4395
4396 gfx_v12_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4397 upper_32_bits(addr), seq, 0xffffffff, 4);
4398 }
4399
gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)4400 static void gfx_v12_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
4401 uint16_t pasid, uint32_t flush_type,
4402 bool all_hub, uint8_t dst_sel)
4403 {
4404 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
4405 amdgpu_ring_write(ring,
4406 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
4407 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
4408 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
4409 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
4410 }
4411
gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)4412 static void gfx_v12_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4413 unsigned vmid, uint64_t pd_addr)
4414 {
4415 if (ring->is_mes_queue)
4416 gfx_v12_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
4417 else
4418 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4419
4420 /* compute doesn't have PFP */
4421 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4422 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4423 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4424 amdgpu_ring_write(ring, 0x0);
4425 }
4426 }
4427
gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)4428 static void gfx_v12_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4429 u64 seq, unsigned int flags)
4430 {
4431 struct amdgpu_device *adev = ring->adev;
4432
4433 /* we only allocate 32bit for each seq wb address */
4434 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4435
4436 /* write fence seq to the "addr" */
4437 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4438 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4439 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4440 amdgpu_ring_write(ring, lower_32_bits(addr));
4441 amdgpu_ring_write(ring, upper_32_bits(addr));
4442 amdgpu_ring_write(ring, lower_32_bits(seq));
4443
4444 if (flags & AMDGPU_FENCE_FLAG_INT) {
4445 /* set register to trigger INT */
4446 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4447 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4448 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4449 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
4450 amdgpu_ring_write(ring, 0);
4451 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4452 }
4453 }
4454
gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)4455 static void gfx_v12_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
4456 uint32_t flags)
4457 {
4458 uint32_t dw2 = 0;
4459
4460 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4461 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4462 /* set load_global_config & load_global_uconfig */
4463 dw2 |= 0x8001;
4464 /* set load_cs_sh_regs */
4465 dw2 |= 0x01000000;
4466 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4467 dw2 |= 0x10002;
4468 }
4469
4470 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4471 amdgpu_ring_write(ring, dw2);
4472 amdgpu_ring_write(ring, 0);
4473 }
4474
gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)4475 static unsigned gfx_v12_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
4476 uint64_t addr)
4477 {
4478 unsigned ret;
4479
4480 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4481 amdgpu_ring_write(ring, lower_32_bits(addr));
4482 amdgpu_ring_write(ring, upper_32_bits(addr));
4483 /* discard following DWs if *cond_exec_gpu_addr==0 */
4484 amdgpu_ring_write(ring, 0);
4485 ret = ring->wptr & ring->buf_mask;
4486 /* patch dummy value later */
4487 amdgpu_ring_write(ring, 0);
4488
4489 return ret;
4490 }
4491
gfx_v12_0_ring_preempt_ib(struct amdgpu_ring * ring)4492 static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring)
4493 {
4494 int i, r = 0;
4495 struct amdgpu_device *adev = ring->adev;
4496 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4497 struct amdgpu_ring *kiq_ring = &kiq->ring;
4498 unsigned long flags;
4499
4500 if (adev->enable_mes)
4501 return -EINVAL;
4502
4503 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4504 return -EINVAL;
4505
4506 spin_lock_irqsave(&kiq->ring_lock, flags);
4507
4508 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
4509 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4510 return -ENOMEM;
4511 }
4512
4513 /* assert preemption condition */
4514 amdgpu_ring_set_preempt_cond_exec(ring, false);
4515
4516 /* assert IB preemption, emit the trailing fence */
4517 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4518 ring->trail_fence_gpu_addr,
4519 ++ring->trail_seq);
4520 amdgpu_ring_commit(kiq_ring);
4521
4522 spin_unlock_irqrestore(&kiq->ring_lock, flags);
4523
4524 /* poll the trailing fence */
4525 for (i = 0; i < adev->usec_timeout; i++) {
4526 if (ring->trail_seq ==
4527 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4528 break;
4529 udelay(1);
4530 }
4531
4532 if (i >= adev->usec_timeout) {
4533 r = -EINVAL;
4534 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4535 }
4536
4537 /* deassert preemption condition */
4538 amdgpu_ring_set_preempt_cond_exec(ring, true);
4539 return r;
4540 }
4541
gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)4542 static void gfx_v12_0_ring_emit_frame_cntl(struct amdgpu_ring *ring,
4543 bool start,
4544 bool secure)
4545 {
4546 uint32_t v = secure ? FRAME_TMZ : 0;
4547
4548 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4549 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
4550 }
4551
gfx_v12_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)4552 static void gfx_v12_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
4553 uint32_t reg_val_offs)
4554 {
4555 struct amdgpu_device *adev = ring->adev;
4556
4557 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4558 amdgpu_ring_write(ring, 0 | /* src: register*/
4559 (5 << 8) | /* dst: memory */
4560 (1 << 20)); /* write confirm */
4561 amdgpu_ring_write(ring, reg);
4562 amdgpu_ring_write(ring, 0);
4563 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4564 reg_val_offs * 4));
4565 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4566 reg_val_offs * 4));
4567 }
4568
gfx_v12_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)4569 static void gfx_v12_0_ring_emit_wreg(struct amdgpu_ring *ring,
4570 uint32_t reg,
4571 uint32_t val)
4572 {
4573 uint32_t cmd = 0;
4574
4575 switch (ring->funcs->type) {
4576 case AMDGPU_RING_TYPE_GFX:
4577 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4578 break;
4579 case AMDGPU_RING_TYPE_KIQ:
4580 cmd = (1 << 16); /* no inc addr */
4581 break;
4582 default:
4583 cmd = WR_CONFIRM;
4584 break;
4585 }
4586 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4587 amdgpu_ring_write(ring, cmd);
4588 amdgpu_ring_write(ring, reg);
4589 amdgpu_ring_write(ring, 0);
4590 amdgpu_ring_write(ring, val);
4591 }
4592
gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)4593 static void gfx_v12_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4594 uint32_t val, uint32_t mask)
4595 {
4596 gfx_v12_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4597 }
4598
gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)4599 static void gfx_v12_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4600 uint32_t reg0, uint32_t reg1,
4601 uint32_t ref, uint32_t mask)
4602 {
4603 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4604
4605 gfx_v12_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4606 ref, mask, 0x20);
4607 }
4608
gfx_v12_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned vmid)4609 static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring,
4610 unsigned vmid)
4611 {
4612 struct amdgpu_device *adev = ring->adev;
4613 uint32_t value = 0;
4614
4615 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4616 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4617 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4618 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4619 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4620 WREG32_SOC15(GC, 0, regSQ_CMD, value);
4621 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4622 }
4623
4624 static void
gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)4625 gfx_v12_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4626 uint32_t me, uint32_t pipe,
4627 enum amdgpu_interrupt_state state)
4628 {
4629 uint32_t cp_int_cntl, cp_int_cntl_reg;
4630
4631 if (!me) {
4632 switch (pipe) {
4633 case 0:
4634 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
4635 break;
4636 default:
4637 DRM_DEBUG("invalid pipe %d\n", pipe);
4638 return;
4639 }
4640 } else {
4641 DRM_DEBUG("invalid me %d\n", me);
4642 return;
4643 }
4644
4645 switch (state) {
4646 case AMDGPU_IRQ_STATE_DISABLE:
4647 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4648 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4649 TIME_STAMP_INT_ENABLE, 0);
4650 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4651 GENERIC0_INT_ENABLE, 0);
4652 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4653 break;
4654 case AMDGPU_IRQ_STATE_ENABLE:
4655 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4656 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4657 TIME_STAMP_INT_ENABLE, 1);
4658 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4659 GENERIC0_INT_ENABLE, 1);
4660 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4661 break;
4662 default:
4663 break;
4664 }
4665 }
4666
gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)4667 static void gfx_v12_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4668 int me, int pipe,
4669 enum amdgpu_interrupt_state state)
4670 {
4671 u32 mec_int_cntl, mec_int_cntl_reg;
4672
4673 /*
4674 * amdgpu controls only the first MEC. That's why this function only
4675 * handles the setting of interrupts for this specific MEC. All other
4676 * pipes' interrupts are set by amdkfd.
4677 */
4678
4679 if (me == 1) {
4680 switch (pipe) {
4681 case 0:
4682 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
4683 break;
4684 case 1:
4685 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
4686 break;
4687 default:
4688 DRM_DEBUG("invalid pipe %d\n", pipe);
4689 return;
4690 }
4691 } else {
4692 DRM_DEBUG("invalid me %d\n", me);
4693 return;
4694 }
4695
4696 switch (state) {
4697 case AMDGPU_IRQ_STATE_DISABLE:
4698 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4699 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4700 TIME_STAMP_INT_ENABLE, 0);
4701 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4702 GENERIC0_INT_ENABLE, 0);
4703 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4704 break;
4705 case AMDGPU_IRQ_STATE_ENABLE:
4706 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4707 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4708 TIME_STAMP_INT_ENABLE, 1);
4709 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4710 GENERIC0_INT_ENABLE, 1);
4711 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4712 break;
4713 default:
4714 break;
4715 }
4716 }
4717
gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)4718 static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4719 struct amdgpu_irq_src *src,
4720 unsigned type,
4721 enum amdgpu_interrupt_state state)
4722 {
4723 switch (type) {
4724 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4725 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4726 break;
4727 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4728 gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4729 break;
4730 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4731 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4732 break;
4733 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4734 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4735 break;
4736 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4737 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4738 break;
4739 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4740 gfx_v12_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4741 break;
4742 default:
4743 break;
4744 }
4745 return 0;
4746 }
4747
gfx_v12_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4748 static int gfx_v12_0_eop_irq(struct amdgpu_device *adev,
4749 struct amdgpu_irq_src *source,
4750 struct amdgpu_iv_entry *entry)
4751 {
4752 int i;
4753 u8 me_id, pipe_id, queue_id;
4754 struct amdgpu_ring *ring;
4755 uint32_t mes_queue_id = entry->src_data[0];
4756
4757 DRM_DEBUG("IH: CP EOP\n");
4758
4759 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
4760 struct amdgpu_mes_queue *queue;
4761
4762 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
4763
4764 spin_lock(&adev->mes.queue_id_lock);
4765 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
4766 if (queue) {
4767 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
4768 amdgpu_fence_process(queue->ring);
4769 }
4770 spin_unlock(&adev->mes.queue_id_lock);
4771 } else {
4772 me_id = (entry->ring_id & 0x0c) >> 2;
4773 pipe_id = (entry->ring_id & 0x03) >> 0;
4774 queue_id = (entry->ring_id & 0x70) >> 4;
4775
4776 switch (me_id) {
4777 case 0:
4778 if (pipe_id == 0)
4779 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4780 else
4781 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4782 break;
4783 case 1:
4784 case 2:
4785 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4786 ring = &adev->gfx.compute_ring[i];
4787 /* Per-queue interrupt is supported for MEC starting from VI.
4788 * The interrupt can only be enabled/disabled per pipe instead
4789 * of per queue.
4790 */
4791 if ((ring->me == me_id) &&
4792 (ring->pipe == pipe_id) &&
4793 (ring->queue == queue_id))
4794 amdgpu_fence_process(ring);
4795 }
4796 break;
4797 }
4798 }
4799
4800 return 0;
4801 }
4802
gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4803 static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4804 struct amdgpu_irq_src *source,
4805 unsigned int type,
4806 enum amdgpu_interrupt_state state)
4807 {
4808 u32 cp_int_cntl_reg, cp_int_cntl;
4809 int i, j;
4810
4811 switch (state) {
4812 case AMDGPU_IRQ_STATE_DISABLE:
4813 case AMDGPU_IRQ_STATE_ENABLE:
4814 for (i = 0; i < adev->gfx.me.num_me; i++) {
4815 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4816 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4817
4818 if (cp_int_cntl_reg) {
4819 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4820 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4821 PRIV_REG_INT_ENABLE,
4822 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4823 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4824 }
4825 }
4826 }
4827 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4828 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4829 /* MECs start at 1 */
4830 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4831
4832 if (cp_int_cntl_reg) {
4833 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4834 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4835 PRIV_REG_INT_ENABLE,
4836 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4837 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4838 }
4839 }
4840 }
4841 break;
4842 default:
4843 break;
4844 }
4845
4846 return 0;
4847 }
4848
gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)4849 static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
4850 struct amdgpu_irq_src *source,
4851 unsigned type,
4852 enum amdgpu_interrupt_state state)
4853 {
4854 u32 cp_int_cntl_reg, cp_int_cntl;
4855 int i, j;
4856
4857 switch (state) {
4858 case AMDGPU_IRQ_STATE_DISABLE:
4859 case AMDGPU_IRQ_STATE_ENABLE:
4860 for (i = 0; i < adev->gfx.me.num_me; i++) {
4861 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4862 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4863
4864 if (cp_int_cntl_reg) {
4865 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4866 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4867 OPCODE_ERROR_INT_ENABLE,
4868 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4869 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4870 }
4871 }
4872 }
4873 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
4874 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
4875 /* MECs start at 1 */
4876 cp_int_cntl_reg = gfx_v12_0_get_cpc_int_cntl(adev, i + 1, j);
4877
4878 if (cp_int_cntl_reg) {
4879 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4880 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4881 OPCODE_ERROR_INT_ENABLE,
4882 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4883 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4884 }
4885 }
4886 }
4887 break;
4888 default:
4889 break;
4890 }
4891 return 0;
4892 }
4893
gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)4894 static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4895 struct amdgpu_irq_src *source,
4896 unsigned int type,
4897 enum amdgpu_interrupt_state state)
4898 {
4899 u32 cp_int_cntl_reg, cp_int_cntl;
4900 int i, j;
4901
4902 switch (state) {
4903 case AMDGPU_IRQ_STATE_DISABLE:
4904 case AMDGPU_IRQ_STATE_ENABLE:
4905 for (i = 0; i < adev->gfx.me.num_me; i++) {
4906 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
4907 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j);
4908
4909 if (cp_int_cntl_reg) {
4910 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4911 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4912 PRIV_INSTR_INT_ENABLE,
4913 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4914 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4915 }
4916 }
4917 }
4918 break;
4919 default:
4920 break;
4921 }
4922
4923 return 0;
4924 }
4925
gfx_v12_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)4926 static void gfx_v12_0_handle_priv_fault(struct amdgpu_device *adev,
4927 struct amdgpu_iv_entry *entry)
4928 {
4929 u8 me_id, pipe_id, queue_id;
4930 struct amdgpu_ring *ring;
4931 int i;
4932
4933 me_id = (entry->ring_id & 0x0c) >> 2;
4934 pipe_id = (entry->ring_id & 0x03) >> 0;
4935 queue_id = (entry->ring_id & 0x70) >> 4;
4936
4937 switch (me_id) {
4938 case 0:
4939 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4940 ring = &adev->gfx.gfx_ring[i];
4941 if (ring->me == me_id && ring->pipe == pipe_id &&
4942 ring->queue == queue_id)
4943 drm_sched_fault(&ring->sched);
4944 }
4945 break;
4946 case 1:
4947 case 2:
4948 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4949 ring = &adev->gfx.compute_ring[i];
4950 if (ring->me == me_id && ring->pipe == pipe_id &&
4951 ring->queue == queue_id)
4952 drm_sched_fault(&ring->sched);
4953 }
4954 break;
4955 default:
4956 BUG();
4957 break;
4958 }
4959 }
4960
gfx_v12_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4961 static int gfx_v12_0_priv_reg_irq(struct amdgpu_device *adev,
4962 struct amdgpu_irq_src *source,
4963 struct amdgpu_iv_entry *entry)
4964 {
4965 DRM_ERROR("Illegal register access in command stream\n");
4966 gfx_v12_0_handle_priv_fault(adev, entry);
4967 return 0;
4968 }
4969
gfx_v12_0_bad_op_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4970 static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev,
4971 struct amdgpu_irq_src *source,
4972 struct amdgpu_iv_entry *entry)
4973 {
4974 DRM_ERROR("Illegal opcode in command stream \n");
4975 gfx_v12_0_handle_priv_fault(adev, entry);
4976 return 0;
4977 }
4978
gfx_v12_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)4979 static int gfx_v12_0_priv_inst_irq(struct amdgpu_device *adev,
4980 struct amdgpu_irq_src *source,
4981 struct amdgpu_iv_entry *entry)
4982 {
4983 DRM_ERROR("Illegal instruction in command stream\n");
4984 gfx_v12_0_handle_priv_fault(adev, entry);
4985 return 0;
4986 }
4987
gfx_v12_0_emit_mem_sync(struct amdgpu_ring * ring)4988 static void gfx_v12_0_emit_mem_sync(struct amdgpu_ring *ring)
4989 {
4990 const unsigned int gcr_cntl =
4991 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
4992 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
4993 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
4994 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
4995 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
4996 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
4997 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
4998 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
4999
5000 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
5001 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
5002 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
5003 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
5004 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
5005 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
5006 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
5007 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
5008 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
5009 }
5010
gfx_v12_ring_insert_nop(struct amdgpu_ring * ring,uint32_t num_nop)5011 static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
5012 {
5013 /* Header itself is a NOP packet */
5014 if (num_nop == 1) {
5015 amdgpu_ring_write(ring, ring->funcs->nop);
5016 return;
5017 }
5018
5019 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
5020 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
5021
5022 /* Header is at index 0, followed by num_nops - 1 NOP packet's */
5023 amdgpu_ring_insert_nop(ring, num_nop - 1);
5024 }
5025
gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring * ring)5026 static void gfx_v12_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
5027 {
5028 /* Emit the cleaner shader */
5029 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
5030 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
5031 }
5032
gfx_v12_ip_print(struct amdgpu_ip_block * ip_block,struct drm_printer * p)5033 static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
5034 {
5035 struct amdgpu_device *adev = ip_block->adev;
5036 uint32_t i, j, k, reg, index = 0;
5037 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5038
5039 if (!adev->gfx.ip_dump_core)
5040 return;
5041
5042 for (i = 0; i < reg_count; i++)
5043 drm_printf(p, "%-50s \t 0x%08x\n",
5044 gc_reg_list_12_0[i].reg_name,
5045 adev->gfx.ip_dump_core[i]);
5046
5047 /* print compute queue registers for all instances */
5048 if (!adev->gfx.ip_dump_compute_queues)
5049 return;
5050
5051 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5052 drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
5053 adev->gfx.mec.num_mec,
5054 adev->gfx.mec.num_pipe_per_mec,
5055 adev->gfx.mec.num_queue_per_pipe);
5056
5057 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5058 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5059 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5060 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
5061 for (reg = 0; reg < reg_count; reg++) {
5062 drm_printf(p, "%-50s \t 0x%08x\n",
5063 gc_cp_reg_list_12[reg].reg_name,
5064 adev->gfx.ip_dump_compute_queues[index + reg]);
5065 }
5066 index += reg_count;
5067 }
5068 }
5069 }
5070
5071 /* print gfx queue registers for all instances */
5072 if (!adev->gfx.ip_dump_gfx_queues)
5073 return;
5074
5075 index = 0;
5076 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5077 drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
5078 adev->gfx.me.num_me,
5079 adev->gfx.me.num_pipe_per_me,
5080 adev->gfx.me.num_queue_per_pipe);
5081
5082 for (i = 0; i < adev->gfx.me.num_me; i++) {
5083 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5084 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5085 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
5086 for (reg = 0; reg < reg_count; reg++) {
5087 drm_printf(p, "%-50s \t 0x%08x\n",
5088 gc_gfx_queue_reg_list_12[reg].reg_name,
5089 adev->gfx.ip_dump_gfx_queues[index + reg]);
5090 }
5091 index += reg_count;
5092 }
5093 }
5094 }
5095 }
5096
gfx_v12_ip_dump(struct amdgpu_ip_block * ip_block)5097 static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block)
5098 {
5099 struct amdgpu_device *adev = ip_block->adev;
5100 uint32_t i, j, k, reg, index = 0;
5101 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0);
5102
5103 if (!adev->gfx.ip_dump_core)
5104 return;
5105
5106 amdgpu_gfx_off_ctrl(adev, false);
5107 for (i = 0; i < reg_count; i++)
5108 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_12_0[i]));
5109 amdgpu_gfx_off_ctrl(adev, true);
5110
5111 /* dump compute queue registers for all instances */
5112 if (!adev->gfx.ip_dump_compute_queues)
5113 return;
5114
5115 reg_count = ARRAY_SIZE(gc_cp_reg_list_12);
5116 amdgpu_gfx_off_ctrl(adev, false);
5117 mutex_lock(&adev->srbm_mutex);
5118 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
5119 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
5120 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
5121 /* ME0 is for GFX so start from 1 for CP */
5122 soc24_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
5123 for (reg = 0; reg < reg_count; reg++) {
5124 adev->gfx.ip_dump_compute_queues[index + reg] =
5125 RREG32(SOC15_REG_ENTRY_OFFSET(
5126 gc_cp_reg_list_12[reg]));
5127 }
5128 index += reg_count;
5129 }
5130 }
5131 }
5132 soc24_grbm_select(adev, 0, 0, 0, 0);
5133 mutex_unlock(&adev->srbm_mutex);
5134 amdgpu_gfx_off_ctrl(adev, true);
5135
5136 /* dump gfx queue registers for all instances */
5137 if (!adev->gfx.ip_dump_gfx_queues)
5138 return;
5139
5140 index = 0;
5141 reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_12);
5142 amdgpu_gfx_off_ctrl(adev, false);
5143 mutex_lock(&adev->srbm_mutex);
5144 for (i = 0; i < adev->gfx.me.num_me; i++) {
5145 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5146 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
5147 soc24_grbm_select(adev, i, j, k, 0);
5148
5149 for (reg = 0; reg < reg_count; reg++) {
5150 adev->gfx.ip_dump_gfx_queues[index + reg] =
5151 RREG32(SOC15_REG_ENTRY_OFFSET(
5152 gc_gfx_queue_reg_list_12[reg]));
5153 }
5154 index += reg_count;
5155 }
5156 }
5157 }
5158 soc24_grbm_select(adev, 0, 0, 0, 0);
5159 mutex_unlock(&adev->srbm_mutex);
5160 amdgpu_gfx_off_ctrl(adev, true);
5161 }
5162
gfx_v12_0_reset_kgq(struct amdgpu_ring * ring,unsigned int vmid)5163 static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
5164 {
5165 struct amdgpu_device *adev = ring->adev;
5166 int r;
5167
5168 if (amdgpu_sriov_vf(adev))
5169 return -EINVAL;
5170
5171 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false);
5172 if (r) {
5173 dev_err(adev->dev, "reset via MES failed %d\n", r);
5174 return r;
5175 }
5176
5177 r = gfx_v12_0_kgq_init_queue(ring, true);
5178 if (r) {
5179 dev_err(adev->dev, "failed to init kgq\n");
5180 return r;
5181 }
5182
5183 r = amdgpu_mes_map_legacy_queue(adev, ring);
5184 if (r) {
5185 dev_err(adev->dev, "failed to remap kgq\n");
5186 return r;
5187 }
5188
5189 return amdgpu_ring_test_ring(ring);
5190 }
5191
gfx_v12_0_reset_kcq(struct amdgpu_ring * ring,unsigned int vmid)5192 static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
5193 {
5194 struct amdgpu_device *adev = ring->adev;
5195 int r;
5196
5197 if (amdgpu_sriov_vf(adev))
5198 return -EINVAL;
5199
5200 r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true);
5201 if (r) {
5202 dev_err(adev->dev, "reset via MMIO failed %d\n", r);
5203 return r;
5204 }
5205
5206 r = gfx_v12_0_kcq_init_queue(ring, true);
5207 if (r) {
5208 dev_err(adev->dev, "failed to init kcq\n");
5209 return r;
5210 }
5211 r = amdgpu_mes_map_legacy_queue(adev, ring);
5212 if (r) {
5213 dev_err(adev->dev, "failed to remap kcq\n");
5214 return r;
5215 }
5216
5217 return amdgpu_ring_test_ring(ring);
5218 }
5219
gfx_v12_0_ring_begin_use(struct amdgpu_ring * ring)5220 static void gfx_v12_0_ring_begin_use(struct amdgpu_ring *ring)
5221 {
5222 amdgpu_gfx_profile_ring_begin_use(ring);
5223
5224 amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
5225 }
5226
gfx_v12_0_ring_end_use(struct amdgpu_ring * ring)5227 static void gfx_v12_0_ring_end_use(struct amdgpu_ring *ring)
5228 {
5229 amdgpu_gfx_profile_ring_end_use(ring);
5230
5231 amdgpu_gfx_enforce_isolation_ring_end_use(ring);
5232 }
5233
5234 static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
5235 .name = "gfx_v12_0",
5236 .early_init = gfx_v12_0_early_init,
5237 .late_init = gfx_v12_0_late_init,
5238 .sw_init = gfx_v12_0_sw_init,
5239 .sw_fini = gfx_v12_0_sw_fini,
5240 .hw_init = gfx_v12_0_hw_init,
5241 .hw_fini = gfx_v12_0_hw_fini,
5242 .suspend = gfx_v12_0_suspend,
5243 .resume = gfx_v12_0_resume,
5244 .is_idle = gfx_v12_0_is_idle,
5245 .wait_for_idle = gfx_v12_0_wait_for_idle,
5246 .set_clockgating_state = gfx_v12_0_set_clockgating_state,
5247 .set_powergating_state = gfx_v12_0_set_powergating_state,
5248 .get_clockgating_state = gfx_v12_0_get_clockgating_state,
5249 .dump_ip_state = gfx_v12_ip_dump,
5250 .print_ip_state = gfx_v12_ip_print,
5251 };
5252
5253 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = {
5254 .type = AMDGPU_RING_TYPE_GFX,
5255 .align_mask = 0xff,
5256 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5257 .support_64bit_ptrs = true,
5258 .secure_submission_supported = true,
5259 .get_rptr = gfx_v12_0_ring_get_rptr_gfx,
5260 .get_wptr = gfx_v12_0_ring_get_wptr_gfx,
5261 .set_wptr = gfx_v12_0_ring_set_wptr_gfx,
5262 .emit_frame_size = /* totally 242 maximum if 16 IBs */
5263 5 + /* COND_EXEC */
5264 7 + /* PIPELINE_SYNC */
5265 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5266 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5267 2 + /* VM_FLUSH */
5268 8 + /* FENCE for VM_FLUSH */
5269 5 + /* COND_EXEC */
5270 7 + /* HDP_flush */
5271 4 + /* VGT_flush */
5272 31 + /* DE_META */
5273 3 + /* CNTX_CTRL */
5274 5 + /* HDP_INVL */
5275 8 + 8 + /* FENCE x2 */
5276 8 + /* gfx_v12_0_emit_mem_sync */
5277 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5278 .emit_ib_size = 4, /* gfx_v12_0_ring_emit_ib_gfx */
5279 .emit_ib = gfx_v12_0_ring_emit_ib_gfx,
5280 .emit_fence = gfx_v12_0_ring_emit_fence,
5281 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5282 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5283 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5284 .test_ring = gfx_v12_0_ring_test_ring,
5285 .test_ib = gfx_v12_0_ring_test_ib,
5286 .insert_nop = gfx_v12_ring_insert_nop,
5287 .pad_ib = amdgpu_ring_generic_pad_ib,
5288 .emit_cntxcntl = gfx_v12_0_ring_emit_cntxcntl,
5289 .init_cond_exec = gfx_v12_0_ring_emit_init_cond_exec,
5290 .preempt_ib = gfx_v12_0_ring_preempt_ib,
5291 .emit_frame_cntl = gfx_v12_0_ring_emit_frame_cntl,
5292 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5293 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5294 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5295 .soft_recovery = gfx_v12_0_ring_soft_recovery,
5296 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5297 .reset = gfx_v12_0_reset_kgq,
5298 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5299 .begin_use = gfx_v12_0_ring_begin_use,
5300 .end_use = gfx_v12_0_ring_end_use,
5301 };
5302
5303 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
5304 .type = AMDGPU_RING_TYPE_COMPUTE,
5305 .align_mask = 0xff,
5306 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5307 .support_64bit_ptrs = true,
5308 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5309 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5310 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5311 .emit_frame_size =
5312 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5313 5 + /* hdp invalidate */
5314 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5315 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5316 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5317 2 + /* gfx_v12_0_ring_emit_vm_flush */
5318 8 + 8 + 8 + /* gfx_v12_0_ring_emit_fence x3 for user fence, vm fence */
5319 8 + /* gfx_v12_0_emit_mem_sync */
5320 2, /* gfx_v12_0_ring_emit_cleaner_shader */
5321 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5322 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5323 .emit_fence = gfx_v12_0_ring_emit_fence,
5324 .emit_pipeline_sync = gfx_v12_0_ring_emit_pipeline_sync,
5325 .emit_vm_flush = gfx_v12_0_ring_emit_vm_flush,
5326 .emit_hdp_flush = gfx_v12_0_ring_emit_hdp_flush,
5327 .test_ring = gfx_v12_0_ring_test_ring,
5328 .test_ib = gfx_v12_0_ring_test_ib,
5329 .insert_nop = gfx_v12_ring_insert_nop,
5330 .pad_ib = amdgpu_ring_generic_pad_ib,
5331 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5332 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5333 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5334 .soft_recovery = gfx_v12_0_ring_soft_recovery,
5335 .emit_mem_sync = gfx_v12_0_emit_mem_sync,
5336 .reset = gfx_v12_0_reset_kcq,
5337 .emit_cleaner_shader = gfx_v12_0_ring_emit_cleaner_shader,
5338 .begin_use = gfx_v12_0_ring_begin_use,
5339 .end_use = gfx_v12_0_ring_end_use,
5340 };
5341
5342 static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
5343 .type = AMDGPU_RING_TYPE_KIQ,
5344 .align_mask = 0xff,
5345 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5346 .support_64bit_ptrs = true,
5347 .get_rptr = gfx_v12_0_ring_get_rptr_compute,
5348 .get_wptr = gfx_v12_0_ring_get_wptr_compute,
5349 .set_wptr = gfx_v12_0_ring_set_wptr_compute,
5350 .emit_frame_size =
5351 7 + /* gfx_v12_0_ring_emit_hdp_flush */
5352 5 + /*hdp invalidate */
5353 7 + /* gfx_v12_0_ring_emit_pipeline_sync */
5354 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5355 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5356 2 + /* gfx_v12_0_ring_emit_vm_flush */
5357 8 + 8 + 8, /* gfx_v12_0_ring_emit_fence_kiq x3 for user fence, vm fence */
5358 .emit_ib_size = 7, /* gfx_v12_0_ring_emit_ib_compute */
5359 .emit_ib = gfx_v12_0_ring_emit_ib_compute,
5360 .emit_fence = gfx_v12_0_ring_emit_fence_kiq,
5361 .test_ring = gfx_v12_0_ring_test_ring,
5362 .test_ib = gfx_v12_0_ring_test_ib,
5363 .insert_nop = amdgpu_ring_insert_nop,
5364 .pad_ib = amdgpu_ring_generic_pad_ib,
5365 .emit_rreg = gfx_v12_0_ring_emit_rreg,
5366 .emit_wreg = gfx_v12_0_ring_emit_wreg,
5367 .emit_reg_wait = gfx_v12_0_ring_emit_reg_wait,
5368 .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait,
5369 };
5370
gfx_v12_0_set_ring_funcs(struct amdgpu_device * adev)5371 static void gfx_v12_0_set_ring_funcs(struct amdgpu_device *adev)
5372 {
5373 int i;
5374
5375 adev->gfx.kiq[0].ring.funcs = &gfx_v12_0_ring_funcs_kiq;
5376
5377 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5378 adev->gfx.gfx_ring[i].funcs = &gfx_v12_0_ring_funcs_gfx;
5379
5380 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5381 adev->gfx.compute_ring[i].funcs = &gfx_v12_0_ring_funcs_compute;
5382 }
5383
5384 static const struct amdgpu_irq_src_funcs gfx_v12_0_eop_irq_funcs = {
5385 .set = gfx_v12_0_set_eop_interrupt_state,
5386 .process = gfx_v12_0_eop_irq,
5387 };
5388
5389 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_reg_irq_funcs = {
5390 .set = gfx_v12_0_set_priv_reg_fault_state,
5391 .process = gfx_v12_0_priv_reg_irq,
5392 };
5393
5394 static const struct amdgpu_irq_src_funcs gfx_v12_0_bad_op_irq_funcs = {
5395 .set = gfx_v12_0_set_bad_op_fault_state,
5396 .process = gfx_v12_0_bad_op_irq,
5397 };
5398
5399 static const struct amdgpu_irq_src_funcs gfx_v12_0_priv_inst_irq_funcs = {
5400 .set = gfx_v12_0_set_priv_inst_fault_state,
5401 .process = gfx_v12_0_priv_inst_irq,
5402 };
5403
gfx_v12_0_set_irq_funcs(struct amdgpu_device * adev)5404 static void gfx_v12_0_set_irq_funcs(struct amdgpu_device *adev)
5405 {
5406 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5407 adev->gfx.eop_irq.funcs = &gfx_v12_0_eop_irq_funcs;
5408
5409 adev->gfx.priv_reg_irq.num_types = 1;
5410 adev->gfx.priv_reg_irq.funcs = &gfx_v12_0_priv_reg_irq_funcs;
5411
5412 adev->gfx.bad_op_irq.num_types = 1;
5413 adev->gfx.bad_op_irq.funcs = &gfx_v12_0_bad_op_irq_funcs;
5414
5415 adev->gfx.priv_inst_irq.num_types = 1;
5416 adev->gfx.priv_inst_irq.funcs = &gfx_v12_0_priv_inst_irq_funcs;
5417 }
5418
gfx_v12_0_set_imu_funcs(struct amdgpu_device * adev)5419 static void gfx_v12_0_set_imu_funcs(struct amdgpu_device *adev)
5420 {
5421 if (adev->flags & AMD_IS_APU)
5422 adev->gfx.imu.mode = MISSION_MODE;
5423 else
5424 adev->gfx.imu.mode = DEBUG_MODE;
5425
5426 adev->gfx.imu.funcs = &gfx_v12_0_imu_funcs;
5427 }
5428
gfx_v12_0_set_rlc_funcs(struct amdgpu_device * adev)5429 static void gfx_v12_0_set_rlc_funcs(struct amdgpu_device *adev)
5430 {
5431 adev->gfx.rlc.funcs = &gfx_v12_0_rlc_funcs;
5432 }
5433
gfx_v12_0_set_mqd_funcs(struct amdgpu_device * adev)5434 static void gfx_v12_0_set_mqd_funcs(struct amdgpu_device *adev)
5435 {
5436 /* set gfx eng mqd */
5437 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
5438 sizeof(struct v12_gfx_mqd);
5439 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
5440 gfx_v12_0_gfx_mqd_init;
5441 /* set compute eng mqd */
5442 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
5443 sizeof(struct v12_compute_mqd);
5444 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
5445 gfx_v12_0_compute_mqd_init;
5446 }
5447
gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)5448 static void gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5449 u32 bitmap)
5450 {
5451 u32 data;
5452
5453 if (!bitmap)
5454 return;
5455
5456 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5457 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5458
5459 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
5460 }
5461
gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)5462 static u32 gfx_v12_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5463 {
5464 u32 data, wgp_bitmask;
5465 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
5466 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
5467
5468 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5469 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5470
5471 wgp_bitmask =
5472 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5473
5474 return (~data) & wgp_bitmask;
5475 }
5476
gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)5477 static u32 gfx_v12_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5478 {
5479 u32 wgp_idx, wgp_active_bitmap;
5480 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5481
5482 wgp_active_bitmap = gfx_v12_0_get_wgp_active_bitmap_per_sh(adev);
5483 cu_active_bitmap = 0;
5484
5485 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5486 /* if there is one WGP enabled, it means 2 CUs will be enabled */
5487 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5488 if (wgp_active_bitmap & (1 << wgp_idx))
5489 cu_active_bitmap |= cu_bitmap_per_wgp;
5490 }
5491
5492 return cu_active_bitmap;
5493 }
5494
gfx_v12_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)5495 static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev,
5496 struct amdgpu_cu_info *cu_info)
5497 {
5498 int i, j, k, counter, active_cu_number = 0;
5499 u32 mask, bitmap;
5500 unsigned disable_masks[8 * 2];
5501
5502 if (!adev || !cu_info)
5503 return -EINVAL;
5504
5505 amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
5506
5507 mutex_lock(&adev->grbm_idx_mutex);
5508 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5509 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5510 bitmap = i * adev->gfx.config.max_sh_per_se + j;
5511 if (!((gfx_v12_0_get_sa_active_bitmap(adev) >> bitmap) & 1))
5512 continue;
5513 mask = 1;
5514 counter = 0;
5515 gfx_v12_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5516 if (i < 8 && j < 2)
5517 gfx_v12_0_set_user_wgp_inactive_bitmap_per_sh(
5518 adev, disable_masks[i * 2 + j]);
5519 bitmap = gfx_v12_0_get_cu_active_bitmap_per_sh(adev);
5520
5521 /**
5522 * GFX12 could support more than 4 SEs, while the bitmap
5523 * in cu_info struct is 4x4 and ioctl interface struct
5524 * drm_amdgpu_info_device should keep stable.
5525 * So we use last two columns of bitmap to store cu mask for
5526 * SEs 4 to 7, the layout of the bitmap is as below:
5527 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
5528 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
5529 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
5530 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
5531 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
5532 * SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
5533 * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
5534 * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
5535 */
5536 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
5537
5538 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5539 if (bitmap & mask)
5540 counter++;
5541
5542 mask <<= 1;
5543 }
5544 active_cu_number += counter;
5545 }
5546 }
5547 gfx_v12_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5548 mutex_unlock(&adev->grbm_idx_mutex);
5549
5550 cu_info->number = active_cu_number;
5551 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5552
5553 return 0;
5554 }
5555
5556 const struct amdgpu_ip_block_version gfx_v12_0_ip_block = {
5557 .type = AMD_IP_BLOCK_TYPE_GFX,
5558 .major = 12,
5559 .minor = 0,
5560 .rev = 0,
5561 .funcs = &gfx_v12_0_ip_funcs,
5562 };
5563