1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "amdgpu_ras_eeprom.h"
25 #include "amdgpu.h"
26 #include "amdgpu_ras.h"
27 #include <linux/bits.h>
28 #include "atom.h"
29 #include "amdgpu_eeprom.h"
30 #include "amdgpu_atomfirmware.h"
31 #include <linux/debugfs.h>
32 #include <linux/uaccess.h>
33
34 #include "amdgpu_reset.h"
35
36 /* These are memory addresses as would be seen by one or more EEPROM
37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
38 * set of EEPROM devices. They form a continuous memory space.
39 *
40 * The I2C device address includes the device type identifier, 1010b,
41 * which is a reserved value and indicates that this is an I2C EEPROM
42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory
43 * address, namely bits 18, 17, and 16. This makes up the 7 bit
44 * address sent on the I2C bus with bit 0 being the direction bit,
45 * which is not represented here, and sent by the hardware directly.
46 *
47 * For instance,
48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0.
49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h.
50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h.
51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
52 * address memory in a device or a device on the I2C bus, depending on
53 * the status of pins 1-3. See top of amdgpu_eeprom.c.
54 *
55 * The RAS table lives either at address 0 or address 40000h of EEPROM.
56 */
57 #define EEPROM_I2C_MADDR_0 0x0
58 #define EEPROM_I2C_MADDR_4 0x40000
59
60 /*
61 * The 2 macros below represent the actual size in bytes that
62 * those entities occupy in the EEPROM memory.
63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
64 * uses uint64 to store 6b fields such as retired_page.
65 */
66 #define RAS_TABLE_HEADER_SIZE 20
67 #define RAS_TABLE_RECORD_SIZE 24
68
69 /* Table hdr is 'AMDR' */
70 #define RAS_TABLE_HDR_VAL 0x414d4452
71
72 /* Bad GPU tag ‘BADG’ */
73 #define RAS_TABLE_HDR_BAD 0x42414447
74
75 /*
76 * EEPROM Table structure v1
77 * ---------------------------------
78 * | |
79 * | EEPROM TABLE HEADER |
80 * | ( size 20 Bytes ) |
81 * | |
82 * ---------------------------------
83 * | |
84 * | BAD PAGE RECORD AREA |
85 * | |
86 * ---------------------------------
87 */
88
89 /* Assume 2-Mbit size EEPROM and take up the whole space. */
90 #define RAS_TBL_SIZE_BYTES (256 * 1024)
91 #define RAS_TABLE_START 0
92 #define RAS_HDR_START RAS_TABLE_START
93 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE)
94 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \
95 / RAS_TABLE_RECORD_SIZE)
96
97 /*
98 * EEPROM Table structrue v2.1
99 * ---------------------------------
100 * | |
101 * | EEPROM TABLE HEADER |
102 * | ( size 20 Bytes ) |
103 * | |
104 * ---------------------------------
105 * | |
106 * | EEPROM TABLE RAS INFO |
107 * | (available info size 4 Bytes) |
108 * | ( reserved size 252 Bytes ) |
109 * | |
110 * ---------------------------------
111 * | |
112 * | BAD PAGE RECORD AREA |
113 * | |
114 * ---------------------------------
115 */
116
117 /* EEPROM Table V2_1 */
118 #define RAS_TABLE_V2_1_INFO_SIZE 256
119 #define RAS_TABLE_V2_1_INFO_START RAS_TABLE_HEADER_SIZE
120 #define RAS_RECORD_START_V2_1 (RAS_HDR_START + RAS_TABLE_HEADER_SIZE + \
121 RAS_TABLE_V2_1_INFO_SIZE)
122 #define RAS_MAX_RECORD_COUNT_V2_1 ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE - \
123 RAS_TABLE_V2_1_INFO_SIZE) \
124 / RAS_TABLE_RECORD_SIZE)
125
126 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM
127 * offset off of RAS_TABLE_START. That is, this is something you can
128 * add to control->i2c_address, and then tell I2C layer to read
129 * from/write to there. _N is the so called absolute index,
130 * because it starts right after the table header.
131 */
132 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \
133 (_N) * RAS_TABLE_RECORD_SIZE)
134
135 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \
136 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE)
137
138 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off
139 * of "fri", return the absolute record index off of the end of
140 * the table header.
141 */
142 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \
143 (_C)->ras_max_record_count)
144
145 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
146 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE)
147
148 #define RAS_NUM_RECS_V2_1(_tbl_hdr) (((_tbl_hdr)->tbl_size - \
149 RAS_TABLE_HEADER_SIZE - \
150 RAS_TABLE_V2_1_INFO_SIZE) / RAS_TABLE_RECORD_SIZE)
151
152 #define to_amdgpu_device(x) ((container_of(x, struct amdgpu_ras, eeprom_control))->adev)
153
__is_ras_eeprom_supported(struct amdgpu_device * adev)154 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
155 {
156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
157 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
158 case IP_VERSION(11, 0, 7): /* Sienna cichlid */
159 case IP_VERSION(13, 0, 0):
160 case IP_VERSION(13, 0, 2): /* Aldebaran */
161 case IP_VERSION(13, 0, 10):
162 return true;
163 case IP_VERSION(13, 0, 6):
164 case IP_VERSION(13, 0, 12):
165 case IP_VERSION(13, 0, 14):
166 return (adev->gmc.is_app_apu) ? false : true;
167 default:
168 return false;
169 }
170 }
171
__get_eeprom_i2c_addr(struct amdgpu_device * adev,struct amdgpu_ras_eeprom_control * control)172 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
173 struct amdgpu_ras_eeprom_control *control)
174 {
175 struct atom_context *atom_ctx = adev->mode_info.atom_context;
176 u8 i2c_addr;
177
178 if (!control)
179 return false;
180
181 if (adev->bios && amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) {
182 /* The address given by VBIOS is an 8-bit, wire-format
183 * address, i.e. the most significant byte.
184 *
185 * Normalize it to a 19-bit EEPROM address. Remove the
186 * device type identifier and make it a 7-bit address;
187 * then make it a 19-bit EEPROM address. See top of
188 * amdgpu_eeprom.c.
189 */
190 i2c_addr = (i2c_addr & 0x0F) >> 1;
191 control->i2c_address = ((u32) i2c_addr) << 16;
192
193 return true;
194 }
195
196 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
197 case IP_VERSION(11, 0, 2):
198 /* VEGA20 and ARCTURUS */
199 if (adev->asic_type == CHIP_VEGA20)
200 control->i2c_address = EEPROM_I2C_MADDR_0;
201 else if (strnstr(atom_ctx->vbios_pn,
202 "D342",
203 sizeof(atom_ctx->vbios_pn)))
204 control->i2c_address = EEPROM_I2C_MADDR_0;
205 else
206 control->i2c_address = EEPROM_I2C_MADDR_4;
207 return true;
208 case IP_VERSION(11, 0, 7):
209 control->i2c_address = EEPROM_I2C_MADDR_0;
210 return true;
211 case IP_VERSION(13, 0, 2):
212 if (strnstr(atom_ctx->vbios_pn, "D673",
213 sizeof(atom_ctx->vbios_pn)))
214 control->i2c_address = EEPROM_I2C_MADDR_4;
215 else
216 control->i2c_address = EEPROM_I2C_MADDR_0;
217 return true;
218 case IP_VERSION(13, 0, 0):
219 if (strnstr(atom_ctx->vbios_pn, "D707",
220 sizeof(atom_ctx->vbios_pn)))
221 control->i2c_address = EEPROM_I2C_MADDR_0;
222 else
223 control->i2c_address = EEPROM_I2C_MADDR_4;
224 return true;
225 case IP_VERSION(13, 0, 6):
226 case IP_VERSION(13, 0, 10):
227 case IP_VERSION(13, 0, 12):
228 case IP_VERSION(13, 0, 14):
229 control->i2c_address = EEPROM_I2C_MADDR_4;
230 return true;
231 default:
232 return false;
233 }
234 }
235
236 static void
__encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)237 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
238 unsigned char *buf)
239 {
240 u32 *pp = (uint32_t *)buf;
241
242 pp[0] = cpu_to_le32(hdr->header);
243 pp[1] = cpu_to_le32(hdr->version);
244 pp[2] = cpu_to_le32(hdr->first_rec_offset);
245 pp[3] = cpu_to_le32(hdr->tbl_size);
246 pp[4] = cpu_to_le32(hdr->checksum);
247 }
248
249 static void
__decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header * hdr,unsigned char * buf)250 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
251 unsigned char *buf)
252 {
253 u32 *pp = (uint32_t *)buf;
254
255 hdr->header = le32_to_cpu(pp[0]);
256 hdr->version = le32_to_cpu(pp[1]);
257 hdr->first_rec_offset = le32_to_cpu(pp[2]);
258 hdr->tbl_size = le32_to_cpu(pp[3]);
259 hdr->checksum = le32_to_cpu(pp[4]);
260 }
261
__write_table_header(struct amdgpu_ras_eeprom_control * control)262 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)
263 {
264 u8 buf[RAS_TABLE_HEADER_SIZE];
265 struct amdgpu_device *adev = to_amdgpu_device(control);
266 int res;
267
268 memset(buf, 0, sizeof(buf));
269 __encode_table_header_to_buf(&control->tbl_hdr, buf);
270
271 /* i2c may be unstable in gpu reset */
272 down_read(&adev->reset_domain->sem);
273 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
274 control->i2c_address +
275 control->ras_header_offset,
276 buf, RAS_TABLE_HEADER_SIZE);
277 up_read(&adev->reset_domain->sem);
278
279 if (res < 0) {
280 DRM_ERROR("Failed to write EEPROM table header:%d", res);
281 } else if (res < RAS_TABLE_HEADER_SIZE) {
282 DRM_ERROR("Short write:%d out of %d\n",
283 res, RAS_TABLE_HEADER_SIZE);
284 res = -EIO;
285 } else {
286 res = 0;
287 }
288
289 return res;
290 }
291
292 static void
__encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info * rai,unsigned char * buf)293 __encode_table_ras_info_to_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
294 unsigned char *buf)
295 {
296 u32 *pp = (uint32_t *)buf;
297 u32 tmp;
298
299 tmp = ((uint32_t)(rai->rma_status) & 0xFF) |
300 (((uint32_t)(rai->health_percent) << 8) & 0xFF00) |
301 (((uint32_t)(rai->ecc_page_threshold) << 16) & 0xFFFF0000);
302 pp[0] = cpu_to_le32(tmp);
303 }
304
305 static void
__decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info * rai,unsigned char * buf)306 __decode_table_ras_info_from_buf(struct amdgpu_ras_eeprom_table_ras_info *rai,
307 unsigned char *buf)
308 {
309 u32 *pp = (uint32_t *)buf;
310 u32 tmp;
311
312 tmp = le32_to_cpu(pp[0]);
313 rai->rma_status = tmp & 0xFF;
314 rai->health_percent = (tmp >> 8) & 0xFF;
315 rai->ecc_page_threshold = (tmp >> 16) & 0xFFFF;
316 }
317
__write_table_ras_info(struct amdgpu_ras_eeprom_control * control)318 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)
319 {
320 struct amdgpu_device *adev = to_amdgpu_device(control);
321 u8 *buf;
322 int res;
323
324 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
325 if (!buf) {
326 DRM_ERROR("Failed to alloc buf to write table ras info\n");
327 return -ENOMEM;
328 }
329
330 __encode_table_ras_info_to_buf(&control->tbl_rai, buf);
331
332 /* i2c may be unstable in gpu reset */
333 down_read(&adev->reset_domain->sem);
334 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
335 control->i2c_address +
336 control->ras_info_offset,
337 buf, RAS_TABLE_V2_1_INFO_SIZE);
338 up_read(&adev->reset_domain->sem);
339
340 if (res < 0) {
341 DRM_ERROR("Failed to write EEPROM table ras info:%d", res);
342 } else if (res < RAS_TABLE_V2_1_INFO_SIZE) {
343 DRM_ERROR("Short write:%d out of %d\n",
344 res, RAS_TABLE_V2_1_INFO_SIZE);
345 res = -EIO;
346 } else {
347 res = 0;
348 }
349
350 kfree(buf);
351
352 return res;
353 }
354
__calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control * control)355 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)
356 {
357 int ii;
358 u8 *pp, csum;
359 size_t sz;
360
361 /* Header checksum, skip checksum field in the calculation */
362 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);
363 pp = (u8 *) &control->tbl_hdr;
364 csum = 0;
365 for (ii = 0; ii < sz; ii++, pp++)
366 csum += *pp;
367
368 return csum;
369 }
370
__calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control * control)371 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)
372 {
373 int ii;
374 u8 *pp, csum;
375 size_t sz;
376
377 sz = sizeof(control->tbl_rai);
378 pp = (u8 *) &control->tbl_rai;
379 csum = 0;
380 for (ii = 0; ii < sz; ii++, pp++)
381 csum += *pp;
382
383 return csum;
384 }
385
amdgpu_ras_eeprom_correct_header_tag(struct amdgpu_ras_eeprom_control * control,uint32_t header)386 static int amdgpu_ras_eeprom_correct_header_tag(
387 struct amdgpu_ras_eeprom_control *control,
388 uint32_t header)
389 {
390 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
391 u8 *hh;
392 int res;
393 u8 csum;
394
395 csum = -hdr->checksum;
396
397 hh = (void *) &hdr->header;
398 csum -= (hh[0] + hh[1] + hh[2] + hh[3]);
399 hh = (void *) &header;
400 csum += hh[0] + hh[1] + hh[2] + hh[3];
401 csum = -csum;
402 mutex_lock(&control->ras_tbl_mutex);
403 hdr->header = header;
404 hdr->checksum = csum;
405 res = __write_table_header(control);
406 mutex_unlock(&control->ras_tbl_mutex);
407
408 return res;
409 }
410
amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control * control)411 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control)
412 {
413 struct amdgpu_device *adev = to_amdgpu_device(control);
414 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
415
416 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
417 case IP_VERSION(8, 10, 0):
418 hdr->version = RAS_TABLE_VER_V2_1;
419 return;
420 case IP_VERSION(12, 0, 0):
421 hdr->version = RAS_TABLE_VER_V3;
422 return;
423 default:
424 hdr->version = RAS_TABLE_VER_V1;
425 return;
426 }
427 }
428
429 /**
430 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table
431 * @control: pointer to control structure
432 *
433 * Reset the contents of the header of the RAS EEPROM table.
434 * Return 0 on success, -errno on error.
435 */
amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control * control)436 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
437 {
438 struct amdgpu_device *adev = to_amdgpu_device(control);
439 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
440 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
441 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
442 u8 csum;
443 int res;
444
445 mutex_lock(&control->ras_tbl_mutex);
446
447 hdr->header = RAS_TABLE_HDR_VAL;
448 amdgpu_ras_set_eeprom_table_version(control);
449
450 if (hdr->version >= RAS_TABLE_VER_V2_1) {
451 hdr->first_rec_offset = RAS_RECORD_START_V2_1;
452 hdr->tbl_size = RAS_TABLE_HEADER_SIZE +
453 RAS_TABLE_V2_1_INFO_SIZE;
454 rai->rma_status = GPU_HEALTH_USABLE;
455 /**
456 * GPU health represented as a percentage.
457 * 0 means worst health, 100 means fully health.
458 */
459 rai->health_percent = 100;
460 /* ecc_page_threshold = 0 means disable bad page retirement */
461 rai->ecc_page_threshold = con->bad_page_cnt_threshold;
462 } else {
463 hdr->first_rec_offset = RAS_RECORD_START;
464 hdr->tbl_size = RAS_TABLE_HEADER_SIZE;
465 }
466
467 csum = __calc_hdr_byte_sum(control);
468 if (hdr->version >= RAS_TABLE_VER_V2_1)
469 csum += __calc_ras_info_byte_sum(control);
470 csum = -csum;
471 hdr->checksum = csum;
472 res = __write_table_header(control);
473 if (!res && hdr->version > RAS_TABLE_VER_V1)
474 res = __write_table_ras_info(control);
475
476 control->ras_num_recs = 0;
477 control->ras_num_bad_pages = 0;
478 control->ras_fri = 0;
479
480 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages);
481
482 control->bad_channel_bitmap = 0;
483 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);
484 con->update_channel_flag = false;
485
486 amdgpu_ras_debugfs_set_ret_size(control);
487
488 mutex_unlock(&control->ras_tbl_mutex);
489
490 return res;
491 }
492
493 static void
__encode_table_record_to_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)494 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
495 struct eeprom_table_record *record,
496 unsigned char *buf)
497 {
498 __le64 tmp = 0;
499 int i = 0;
500
501 /* Next are all record fields according to EEPROM page spec in LE foramt */
502 buf[i++] = record->err_type;
503
504 buf[i++] = record->bank;
505
506 tmp = cpu_to_le64(record->ts);
507 memcpy(buf + i, &tmp, 8);
508 i += 8;
509
510 tmp = cpu_to_le64((record->offset & 0xffffffffffff));
511 memcpy(buf + i, &tmp, 6);
512 i += 6;
513
514 buf[i++] = record->mem_channel;
515 buf[i++] = record->mcumc_id;
516
517 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
518 memcpy(buf + i, &tmp, 6);
519 }
520
521 static void
__decode_table_record_from_buf(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,unsigned char * buf)522 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
523 struct eeprom_table_record *record,
524 unsigned char *buf)
525 {
526 __le64 tmp = 0;
527 int i = 0;
528
529 /* Next are all record fields according to EEPROM page spec in LE foramt */
530 record->err_type = buf[i++];
531
532 record->bank = buf[i++];
533
534 memcpy(&tmp, buf + i, 8);
535 record->ts = le64_to_cpu(tmp);
536 i += 8;
537
538 memcpy(&tmp, buf + i, 6);
539 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
540 i += 6;
541
542 record->mem_channel = buf[i++];
543 record->mcumc_id = buf[i++];
544
545 memcpy(&tmp, buf + i, 6);
546 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
547 }
548
amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device * adev)549 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev)
550 {
551 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
552
553 if (!__is_ras_eeprom_supported(adev) ||
554 !amdgpu_bad_page_threshold)
555 return false;
556
557 /* skip check eeprom table for VEGA20 Gaming */
558 if (!con)
559 return false;
560 else
561 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC)))
562 return false;
563
564 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) {
565 if (con->eeprom_control.ras_num_bad_pages > con->bad_page_cnt_threshold)
566 dev_warn(adev->dev, "RAS records:%d exceed threshold:%d",
567 con->eeprom_control.ras_num_bad_pages, con->bad_page_cnt_threshold);
568 if ((amdgpu_bad_page_threshold == -1) ||
569 (amdgpu_bad_page_threshold == -2)) {
570 dev_warn(adev->dev,
571 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n");
572 return false;
573 } else {
574 dev_warn(adev->dev,
575 "Please consider adjusting the customized threshold.\n");
576 return true;
577 }
578 }
579
580 return false;
581 }
582
583 /**
584 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM
585 * @control: pointer to control structure
586 * @buf: pointer to buffer containing data to write
587 * @fri: start writing at this index
588 * @num: number of records to write
589 *
590 * The caller must hold the table mutex in @control.
591 * Return 0 on success, -errno otherwise.
592 */
__amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)593 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,
594 u8 *buf, const u32 fri, const u32 num)
595 {
596 struct amdgpu_device *adev = to_amdgpu_device(control);
597 u32 buf_size;
598 int res;
599
600 /* i2c may be unstable in gpu reset */
601 down_read(&adev->reset_domain->sem);
602 buf_size = num * RAS_TABLE_RECORD_SIZE;
603 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
604 control->i2c_address +
605 RAS_INDEX_TO_OFFSET(control, fri),
606 buf, buf_size);
607 up_read(&adev->reset_domain->sem);
608 if (res < 0) {
609 DRM_ERROR("Writing %d EEPROM table records error:%d",
610 num, res);
611 } else if (res < buf_size) {
612 /* Short write, return error.
613 */
614 DRM_ERROR("Wrote %d records out of %d",
615 res / RAS_TABLE_RECORD_SIZE, num);
616 res = -EIO;
617 } else {
618 res = 0;
619 }
620
621 return res;
622 }
623
624 static int
amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)625 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,
626 struct eeprom_table_record *record,
627 const u32 num)
628 {
629 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));
630 struct amdgpu_device *adev = to_amdgpu_device(control);
631 u32 a, b, i;
632 u8 *buf, *pp;
633 int res;
634
635 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
636 if (!buf)
637 return -ENOMEM;
638
639 /* Encode all of them in one go.
640 */
641 pp = buf;
642 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
643 __encode_table_record_to_buf(control, &record[i], pp);
644
645 /* update bad channel bitmap */
646 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
647 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
648 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
649 con->update_channel_flag = true;
650 }
651 }
652
653 /* a, first record index to write into.
654 * b, last record index to write into.
655 * a = first index to read (fri) + number of records in the table,
656 * b = a + @num - 1.
657 * Let N = control->ras_max_num_record_count, then we have,
658 * case 0: 0 <= a <= b < N,
659 * just append @num records starting at a;
660 * case 1: 0 <= a < N <= b,
661 * append (N - a) records starting at a, and
662 * append the remainder, b % N + 1, starting at 0.
663 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases,
664 * case 2a: 0 <= a <= b < N
665 * append num records starting at a; and fix fri if b overwrote it,
666 * and since a <= b, if b overwrote it then a must've also,
667 * and if b didn't overwrite it, then a didn't also.
668 * case 2b: 0 <= b < a < N
669 * write num records starting at a, which wraps around 0=N
670 * and overwrite fri unconditionally. Now from case 2a,
671 * this means that b eclipsed fri to overwrite it and wrap
672 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally
673 * set fri = b + 1 (mod N).
674 * Now, since fri is updated in every case, except the trivial case 0,
675 * the number of records present in the table after writing, is,
676 * num_recs - 1 = b - fri (mod N), and we take the positive value,
677 * by adding an arbitrary multiple of N before taking the modulo N
678 * as shown below.
679 */
680 a = control->ras_fri + control->ras_num_recs;
681 b = a + num - 1;
682 if (b < control->ras_max_record_count) {
683 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
684 } else if (a < control->ras_max_record_count) {
685 u32 g0, g1;
686
687 g0 = control->ras_max_record_count - a;
688 g1 = b % control->ras_max_record_count + 1;
689 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
690 if (res)
691 goto Out;
692 res = __amdgpu_ras_eeprom_write(control,
693 buf + g0 * RAS_TABLE_RECORD_SIZE,
694 0, g1);
695 if (res)
696 goto Out;
697 if (g1 > control->ras_fri)
698 control->ras_fri = g1 % control->ras_max_record_count;
699 } else {
700 a %= control->ras_max_record_count;
701 b %= control->ras_max_record_count;
702
703 if (a <= b) {
704 /* Note that, b - a + 1 = num. */
705 res = __amdgpu_ras_eeprom_write(control, buf, a, num);
706 if (res)
707 goto Out;
708 if (b >= control->ras_fri)
709 control->ras_fri = (b + 1) % control->ras_max_record_count;
710 } else {
711 u32 g0, g1;
712
713 /* b < a, which means, we write from
714 * a to the end of the table, and from
715 * the start of the table to b.
716 */
717 g0 = control->ras_max_record_count - a;
718 g1 = b + 1;
719 res = __amdgpu_ras_eeprom_write(control, buf, a, g0);
720 if (res)
721 goto Out;
722 res = __amdgpu_ras_eeprom_write(control,
723 buf + g0 * RAS_TABLE_RECORD_SIZE,
724 0, g1);
725 if (res)
726 goto Out;
727 control->ras_fri = g1 % control->ras_max_record_count;
728 }
729 }
730 control->ras_num_recs = 1 + (control->ras_max_record_count + b
731 - control->ras_fri)
732 % control->ras_max_record_count;
733
734 /*old asics only save pa to eeprom like before*/
735 if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12)
736 control->ras_num_pa_recs += num;
737 else
738 control->ras_num_mca_recs += num;
739
740 control->ras_num_bad_pages = control->ras_num_pa_recs +
741 control->ras_num_mca_recs * adev->umc.retire_unit;
742 Out:
743 kfree(buf);
744 return res;
745 }
746
747 static int
amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control * control)748 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)
749 {
750 struct amdgpu_device *adev = to_amdgpu_device(control);
751 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
752 u8 *buf, *pp, csum;
753 u32 buf_size;
754 int res;
755
756 /* Modify the header if it exceeds.
757 */
758 if (amdgpu_bad_page_threshold != 0 &&
759 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) {
760 dev_warn(adev->dev,
761 "Saved bad pages %d reaches threshold value %d\n",
762 control->ras_num_bad_pages, ras->bad_page_cnt_threshold);
763 control->tbl_hdr.header = RAS_TABLE_HDR_BAD;
764 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) {
765 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;
766 control->tbl_rai.health_percent = 0;
767 }
768
769 if ((amdgpu_bad_page_threshold != -1) &&
770 (amdgpu_bad_page_threshold != -2))
771 ras->is_rma = true;
772
773 /* ignore the -ENOTSUPP return value */
774 amdgpu_dpm_send_rma_reason(adev);
775 }
776
777 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
778 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
779 RAS_TABLE_V2_1_INFO_SIZE +
780 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
781 else
782 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +
783 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
784 control->tbl_hdr.checksum = 0;
785
786 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
787 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
788 if (!buf) {
789 DRM_ERROR("allocating memory for table of size %d bytes failed\n",
790 control->tbl_hdr.tbl_size);
791 res = -ENOMEM;
792 goto Out;
793 }
794
795 down_read(&adev->reset_domain->sem);
796 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
797 control->i2c_address +
798 control->ras_record_offset,
799 buf, buf_size);
800 up_read(&adev->reset_domain->sem);
801 if (res < 0) {
802 DRM_ERROR("EEPROM failed reading records:%d\n",
803 res);
804 goto Out;
805 } else if (res < buf_size) {
806 DRM_ERROR("EEPROM read %d out of %d bytes\n",
807 res, buf_size);
808 res = -EIO;
809 goto Out;
810 }
811
812 /**
813 * bad page records have been stored in eeprom,
814 * now calculate gpu health percent
815 */
816 if (amdgpu_bad_page_threshold != 0 &&
817 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 &&
818 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold)
819 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold -
820 control->ras_num_bad_pages) * 100) /
821 ras->bad_page_cnt_threshold;
822
823 /* Recalc the checksum.
824 */
825 csum = 0;
826 for (pp = buf; pp < buf + buf_size; pp++)
827 csum += *pp;
828
829 csum += __calc_hdr_byte_sum(control);
830 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
831 csum += __calc_ras_info_byte_sum(control);
832 /* avoid sign extension when assigning to "checksum" */
833 csum = -csum;
834 control->tbl_hdr.checksum = csum;
835 res = __write_table_header(control);
836 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1)
837 res = __write_table_ras_info(control);
838 Out:
839 kfree(buf);
840 return res;
841 }
842
843 /**
844 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table
845 * @control: pointer to control structure
846 * @record: array of records to append
847 * @num: number of records in @record array
848 *
849 * Append @num records to the table, calculate the checksum and write
850 * the table back to EEPROM. The maximum number of records that
851 * can be appended is between 1 and control->ras_max_record_count,
852 * regardless of how many records are already stored in the table.
853 *
854 * Return 0 on success or if EEPROM is not supported, -errno on error.
855 */
amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)856 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
857 struct eeprom_table_record *record,
858 const u32 num)
859 {
860 struct amdgpu_device *adev = to_amdgpu_device(control);
861 int res, i;
862 uint64_t nps = AMDGPU_NPS1_PARTITION_MODE;
863
864 if (!__is_ras_eeprom_supported(adev))
865 return 0;
866
867 if (num == 0) {
868 DRM_ERROR("will not append 0 records\n");
869 return -EINVAL;
870 } else if (num > control->ras_max_record_count) {
871 DRM_ERROR("cannot append %d records than the size of table %d\n",
872 num, control->ras_max_record_count);
873 return -EINVAL;
874 }
875
876 if (adev->gmc.gmc_funcs->query_mem_partition_mode)
877 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
878
879 /* set the new channel index flag */
880 for (i = 0; i < num; i++)
881 record[i].retired_page |= (nps << UMC_NPS_SHIFT);
882
883 mutex_lock(&control->ras_tbl_mutex);
884
885 res = amdgpu_ras_eeprom_append_table(control, record, num);
886 if (!res)
887 res = amdgpu_ras_eeprom_update_header(control);
888 if (!res)
889 amdgpu_ras_debugfs_set_ret_size(control);
890
891 mutex_unlock(&control->ras_tbl_mutex);
892
893 /* clear channel index flag, the flag is only saved on eeprom */
894 for (i = 0; i < num; i++)
895 record[i].retired_page &= ~(nps << UMC_NPS_SHIFT);
896
897 return res;
898 }
899
900 /**
901 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer
902 * @control: pointer to control structure
903 * @buf: pointer to buffer to read into
904 * @fri: first record index, start reading at this index, absolute index
905 * @num: number of records to read
906 *
907 * The caller must hold the table mutex in @control.
908 * Return 0 on success, -errno otherwise.
909 */
__amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,u8 * buf,const u32 fri,const u32 num)910 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
911 u8 *buf, const u32 fri, const u32 num)
912 {
913 struct amdgpu_device *adev = to_amdgpu_device(control);
914 u32 buf_size;
915 int res;
916
917 /* i2c may be unstable in gpu reset */
918 down_read(&adev->reset_domain->sem);
919 buf_size = num * RAS_TABLE_RECORD_SIZE;
920 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
921 control->i2c_address +
922 RAS_INDEX_TO_OFFSET(control, fri),
923 buf, buf_size);
924 up_read(&adev->reset_domain->sem);
925 if (res < 0) {
926 DRM_ERROR("Reading %d EEPROM table records error:%d",
927 num, res);
928 } else if (res < buf_size) {
929 /* Short read, return error.
930 */
931 DRM_ERROR("Read %d records out of %d",
932 res / RAS_TABLE_RECORD_SIZE, num);
933 res = -EIO;
934 } else {
935 res = 0;
936 }
937
938 return res;
939 }
940
941 /**
942 * amdgpu_ras_eeprom_read -- read EEPROM
943 * @control: pointer to control structure
944 * @record: array of records to read into
945 * @num: number of records in @record
946 *
947 * Reads num records from the RAS table in EEPROM and
948 * writes the data into @record array.
949 *
950 * Returns 0 on success, -errno on error.
951 */
amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control * control,struct eeprom_table_record * record,const u32 num)952 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
953 struct eeprom_table_record *record,
954 const u32 num)
955 {
956 struct amdgpu_device *adev = to_amdgpu_device(control);
957 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
958 int i, res;
959 u8 *buf, *pp;
960 u32 g0, g1;
961
962 if (!__is_ras_eeprom_supported(adev))
963 return 0;
964
965 if (num == 0) {
966 DRM_ERROR("will not read 0 records\n");
967 return -EINVAL;
968 } else if (num > control->ras_num_recs) {
969 DRM_ERROR("too many records to read:%d available:%d\n",
970 num, control->ras_num_recs);
971 return -EINVAL;
972 }
973
974 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
975 if (!buf)
976 return -ENOMEM;
977
978 /* Determine how many records to read, from the first record
979 * index, fri, to the end of the table, and from the beginning
980 * of the table, such that the total number of records is
981 * @num, and we handle wrap around when fri > 0 and
982 * fri + num > RAS_MAX_RECORD_COUNT.
983 *
984 * First we compute the index of the last element
985 * which would be fetched from each region,
986 * g0 is in [fri, fri + num - 1], and
987 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1].
988 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of
989 * the last element to fetch, we set g0 to _the number_
990 * of elements to fetch, @num, since we know that the last
991 * indexed to be fetched does not exceed the table.
992 *
993 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then
994 * we set g0 to the number of elements to read
995 * until the end of the table, and g1 to the number of
996 * elements to read from the beginning of the table.
997 */
998 g0 = control->ras_fri + num - 1;
999 g1 = g0 % control->ras_max_record_count;
1000 if (g0 < control->ras_max_record_count) {
1001 g0 = num;
1002 g1 = 0;
1003 } else {
1004 g0 = control->ras_max_record_count - control->ras_fri;
1005 g1 += 1;
1006 }
1007
1008 mutex_lock(&control->ras_tbl_mutex);
1009 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);
1010 if (res)
1011 goto Out;
1012 if (g1) {
1013 res = __amdgpu_ras_eeprom_read(control,
1014 buf + g0 * RAS_TABLE_RECORD_SIZE,
1015 0, g1);
1016 if (res)
1017 goto Out;
1018 }
1019
1020 res = 0;
1021
1022 /* Read up everything? Then transform.
1023 */
1024 pp = buf;
1025 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) {
1026 __decode_table_record_from_buf(control, &record[i], pp);
1027
1028 /* update bad channel bitmap */
1029 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&
1030 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {
1031 control->bad_channel_bitmap |= 1 << record[i].mem_channel;
1032 con->update_channel_flag = true;
1033 }
1034 }
1035 Out:
1036 kfree(buf);
1037 mutex_unlock(&control->ras_tbl_mutex);
1038
1039 return res;
1040 }
1041
amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control * control)1042 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)
1043 {
1044 /* get available eeprom table version first before eeprom table init */
1045 amdgpu_ras_set_eeprom_table_version(control);
1046
1047 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
1048 return RAS_MAX_RECORD_COUNT_V2_1;
1049 else
1050 return RAS_MAX_RECORD_COUNT;
1051 }
1052
1053 static ssize_t
amdgpu_ras_debugfs_eeprom_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1054 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf,
1055 size_t size, loff_t *pos)
1056 {
1057 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1058 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1059 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1060 u8 data[50];
1061 int res;
1062
1063 if (!size)
1064 return size;
1065
1066 if (!ras || !control) {
1067 res = snprintf(data, sizeof(data), "Not supported\n");
1068 } else {
1069 res = snprintf(data, sizeof(data), "%d bytes or %d records\n",
1070 RAS_TBL_SIZE_BYTES, control->ras_max_record_count);
1071 }
1072
1073 if (*pos >= res)
1074 return 0;
1075
1076 res -= *pos;
1077 res = min_t(size_t, res, size);
1078
1079 if (copy_to_user(buf, &data[*pos], res))
1080 return -EFAULT;
1081
1082 *pos += res;
1083
1084 return res;
1085 }
1086
1087 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
1088 .owner = THIS_MODULE,
1089 .read = amdgpu_ras_debugfs_eeprom_size_read,
1090 .write = NULL,
1091 .llseek = default_llseek,
1092 };
1093
1094 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
1095 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
1096 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
1097 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
1098 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
1099 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
1100
1101 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
1102 "ignore",
1103 "re",
1104 "ue",
1105 };
1106
amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control * control)1107 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
1108 {
1109 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
1110 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
1111 }
1112
amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control * control)1113 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
1114 {
1115 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
1116 eeprom_control);
1117 struct dentry *de = ras->de_ras_eeprom_table;
1118
1119 if (de)
1120 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
1121 }
1122
amdgpu_ras_debugfs_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1123 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
1124 size_t size, loff_t *pos)
1125 {
1126 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1127 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1128 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
1129 const size_t orig_size = size;
1130 int res = -EFAULT;
1131 size_t data_len;
1132
1133 mutex_lock(&control->ras_tbl_mutex);
1134
1135 /* We want *pos - data_len > 0, which means there's
1136 * bytes to be printed from data.
1137 */
1138 data_len = strlen(tbl_hdr_str);
1139 if (*pos < data_len) {
1140 data_len -= *pos;
1141 data_len = min_t(size_t, data_len, size);
1142 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
1143 goto Out;
1144 buf += data_len;
1145 size -= data_len;
1146 *pos += data_len;
1147 }
1148
1149 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
1150 if (*pos < data_len && size > 0) {
1151 u8 data[tbl_hdr_fmt_size + 1];
1152 loff_t lpos;
1153
1154 snprintf(data, sizeof(data), tbl_hdr_fmt,
1155 control->tbl_hdr.header,
1156 control->tbl_hdr.version,
1157 control->tbl_hdr.first_rec_offset,
1158 control->tbl_hdr.tbl_size,
1159 control->tbl_hdr.checksum);
1160
1161 data_len -= *pos;
1162 data_len = min_t(size_t, data_len, size);
1163 lpos = *pos - strlen(tbl_hdr_str);
1164 if (copy_to_user(buf, &data[lpos], data_len))
1165 goto Out;
1166 buf += data_len;
1167 size -= data_len;
1168 *pos += data_len;
1169 }
1170
1171 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
1172 if (*pos < data_len && size > 0) {
1173 loff_t lpos;
1174
1175 data_len -= *pos;
1176 data_len = min_t(size_t, data_len, size);
1177 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size;
1178 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len))
1179 goto Out;
1180 buf += data_len;
1181 size -= data_len;
1182 *pos += data_len;
1183 }
1184
1185 data_len = amdgpu_ras_debugfs_table_size(control);
1186 if (*pos < data_len && size > 0) {
1187 u8 dare[RAS_TABLE_RECORD_SIZE];
1188 u8 data[rec_hdr_fmt_size + 1];
1189 struct eeprom_table_record record;
1190 int s, r;
1191
1192 /* Find the starting record index
1193 */
1194 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1195 strlen(rec_hdr_str);
1196 s = s / rec_hdr_fmt_size;
1197 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size -
1198 strlen(rec_hdr_str);
1199 r = r % rec_hdr_fmt_size;
1200
1201 for ( ; size > 0 && s < control->ras_num_recs; s++) {
1202 u32 ai = RAS_RI_TO_AI(control, s);
1203 /* Read a single record
1204 */
1205 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);
1206 if (res)
1207 goto Out;
1208 __decode_table_record_from_buf(control, &record, dare);
1209 snprintf(data, sizeof(data), rec_hdr_fmt,
1210 s,
1211 RAS_INDEX_TO_OFFSET(control, ai),
1212 record_err_type_str[record.err_type],
1213 record.bank,
1214 record.ts,
1215 record.offset,
1216 record.mem_channel,
1217 record.mcumc_id,
1218 record.retired_page);
1219
1220 data_len = min_t(size_t, rec_hdr_fmt_size - r, size);
1221 if (copy_to_user(buf, &data[r], data_len)) {
1222 res = -EFAULT;
1223 goto Out;
1224 }
1225 buf += data_len;
1226 size -= data_len;
1227 *pos += data_len;
1228 r = 0;
1229 }
1230 }
1231 res = 0;
1232 Out:
1233 mutex_unlock(&control->ras_tbl_mutex);
1234 return res < 0 ? res : orig_size - size;
1235 }
1236
1237 static ssize_t
amdgpu_ras_debugfs_eeprom_table_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1238 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf,
1239 size_t size, loff_t *pos)
1240 {
1241 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1242 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1243 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;
1244 u8 data[81];
1245 int res;
1246
1247 if (!size)
1248 return size;
1249
1250 if (!ras || !control) {
1251 res = snprintf(data, sizeof(data), "Not supported\n");
1252 if (*pos >= res)
1253 return 0;
1254
1255 res -= *pos;
1256 res = min_t(size_t, res, size);
1257
1258 if (copy_to_user(buf, &data[*pos], res))
1259 return -EFAULT;
1260
1261 *pos += res;
1262
1263 return res;
1264 } else {
1265 return amdgpu_ras_debugfs_table_read(f, buf, size, pos);
1266 }
1267 }
1268
1269 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = {
1270 .owner = THIS_MODULE,
1271 .read = amdgpu_ras_debugfs_eeprom_table_read,
1272 .write = NULL,
1273 .llseek = default_llseek,
1274 };
1275
1276 /**
1277 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum
1278 * @control: pointer to control structure
1279 *
1280 * Check the checksum of the stored in EEPROM RAS table.
1281 *
1282 * Return 0 if the checksum is correct,
1283 * positive if it is not correct, and
1284 * -errno on I/O error.
1285 */
__verify_ras_table_checksum(struct amdgpu_ras_eeprom_control * control)1286 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)
1287 {
1288 struct amdgpu_device *adev = to_amdgpu_device(control);
1289 int buf_size, res;
1290 u8 csum, *buf, *pp;
1291
1292 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1)
1293 buf_size = RAS_TABLE_HEADER_SIZE +
1294 RAS_TABLE_V2_1_INFO_SIZE +
1295 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1296 else
1297 buf_size = RAS_TABLE_HEADER_SIZE +
1298 control->ras_num_recs * RAS_TABLE_RECORD_SIZE;
1299
1300 buf = kzalloc(buf_size, GFP_KERNEL);
1301 if (!buf) {
1302 DRM_ERROR("Out of memory checking RAS table checksum.\n");
1303 return -ENOMEM;
1304 }
1305
1306 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1307 control->i2c_address +
1308 control->ras_header_offset,
1309 buf, buf_size);
1310 if (res < buf_size) {
1311 DRM_ERROR("Partial read for checksum, res:%d\n", res);
1312 /* On partial reads, return -EIO.
1313 */
1314 if (res >= 0)
1315 res = -EIO;
1316 goto Out;
1317 }
1318
1319 csum = 0;
1320 for (pp = buf; pp < buf + buf_size; pp++)
1321 csum += *pp;
1322 Out:
1323 kfree(buf);
1324 return res < 0 ? res : csum;
1325 }
1326
__read_table_ras_info(struct amdgpu_ras_eeprom_control * control)1327 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)
1328 {
1329 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;
1330 struct amdgpu_device *adev = to_amdgpu_device(control);
1331 unsigned char *buf;
1332 int res;
1333
1334 buf = kzalloc(RAS_TABLE_V2_1_INFO_SIZE, GFP_KERNEL);
1335 if (!buf) {
1336 DRM_ERROR("Failed to alloc buf to read EEPROM table ras info\n");
1337 return -ENOMEM;
1338 }
1339
1340 /**
1341 * EEPROM table V2_1 supports ras info,
1342 * read EEPROM table ras info
1343 */
1344 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1345 control->i2c_address + control->ras_info_offset,
1346 buf, RAS_TABLE_V2_1_INFO_SIZE);
1347 if (res < RAS_TABLE_V2_1_INFO_SIZE) {
1348 DRM_ERROR("Failed to read EEPROM table ras info, res:%d", res);
1349 res = res >= 0 ? -EIO : res;
1350 goto Out;
1351 }
1352
1353 __decode_table_ras_info_from_buf(rai, buf);
1354
1355 Out:
1356 kfree(buf);
1357 return res == RAS_TABLE_V2_1_INFO_SIZE ? 0 : res;
1358 }
1359
amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control * control)1360 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
1361 {
1362 struct amdgpu_device *adev = to_amdgpu_device(control);
1363 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
1364 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1365 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1366 int res;
1367
1368 ras->is_rma = false;
1369
1370 if (!__is_ras_eeprom_supported(adev))
1371 return 0;
1372
1373 /* Verify i2c adapter is initialized */
1374 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1375 return -ENOENT;
1376
1377 if (!__get_eeprom_i2c_addr(adev, control))
1378 return -EINVAL;
1379
1380 control->ras_header_offset = RAS_HDR_START;
1381 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START;
1382 mutex_init(&control->ras_tbl_mutex);
1383
1384 /* Read the table header from EEPROM address */
1385 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
1386 control->i2c_address + control->ras_header_offset,
1387 buf, RAS_TABLE_HEADER_SIZE);
1388 if (res < RAS_TABLE_HEADER_SIZE) {
1389 DRM_ERROR("Failed to read EEPROM table header, res:%d", res);
1390 return res >= 0 ? -EIO : res;
1391 }
1392
1393 __decode_table_header_from_buf(hdr, buf);
1394
1395 if (hdr->version >= RAS_TABLE_VER_V2_1) {
1396 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);
1397 control->ras_record_offset = RAS_RECORD_START_V2_1;
1398 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;
1399 } else {
1400 control->ras_num_recs = RAS_NUM_RECS(hdr);
1401 control->ras_record_offset = RAS_RECORD_START;
1402 control->ras_max_record_count = RAS_MAX_RECORD_COUNT;
1403 }
1404 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);
1405
1406 control->ras_num_mca_recs = 0;
1407 control->ras_num_pa_recs = 0;
1408 return 0;
1409 }
1410
amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control * control)1411 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control)
1412 {
1413 struct amdgpu_device *adev = to_amdgpu_device(control);
1414 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
1415 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1416 int res;
1417
1418 if (!__is_ras_eeprom_supported(adev))
1419 return 0;
1420
1421 /* Verify i2c adapter is initialized */
1422 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
1423 return -ENOENT;
1424
1425 if (!__get_eeprom_i2c_addr(adev, control))
1426 return -EINVAL;
1427
1428 control->ras_num_bad_pages = control->ras_num_pa_recs +
1429 control->ras_num_mca_recs * adev->umc.retire_unit;
1430
1431 if (hdr->header == RAS_TABLE_HDR_VAL) {
1432 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
1433 control->ras_num_bad_pages);
1434
1435 if (hdr->version >= RAS_TABLE_VER_V2_1) {
1436 res = __read_table_ras_info(control);
1437 if (res)
1438 return res;
1439 }
1440
1441 res = __verify_ras_table_checksum(control);
1442 if (res)
1443 dev_err(adev->dev,
1444 "RAS table incorrect checksum or error:%d\n",
1445 res);
1446
1447 /* Warn if we are at 90% of the threshold or above
1448 */
1449 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold)
1450 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d",
1451 control->ras_num_bad_pages,
1452 ras->bad_page_cnt_threshold);
1453 } else if (hdr->header == RAS_TABLE_HDR_BAD &&
1454 amdgpu_bad_page_threshold != 0) {
1455 if (hdr->version >= RAS_TABLE_VER_V2_1) {
1456 res = __read_table_ras_info(control);
1457 if (res)
1458 return res;
1459 }
1460
1461 res = __verify_ras_table_checksum(control);
1462 if (res) {
1463 dev_err(adev->dev,
1464 "RAS Table incorrect checksum or error:%d\n",
1465 res);
1466 return -EINVAL;
1467 }
1468 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) {
1469 /* This means that, the threshold was increased since
1470 * the last time the system was booted, and now,
1471 * ras->bad_page_cnt_threshold - control->num_recs > 0,
1472 * so that at least one more record can be saved,
1473 * before the page count threshold is reached.
1474 */
1475 dev_info(adev->dev,
1476 "records:%d threshold:%d, resetting "
1477 "RAS table header signature",
1478 control->ras_num_bad_pages,
1479 ras->bad_page_cnt_threshold);
1480 res = amdgpu_ras_eeprom_correct_header_tag(control,
1481 RAS_TABLE_HDR_VAL);
1482 } else {
1483 dev_warn(adev->dev,
1484 "RAS records:%d exceed threshold:%d\n",
1485 control->ras_num_bad_pages, ras->bad_page_cnt_threshold);
1486 if ((amdgpu_bad_page_threshold == -1) ||
1487 (amdgpu_bad_page_threshold == -2)) {
1488 res = 0;
1489 dev_warn(adev->dev,
1490 "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n");
1491 } else {
1492 ras->is_rma = true;
1493 dev_warn(adev->dev,
1494 "User defined threshold is set, runtime service will be halt when threshold is reached\n");
1495 }
1496 }
1497 } else {
1498 DRM_INFO("Creating a new EEPROM table");
1499
1500 res = amdgpu_ras_eeprom_reset_table(control);
1501 }
1502
1503 return res < 0 ? res : 0;
1504 }
1505