1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/export.h>
28 #include <linux/pci.h>
29
30 #include <drm/drm_edid.h>
31 #include <drm/amdgpu_drm.h>
32 #include "amdgpu.h"
33 #include "amdgpu_i2c.h"
34 #include "amdgpu_atombios.h"
35 #include "atom.h"
36 #include "atombios_dp.h"
37 #include "atombios_i2c.h"
38
39 /* bit banging i2c */
amdgpu_i2c_pre_xfer(struct i2c_adapter * i2c_adap)40 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
41 {
42 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
43 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
44 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
45 uint32_t temp;
46
47 mutex_lock(&i2c->mutex);
48
49 /* switch the pads to ddc mode */
50 if (rec->hw_capable) {
51 temp = RREG32(rec->mask_clk_reg);
52 temp &= ~(1 << 16);
53 WREG32(rec->mask_clk_reg, temp);
54 }
55
56 /* clear the output pin values */
57 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
58 WREG32(rec->a_clk_reg, temp);
59
60 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
61 WREG32(rec->a_data_reg, temp);
62
63 /* set the pins to input */
64 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
65 WREG32(rec->en_clk_reg, temp);
66
67 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
68 WREG32(rec->en_data_reg, temp);
69
70 /* mask the gpio pins for software use */
71 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
72 WREG32(rec->mask_clk_reg, temp);
73 temp = RREG32(rec->mask_clk_reg);
74
75 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
76 WREG32(rec->mask_data_reg, temp);
77 temp = RREG32(rec->mask_data_reg);
78
79 return 0;
80 }
81
amdgpu_i2c_post_xfer(struct i2c_adapter * i2c_adap)82 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
83 {
84 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
85 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
86 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
87 uint32_t temp;
88
89 /* unmask the gpio pins for software use */
90 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
91 WREG32(rec->mask_clk_reg, temp);
92 temp = RREG32(rec->mask_clk_reg);
93
94 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
95 WREG32(rec->mask_data_reg, temp);
96 temp = RREG32(rec->mask_data_reg);
97
98 mutex_unlock(&i2c->mutex);
99 }
100
amdgpu_i2c_get_clock(void * i2c_priv)101 static int amdgpu_i2c_get_clock(void *i2c_priv)
102 {
103 struct amdgpu_i2c_chan *i2c = i2c_priv;
104 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
105 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
106 uint32_t val;
107
108 /* read the value off the pin */
109 val = RREG32(rec->y_clk_reg);
110 val &= rec->y_clk_mask;
111
112 return (val != 0);
113 }
114
115
amdgpu_i2c_get_data(void * i2c_priv)116 static int amdgpu_i2c_get_data(void *i2c_priv)
117 {
118 struct amdgpu_i2c_chan *i2c = i2c_priv;
119 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
120 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
121 uint32_t val;
122
123 /* read the value off the pin */
124 val = RREG32(rec->y_data_reg);
125 val &= rec->y_data_mask;
126
127 return (val != 0);
128 }
129
amdgpu_i2c_set_clock(void * i2c_priv,int clock)130 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
131 {
132 struct amdgpu_i2c_chan *i2c = i2c_priv;
133 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
134 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
135 uint32_t val;
136
137 /* set pin direction */
138 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
139 val |= clock ? 0 : rec->en_clk_mask;
140 WREG32(rec->en_clk_reg, val);
141 }
142
amdgpu_i2c_set_data(void * i2c_priv,int data)143 static void amdgpu_i2c_set_data(void *i2c_priv, int data)
144 {
145 struct amdgpu_i2c_chan *i2c = i2c_priv;
146 struct amdgpu_device *adev = drm_to_adev(i2c->dev);
147 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
148 uint32_t val;
149
150 /* set pin direction */
151 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
152 val |= data ? 0 : rec->en_data_mask;
153 WREG32(rec->en_data_reg, val);
154 }
155
156 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
157 .master_xfer = amdgpu_atombios_i2c_xfer,
158 .functionality = amdgpu_atombios_i2c_func,
159 };
160
amdgpu_i2c_create(struct drm_device * dev,const struct amdgpu_i2c_bus_rec * rec,const char * name)161 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
162 const struct amdgpu_i2c_bus_rec *rec,
163 const char *name)
164 {
165 struct amdgpu_i2c_chan *i2c;
166 int ret;
167
168 /* don't add the mm_i2c bus unless hw_i2c is enabled */
169 if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
170 return NULL;
171
172 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
173 if (i2c == NULL)
174 return NULL;
175
176 i2c->rec = *rec;
177 i2c->adapter.owner = THIS_MODULE;
178 i2c->adapter.dev.parent = dev->dev;
179 i2c->dev = dev;
180 i2c_set_adapdata(&i2c->adapter, i2c);
181 mutex_init(&i2c->mutex);
182 if (rec->hw_capable &&
183 amdgpu_hw_i2c) {
184 /* hw i2c using atom */
185 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
186 "AMDGPU i2c hw bus %s", name);
187 i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
188 ret = i2c_add_adapter(&i2c->adapter);
189 if (ret)
190 goto out_free;
191 } else {
192 /* set the amdgpu bit adapter */
193 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
194 "AMDGPU i2c bit bus %s", name);
195 i2c->adapter.algo_data = &i2c->bit;
196 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
197 i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
198 i2c->bit.setsda = amdgpu_i2c_set_data;
199 i2c->bit.setscl = amdgpu_i2c_set_clock;
200 i2c->bit.getsda = amdgpu_i2c_get_data;
201 i2c->bit.getscl = amdgpu_i2c_get_clock;
202 i2c->bit.udelay = 10;
203 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
204 i2c->bit.data = i2c;
205 ret = i2c_bit_add_bus(&i2c->adapter);
206 if (ret) {
207 DRM_ERROR("Failed to register bit i2c %s\n", name);
208 goto out_free;
209 }
210 }
211
212 return i2c;
213 out_free:
214 kfree(i2c);
215 return NULL;
216
217 }
218
amdgpu_i2c_destroy(struct amdgpu_i2c_chan * i2c)219 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
220 {
221 if (!i2c)
222 return;
223 WARN_ON(i2c->has_aux);
224 i2c_del_adapter(&i2c->adapter);
225 kfree(i2c);
226 }
227
amdgpu_i2c_init(struct amdgpu_device * adev)228 void amdgpu_i2c_init(struct amdgpu_device *adev)
229 {
230 if (!adev->is_atom_fw) {
231 if (!amdgpu_device_has_dc_support(adev)) {
232 amdgpu_atombios_i2c_init(adev);
233 } else {
234 switch (adev->asic_type) {
235 case CHIP_POLARIS10:
236 case CHIP_POLARIS11:
237 case CHIP_POLARIS12:
238 amdgpu_atombios_oem_i2c_init(adev, 0x97);
239 break;
240 default:
241 break;
242 }
243 }
244 }
245 }
246
247 /* remove all the buses */
amdgpu_i2c_fini(struct amdgpu_device * adev)248 void amdgpu_i2c_fini(struct amdgpu_device *adev)
249 {
250 int i;
251
252 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
253 if (adev->i2c_bus[i]) {
254 amdgpu_i2c_destroy(adev->i2c_bus[i]);
255 adev->i2c_bus[i] = NULL;
256 }
257 }
258 }
259
260 /* looks up bus based on id */
261 struct amdgpu_i2c_chan *
amdgpu_i2c_lookup(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * i2c_bus)262 amdgpu_i2c_lookup(struct amdgpu_device *adev,
263 const struct amdgpu_i2c_bus_rec *i2c_bus)
264 {
265 int i;
266
267 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
268 if (adev->i2c_bus[i] &&
269 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
270 return adev->i2c_bus[i];
271 }
272 }
273 return NULL;
274 }
275
amdgpu_i2c_get_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 * val)276 static int amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
277 u8 slave_addr,
278 u8 addr,
279 u8 *val)
280 {
281 u8 out_buf[2];
282 u8 in_buf[2];
283 struct i2c_msg msgs[] = {
284 {
285 .addr = slave_addr,
286 .flags = 0,
287 .len = 1,
288 .buf = out_buf,
289 },
290 {
291 .addr = slave_addr,
292 .flags = I2C_M_RD,
293 .len = 1,
294 .buf = in_buf,
295 }
296 };
297
298 out_buf[0] = addr;
299 out_buf[1] = 0;
300
301 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) != 2) {
302 DRM_DEBUG("i2c 0x%02x read failed\n", addr);
303 return -EIO;
304 }
305
306 *val = in_buf[0];
307 DRM_DEBUG("val = 0x%02x\n", *val);
308
309 return 0;
310 }
311
amdgpu_i2c_put_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 val)312 static int amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
313 u8 slave_addr,
314 u8 addr,
315 u8 val)
316 {
317 uint8_t out_buf[2];
318 struct i2c_msg msg = {
319 .addr = slave_addr,
320 .flags = 0,
321 .len = 2,
322 .buf = out_buf,
323 };
324
325 out_buf[0] = addr;
326 out_buf[1] = val;
327
328 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) {
329 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", addr, val);
330 return -EIO;
331 }
332
333 return 0;
334 }
335
336 /* ddc router switching */
337 void
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector * amdgpu_connector)338 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
339 {
340 u8 val = 0;
341
342 if (!amdgpu_connector->router.ddc_valid)
343 return;
344
345 if (!amdgpu_connector->router_bus)
346 return;
347
348 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
349 amdgpu_connector->router.i2c_addr,
350 0x3, &val))
351 return;
352 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
353 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
354 amdgpu_connector->router.i2c_addr,
355 0x3, val);
356 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
357 amdgpu_connector->router.i2c_addr,
358 0x1, &val))
359 return;
360 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
361 val |= amdgpu_connector->router.ddc_mux_state;
362 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
363 amdgpu_connector->router.i2c_addr,
364 0x1, val);
365 }
366
367 /* clock/data router switching */
368 void
amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector * amdgpu_connector)369 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
370 {
371 u8 val;
372
373 if (!amdgpu_connector->router.cd_valid)
374 return;
375
376 if (!amdgpu_connector->router_bus)
377 return;
378
379 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
380 amdgpu_connector->router.i2c_addr,
381 0x3, &val))
382 return;
383 val &= ~amdgpu_connector->router.cd_mux_control_pin;
384 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
385 amdgpu_connector->router.i2c_addr,
386 0x3, val);
387 if (amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
388 amdgpu_connector->router.i2c_addr,
389 0x1, &val))
390 return;
391 val &= ~amdgpu_connector->router.cd_mux_control_pin;
392 val |= amdgpu_connector->router.cd_mux_state;
393 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
394 amdgpu_connector->router.i2c_addr,
395 0x1, val);
396 }
397