1 /*
2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_discovery.h"
28 #include "soc15_hw_ip.h"
29 #include "discovery.h"
30 #include "amdgpu_ras.h"
31
32 #include "soc15.h"
33 #include "gfx_v9_0.h"
34 #include "gfx_v9_4_3.h"
35 #include "gmc_v9_0.h"
36 #include "df_v1_7.h"
37 #include "df_v3_6.h"
38 #include "df_v4_3.h"
39 #include "df_v4_6_2.h"
40 #include "df_v4_15.h"
41 #include "nbio_v6_1.h"
42 #include "nbio_v7_0.h"
43 #include "nbio_v7_4.h"
44 #include "nbio_v7_9.h"
45 #include "nbio_v7_11.h"
46 #include "hdp_v4_0.h"
47 #include "vega10_ih.h"
48 #include "vega20_ih.h"
49 #include "sdma_v4_0.h"
50 #include "sdma_v4_4_2.h"
51 #include "uvd_v7_0.h"
52 #include "vce_v4_0.h"
53 #include "vcn_v1_0.h"
54 #include "vcn_v2_5.h"
55 #include "jpeg_v2_5.h"
56 #include "smuio_v9_0.h"
57 #include "gmc_v10_0.h"
58 #include "gmc_v11_0.h"
59 #include "gmc_v12_0.h"
60 #include "gfxhub_v2_0.h"
61 #include "mmhub_v2_0.h"
62 #include "nbio_v2_3.h"
63 #include "nbio_v4_3.h"
64 #include "nbio_v7_2.h"
65 #include "nbio_v7_7.h"
66 #include "nbif_v6_3_1.h"
67 #include "hdp_v5_0.h"
68 #include "hdp_v5_2.h"
69 #include "hdp_v6_0.h"
70 #include "hdp_v7_0.h"
71 #include "nv.h"
72 #include "soc21.h"
73 #include "soc24.h"
74 #include "navi10_ih.h"
75 #include "ih_v6_0.h"
76 #include "ih_v6_1.h"
77 #include "ih_v7_0.h"
78 #include "gfx_v10_0.h"
79 #include "gfx_v11_0.h"
80 #include "gfx_v12_0.h"
81 #include "sdma_v5_0.h"
82 #include "sdma_v5_2.h"
83 #include "sdma_v6_0.h"
84 #include "sdma_v7_0.h"
85 #include "lsdma_v6_0.h"
86 #include "lsdma_v7_0.h"
87 #include "vcn_v2_0.h"
88 #include "jpeg_v2_0.h"
89 #include "vcn_v3_0.h"
90 #include "jpeg_v3_0.h"
91 #include "vcn_v4_0.h"
92 #include "jpeg_v4_0.h"
93 #include "vcn_v4_0_3.h"
94 #include "jpeg_v4_0_3.h"
95 #include "vcn_v4_0_5.h"
96 #include "jpeg_v4_0_5.h"
97 #include "amdgpu_vkms.h"
98 #include "mes_v11_0.h"
99 #include "mes_v12_0.h"
100 #include "smuio_v11_0.h"
101 #include "smuio_v11_0_6.h"
102 #include "smuio_v13_0.h"
103 #include "smuio_v13_0_3.h"
104 #include "smuio_v13_0_6.h"
105 #include "smuio_v14_0_2.h"
106 #include "vcn_v5_0_0.h"
107 #include "vcn_v5_0_1.h"
108 #include "jpeg_v5_0_0.h"
109 #include "jpeg_v5_0_1.h"
110
111 #include "amdgpu_vpe.h"
112 #if defined(CONFIG_DRM_AMD_ISP)
113 #include "amdgpu_isp.h"
114 #endif
115
116 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
117 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin");
118 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin");
119 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin");
120 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");
121 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");
122 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");
123 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin");
124 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin");
125
126 #define mmIP_DISCOVERY_VERSION 0x16A00
127 #define mmRCC_CONFIG_MEMSIZE 0xde3
128 #define mmMP0_SMN_C2PMSG_33 0x16061
129 #define mmMM_INDEX 0x0
130 #define mmMM_INDEX_HI 0x6
131 #define mmMM_DATA 0x1
132
133 static const char *hw_id_names[HW_ID_MAX] = {
134 [MP1_HWID] = "MP1",
135 [MP2_HWID] = "MP2",
136 [THM_HWID] = "THM",
137 [SMUIO_HWID] = "SMUIO",
138 [FUSE_HWID] = "FUSE",
139 [CLKA_HWID] = "CLKA",
140 [PWR_HWID] = "PWR",
141 [GC_HWID] = "GC",
142 [UVD_HWID] = "UVD",
143 [AUDIO_AZ_HWID] = "AUDIO_AZ",
144 [ACP_HWID] = "ACP",
145 [DCI_HWID] = "DCI",
146 [DMU_HWID] = "DMU",
147 [DCO_HWID] = "DCO",
148 [DIO_HWID] = "DIO",
149 [XDMA_HWID] = "XDMA",
150 [DCEAZ_HWID] = "DCEAZ",
151 [DAZ_HWID] = "DAZ",
152 [SDPMUX_HWID] = "SDPMUX",
153 [NTB_HWID] = "NTB",
154 [IOHC_HWID] = "IOHC",
155 [L2IMU_HWID] = "L2IMU",
156 [VCE_HWID] = "VCE",
157 [MMHUB_HWID] = "MMHUB",
158 [ATHUB_HWID] = "ATHUB",
159 [DBGU_NBIO_HWID] = "DBGU_NBIO",
160 [DFX_HWID] = "DFX",
161 [DBGU0_HWID] = "DBGU0",
162 [DBGU1_HWID] = "DBGU1",
163 [OSSSYS_HWID] = "OSSSYS",
164 [HDP_HWID] = "HDP",
165 [SDMA0_HWID] = "SDMA0",
166 [SDMA1_HWID] = "SDMA1",
167 [SDMA2_HWID] = "SDMA2",
168 [SDMA3_HWID] = "SDMA3",
169 [LSDMA_HWID] = "LSDMA",
170 [ISP_HWID] = "ISP",
171 [DBGU_IO_HWID] = "DBGU_IO",
172 [DF_HWID] = "DF",
173 [CLKB_HWID] = "CLKB",
174 [FCH_HWID] = "FCH",
175 [DFX_DAP_HWID] = "DFX_DAP",
176 [L1IMU_PCIE_HWID] = "L1IMU_PCIE",
177 [L1IMU_NBIF_HWID] = "L1IMU_NBIF",
178 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
179 [L1IMU3_HWID] = "L1IMU3",
180 [L1IMU4_HWID] = "L1IMU4",
181 [L1IMU5_HWID] = "L1IMU5",
182 [L1IMU6_HWID] = "L1IMU6",
183 [L1IMU7_HWID] = "L1IMU7",
184 [L1IMU8_HWID] = "L1IMU8",
185 [L1IMU9_HWID] = "L1IMU9",
186 [L1IMU10_HWID] = "L1IMU10",
187 [L1IMU11_HWID] = "L1IMU11",
188 [L1IMU12_HWID] = "L1IMU12",
189 [L1IMU13_HWID] = "L1IMU13",
190 [L1IMU14_HWID] = "L1IMU14",
191 [L1IMU15_HWID] = "L1IMU15",
192 [WAFLC_HWID] = "WAFLC",
193 [FCH_USB_PD_HWID] = "FCH_USB_PD",
194 [PCIE_HWID] = "PCIE",
195 [PCS_HWID] = "PCS",
196 [DDCL_HWID] = "DDCL",
197 [SST_HWID] = "SST",
198 [IOAGR_HWID] = "IOAGR",
199 [NBIF_HWID] = "NBIF",
200 [IOAPIC_HWID] = "IOAPIC",
201 [SYSTEMHUB_HWID] = "SYSTEMHUB",
202 [NTBCCP_HWID] = "NTBCCP",
203 [UMC_HWID] = "UMC",
204 [SATA_HWID] = "SATA",
205 [USB_HWID] = "USB",
206 [CCXSEC_HWID] = "CCXSEC",
207 [XGMI_HWID] = "XGMI",
208 [XGBE_HWID] = "XGBE",
209 [MP0_HWID] = "MP0",
210 [VPE_HWID] = "VPE",
211 };
212
213 static int hw_id_map[MAX_HWIP] = {
214 [GC_HWIP] = GC_HWID,
215 [HDP_HWIP] = HDP_HWID,
216 [SDMA0_HWIP] = SDMA0_HWID,
217 [SDMA1_HWIP] = SDMA1_HWID,
218 [SDMA2_HWIP] = SDMA2_HWID,
219 [SDMA3_HWIP] = SDMA3_HWID,
220 [LSDMA_HWIP] = LSDMA_HWID,
221 [MMHUB_HWIP] = MMHUB_HWID,
222 [ATHUB_HWIP] = ATHUB_HWID,
223 [NBIO_HWIP] = NBIF_HWID,
224 [MP0_HWIP] = MP0_HWID,
225 [MP1_HWIP] = MP1_HWID,
226 [UVD_HWIP] = UVD_HWID,
227 [VCE_HWIP] = VCE_HWID,
228 [DF_HWIP] = DF_HWID,
229 [DCE_HWIP] = DMU_HWID,
230 [OSSSYS_HWIP] = OSSSYS_HWID,
231 [SMUIO_HWIP] = SMUIO_HWID,
232 [PWR_HWIP] = PWR_HWID,
233 [NBIF_HWIP] = NBIF_HWID,
234 [THM_HWIP] = THM_HWID,
235 [CLK_HWIP] = CLKA_HWID,
236 [UMC_HWIP] = UMC_HWID,
237 [XGMI_HWIP] = XGMI_HWID,
238 [DCI_HWIP] = DCI_HWID,
239 [PCIE_HWIP] = PCIE_HWID,
240 [VPE_HWIP] = VPE_HWID,
241 [ISP_HWIP] = ISP_HWID,
242 };
243
amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device * adev,uint8_t * binary)244 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
245 {
246 u64 tmr_offset, tmr_size, pos;
247 void *discv_regn;
248 int ret;
249
250 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
251 if (ret)
252 return ret;
253
254 pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
255
256 /* This region is read-only and reserved from system use */
257 discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC);
258 if (discv_regn) {
259 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size);
260 memunmap(discv_regn);
261 return 0;
262 }
263
264 return -ENOENT;
265 }
266
267 #define IP_DISCOVERY_V2 2
268 #define IP_DISCOVERY_V4 4
269
amdgpu_discovery_read_binary_from_mem(struct amdgpu_device * adev,uint8_t * binary)270 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
271 uint8_t *binary)
272 {
273 uint64_t vram_size;
274 u32 msg;
275 int i, ret = 0;
276
277 if (!amdgpu_sriov_vf(adev)) {
278 /* It can take up to a second for IFWI init to complete on some dGPUs,
279 * but generally it should be in the 60-100ms range. Normally this starts
280 * as soon as the device gets power so by the time the OS loads this has long
281 * completed. However, when a card is hotplugged via e.g., USB4, we need to
282 * wait for this to complete. Once the C2PMSG is updated, we can
283 * continue.
284 */
285
286 for (i = 0; i < 1000; i++) {
287 msg = RREG32(mmMP0_SMN_C2PMSG_33);
288 if (msg & 0x80000000)
289 break;
290 msleep(1);
291 }
292 }
293
294 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
295
296 if (vram_size) {
297 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
298 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
299 adev->mman.discovery_tmr_size, false);
300 } else {
301 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
302 }
303
304 return ret;
305 }
306
amdgpu_discovery_read_binary_from_file(struct amdgpu_device * adev,uint8_t * binary,const char * fw_name)307 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev,
308 uint8_t *binary,
309 const char *fw_name)
310 {
311 const struct firmware *fw;
312 int r;
313
314 r = request_firmware(&fw, fw_name, adev->dev);
315 if (r) {
316 dev_err(adev->dev, "can't load firmware \"%s\"\n",
317 fw_name);
318 return r;
319 }
320
321 memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
322 release_firmware(fw);
323
324 return 0;
325 }
326
amdgpu_discovery_calculate_checksum(uint8_t * data,uint32_t size)327 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
328 {
329 uint16_t checksum = 0;
330 int i;
331
332 for (i = 0; i < size; i++)
333 checksum += data[i];
334
335 return checksum;
336 }
337
amdgpu_discovery_verify_checksum(uint8_t * data,uint32_t size,uint16_t expected)338 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
339 uint16_t expected)
340 {
341 return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
342 }
343
amdgpu_discovery_verify_binary_signature(uint8_t * binary)344 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
345 {
346 struct binary_header *bhdr;
347 bhdr = (struct binary_header *)binary;
348
349 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
350 }
351
amdgpu_discovery_harvest_config_quirk(struct amdgpu_device * adev)352 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
353 {
354 /*
355 * So far, apply this quirk only on those Navy Flounder boards which
356 * have a bad harvest table of VCN config.
357 */
358 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) &&
359 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) {
360 switch (adev->pdev->revision) {
361 case 0xC1:
362 case 0xC2:
363 case 0xC3:
364 case 0xC5:
365 case 0xC7:
366 case 0xCF:
367 case 0xDF:
368 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
369 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
370 break;
371 default:
372 break;
373 }
374 }
375 }
376
amdgpu_discovery_verify_npsinfo(struct amdgpu_device * adev,struct binary_header * bhdr)377 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev,
378 struct binary_header *bhdr)
379 {
380 struct table_info *info;
381 uint16_t checksum;
382 uint16_t offset;
383
384 info = &bhdr->table_list[NPS_INFO];
385 offset = le16_to_cpu(info->offset);
386 checksum = le16_to_cpu(info->checksum);
387
388 struct nps_info_header *nhdr =
389 (struct nps_info_header *)(adev->mman.discovery_bin + offset);
390
391 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) {
392 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n");
393 return -EINVAL;
394 }
395
396 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
397 le32_to_cpu(nhdr->size_bytes),
398 checksum)) {
399 dev_dbg(adev->dev, "invalid nps info data table checksum\n");
400 return -EINVAL;
401 }
402
403 return 0;
404 }
405
amdgpu_discovery_get_fw_name(struct amdgpu_device * adev)406 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev)
407 {
408 if (amdgpu_discovery == 2)
409 return "amdgpu/ip_discovery.bin";
410
411 switch (adev->asic_type) {
412 case CHIP_VEGA10:
413 return "amdgpu/vega10_ip_discovery.bin";
414 case CHIP_VEGA12:
415 return "amdgpu/vega12_ip_discovery.bin";
416 case CHIP_RAVEN:
417 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
418 return "amdgpu/raven2_ip_discovery.bin";
419 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
420 return "amdgpu/picasso_ip_discovery.bin";
421 else
422 return "amdgpu/raven_ip_discovery.bin";
423 case CHIP_VEGA20:
424 return "amdgpu/vega20_ip_discovery.bin";
425 case CHIP_ARCTURUS:
426 return "amdgpu/arcturus_ip_discovery.bin";
427 case CHIP_ALDEBARAN:
428 return "amdgpu/aldebaran_ip_discovery.bin";
429 default:
430 return NULL;
431 }
432 }
433
amdgpu_discovery_init(struct amdgpu_device * adev)434 static int amdgpu_discovery_init(struct amdgpu_device *adev)
435 {
436 struct table_info *info;
437 struct binary_header *bhdr;
438 const char *fw_name;
439 uint16_t offset;
440 uint16_t size;
441 uint16_t checksum;
442 int r;
443
444 adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
445 adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
446 if (!adev->mman.discovery_bin)
447 return -ENOMEM;
448
449 /* Read from file if it is the preferred option */
450 fw_name = amdgpu_discovery_get_fw_name(adev);
451 if (fw_name != NULL) {
452 dev_info(adev->dev, "use ip discovery information from file");
453 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin, fw_name);
454
455 if (r) {
456 dev_err(adev->dev, "failed to read ip discovery binary from file\n");
457 r = -EINVAL;
458 goto out;
459 }
460
461 } else {
462 r = amdgpu_discovery_read_binary_from_mem(
463 adev, adev->mman.discovery_bin);
464 if (r)
465 goto out;
466 }
467
468 /* check the ip discovery binary signature */
469 if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
470 dev_err(adev->dev,
471 "get invalid ip discovery binary signature\n");
472 r = -EINVAL;
473 goto out;
474 }
475
476 bhdr = (struct binary_header *)adev->mman.discovery_bin;
477
478 offset = offsetof(struct binary_header, binary_checksum) +
479 sizeof(bhdr->binary_checksum);
480 size = le16_to_cpu(bhdr->binary_size) - offset;
481 checksum = le16_to_cpu(bhdr->binary_checksum);
482
483 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
484 size, checksum)) {
485 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
486 r = -EINVAL;
487 goto out;
488 }
489
490 info = &bhdr->table_list[IP_DISCOVERY];
491 offset = le16_to_cpu(info->offset);
492 checksum = le16_to_cpu(info->checksum);
493
494 if (offset) {
495 struct ip_discovery_header *ihdr =
496 (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
497 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
498 dev_err(adev->dev, "invalid ip discovery data table signature\n");
499 r = -EINVAL;
500 goto out;
501 }
502
503 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
504 le16_to_cpu(ihdr->size), checksum)) {
505 dev_err(adev->dev, "invalid ip discovery data table checksum\n");
506 r = -EINVAL;
507 goto out;
508 }
509 }
510
511 info = &bhdr->table_list[GC];
512 offset = le16_to_cpu(info->offset);
513 checksum = le16_to_cpu(info->checksum);
514
515 if (offset) {
516 struct gpu_info_header *ghdr =
517 (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
518
519 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {
520 dev_err(adev->dev, "invalid ip discovery gc table id\n");
521 r = -EINVAL;
522 goto out;
523 }
524
525 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
526 le32_to_cpu(ghdr->size), checksum)) {
527 dev_err(adev->dev, "invalid gc data table checksum\n");
528 r = -EINVAL;
529 goto out;
530 }
531 }
532
533 info = &bhdr->table_list[HARVEST_INFO];
534 offset = le16_to_cpu(info->offset);
535 checksum = le16_to_cpu(info->checksum);
536
537 if (offset) {
538 struct harvest_info_header *hhdr =
539 (struct harvest_info_header *)(adev->mman.discovery_bin + offset);
540
541 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) {
542 dev_err(adev->dev, "invalid ip discovery harvest table signature\n");
543 r = -EINVAL;
544 goto out;
545 }
546
547 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
548 sizeof(struct harvest_table), checksum)) {
549 dev_err(adev->dev, "invalid harvest data table checksum\n");
550 r = -EINVAL;
551 goto out;
552 }
553 }
554
555 info = &bhdr->table_list[VCN_INFO];
556 offset = le16_to_cpu(info->offset);
557 checksum = le16_to_cpu(info->checksum);
558
559 if (offset) {
560 struct vcn_info_header *vhdr =
561 (struct vcn_info_header *)(adev->mman.discovery_bin + offset);
562
563 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) {
564 dev_err(adev->dev, "invalid ip discovery vcn table id\n");
565 r = -EINVAL;
566 goto out;
567 }
568
569 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
570 le32_to_cpu(vhdr->size_bytes), checksum)) {
571 dev_err(adev->dev, "invalid vcn data table checksum\n");
572 r = -EINVAL;
573 goto out;
574 }
575 }
576
577 info = &bhdr->table_list[MALL_INFO];
578 offset = le16_to_cpu(info->offset);
579 checksum = le16_to_cpu(info->checksum);
580
581 if (0 && offset) {
582 struct mall_info_header *mhdr =
583 (struct mall_info_header *)(adev->mman.discovery_bin + offset);
584
585 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) {
586 dev_err(adev->dev, "invalid ip discovery mall table id\n");
587 r = -EINVAL;
588 goto out;
589 }
590
591 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
592 le32_to_cpu(mhdr->size_bytes), checksum)) {
593 dev_err(adev->dev, "invalid mall data table checksum\n");
594 r = -EINVAL;
595 goto out;
596 }
597 }
598
599 return 0;
600
601 out:
602 kfree(adev->mman.discovery_bin);
603 adev->mman.discovery_bin = NULL;
604 if ((amdgpu_discovery != 2) &&
605 (RREG32(mmIP_DISCOVERY_VERSION) == 4))
606 amdgpu_ras_query_boot_status(adev, 4);
607 return r;
608 }
609
610 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
611
amdgpu_discovery_fini(struct amdgpu_device * adev)612 void amdgpu_discovery_fini(struct amdgpu_device *adev)
613 {
614 amdgpu_discovery_sysfs_fini(adev);
615 kfree(adev->mman.discovery_bin);
616 adev->mman.discovery_bin = NULL;
617 }
618
amdgpu_discovery_validate_ip(struct amdgpu_device * adev,uint8_t instance,uint16_t hw_id)619 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev,
620 uint8_t instance, uint16_t hw_id)
621 {
622 if (instance >= HWIP_MAX_INSTANCE) {
623 dev_err(adev->dev,
624 "Unexpected instance_number (%d) from ip discovery blob\n",
625 instance);
626 return -EINVAL;
627 }
628 if (hw_id >= HW_ID_MAX) {
629 dev_err(adev->dev,
630 "Unexpected hw_id (%d) from ip discovery blob\n",
631 hw_id);
632 return -EINVAL;
633 }
634
635 return 0;
636 }
637
amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device * adev,uint32_t * vcn_harvest_count)638 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
639 uint32_t *vcn_harvest_count)
640 {
641 struct binary_header *bhdr;
642 struct ip_discovery_header *ihdr;
643 struct die_header *dhdr;
644 struct ip *ip;
645 uint16_t die_offset, ip_offset, num_dies, num_ips;
646 uint16_t hw_id;
647 uint8_t inst;
648 int i, j;
649
650 bhdr = (struct binary_header *)adev->mman.discovery_bin;
651 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
652 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
653 num_dies = le16_to_cpu(ihdr->num_dies);
654
655 /* scan harvest bit of all IP data structures */
656 for (i = 0; i < num_dies; i++) {
657 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
658 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
659 num_ips = le16_to_cpu(dhdr->num_ips);
660 ip_offset = die_offset + sizeof(*dhdr);
661
662 for (j = 0; j < num_ips; j++) {
663 ip = (struct ip *)(adev->mman.discovery_bin +
664 ip_offset);
665 inst = ip->number_instance;
666 hw_id = le16_to_cpu(ip->hw_id);
667 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
668 goto next_ip;
669
670 if (ip->harvest == 1) {
671 switch (hw_id) {
672 case VCN_HWID:
673 (*vcn_harvest_count)++;
674 if (inst == 0) {
675 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
676 adev->vcn.inst_mask &=
677 ~AMDGPU_VCN_HARVEST_VCN0;
678 adev->jpeg.inst_mask &=
679 ~AMDGPU_VCN_HARVEST_VCN0;
680 } else {
681 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
682 adev->vcn.inst_mask &=
683 ~AMDGPU_VCN_HARVEST_VCN1;
684 adev->jpeg.inst_mask &=
685 ~AMDGPU_VCN_HARVEST_VCN1;
686 }
687 break;
688 case DMU_HWID:
689 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
690 break;
691 default:
692 break;
693 }
694 }
695 next_ip:
696 ip_offset += struct_size(ip, base_address,
697 ip->num_base_address);
698 }
699 }
700 }
701
amdgpu_discovery_read_from_harvest_table(struct amdgpu_device * adev,uint32_t * vcn_harvest_count,uint32_t * umc_harvest_count)702 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
703 uint32_t *vcn_harvest_count,
704 uint32_t *umc_harvest_count)
705 {
706 struct binary_header *bhdr;
707 struct harvest_table *harvest_info;
708 u16 offset;
709 int i;
710 uint32_t umc_harvest_config = 0;
711
712 bhdr = (struct binary_header *)adev->mman.discovery_bin;
713 offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
714
715 if (!offset) {
716 dev_err(adev->dev, "invalid harvest table offset\n");
717 return;
718 }
719
720 harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset);
721
722 for (i = 0; i < 32; i++) {
723 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
724 break;
725
726 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
727 case VCN_HWID:
728 (*vcn_harvest_count)++;
729 adev->vcn.harvest_config |=
730 (1 << harvest_info->list[i].number_instance);
731 adev->jpeg.harvest_config |=
732 (1 << harvest_info->list[i].number_instance);
733
734 adev->vcn.inst_mask &=
735 ~(1U << harvest_info->list[i].number_instance);
736 adev->jpeg.inst_mask &=
737 ~(1U << harvest_info->list[i].number_instance);
738 break;
739 case DMU_HWID:
740 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
741 break;
742 case UMC_HWID:
743 umc_harvest_config |=
744 1 << (le16_to_cpu(harvest_info->list[i].number_instance));
745 (*umc_harvest_count)++;
746 break;
747 case GC_HWID:
748 adev->gfx.xcc_mask &=
749 ~(1U << harvest_info->list[i].number_instance);
750 break;
751 case SDMA0_HWID:
752 adev->sdma.sdma_mask &=
753 ~(1U << harvest_info->list[i].number_instance);
754 break;
755 #if defined(CONFIG_DRM_AMD_ISP)
756 case ISP_HWID:
757 adev->isp.harvest_config |=
758 ~(1U << harvest_info->list[i].number_instance);
759 break;
760 #endif
761 default:
762 break;
763 }
764 }
765
766 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
767 ~umc_harvest_config;
768 }
769
770 /* ================================================== */
771
772 struct ip_hw_instance {
773 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
774
775 int hw_id;
776 u8 num_instance;
777 u8 major, minor, revision;
778 u8 harvest;
779
780 int num_base_addresses;
781 u32 base_addr[] __counted_by(num_base_addresses);
782 };
783
784 struct ip_hw_id {
785 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
786 int hw_id;
787 };
788
789 struct ip_die_entry {
790 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
791 u16 num_ips;
792 };
793
794 /* -------------------------------------------------- */
795
796 struct ip_hw_instance_attr {
797 struct attribute attr;
798 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
799 };
800
hw_id_show(struct ip_hw_instance * ip_hw_instance,char * buf)801 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
802 {
803 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
804 }
805
num_instance_show(struct ip_hw_instance * ip_hw_instance,char * buf)806 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
807 {
808 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
809 }
810
major_show(struct ip_hw_instance * ip_hw_instance,char * buf)811 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
812 {
813 return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
814 }
815
minor_show(struct ip_hw_instance * ip_hw_instance,char * buf)816 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
817 {
818 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
819 }
820
revision_show(struct ip_hw_instance * ip_hw_instance,char * buf)821 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
822 {
823 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
824 }
825
harvest_show(struct ip_hw_instance * ip_hw_instance,char * buf)826 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
827 {
828 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
829 }
830
num_base_addresses_show(struct ip_hw_instance * ip_hw_instance,char * buf)831 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
832 {
833 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
834 }
835
base_addr_show(struct ip_hw_instance * ip_hw_instance,char * buf)836 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
837 {
838 ssize_t res, at;
839 int ii;
840
841 for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
842 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
843 */
844 if (at + 12 > PAGE_SIZE)
845 break;
846 res = sysfs_emit_at(buf, at, "0x%08X\n",
847 ip_hw_instance->base_addr[ii]);
848 if (res <= 0)
849 break;
850 at += res;
851 }
852
853 return res < 0 ? res : at;
854 }
855
856 static struct ip_hw_instance_attr ip_hw_attr[] = {
857 __ATTR_RO(hw_id),
858 __ATTR_RO(num_instance),
859 __ATTR_RO(major),
860 __ATTR_RO(minor),
861 __ATTR_RO(revision),
862 __ATTR_RO(harvest),
863 __ATTR_RO(num_base_addresses),
864 __ATTR_RO(base_addr),
865 };
866
867 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
868 ATTRIBUTE_GROUPS(ip_hw_instance);
869
870 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
871 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
872
ip_hw_instance_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)873 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
874 struct attribute *attr,
875 char *buf)
876 {
877 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
878 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
879
880 if (!ip_hw_attr->show)
881 return -EIO;
882
883 return ip_hw_attr->show(ip_hw_instance, buf);
884 }
885
886 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
887 .show = ip_hw_instance_attr_show,
888 };
889
ip_hw_instance_release(struct kobject * kobj)890 static void ip_hw_instance_release(struct kobject *kobj)
891 {
892 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
893
894 kfree(ip_hw_instance);
895 }
896
897 static const struct kobj_type ip_hw_instance_ktype = {
898 .release = ip_hw_instance_release,
899 .sysfs_ops = &ip_hw_instance_sysfs_ops,
900 .default_groups = ip_hw_instance_groups,
901 };
902
903 /* -------------------------------------------------- */
904
905 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
906
ip_hw_id_release(struct kobject * kobj)907 static void ip_hw_id_release(struct kobject *kobj)
908 {
909 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
910
911 if (!list_empty(&ip_hw_id->hw_id_kset.list))
912 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
913 kfree(ip_hw_id);
914 }
915
916 static const struct kobj_type ip_hw_id_ktype = {
917 .release = ip_hw_id_release,
918 .sysfs_ops = &kobj_sysfs_ops,
919 };
920
921 /* -------------------------------------------------- */
922
923 static void die_kobj_release(struct kobject *kobj);
924 static void ip_disc_release(struct kobject *kobj);
925
926 struct ip_die_entry_attribute {
927 struct attribute attr;
928 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
929 };
930
931 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
932
num_ips_show(struct ip_die_entry * ip_die_entry,char * buf)933 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
934 {
935 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
936 }
937
938 /* If there are more ip_die_entry attrs, other than the number of IPs,
939 * we can make this intro an array of attrs, and then initialize
940 * ip_die_entry_attrs in a loop.
941 */
942 static struct ip_die_entry_attribute num_ips_attr =
943 __ATTR_RO(num_ips);
944
945 static struct attribute *ip_die_entry_attrs[] = {
946 &num_ips_attr.attr,
947 NULL,
948 };
949 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
950
951 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
952
ip_die_entry_attr_show(struct kobject * kobj,struct attribute * attr,char * buf)953 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
954 struct attribute *attr,
955 char *buf)
956 {
957 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
958 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
959
960 if (!ip_die_entry_attr->show)
961 return -EIO;
962
963 return ip_die_entry_attr->show(ip_die_entry, buf);
964 }
965
ip_die_entry_release(struct kobject * kobj)966 static void ip_die_entry_release(struct kobject *kobj)
967 {
968 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
969
970 if (!list_empty(&ip_die_entry->ip_kset.list))
971 DRM_ERROR("ip_die_entry->ip_kset is not empty");
972 kfree(ip_die_entry);
973 }
974
975 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
976 .show = ip_die_entry_attr_show,
977 };
978
979 static const struct kobj_type ip_die_entry_ktype = {
980 .release = ip_die_entry_release,
981 .sysfs_ops = &ip_die_entry_sysfs_ops,
982 .default_groups = ip_die_entry_groups,
983 };
984
985 static const struct kobj_type die_kobj_ktype = {
986 .release = die_kobj_release,
987 .sysfs_ops = &kobj_sysfs_ops,
988 };
989
990 static const struct kobj_type ip_discovery_ktype = {
991 .release = ip_disc_release,
992 .sysfs_ops = &kobj_sysfs_ops,
993 };
994
995 struct ip_discovery_top {
996 struct kobject kobj; /* ip_discovery/ */
997 struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */
998 struct amdgpu_device *adev;
999 };
1000
die_kobj_release(struct kobject * kobj)1001 static void die_kobj_release(struct kobject *kobj)
1002 {
1003 struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
1004 struct ip_discovery_top,
1005 die_kset);
1006 if (!list_empty(&ip_top->die_kset.list))
1007 DRM_ERROR("ip_top->die_kset is not empty");
1008 }
1009
ip_disc_release(struct kobject * kobj)1010 static void ip_disc_release(struct kobject *kobj)
1011 {
1012 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
1013 kobj);
1014 struct amdgpu_device *adev = ip_top->adev;
1015
1016 adev->ip_top = NULL;
1017 kfree(ip_top);
1018 }
1019
amdgpu_discovery_get_harvest_info(struct amdgpu_device * adev,uint16_t hw_id,uint8_t inst)1020 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
1021 uint16_t hw_id, uint8_t inst)
1022 {
1023 uint8_t harvest = 0;
1024
1025 /* Until a uniform way is figured, get mask based on hwid */
1026 switch (hw_id) {
1027 case VCN_HWID:
1028 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
1029 break;
1030 case DMU_HWID:
1031 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
1032 harvest = 0x1;
1033 break;
1034 case UMC_HWID:
1035 /* TODO: It needs another parsing; for now, ignore.*/
1036 break;
1037 case GC_HWID:
1038 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1039 break;
1040 case SDMA0_HWID:
1041 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
1042 break;
1043 default:
1044 break;
1045 }
1046
1047 return harvest;
1048 }
1049
amdgpu_discovery_sysfs_ips(struct amdgpu_device * adev,struct ip_die_entry * ip_die_entry,const size_t _ip_offset,const int num_ips,bool reg_base_64)1050 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
1051 struct ip_die_entry *ip_die_entry,
1052 const size_t _ip_offset, const int num_ips,
1053 bool reg_base_64)
1054 {
1055 int ii, jj, kk, res;
1056 uint16_t hw_id;
1057 uint8_t inst;
1058
1059 DRM_DEBUG("num_ips:%d", num_ips);
1060
1061 /* Find all IPs of a given HW ID, and add their instance to
1062 * #die/#hw_id/#instance/<attributes>
1063 */
1064 for (ii = 0; ii < HW_ID_MAX; ii++) {
1065 struct ip_hw_id *ip_hw_id = NULL;
1066 size_t ip_offset = _ip_offset;
1067
1068 for (jj = 0; jj < num_ips; jj++) {
1069 struct ip_v4 *ip;
1070 struct ip_hw_instance *ip_hw_instance;
1071
1072 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1073 inst = ip->instance_number;
1074 hw_id = le16_to_cpu(ip->hw_id);
1075 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) ||
1076 hw_id != ii)
1077 goto next_ip;
1078
1079 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
1080
1081 /* We have a hw_id match; register the hw
1082 * block if not yet registered.
1083 */
1084 if (!ip_hw_id) {
1085 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
1086 if (!ip_hw_id)
1087 return -ENOMEM;
1088 ip_hw_id->hw_id = ii;
1089
1090 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
1091 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
1092 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
1093 res = kset_register(&ip_hw_id->hw_id_kset);
1094 if (res) {
1095 DRM_ERROR("Couldn't register ip_hw_id kset");
1096 kfree(ip_hw_id);
1097 return res;
1098 }
1099 if (hw_id_names[ii]) {
1100 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
1101 &ip_hw_id->hw_id_kset.kobj,
1102 hw_id_names[ii]);
1103 if (res) {
1104 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
1105 hw_id_names[ii],
1106 kobject_name(&ip_die_entry->ip_kset.kobj));
1107 }
1108 }
1109 }
1110
1111 /* Now register its instance.
1112 */
1113 ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
1114 base_addr,
1115 ip->num_base_address),
1116 GFP_KERNEL);
1117 if (!ip_hw_instance) {
1118 DRM_ERROR("no memory for ip_hw_instance");
1119 return -ENOMEM;
1120 }
1121 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
1122 ip_hw_instance->num_instance = ip->instance_number;
1123 ip_hw_instance->major = ip->major;
1124 ip_hw_instance->minor = ip->minor;
1125 ip_hw_instance->revision = ip->revision;
1126 ip_hw_instance->harvest =
1127 amdgpu_discovery_get_harvest_info(
1128 adev, ip_hw_instance->hw_id,
1129 ip_hw_instance->num_instance);
1130 ip_hw_instance->num_base_addresses = ip->num_base_address;
1131
1132 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1133 if (reg_base_64)
1134 ip_hw_instance->base_addr[kk] =
1135 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1136 else
1137 ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1138 }
1139
1140 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1141 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1142 res = kobject_add(&ip_hw_instance->kobj, NULL,
1143 "%d", ip_hw_instance->num_instance);
1144 next_ip:
1145 if (reg_base_64)
1146 ip_offset += struct_size(ip, base_address_64,
1147 ip->num_base_address);
1148 else
1149 ip_offset += struct_size(ip, base_address,
1150 ip->num_base_address);
1151 }
1152 }
1153
1154 return 0;
1155 }
1156
amdgpu_discovery_sysfs_recurse(struct amdgpu_device * adev)1157 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
1158 {
1159 struct binary_header *bhdr;
1160 struct ip_discovery_header *ihdr;
1161 struct die_header *dhdr;
1162 struct kset *die_kset = &adev->ip_top->die_kset;
1163 u16 num_dies, die_offset, num_ips;
1164 size_t ip_offset;
1165 int ii, res;
1166
1167 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1168 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1169 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1170 num_dies = le16_to_cpu(ihdr->num_dies);
1171
1172 DRM_DEBUG("number of dies: %d\n", num_dies);
1173
1174 for (ii = 0; ii < num_dies; ii++) {
1175 struct ip_die_entry *ip_die_entry;
1176
1177 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1178 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1179 num_ips = le16_to_cpu(dhdr->num_ips);
1180 ip_offset = die_offset + sizeof(*dhdr);
1181
1182 /* Add the die to the kset.
1183 *
1184 * dhdr->die_id == ii, which was checked in
1185 * amdgpu_discovery_reg_base_init().
1186 */
1187
1188 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
1189 if (!ip_die_entry)
1190 return -ENOMEM;
1191
1192 ip_die_entry->num_ips = num_ips;
1193
1194 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1195 ip_die_entry->ip_kset.kobj.kset = die_kset;
1196 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1197 res = kset_register(&ip_die_entry->ip_kset);
1198 if (res) {
1199 DRM_ERROR("Couldn't register ip_die_entry kset");
1200 kfree(ip_die_entry);
1201 return res;
1202 }
1203
1204 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit);
1205 }
1206
1207 return 0;
1208 }
1209
amdgpu_discovery_sysfs_init(struct amdgpu_device * adev)1210 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1211 {
1212 struct kset *die_kset;
1213 int res, ii;
1214
1215 if (!adev->mman.discovery_bin)
1216 return -EINVAL;
1217
1218 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
1219 if (!adev->ip_top)
1220 return -ENOMEM;
1221
1222 adev->ip_top->adev = adev;
1223
1224 res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
1225 &adev->dev->kobj, "ip_discovery");
1226 if (res) {
1227 DRM_ERROR("Couldn't init and add ip_discovery/");
1228 goto Err;
1229 }
1230
1231 die_kset = &adev->ip_top->die_kset;
1232 kobject_set_name(&die_kset->kobj, "%s", "die");
1233 die_kset->kobj.parent = &adev->ip_top->kobj;
1234 die_kset->kobj.ktype = &die_kobj_ktype;
1235 res = kset_register(&adev->ip_top->die_kset);
1236 if (res) {
1237 DRM_ERROR("Couldn't register die_kset");
1238 goto Err;
1239 }
1240
1241 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1242 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1243 ip_hw_instance_attrs[ii] = NULL;
1244
1245 res = amdgpu_discovery_sysfs_recurse(adev);
1246
1247 return res;
1248 Err:
1249 kobject_put(&adev->ip_top->kobj);
1250 return res;
1251 }
1252
1253 /* -------------------------------------------------- */
1254
1255 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1256
amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id * ip_hw_id)1257 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1258 {
1259 struct list_head *el, *tmp;
1260 struct kset *hw_id_kset;
1261
1262 hw_id_kset = &ip_hw_id->hw_id_kset;
1263 spin_lock(&hw_id_kset->list_lock);
1264 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1265 list_del_init(el);
1266 spin_unlock(&hw_id_kset->list_lock);
1267 /* kobject is embedded in ip_hw_instance */
1268 kobject_put(list_to_kobj(el));
1269 spin_lock(&hw_id_kset->list_lock);
1270 }
1271 spin_unlock(&hw_id_kset->list_lock);
1272 kobject_put(&ip_hw_id->hw_id_kset.kobj);
1273 }
1274
amdgpu_discovery_sysfs_die_free(struct ip_die_entry * ip_die_entry)1275 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1276 {
1277 struct list_head *el, *tmp;
1278 struct kset *ip_kset;
1279
1280 ip_kset = &ip_die_entry->ip_kset;
1281 spin_lock(&ip_kset->list_lock);
1282 list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1283 list_del_init(el);
1284 spin_unlock(&ip_kset->list_lock);
1285 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1286 spin_lock(&ip_kset->list_lock);
1287 }
1288 spin_unlock(&ip_kset->list_lock);
1289 kobject_put(&ip_die_entry->ip_kset.kobj);
1290 }
1291
amdgpu_discovery_sysfs_fini(struct amdgpu_device * adev)1292 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1293 {
1294 struct list_head *el, *tmp;
1295 struct kset *die_kset;
1296
1297 die_kset = &adev->ip_top->die_kset;
1298 spin_lock(&die_kset->list_lock);
1299 list_for_each_prev_safe(el, tmp, &die_kset->list) {
1300 list_del_init(el);
1301 spin_unlock(&die_kset->list_lock);
1302 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1303 spin_lock(&die_kset->list_lock);
1304 }
1305 spin_unlock(&die_kset->list_lock);
1306 kobject_put(&adev->ip_top->die_kset.kobj);
1307 kobject_put(&adev->ip_top->kobj);
1308 }
1309
1310 /* ================================================== */
1311
amdgpu_discovery_reg_base_init(struct amdgpu_device * adev)1312 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1313 {
1314 uint8_t num_base_address, subrev, variant;
1315 struct binary_header *bhdr;
1316 struct ip_discovery_header *ihdr;
1317 struct die_header *dhdr;
1318 struct ip_v4 *ip;
1319 uint16_t die_offset;
1320 uint16_t ip_offset;
1321 uint16_t num_dies;
1322 uint32_t wafl_ver;
1323 uint16_t num_ips;
1324 uint16_t hw_id;
1325 uint8_t inst;
1326 int hw_ip;
1327 int i, j, k;
1328 int r;
1329
1330 r = amdgpu_discovery_init(adev);
1331 if (r) {
1332 DRM_ERROR("amdgpu_discovery_init failed\n");
1333 return r;
1334 }
1335
1336 wafl_ver = 0;
1337 adev->gfx.xcc_mask = 0;
1338 adev->sdma.sdma_mask = 0;
1339 adev->vcn.inst_mask = 0;
1340 adev->jpeg.inst_mask = 0;
1341 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1342 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1343 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1344 num_dies = le16_to_cpu(ihdr->num_dies);
1345
1346 DRM_DEBUG("number of dies: %d\n", num_dies);
1347
1348 for (i = 0; i < num_dies; i++) {
1349 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1350 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1351 num_ips = le16_to_cpu(dhdr->num_ips);
1352 ip_offset = die_offset + sizeof(*dhdr);
1353
1354 if (le16_to_cpu(dhdr->die_id) != i) {
1355 DRM_ERROR("invalid die id %d, expected %d\n",
1356 le16_to_cpu(dhdr->die_id), i);
1357 return -EINVAL;
1358 }
1359
1360 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1361 le16_to_cpu(dhdr->die_id), num_ips);
1362
1363 for (j = 0; j < num_ips; j++) {
1364 ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1365
1366 inst = ip->instance_number;
1367 hw_id = le16_to_cpu(ip->hw_id);
1368 if (amdgpu_discovery_validate_ip(adev, inst, hw_id))
1369 goto next_ip;
1370
1371 num_base_address = ip->num_base_address;
1372
1373 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1374 hw_id_names[le16_to_cpu(ip->hw_id)],
1375 le16_to_cpu(ip->hw_id),
1376 ip->instance_number,
1377 ip->major, ip->minor,
1378 ip->revision);
1379
1380 if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1381 /* Bit [5:0]: original revision value
1382 * Bit [7:6]: en/decode capability:
1383 * 0b00 : VCN function normally
1384 * 0b10 : encode is disabled
1385 * 0b01 : decode is disabled
1386 */
1387 if (adev->vcn.num_vcn_inst <
1388 AMDGPU_MAX_VCN_INSTANCES) {
1389 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
1390 ip->revision & 0xc0;
1391 adev->vcn.num_vcn_inst++;
1392 adev->vcn.inst_mask |=
1393 (1U << ip->instance_number);
1394 adev->jpeg.inst_mask |=
1395 (1U << ip->instance_number);
1396 } else {
1397 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1398 adev->vcn.num_vcn_inst + 1,
1399 AMDGPU_MAX_VCN_INSTANCES);
1400 }
1401 ip->revision &= ~0xc0;
1402 }
1403 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1404 le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1405 le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1406 le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1407 if (adev->sdma.num_instances <
1408 AMDGPU_MAX_SDMA_INSTANCES) {
1409 adev->sdma.num_instances++;
1410 adev->sdma.sdma_mask |=
1411 (1U << ip->instance_number);
1412 } else {
1413 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1414 adev->sdma.num_instances + 1,
1415 AMDGPU_MAX_SDMA_INSTANCES);
1416 }
1417 }
1418
1419 if (le16_to_cpu(ip->hw_id) == VPE_HWID) {
1420 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES)
1421 adev->vpe.num_instances++;
1422 else
1423 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n",
1424 adev->vpe.num_instances + 1,
1425 AMDGPU_MAX_VPE_INSTANCES);
1426 }
1427
1428 if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1429 adev->gmc.num_umc++;
1430 adev->umc.node_inst_num++;
1431 }
1432
1433 if (le16_to_cpu(ip->hw_id) == GC_HWID)
1434 adev->gfx.xcc_mask |=
1435 (1U << ip->instance_number);
1436
1437 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID)
1438 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor,
1439 ip->revision, 0, 0);
1440
1441 for (k = 0; k < num_base_address; k++) {
1442 /*
1443 * convert the endianness of base addresses in place,
1444 * so that we don't need to convert them when accessing adev->reg_offset.
1445 */
1446 if (ihdr->base_addr_64_bit)
1447 /* Truncate the 64bit base address from ip discovery
1448 * and only store lower 32bit ip base in reg_offset[].
1449 * Bits > 32 follows ASIC specific format, thus just
1450 * discard them and handle it within specific ASIC.
1451 * By this way reg_offset[] and related helpers can
1452 * stay unchanged.
1453 * The base address is in dwords, thus clear the
1454 * highest 2 bits to store.
1455 */
1456 ip->base_address[k] =
1457 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1458 else
1459 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1460 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1461 }
1462
1463 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1464 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1465 hw_id_map[hw_ip] != 0) {
1466 DRM_DEBUG("set register base offset for %s\n",
1467 hw_id_names[le16_to_cpu(ip->hw_id)]);
1468 adev->reg_offset[hw_ip][ip->instance_number] =
1469 ip->base_address;
1470 /* Instance support is somewhat inconsistent.
1471 * SDMA is a good example. Sienna cichlid has 4 total
1472 * SDMA instances, each enumerated separately (HWIDs
1473 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances,
1474 * but they are enumerated as multiple instances of the
1475 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another
1476 * example. On most chips there are multiple instances
1477 * with the same HWID.
1478 */
1479
1480 if (ihdr->version < 3) {
1481 subrev = 0;
1482 variant = 0;
1483 } else {
1484 subrev = ip->sub_revision;
1485 variant = ip->variant;
1486 }
1487
1488 adev->ip_versions[hw_ip]
1489 [ip->instance_number] =
1490 IP_VERSION_FULL(ip->major,
1491 ip->minor,
1492 ip->revision,
1493 variant,
1494 subrev);
1495 }
1496 }
1497
1498 next_ip:
1499 if (ihdr->base_addr_64_bit)
1500 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1501 else
1502 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1503 }
1504 }
1505
1506 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0])
1507 adev->ip_versions[XGMI_HWIP][0] = wafl_ver;
1508
1509 return 0;
1510 }
1511
amdgpu_discovery_harvest_ip(struct amdgpu_device * adev)1512 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1513 {
1514 struct ip_discovery_header *ihdr;
1515 struct binary_header *bhdr;
1516 int vcn_harvest_count = 0;
1517 int umc_harvest_count = 0;
1518 uint16_t offset, ihdr_ver;
1519
1520 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1521 offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset);
1522 ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1523 offset);
1524 ihdr_ver = le16_to_cpu(ihdr->version);
1525 /*
1526 * Harvest table does not fit Navi1x and legacy GPUs,
1527 * so read harvest bit per IP data structure to set
1528 * harvest configuration.
1529 */
1530 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) &&
1531 ihdr_ver <= 2) {
1532 if ((adev->pdev->device == 0x731E &&
1533 (adev->pdev->revision == 0xC6 ||
1534 adev->pdev->revision == 0xC7)) ||
1535 (adev->pdev->device == 0x7340 &&
1536 adev->pdev->revision == 0xC9) ||
1537 (adev->pdev->device == 0x7360 &&
1538 adev->pdev->revision == 0xC7))
1539 amdgpu_discovery_read_harvest_bit_per_ip(adev,
1540 &vcn_harvest_count);
1541 } else {
1542 amdgpu_discovery_read_from_harvest_table(adev,
1543 &vcn_harvest_count,
1544 &umc_harvest_count);
1545 }
1546
1547 amdgpu_discovery_harvest_config_quirk(adev);
1548
1549 if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1550 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1551 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1552 }
1553
1554 if (umc_harvest_count < adev->gmc.num_umc) {
1555 adev->gmc.num_umc -= umc_harvest_count;
1556 }
1557 }
1558
1559 union gc_info {
1560 struct gc_info_v1_0 v1;
1561 struct gc_info_v1_1 v1_1;
1562 struct gc_info_v1_2 v1_2;
1563 struct gc_info_v1_3 v1_3;
1564 struct gc_info_v2_0 v2;
1565 struct gc_info_v2_1 v2_1;
1566 };
1567
amdgpu_discovery_get_gfx_info(struct amdgpu_device * adev)1568 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1569 {
1570 struct binary_header *bhdr;
1571 union gc_info *gc_info;
1572 u16 offset;
1573
1574 if (!adev->mman.discovery_bin) {
1575 DRM_ERROR("ip discovery uninitialized\n");
1576 return -EINVAL;
1577 }
1578
1579 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1580 offset = le16_to_cpu(bhdr->table_list[GC].offset);
1581
1582 if (!offset)
1583 return 0;
1584
1585 gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
1586
1587 switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1588 case 1:
1589 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1590 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1591 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1592 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1593 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1594 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1595 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1596 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1597 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1598 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1599 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1600 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1601 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1602 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1603 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1604 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1605 le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1606 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1607 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) {
1608 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1609 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1610 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1611 }
1612 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) {
1613 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1614 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1615 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1616 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1617 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1618 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1619 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1620 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1621 }
1622 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) {
1623 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu);
1624 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size);
1625 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc);
1626 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size);
1627 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc);
1628 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size);
1629 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size);
1630 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size);
1631 }
1632 break;
1633 case 2:
1634 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1635 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1636 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1637 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1638 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1639 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1640 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1641 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1642 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1643 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1644 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1645 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1646 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1647 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1648 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1649 le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1650 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1651 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) {
1652 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh);
1653 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu);
1654 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */
1655 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc);
1656 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc);
1657 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc);
1658 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */
1659 }
1660 break;
1661 default:
1662 dev_err(adev->dev,
1663 "Unhandled GC info table %d.%d\n",
1664 le16_to_cpu(gc_info->v1.header.version_major),
1665 le16_to_cpu(gc_info->v1.header.version_minor));
1666 return -EINVAL;
1667 }
1668 return 0;
1669 }
1670
1671 union mall_info {
1672 struct mall_info_v1_0 v1;
1673 struct mall_info_v2_0 v2;
1674 };
1675
amdgpu_discovery_get_mall_info(struct amdgpu_device * adev)1676 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1677 {
1678 struct binary_header *bhdr;
1679 union mall_info *mall_info;
1680 u32 u, mall_size_per_umc, m_s_present, half_use;
1681 u64 mall_size;
1682 u16 offset;
1683
1684 if (!adev->mman.discovery_bin) {
1685 DRM_ERROR("ip discovery uninitialized\n");
1686 return -EINVAL;
1687 }
1688
1689 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1690 offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
1691
1692 if (!offset)
1693 return 0;
1694
1695 mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
1696
1697 switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1698 case 1:
1699 mall_size = 0;
1700 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1701 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1702 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1703 for (u = 0; u < adev->gmc.num_umc; u++) {
1704 if (m_s_present & (1 << u))
1705 mall_size += mall_size_per_umc * 2;
1706 else if (half_use & (1 << u))
1707 mall_size += mall_size_per_umc / 2;
1708 else
1709 mall_size += mall_size_per_umc;
1710 }
1711 adev->gmc.mall_size = mall_size;
1712 adev->gmc.m_half_use = half_use;
1713 break;
1714 case 2:
1715 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
1716 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc;
1717 break;
1718 default:
1719 dev_err(adev->dev,
1720 "Unhandled MALL info table %d.%d\n",
1721 le16_to_cpu(mall_info->v1.header.version_major),
1722 le16_to_cpu(mall_info->v1.header.version_minor));
1723 return -EINVAL;
1724 }
1725 return 0;
1726 }
1727
1728 union vcn_info {
1729 struct vcn_info_v1_0 v1;
1730 };
1731
amdgpu_discovery_get_vcn_info(struct amdgpu_device * adev)1732 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1733 {
1734 struct binary_header *bhdr;
1735 union vcn_info *vcn_info;
1736 u16 offset;
1737 int v;
1738
1739 if (!adev->mman.discovery_bin) {
1740 DRM_ERROR("ip discovery uninitialized\n");
1741 return -EINVAL;
1742 }
1743
1744 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1745 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
1746 * but that may change in the future with new GPUs so keep this
1747 * check for defensive purposes.
1748 */
1749 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1750 dev_err(adev->dev, "invalid vcn instances\n");
1751 return -EINVAL;
1752 }
1753
1754 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1755 offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
1756
1757 if (!offset)
1758 return 0;
1759
1760 vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
1761
1762 switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1763 case 1:
1764 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1765 * so this won't overflow.
1766 */
1767 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1768 adev->vcn.inst[v].vcn_codec_disable_mask =
1769 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1770 }
1771 break;
1772 default:
1773 dev_err(adev->dev,
1774 "Unhandled VCN info table %d.%d\n",
1775 le16_to_cpu(vcn_info->v1.header.version_major),
1776 le16_to_cpu(vcn_info->v1.header.version_minor));
1777 return -EINVAL;
1778 }
1779 return 0;
1780 }
1781
1782 union nps_info {
1783 struct nps_info_v1_0 v1;
1784 };
1785
amdgpu_discovery_refresh_nps_info(struct amdgpu_device * adev,union nps_info * nps_data)1786 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev,
1787 union nps_info *nps_data)
1788 {
1789 uint64_t vram_size, pos, offset;
1790 struct nps_info_header *nhdr;
1791 struct binary_header bhdr;
1792 uint16_t checksum;
1793
1794 vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
1795 pos = vram_size - DISCOVERY_TMR_OFFSET;
1796 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
1797
1798 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset);
1799 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum);
1800
1801 amdgpu_device_vram_access(adev, (pos + offset), nps_data,
1802 sizeof(*nps_data), false);
1803
1804 nhdr = (struct nps_info_header *)(nps_data);
1805 if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data,
1806 le32_to_cpu(nhdr->size_bytes),
1807 checksum)) {
1808 dev_err(adev->dev, "nps data refresh, checksum mismatch\n");
1809 return -EINVAL;
1810 }
1811
1812 return 0;
1813 }
1814
amdgpu_discovery_get_nps_info(struct amdgpu_device * adev,uint32_t * nps_type,struct amdgpu_gmc_memrange ** ranges,int * range_cnt,bool refresh)1815 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
1816 uint32_t *nps_type,
1817 struct amdgpu_gmc_memrange **ranges,
1818 int *range_cnt, bool refresh)
1819 {
1820 struct amdgpu_gmc_memrange *mem_ranges;
1821 struct binary_header *bhdr;
1822 union nps_info *nps_info;
1823 union nps_info nps_data;
1824 u16 offset;
1825 int i, r;
1826
1827 if (!nps_type || !range_cnt || !ranges)
1828 return -EINVAL;
1829
1830 if (refresh) {
1831 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data);
1832 if (r)
1833 return r;
1834 nps_info = &nps_data;
1835 } else {
1836 if (!adev->mman.discovery_bin) {
1837 dev_err(adev->dev,
1838 "fetch mem range failed, ip discovery uninitialized\n");
1839 return -EINVAL;
1840 }
1841
1842 bhdr = (struct binary_header *)adev->mman.discovery_bin;
1843 offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset);
1844
1845 if (!offset)
1846 return -ENOENT;
1847
1848 /* If verification fails, return as if NPS table doesn't exist */
1849 if (amdgpu_discovery_verify_npsinfo(adev, bhdr))
1850 return -ENOENT;
1851
1852 nps_info =
1853 (union nps_info *)(adev->mman.discovery_bin + offset);
1854 }
1855
1856 switch (le16_to_cpu(nps_info->v1.header.version_major)) {
1857 case 1:
1858 mem_ranges = kvcalloc(nps_info->v1.count,
1859 sizeof(*mem_ranges),
1860 GFP_KERNEL);
1861 if (!mem_ranges)
1862 return -ENOMEM;
1863 *nps_type = nps_info->v1.nps_type;
1864 *range_cnt = nps_info->v1.count;
1865 for (i = 0; i < *range_cnt; i++) {
1866 mem_ranges[i].base_address =
1867 nps_info->v1.instance_info[i].base_address;
1868 mem_ranges[i].limit_address =
1869 nps_info->v1.instance_info[i].limit_address;
1870 mem_ranges[i].nid_mask = -1;
1871 mem_ranges[i].flags = 0;
1872 }
1873 *ranges = mem_ranges;
1874 break;
1875 default:
1876 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n",
1877 le16_to_cpu(nps_info->v1.header.version_major),
1878 le16_to_cpu(nps_info->v1.header.version_minor));
1879 return -EINVAL;
1880 }
1881
1882 return 0;
1883 }
1884
amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device * adev)1885 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1886 {
1887 /* what IP to use for this? */
1888 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1889 case IP_VERSION(9, 0, 1):
1890 case IP_VERSION(9, 1, 0):
1891 case IP_VERSION(9, 2, 1):
1892 case IP_VERSION(9, 2, 2):
1893 case IP_VERSION(9, 3, 0):
1894 case IP_VERSION(9, 4, 0):
1895 case IP_VERSION(9, 4, 1):
1896 case IP_VERSION(9, 4, 2):
1897 case IP_VERSION(9, 4, 3):
1898 case IP_VERSION(9, 4, 4):
1899 case IP_VERSION(9, 5, 0):
1900 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1901 break;
1902 case IP_VERSION(10, 1, 10):
1903 case IP_VERSION(10, 1, 1):
1904 case IP_VERSION(10, 1, 2):
1905 case IP_VERSION(10, 1, 3):
1906 case IP_VERSION(10, 1, 4):
1907 case IP_VERSION(10, 3, 0):
1908 case IP_VERSION(10, 3, 1):
1909 case IP_VERSION(10, 3, 2):
1910 case IP_VERSION(10, 3, 3):
1911 case IP_VERSION(10, 3, 4):
1912 case IP_VERSION(10, 3, 5):
1913 case IP_VERSION(10, 3, 6):
1914 case IP_VERSION(10, 3, 7):
1915 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1916 break;
1917 case IP_VERSION(11, 0, 0):
1918 case IP_VERSION(11, 0, 1):
1919 case IP_VERSION(11, 0, 2):
1920 case IP_VERSION(11, 0, 3):
1921 case IP_VERSION(11, 0, 4):
1922 case IP_VERSION(11, 5, 0):
1923 case IP_VERSION(11, 5, 1):
1924 case IP_VERSION(11, 5, 2):
1925 case IP_VERSION(11, 5, 3):
1926 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
1927 break;
1928 case IP_VERSION(12, 0, 0):
1929 case IP_VERSION(12, 0, 1):
1930 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block);
1931 break;
1932 default:
1933 dev_err(adev->dev,
1934 "Failed to add common ip block(GC_HWIP:0x%x)\n",
1935 amdgpu_ip_version(adev, GC_HWIP, 0));
1936 return -EINVAL;
1937 }
1938 return 0;
1939 }
1940
amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device * adev)1941 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1942 {
1943 /* use GC or MMHUB IP version */
1944 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1945 case IP_VERSION(9, 0, 1):
1946 case IP_VERSION(9, 1, 0):
1947 case IP_VERSION(9, 2, 1):
1948 case IP_VERSION(9, 2, 2):
1949 case IP_VERSION(9, 3, 0):
1950 case IP_VERSION(9, 4, 0):
1951 case IP_VERSION(9, 4, 1):
1952 case IP_VERSION(9, 4, 2):
1953 case IP_VERSION(9, 4, 3):
1954 case IP_VERSION(9, 4, 4):
1955 case IP_VERSION(9, 5, 0):
1956 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1957 break;
1958 case IP_VERSION(10, 1, 10):
1959 case IP_VERSION(10, 1, 1):
1960 case IP_VERSION(10, 1, 2):
1961 case IP_VERSION(10, 1, 3):
1962 case IP_VERSION(10, 1, 4):
1963 case IP_VERSION(10, 3, 0):
1964 case IP_VERSION(10, 3, 1):
1965 case IP_VERSION(10, 3, 2):
1966 case IP_VERSION(10, 3, 3):
1967 case IP_VERSION(10, 3, 4):
1968 case IP_VERSION(10, 3, 5):
1969 case IP_VERSION(10, 3, 6):
1970 case IP_VERSION(10, 3, 7):
1971 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1972 break;
1973 case IP_VERSION(11, 0, 0):
1974 case IP_VERSION(11, 0, 1):
1975 case IP_VERSION(11, 0, 2):
1976 case IP_VERSION(11, 0, 3):
1977 case IP_VERSION(11, 0, 4):
1978 case IP_VERSION(11, 5, 0):
1979 case IP_VERSION(11, 5, 1):
1980 case IP_VERSION(11, 5, 2):
1981 case IP_VERSION(11, 5, 3):
1982 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
1983 break;
1984 case IP_VERSION(12, 0, 0):
1985 case IP_VERSION(12, 0, 1):
1986 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block);
1987 break;
1988 default:
1989 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1990 amdgpu_ip_version(adev, GC_HWIP, 0));
1991 return -EINVAL;
1992 }
1993 return 0;
1994 }
1995
amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device * adev)1996 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1997 {
1998 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) {
1999 case IP_VERSION(4, 0, 0):
2000 case IP_VERSION(4, 0, 1):
2001 case IP_VERSION(4, 1, 0):
2002 case IP_VERSION(4, 1, 1):
2003 case IP_VERSION(4, 3, 0):
2004 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
2005 break;
2006 case IP_VERSION(4, 2, 0):
2007 case IP_VERSION(4, 2, 1):
2008 case IP_VERSION(4, 4, 0):
2009 case IP_VERSION(4, 4, 2):
2010 case IP_VERSION(4, 4, 5):
2011 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
2012 break;
2013 case IP_VERSION(5, 0, 0):
2014 case IP_VERSION(5, 0, 1):
2015 case IP_VERSION(5, 0, 2):
2016 case IP_VERSION(5, 0, 3):
2017 case IP_VERSION(5, 2, 0):
2018 case IP_VERSION(5, 2, 1):
2019 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
2020 break;
2021 case IP_VERSION(6, 0, 0):
2022 case IP_VERSION(6, 0, 1):
2023 case IP_VERSION(6, 0, 2):
2024 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
2025 break;
2026 case IP_VERSION(6, 1, 0):
2027 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
2028 break;
2029 case IP_VERSION(7, 0, 0):
2030 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block);
2031 break;
2032 default:
2033 dev_err(adev->dev,
2034 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
2035 amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
2036 return -EINVAL;
2037 }
2038 return 0;
2039 }
2040
amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device * adev)2041 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
2042 {
2043 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2044 case IP_VERSION(9, 0, 0):
2045 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
2046 break;
2047 case IP_VERSION(10, 0, 0):
2048 case IP_VERSION(10, 0, 1):
2049 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
2050 break;
2051 case IP_VERSION(11, 0, 0):
2052 case IP_VERSION(11, 0, 2):
2053 case IP_VERSION(11, 0, 4):
2054 case IP_VERSION(11, 0, 5):
2055 case IP_VERSION(11, 0, 9):
2056 case IP_VERSION(11, 0, 7):
2057 case IP_VERSION(11, 0, 11):
2058 case IP_VERSION(11, 0, 12):
2059 case IP_VERSION(11, 0, 13):
2060 case IP_VERSION(11, 5, 0):
2061 case IP_VERSION(11, 5, 2):
2062 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
2063 break;
2064 case IP_VERSION(11, 0, 8):
2065 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
2066 break;
2067 case IP_VERSION(11, 0, 3):
2068 case IP_VERSION(12, 0, 1):
2069 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
2070 break;
2071 case IP_VERSION(13, 0, 0):
2072 case IP_VERSION(13, 0, 1):
2073 case IP_VERSION(13, 0, 2):
2074 case IP_VERSION(13, 0, 3):
2075 case IP_VERSION(13, 0, 5):
2076 case IP_VERSION(13, 0, 6):
2077 case IP_VERSION(13, 0, 7):
2078 case IP_VERSION(13, 0, 8):
2079 case IP_VERSION(13, 0, 10):
2080 case IP_VERSION(13, 0, 11):
2081 case IP_VERSION(13, 0, 12):
2082 case IP_VERSION(13, 0, 14):
2083 case IP_VERSION(14, 0, 0):
2084 case IP_VERSION(14, 0, 1):
2085 case IP_VERSION(14, 0, 4):
2086 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
2087 break;
2088 case IP_VERSION(13, 0, 4):
2089 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
2090 break;
2091 case IP_VERSION(14, 0, 2):
2092 case IP_VERSION(14, 0, 3):
2093 case IP_VERSION(14, 0, 5):
2094 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block);
2095 break;
2096 default:
2097 dev_err(adev->dev,
2098 "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
2099 amdgpu_ip_version(adev, MP0_HWIP, 0));
2100 return -EINVAL;
2101 }
2102 return 0;
2103 }
2104
amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device * adev)2105 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
2106 {
2107 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
2108 case IP_VERSION(9, 0, 0):
2109 case IP_VERSION(10, 0, 0):
2110 case IP_VERSION(10, 0, 1):
2111 case IP_VERSION(11, 0, 2):
2112 if (adev->asic_type == CHIP_ARCTURUS)
2113 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2114 else
2115 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2116 break;
2117 case IP_VERSION(11, 0, 0):
2118 case IP_VERSION(11, 0, 5):
2119 case IP_VERSION(11, 0, 9):
2120 case IP_VERSION(11, 0, 7):
2121 case IP_VERSION(11, 0, 8):
2122 case IP_VERSION(11, 0, 11):
2123 case IP_VERSION(11, 0, 12):
2124 case IP_VERSION(11, 0, 13):
2125 case IP_VERSION(11, 5, 0):
2126 case IP_VERSION(11, 5, 2):
2127 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
2128 break;
2129 case IP_VERSION(12, 0, 0):
2130 case IP_VERSION(12, 0, 1):
2131 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
2132 break;
2133 case IP_VERSION(13, 0, 0):
2134 case IP_VERSION(13, 0, 1):
2135 case IP_VERSION(13, 0, 2):
2136 case IP_VERSION(13, 0, 3):
2137 case IP_VERSION(13, 0, 4):
2138 case IP_VERSION(13, 0, 5):
2139 case IP_VERSION(13, 0, 6):
2140 case IP_VERSION(13, 0, 7):
2141 case IP_VERSION(13, 0, 8):
2142 case IP_VERSION(13, 0, 10):
2143 case IP_VERSION(13, 0, 11):
2144 case IP_VERSION(13, 0, 14):
2145 case IP_VERSION(13, 0, 12):
2146 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
2147 break;
2148 case IP_VERSION(14, 0, 0):
2149 case IP_VERSION(14, 0, 1):
2150 case IP_VERSION(14, 0, 2):
2151 case IP_VERSION(14, 0, 3):
2152 case IP_VERSION(14, 0, 4):
2153 case IP_VERSION(14, 0, 5):
2154 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
2155 break;
2156 default:
2157 dev_err(adev->dev,
2158 "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
2159 amdgpu_ip_version(adev, MP1_HWIP, 0));
2160 return -EINVAL;
2161 }
2162 return 0;
2163 }
2164
2165 #if defined(CONFIG_DRM_AMD_DC)
amdgpu_discovery_set_sriov_display(struct amdgpu_device * adev)2166 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
2167 {
2168 amdgpu_device_set_sriov_virtual_display(adev);
2169 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2170 }
2171 #endif
2172
amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device * adev)2173 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
2174 {
2175 if (adev->enable_virtual_display) {
2176 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2177 return 0;
2178 }
2179
2180 if (!amdgpu_device_has_dc_support(adev))
2181 return 0;
2182
2183 #if defined(CONFIG_DRM_AMD_DC)
2184 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2185 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2186 case IP_VERSION(1, 0, 0):
2187 case IP_VERSION(1, 0, 1):
2188 case IP_VERSION(2, 0, 2):
2189 case IP_VERSION(2, 0, 0):
2190 case IP_VERSION(2, 0, 3):
2191 case IP_VERSION(2, 1, 0):
2192 case IP_VERSION(3, 0, 0):
2193 case IP_VERSION(3, 0, 2):
2194 case IP_VERSION(3, 0, 3):
2195 case IP_VERSION(3, 0, 1):
2196 case IP_VERSION(3, 1, 2):
2197 case IP_VERSION(3, 1, 3):
2198 case IP_VERSION(3, 1, 4):
2199 case IP_VERSION(3, 1, 5):
2200 case IP_VERSION(3, 1, 6):
2201 case IP_VERSION(3, 2, 0):
2202 case IP_VERSION(3, 2, 1):
2203 case IP_VERSION(3, 5, 0):
2204 case IP_VERSION(3, 5, 1):
2205 case IP_VERSION(3, 6, 0):
2206 case IP_VERSION(4, 1, 0):
2207 /* TODO: Fix IP version. DC code expects version 4.0.1 */
2208 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0))
2209 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1);
2210
2211 if (amdgpu_sriov_vf(adev))
2212 amdgpu_discovery_set_sriov_display(adev);
2213 else
2214 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2215 break;
2216 default:
2217 dev_err(adev->dev,
2218 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
2219 amdgpu_ip_version(adev, DCE_HWIP, 0));
2220 return -EINVAL;
2221 }
2222 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2223 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) {
2224 case IP_VERSION(12, 0, 0):
2225 case IP_VERSION(12, 0, 1):
2226 case IP_VERSION(12, 1, 0):
2227 if (amdgpu_sriov_vf(adev))
2228 amdgpu_discovery_set_sriov_display(adev);
2229 else
2230 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2231 break;
2232 default:
2233 dev_err(adev->dev,
2234 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
2235 amdgpu_ip_version(adev, DCI_HWIP, 0));
2236 return -EINVAL;
2237 }
2238 }
2239 #endif
2240 return 0;
2241 }
2242
amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device * adev)2243 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
2244 {
2245 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2246 case IP_VERSION(9, 0, 1):
2247 case IP_VERSION(9, 1, 0):
2248 case IP_VERSION(9, 2, 1):
2249 case IP_VERSION(9, 2, 2):
2250 case IP_VERSION(9, 3, 0):
2251 case IP_VERSION(9, 4, 0):
2252 case IP_VERSION(9, 4, 1):
2253 case IP_VERSION(9, 4, 2):
2254 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
2255 break;
2256 case IP_VERSION(9, 4, 3):
2257 case IP_VERSION(9, 4, 4):
2258 case IP_VERSION(9, 5, 0):
2259 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
2260 break;
2261 case IP_VERSION(10, 1, 10):
2262 case IP_VERSION(10, 1, 2):
2263 case IP_VERSION(10, 1, 1):
2264 case IP_VERSION(10, 1, 3):
2265 case IP_VERSION(10, 1, 4):
2266 case IP_VERSION(10, 3, 0):
2267 case IP_VERSION(10, 3, 2):
2268 case IP_VERSION(10, 3, 1):
2269 case IP_VERSION(10, 3, 4):
2270 case IP_VERSION(10, 3, 5):
2271 case IP_VERSION(10, 3, 6):
2272 case IP_VERSION(10, 3, 3):
2273 case IP_VERSION(10, 3, 7):
2274 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
2275 break;
2276 case IP_VERSION(11, 0, 0):
2277 case IP_VERSION(11, 0, 1):
2278 case IP_VERSION(11, 0, 2):
2279 case IP_VERSION(11, 0, 3):
2280 case IP_VERSION(11, 0, 4):
2281 case IP_VERSION(11, 5, 0):
2282 case IP_VERSION(11, 5, 1):
2283 case IP_VERSION(11, 5, 2):
2284 case IP_VERSION(11, 5, 3):
2285 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
2286 break;
2287 case IP_VERSION(12, 0, 0):
2288 case IP_VERSION(12, 0, 1):
2289 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block);
2290 break;
2291 default:
2292 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
2293 amdgpu_ip_version(adev, GC_HWIP, 0));
2294 return -EINVAL;
2295 }
2296 return 0;
2297 }
2298
amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device * adev)2299 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
2300 {
2301 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
2302 case IP_VERSION(4, 0, 0):
2303 case IP_VERSION(4, 0, 1):
2304 case IP_VERSION(4, 1, 0):
2305 case IP_VERSION(4, 1, 1):
2306 case IP_VERSION(4, 1, 2):
2307 case IP_VERSION(4, 2, 0):
2308 case IP_VERSION(4, 2, 2):
2309 case IP_VERSION(4, 4, 0):
2310 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
2311 break;
2312 case IP_VERSION(4, 4, 2):
2313 case IP_VERSION(4, 4, 5):
2314 case IP_VERSION(4, 4, 4):
2315 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
2316 break;
2317 case IP_VERSION(5, 0, 0):
2318 case IP_VERSION(5, 0, 1):
2319 case IP_VERSION(5, 0, 2):
2320 case IP_VERSION(5, 0, 5):
2321 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
2322 break;
2323 case IP_VERSION(5, 2, 0):
2324 case IP_VERSION(5, 2, 2):
2325 case IP_VERSION(5, 2, 4):
2326 case IP_VERSION(5, 2, 5):
2327 case IP_VERSION(5, 2, 6):
2328 case IP_VERSION(5, 2, 3):
2329 case IP_VERSION(5, 2, 1):
2330 case IP_VERSION(5, 2, 7):
2331 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
2332 break;
2333 case IP_VERSION(6, 0, 0):
2334 case IP_VERSION(6, 0, 1):
2335 case IP_VERSION(6, 0, 2):
2336 case IP_VERSION(6, 0, 3):
2337 case IP_VERSION(6, 1, 0):
2338 case IP_VERSION(6, 1, 1):
2339 case IP_VERSION(6, 1, 2):
2340 case IP_VERSION(6, 1, 3):
2341 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
2342 break;
2343 case IP_VERSION(7, 0, 0):
2344 case IP_VERSION(7, 0, 1):
2345 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block);
2346 break;
2347 default:
2348 dev_err(adev->dev,
2349 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
2350 amdgpu_ip_version(adev, SDMA0_HWIP, 0));
2351 return -EINVAL;
2352 }
2353 return 0;
2354 }
2355
amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device * adev)2356 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
2357 {
2358 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2359 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2360 case IP_VERSION(7, 0, 0):
2361 case IP_VERSION(7, 2, 0):
2362 /* UVD is not supported on vega20 SR-IOV */
2363 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2364 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
2365 break;
2366 default:
2367 dev_err(adev->dev,
2368 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2369 amdgpu_ip_version(adev, UVD_HWIP, 0));
2370 return -EINVAL;
2371 }
2372 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
2373 case IP_VERSION(4, 0, 0):
2374 case IP_VERSION(4, 1, 0):
2375 /* VCE is not supported on vega20 SR-IOV */
2376 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2377 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2378 break;
2379 default:
2380 dev_err(adev->dev,
2381 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2382 amdgpu_ip_version(adev, VCE_HWIP, 0));
2383 return -EINVAL;
2384 }
2385 } else {
2386 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
2387 case IP_VERSION(1, 0, 0):
2388 case IP_VERSION(1, 0, 1):
2389 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2390 break;
2391 case IP_VERSION(2, 0, 0):
2392 case IP_VERSION(2, 0, 2):
2393 case IP_VERSION(2, 2, 0):
2394 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2395 if (!amdgpu_sriov_vf(adev))
2396 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2397 break;
2398 case IP_VERSION(2, 0, 3):
2399 break;
2400 case IP_VERSION(2, 5, 0):
2401 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2402 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2403 break;
2404 case IP_VERSION(2, 6, 0):
2405 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2406 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2407 break;
2408 case IP_VERSION(3, 0, 0):
2409 case IP_VERSION(3, 0, 16):
2410 case IP_VERSION(3, 1, 1):
2411 case IP_VERSION(3, 1, 2):
2412 case IP_VERSION(3, 0, 2):
2413 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2414 if (!amdgpu_sriov_vf(adev))
2415 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2416 break;
2417 case IP_VERSION(3, 0, 33):
2418 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2419 break;
2420 case IP_VERSION(4, 0, 0):
2421 case IP_VERSION(4, 0, 2):
2422 case IP_VERSION(4, 0, 4):
2423 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2424 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2425 break;
2426 case IP_VERSION(4, 0, 3):
2427 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2428 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2429 break;
2430 case IP_VERSION(4, 0, 5):
2431 case IP_VERSION(4, 0, 6):
2432 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
2433 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
2434 break;
2435 case IP_VERSION(5, 0, 0):
2436 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
2437 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
2438 break;
2439 case IP_VERSION(5, 0, 1):
2440 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block);
2441 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block);
2442 break;
2443 default:
2444 dev_err(adev->dev,
2445 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2446 amdgpu_ip_version(adev, UVD_HWIP, 0));
2447 return -EINVAL;
2448 }
2449 }
2450 return 0;
2451 }
2452
amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device * adev)2453 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2454 {
2455 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2456 case IP_VERSION(11, 0, 0):
2457 case IP_VERSION(11, 0, 1):
2458 case IP_VERSION(11, 0, 2):
2459 case IP_VERSION(11, 0, 3):
2460 case IP_VERSION(11, 0, 4):
2461 case IP_VERSION(11, 5, 0):
2462 case IP_VERSION(11, 5, 1):
2463 case IP_VERSION(11, 5, 2):
2464 case IP_VERSION(11, 5, 3):
2465 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2466 adev->enable_mes = true;
2467 adev->enable_mes_kiq = true;
2468 break;
2469 case IP_VERSION(12, 0, 0):
2470 case IP_VERSION(12, 0, 1):
2471 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block);
2472 adev->enable_mes = true;
2473 adev->enable_mes_kiq = true;
2474 if (amdgpu_uni_mes)
2475 adev->enable_uni_mes = true;
2476 break;
2477 default:
2478 break;
2479 }
2480 return 0;
2481 }
2482
amdgpu_discovery_init_soc_config(struct amdgpu_device * adev)2483 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
2484 {
2485 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2486 case IP_VERSION(9, 4, 3):
2487 case IP_VERSION(9, 4, 4):
2488 case IP_VERSION(9, 5, 0):
2489 aqua_vanjaram_init_soc_config(adev);
2490 break;
2491 default:
2492 break;
2493 }
2494 }
2495
amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device * adev)2496 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
2497 {
2498 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
2499 case IP_VERSION(6, 1, 0):
2500 case IP_VERSION(6, 1, 1):
2501 case IP_VERSION(6, 1, 3):
2502 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
2503 break;
2504 default:
2505 break;
2506 }
2507
2508 return 0;
2509 }
2510
amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device * adev)2511 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev)
2512 {
2513 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) {
2514 case IP_VERSION(4, 0, 5):
2515 case IP_VERSION(4, 0, 6):
2516 if (amdgpu_umsch_mm & 0x1) {
2517 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block);
2518 adev->enable_umsch_mm = true;
2519 }
2520 break;
2521 default:
2522 break;
2523 }
2524
2525 return 0;
2526 }
2527
amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device * adev)2528 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev)
2529 {
2530 #if defined(CONFIG_DRM_AMD_ISP)
2531 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) {
2532 case IP_VERSION(4, 1, 0):
2533 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block);
2534 break;
2535 case IP_VERSION(4, 1, 1):
2536 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block);
2537 break;
2538 default:
2539 break;
2540 }
2541 #endif
2542
2543 return 0;
2544 }
2545
amdgpu_discovery_set_ip_blocks(struct amdgpu_device * adev)2546 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
2547 {
2548 int r;
2549
2550 switch (adev->asic_type) {
2551 case CHIP_VEGA10:
2552 case CHIP_VEGA12:
2553 case CHIP_RAVEN:
2554 case CHIP_VEGA20:
2555 case CHIP_ARCTURUS:
2556 case CHIP_ALDEBARAN:
2557 /* this is not fatal. We have a fallback below
2558 * if the new firmwares are not present. some of
2559 * this will be overridden below to keep things
2560 * consistent with the current behavior.
2561 */
2562 r = amdgpu_discovery_reg_base_init(adev);
2563 if (!r) {
2564 amdgpu_discovery_harvest_ip(adev);
2565 amdgpu_discovery_get_gfx_info(adev);
2566 amdgpu_discovery_get_mall_info(adev);
2567 amdgpu_discovery_get_vcn_info(adev);
2568 }
2569 break;
2570 default:
2571 r = amdgpu_discovery_reg_base_init(adev);
2572 if (r)
2573 return -EINVAL;
2574
2575 amdgpu_discovery_harvest_ip(adev);
2576 amdgpu_discovery_get_gfx_info(adev);
2577 amdgpu_discovery_get_mall_info(adev);
2578 amdgpu_discovery_get_vcn_info(adev);
2579 break;
2580 }
2581
2582 switch (adev->asic_type) {
2583 case CHIP_VEGA10:
2584 vega10_reg_base_init(adev);
2585 adev->sdma.num_instances = 2;
2586 adev->gmc.num_umc = 4;
2587 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2588 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2589 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
2590 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
2591 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
2592 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
2593 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2594 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
2595 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
2596 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2597 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2598 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2599 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
2600 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
2601 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2602 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2603 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2604 break;
2605 case CHIP_VEGA12:
2606 vega10_reg_base_init(adev);
2607 adev->sdma.num_instances = 2;
2608 adev->gmc.num_umc = 4;
2609 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2610 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2611 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
2612 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
2613 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
2614 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
2615 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
2616 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
2617 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
2618 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2619 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2620 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2621 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
2622 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
2623 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2624 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2625 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2626 break;
2627 case CHIP_RAVEN:
2628 vega10_reg_base_init(adev);
2629 adev->sdma.num_instances = 1;
2630 adev->vcn.num_vcn_inst = 1;
2631 adev->gmc.num_umc = 2;
2632 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
2633 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2634 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2635 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
2636 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
2637 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
2638 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
2639 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2640 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2641 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2642 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2643 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2644 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2645 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2646 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2647 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2648 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
2649 } else {
2650 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2651 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2652 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2653 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2654 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2655 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2656 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2657 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2658 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2659 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2660 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2661 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2662 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2663 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2664 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2665 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0);
2666 }
2667 break;
2668 case CHIP_VEGA20:
2669 vega20_reg_base_init(adev);
2670 adev->sdma.num_instances = 2;
2671 adev->gmc.num_umc = 8;
2672 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2673 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2674 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2675 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2676 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2677 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2678 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2679 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2680 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2681 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2682 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2683 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2684 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2685 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2686 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2687 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2688 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2689 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2690 break;
2691 case CHIP_ARCTURUS:
2692 arct_reg_base_init(adev);
2693 adev->sdma.num_instances = 8;
2694 adev->vcn.num_vcn_inst = 2;
2695 adev->gmc.num_umc = 8;
2696 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2697 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2698 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2699 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2700 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2701 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
2702 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
2703 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
2704 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
2705 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
2706 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
2707 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
2708 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
2709 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
2710 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
2711 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
2712 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2713 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
2714 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
2715 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
2716 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
2717 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2718 break;
2719 case CHIP_ALDEBARAN:
2720 aldebaran_reg_base_init(adev);
2721 adev->sdma.num_instances = 5;
2722 adev->vcn.num_vcn_inst = 2;
2723 adev->gmc.num_umc = 4;
2724 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2725 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2726 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
2727 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
2728 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
2729 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
2730 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
2731 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
2732 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
2733 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
2734 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
2735 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
2736 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
2737 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
2738 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
2739 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
2740 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
2741 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
2742 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
2743 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2744 break;
2745 default:
2746 break;
2747 }
2748
2749 amdgpu_discovery_init_soc_config(adev);
2750 amdgpu_discovery_sysfs_init(adev);
2751
2752 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2753 case IP_VERSION(9, 0, 1):
2754 case IP_VERSION(9, 2, 1):
2755 case IP_VERSION(9, 4, 0):
2756 case IP_VERSION(9, 4, 1):
2757 case IP_VERSION(9, 4, 2):
2758 case IP_VERSION(9, 4, 3):
2759 case IP_VERSION(9, 4, 4):
2760 case IP_VERSION(9, 5, 0):
2761 adev->family = AMDGPU_FAMILY_AI;
2762 break;
2763 case IP_VERSION(9, 1, 0):
2764 case IP_VERSION(9, 2, 2):
2765 case IP_VERSION(9, 3, 0):
2766 adev->family = AMDGPU_FAMILY_RV;
2767 break;
2768 case IP_VERSION(10, 1, 10):
2769 case IP_VERSION(10, 1, 1):
2770 case IP_VERSION(10, 1, 2):
2771 case IP_VERSION(10, 1, 3):
2772 case IP_VERSION(10, 1, 4):
2773 case IP_VERSION(10, 3, 0):
2774 case IP_VERSION(10, 3, 2):
2775 case IP_VERSION(10, 3, 4):
2776 case IP_VERSION(10, 3, 5):
2777 adev->family = AMDGPU_FAMILY_NV;
2778 break;
2779 case IP_VERSION(10, 3, 1):
2780 adev->family = AMDGPU_FAMILY_VGH;
2781 adev->apu_flags |= AMD_APU_IS_VANGOGH;
2782 break;
2783 case IP_VERSION(10, 3, 3):
2784 adev->family = AMDGPU_FAMILY_YC;
2785 break;
2786 case IP_VERSION(10, 3, 6):
2787 adev->family = AMDGPU_FAMILY_GC_10_3_6;
2788 break;
2789 case IP_VERSION(10, 3, 7):
2790 adev->family = AMDGPU_FAMILY_GC_10_3_7;
2791 break;
2792 case IP_VERSION(11, 0, 0):
2793 case IP_VERSION(11, 0, 2):
2794 case IP_VERSION(11, 0, 3):
2795 adev->family = AMDGPU_FAMILY_GC_11_0_0;
2796 break;
2797 case IP_VERSION(11, 0, 1):
2798 case IP_VERSION(11, 0, 4):
2799 adev->family = AMDGPU_FAMILY_GC_11_0_1;
2800 break;
2801 case IP_VERSION(11, 5, 0):
2802 case IP_VERSION(11, 5, 1):
2803 case IP_VERSION(11, 5, 2):
2804 case IP_VERSION(11, 5, 3):
2805 adev->family = AMDGPU_FAMILY_GC_11_5_0;
2806 break;
2807 case IP_VERSION(12, 0, 0):
2808 case IP_VERSION(12, 0, 1):
2809 adev->family = AMDGPU_FAMILY_GC_12_0_0;
2810 break;
2811 default:
2812 return -EINVAL;
2813 }
2814
2815 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2816 case IP_VERSION(9, 1, 0):
2817 case IP_VERSION(9, 2, 2):
2818 case IP_VERSION(9, 3, 0):
2819 case IP_VERSION(10, 1, 3):
2820 case IP_VERSION(10, 1, 4):
2821 case IP_VERSION(10, 3, 1):
2822 case IP_VERSION(10, 3, 3):
2823 case IP_VERSION(10, 3, 6):
2824 case IP_VERSION(10, 3, 7):
2825 case IP_VERSION(11, 0, 1):
2826 case IP_VERSION(11, 0, 4):
2827 case IP_VERSION(11, 5, 0):
2828 case IP_VERSION(11, 5, 1):
2829 case IP_VERSION(11, 5, 2):
2830 case IP_VERSION(11, 5, 3):
2831 adev->flags |= AMD_IS_APU;
2832 break;
2833 default:
2834 break;
2835 }
2836
2837 /* set NBIO version */
2838 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2839 case IP_VERSION(6, 1, 0):
2840 case IP_VERSION(6, 2, 0):
2841 adev->nbio.funcs = &nbio_v6_1_funcs;
2842 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
2843 break;
2844 case IP_VERSION(7, 0, 0):
2845 case IP_VERSION(7, 0, 1):
2846 case IP_VERSION(2, 5, 0):
2847 adev->nbio.funcs = &nbio_v7_0_funcs;
2848 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
2849 break;
2850 case IP_VERSION(7, 4, 0):
2851 case IP_VERSION(7, 4, 1):
2852 case IP_VERSION(7, 4, 4):
2853 adev->nbio.funcs = &nbio_v7_4_funcs;
2854 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
2855 break;
2856 case IP_VERSION(7, 9, 0):
2857 case IP_VERSION(7, 9, 1):
2858 adev->nbio.funcs = &nbio_v7_9_funcs;
2859 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
2860 break;
2861 case IP_VERSION(7, 11, 0):
2862 case IP_VERSION(7, 11, 1):
2863 case IP_VERSION(7, 11, 2):
2864 case IP_VERSION(7, 11, 3):
2865 adev->nbio.funcs = &nbio_v7_11_funcs;
2866 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
2867 break;
2868 case IP_VERSION(7, 2, 0):
2869 case IP_VERSION(7, 2, 1):
2870 case IP_VERSION(7, 3, 0):
2871 case IP_VERSION(7, 5, 0):
2872 case IP_VERSION(7, 5, 1):
2873 adev->nbio.funcs = &nbio_v7_2_funcs;
2874 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
2875 break;
2876 case IP_VERSION(2, 1, 1):
2877 case IP_VERSION(2, 3, 0):
2878 case IP_VERSION(2, 3, 1):
2879 case IP_VERSION(2, 3, 2):
2880 case IP_VERSION(3, 3, 0):
2881 case IP_VERSION(3, 3, 1):
2882 case IP_VERSION(3, 3, 2):
2883 case IP_VERSION(3, 3, 3):
2884 adev->nbio.funcs = &nbio_v2_3_funcs;
2885 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
2886 break;
2887 case IP_VERSION(4, 3, 0):
2888 case IP_VERSION(4, 3, 1):
2889 if (amdgpu_sriov_vf(adev))
2890 adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
2891 else
2892 adev->nbio.funcs = &nbio_v4_3_funcs;
2893 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
2894 break;
2895 case IP_VERSION(7, 7, 0):
2896 case IP_VERSION(7, 7, 1):
2897 adev->nbio.funcs = &nbio_v7_7_funcs;
2898 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
2899 break;
2900 case IP_VERSION(6, 3, 1):
2901 adev->nbio.funcs = &nbif_v6_3_1_funcs;
2902 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
2903 break;
2904 default:
2905 break;
2906 }
2907
2908 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) {
2909 case IP_VERSION(4, 0, 0):
2910 case IP_VERSION(4, 0, 1):
2911 case IP_VERSION(4, 1, 0):
2912 case IP_VERSION(4, 1, 1):
2913 case IP_VERSION(4, 1, 2):
2914 case IP_VERSION(4, 2, 0):
2915 case IP_VERSION(4, 2, 1):
2916 case IP_VERSION(4, 4, 0):
2917 case IP_VERSION(4, 4, 2):
2918 case IP_VERSION(4, 4, 5):
2919 adev->hdp.funcs = &hdp_v4_0_funcs;
2920 break;
2921 case IP_VERSION(5, 0, 0):
2922 case IP_VERSION(5, 0, 1):
2923 case IP_VERSION(5, 0, 2):
2924 case IP_VERSION(5, 0, 3):
2925 case IP_VERSION(5, 0, 4):
2926 case IP_VERSION(5, 2, 0):
2927 adev->hdp.funcs = &hdp_v5_0_funcs;
2928 break;
2929 case IP_VERSION(5, 2, 1):
2930 adev->hdp.funcs = &hdp_v5_2_funcs;
2931 break;
2932 case IP_VERSION(6, 0, 0):
2933 case IP_VERSION(6, 0, 1):
2934 case IP_VERSION(6, 1, 0):
2935 adev->hdp.funcs = &hdp_v6_0_funcs;
2936 break;
2937 case IP_VERSION(7, 0, 0):
2938 adev->hdp.funcs = &hdp_v7_0_funcs;
2939 break;
2940 default:
2941 break;
2942 }
2943
2944 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) {
2945 case IP_VERSION(3, 6, 0):
2946 case IP_VERSION(3, 6, 1):
2947 case IP_VERSION(3, 6, 2):
2948 adev->df.funcs = &df_v3_6_funcs;
2949 break;
2950 case IP_VERSION(2, 1, 0):
2951 case IP_VERSION(2, 1, 1):
2952 case IP_VERSION(2, 5, 0):
2953 case IP_VERSION(3, 5, 1):
2954 case IP_VERSION(3, 5, 2):
2955 adev->df.funcs = &df_v1_7_funcs;
2956 break;
2957 case IP_VERSION(4, 3, 0):
2958 adev->df.funcs = &df_v4_3_funcs;
2959 break;
2960 case IP_VERSION(4, 6, 2):
2961 adev->df.funcs = &df_v4_6_2_funcs;
2962 break;
2963 case IP_VERSION(4, 15, 0):
2964 case IP_VERSION(4, 15, 1):
2965 adev->df.funcs = &df_v4_15_funcs;
2966 break;
2967 default:
2968 break;
2969 }
2970
2971 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) {
2972 case IP_VERSION(9, 0, 0):
2973 case IP_VERSION(9, 0, 1):
2974 case IP_VERSION(10, 0, 0):
2975 case IP_VERSION(10, 0, 1):
2976 case IP_VERSION(10, 0, 2):
2977 adev->smuio.funcs = &smuio_v9_0_funcs;
2978 break;
2979 case IP_VERSION(11, 0, 0):
2980 case IP_VERSION(11, 0, 2):
2981 case IP_VERSION(11, 0, 3):
2982 case IP_VERSION(11, 0, 4):
2983 case IP_VERSION(11, 0, 7):
2984 case IP_VERSION(11, 0, 8):
2985 adev->smuio.funcs = &smuio_v11_0_funcs;
2986 break;
2987 case IP_VERSION(11, 0, 6):
2988 case IP_VERSION(11, 0, 10):
2989 case IP_VERSION(11, 0, 11):
2990 case IP_VERSION(11, 5, 0):
2991 case IP_VERSION(11, 5, 2):
2992 case IP_VERSION(13, 0, 1):
2993 case IP_VERSION(13, 0, 9):
2994 case IP_VERSION(13, 0, 10):
2995 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2996 break;
2997 case IP_VERSION(13, 0, 2):
2998 adev->smuio.funcs = &smuio_v13_0_funcs;
2999 break;
3000 case IP_VERSION(13, 0, 3):
3001 case IP_VERSION(13, 0, 11):
3002 adev->smuio.funcs = &smuio_v13_0_3_funcs;
3003 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
3004 adev->flags |= AMD_IS_APU;
3005 }
3006 break;
3007 case IP_VERSION(13, 0, 6):
3008 case IP_VERSION(13, 0, 8):
3009 case IP_VERSION(14, 0, 0):
3010 case IP_VERSION(14, 0, 1):
3011 adev->smuio.funcs = &smuio_v13_0_6_funcs;
3012 break;
3013 case IP_VERSION(14, 0, 2):
3014 adev->smuio.funcs = &smuio_v14_0_2_funcs;
3015 break;
3016 default:
3017 break;
3018 }
3019
3020 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
3021 case IP_VERSION(6, 0, 0):
3022 case IP_VERSION(6, 0, 1):
3023 case IP_VERSION(6, 0, 2):
3024 case IP_VERSION(6, 0, 3):
3025 adev->lsdma.funcs = &lsdma_v6_0_funcs;
3026 break;
3027 case IP_VERSION(7, 0, 0):
3028 case IP_VERSION(7, 0, 1):
3029 adev->lsdma.funcs = &lsdma_v7_0_funcs;
3030 break;
3031 default:
3032 break;
3033 }
3034
3035 r = amdgpu_discovery_set_common_ip_blocks(adev);
3036 if (r)
3037 return r;
3038
3039 r = amdgpu_discovery_set_gmc_ip_blocks(adev);
3040 if (r)
3041 return r;
3042
3043 /* For SR-IOV, PSP needs to be initialized before IH */
3044 if (amdgpu_sriov_vf(adev)) {
3045 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3046 if (r)
3047 return r;
3048 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3049 if (r)
3050 return r;
3051 } else {
3052 r = amdgpu_discovery_set_ih_ip_blocks(adev);
3053 if (r)
3054 return r;
3055
3056 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3057 r = amdgpu_discovery_set_psp_ip_blocks(adev);
3058 if (r)
3059 return r;
3060 }
3061 }
3062
3063 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
3064 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3065 if (r)
3066 return r;
3067 }
3068
3069 r = amdgpu_discovery_set_display_ip_blocks(adev);
3070 if (r)
3071 return r;
3072
3073 r = amdgpu_discovery_set_gc_ip_blocks(adev);
3074 if (r)
3075 return r;
3076
3077 r = amdgpu_discovery_set_sdma_ip_blocks(adev);
3078 if (r)
3079 return r;
3080
3081 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
3082 !amdgpu_sriov_vf(adev)) ||
3083 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
3084 r = amdgpu_discovery_set_smu_ip_blocks(adev);
3085 if (r)
3086 return r;
3087 }
3088
3089 r = amdgpu_discovery_set_mm_ip_blocks(adev);
3090 if (r)
3091 return r;
3092
3093 r = amdgpu_discovery_set_mes_ip_blocks(adev);
3094 if (r)
3095 return r;
3096
3097 r = amdgpu_discovery_set_vpe_ip_blocks(adev);
3098 if (r)
3099 return r;
3100
3101 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev);
3102 if (r)
3103 return r;
3104
3105 r = amdgpu_discovery_set_isp_ip_blocks(adev);
3106 if (r)
3107 return r;
3108 return 0;
3109 }
3110
3111