1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_i2c.h"
32 #include "amdgpu_display.h"
33
34 #include "atom.h"
35 #include "atom-bits.h"
36 #include "atombios_encoders.h"
37 #include "bif/bif_4_1_d.h"
38
amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)39 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
40 {
41 struct amdgpu_i2c_bus_rec i2c;
42
43 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
44
45 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex);
46 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex);
47 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex);
48 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex);
49 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex);
50 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex);
51 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex);
52 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex);
53 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
54 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
55 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
56 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
57 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
58 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
59 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
60 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
61
62 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
63 i2c.hw_capable = true;
64 else
65 i2c.hw_capable = false;
66
67 if (gpio->sucI2cId.ucAccess == 0xa0)
68 i2c.mm_i2c = true;
69 else
70 i2c.mm_i2c = false;
71
72 i2c.i2c_id = gpio->sucI2cId.ucAccess;
73
74 if (i2c.mask_clk_reg)
75 i2c.valid = true;
76 else
77 i2c.valid = false;
78
79 return i2c;
80 }
81
amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device * adev,uint8_t id)82 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev,
83 uint8_t id)
84 {
85 struct atom_context *ctx = adev->mode_info.atom_context;
86 ATOM_GPIO_I2C_ASSIGMENT *gpio;
87 struct amdgpu_i2c_bus_rec i2c;
88 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
89 struct _ATOM_GPIO_I2C_INFO *i2c_info;
90 uint16_t data_offset, size;
91 int i, num_indices;
92
93 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec));
94 i2c.valid = false;
95
96 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
97 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
98
99 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
100 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
101
102 gpio = &i2c_info->asGPIO_Info[0];
103 for (i = 0; i < num_indices; i++) {
104 if (gpio->sucI2cId.ucAccess == id) {
105 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
106 break;
107 }
108 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
109 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
110 }
111 }
112
113 return i2c;
114 }
115
amdgpu_atombios_i2c_init(struct amdgpu_device * adev)116 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev)
117 {
118 struct atom_context *ctx = adev->mode_info.atom_context;
119 ATOM_GPIO_I2C_ASSIGMENT *gpio;
120 struct amdgpu_i2c_bus_rec i2c;
121 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
122 struct _ATOM_GPIO_I2C_INFO *i2c_info;
123 uint16_t data_offset, size;
124 int i, num_indices;
125 char stmp[32];
126
127 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
128 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
129
130 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
131 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
132
133 gpio = &i2c_info->asGPIO_Info[0];
134 for (i = 0; i < num_indices; i++) {
135 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
136
137 if (i2c.valid) {
138 sprintf(stmp, "0x%x", i2c.i2c_id);
139 adev->i2c_bus[i] = amdgpu_i2c_create(adev_to_drm(adev), &i2c, stmp);
140 }
141 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
142 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
143 }
144 }
145 }
146
amdgpu_atombios_oem_i2c_init(struct amdgpu_device * adev,u8 i2c_id)147 void amdgpu_atombios_oem_i2c_init(struct amdgpu_device *adev, u8 i2c_id)
148 {
149 struct atom_context *ctx = adev->mode_info.atom_context;
150 ATOM_GPIO_I2C_ASSIGMENT *gpio;
151 struct amdgpu_i2c_bus_rec i2c;
152 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
153 struct _ATOM_GPIO_I2C_INFO *i2c_info;
154 uint16_t data_offset, size;
155 int i, num_indices;
156 char stmp[32];
157
158 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
159 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
160
161 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
162 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
163
164 gpio = &i2c_info->asGPIO_Info[0];
165 for (i = 0; i < num_indices; i++) {
166 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio);
167
168 if (i2c.valid && i2c.i2c_id == i2c_id) {
169 sprintf(stmp, "OEM 0x%x", i2c.i2c_id);
170 adev->i2c_bus[i] = amdgpu_i2c_create(adev_to_drm(adev), &i2c, stmp);
171 break;
172 }
173 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
174 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
175 }
176 }
177 }
178
179 struct amdgpu_gpio_rec
amdgpu_atombios_lookup_gpio(struct amdgpu_device * adev,u8 id)180 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev,
181 u8 id)
182 {
183 struct atom_context *ctx = adev->mode_info.atom_context;
184 struct amdgpu_gpio_rec gpio;
185 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
186 struct _ATOM_GPIO_PIN_LUT *gpio_info;
187 ATOM_GPIO_PIN_ASSIGNMENT *pin;
188 u16 data_offset, size;
189 int i, num_indices;
190
191 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec));
192 gpio.valid = false;
193
194 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
195 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
196
197 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
198 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
199
200 pin = gpio_info->asGPIO_Pin;
201 for (i = 0; i < num_indices; i++) {
202 if (id == pin->ucGPIO_ID) {
203 gpio.id = pin->ucGPIO_ID;
204 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex);
205 gpio.shift = pin->ucGpioPinBitShift;
206 gpio.mask = (1 << pin->ucGpioPinBitShift);
207 gpio.valid = true;
208 break;
209 }
210 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
211 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
212 }
213 }
214
215 return gpio;
216 }
217
218 static struct amdgpu_hpd
amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device * adev,struct amdgpu_gpio_rec * gpio)219 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
220 struct amdgpu_gpio_rec *gpio)
221 {
222 struct amdgpu_hpd hpd;
223 u32 reg;
224
225 memset(&hpd, 0, sizeof(struct amdgpu_hpd));
226
227 reg = amdgpu_display_hpd_get_gpio_reg(adev);
228
229 hpd.gpio = *gpio;
230 if (gpio->reg == reg) {
231 switch(gpio->mask) {
232 case (1 << 0):
233 hpd.hpd = AMDGPU_HPD_1;
234 break;
235 case (1 << 8):
236 hpd.hpd = AMDGPU_HPD_2;
237 break;
238 case (1 << 16):
239 hpd.hpd = AMDGPU_HPD_3;
240 break;
241 case (1 << 24):
242 hpd.hpd = AMDGPU_HPD_4;
243 break;
244 case (1 << 26):
245 hpd.hpd = AMDGPU_HPD_5;
246 break;
247 case (1 << 28):
248 hpd.hpd = AMDGPU_HPD_6;
249 break;
250 default:
251 hpd.hpd = AMDGPU_HPD_NONE;
252 break;
253 }
254 } else
255 hpd.hpd = AMDGPU_HPD_NONE;
256 return hpd;
257 }
258
259 static const int object_connector_convert[] = {
260 DRM_MODE_CONNECTOR_Unknown,
261 DRM_MODE_CONNECTOR_DVII,
262 DRM_MODE_CONNECTOR_DVII,
263 DRM_MODE_CONNECTOR_DVID,
264 DRM_MODE_CONNECTOR_DVID,
265 DRM_MODE_CONNECTOR_VGA,
266 DRM_MODE_CONNECTOR_Composite,
267 DRM_MODE_CONNECTOR_SVIDEO,
268 DRM_MODE_CONNECTOR_Unknown,
269 DRM_MODE_CONNECTOR_Unknown,
270 DRM_MODE_CONNECTOR_9PinDIN,
271 DRM_MODE_CONNECTOR_Unknown,
272 DRM_MODE_CONNECTOR_HDMIA,
273 DRM_MODE_CONNECTOR_HDMIB,
274 DRM_MODE_CONNECTOR_LVDS,
275 DRM_MODE_CONNECTOR_9PinDIN,
276 DRM_MODE_CONNECTOR_Unknown,
277 DRM_MODE_CONNECTOR_Unknown,
278 DRM_MODE_CONNECTOR_Unknown,
279 DRM_MODE_CONNECTOR_DisplayPort,
280 DRM_MODE_CONNECTOR_eDP,
281 DRM_MODE_CONNECTOR_Unknown
282 };
283
amdgpu_atombios_has_dce_engine_info(struct amdgpu_device * adev)284 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev)
285 {
286 struct amdgpu_mode_info *mode_info = &adev->mode_info;
287 struct atom_context *ctx = mode_info->atom_context;
288 int index = GetIndexIntoMasterTable(DATA, Object_Header);
289 u16 size, data_offset;
290 u8 frev, crev;
291 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
292 ATOM_OBJECT_HEADER *obj_header;
293
294 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
295 return false;
296
297 if (crev < 2)
298 return false;
299
300 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
301 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
302 (ctx->bios + data_offset +
303 le16_to_cpu(obj_header->usDisplayPathTableOffset));
304
305 if (path_obj->ucNumOfDispPath)
306 return true;
307 else
308 return false;
309 }
310
amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * adev)311 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev)
312 {
313 struct amdgpu_mode_info *mode_info = &adev->mode_info;
314 struct atom_context *ctx = mode_info->atom_context;
315 int index = GetIndexIntoMasterTable(DATA, Object_Header);
316 u16 size, data_offset;
317 u8 frev, crev;
318 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
319 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
320 ATOM_OBJECT_TABLE *router_obj;
321 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
322 ATOM_OBJECT_HEADER *obj_header;
323 int i, j, k, path_size, device_support;
324 int connector_type;
325 u16 conn_id, connector_object_id;
326 struct amdgpu_i2c_bus_rec ddc_bus;
327 struct amdgpu_router router;
328 struct amdgpu_gpio_rec gpio;
329 struct amdgpu_hpd hpd;
330
331 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
332 return false;
333
334 if (crev < 2)
335 return false;
336
337 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
338 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
339 (ctx->bios + data_offset +
340 le16_to_cpu(obj_header->usDisplayPathTableOffset));
341 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
342 (ctx->bios + data_offset +
343 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
344 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
345 (ctx->bios + data_offset +
346 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
347 router_obj = (ATOM_OBJECT_TABLE *)
348 (ctx->bios + data_offset +
349 le16_to_cpu(obj_header->usRouterObjectTableOffset));
350 device_support = le16_to_cpu(obj_header->usDeviceSupport);
351
352 path_size = 0;
353 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
354 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
355 ATOM_DISPLAY_OBJECT_PATH *path;
356 addr += path_size;
357 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
358 path_size += le16_to_cpu(path->usSize);
359
360 if (device_support & le16_to_cpu(path->usDeviceTag)) {
361 uint8_t con_obj_id =
362 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
363 >> OBJECT_ID_SHIFT;
364
365 /* Skip TV/CV support */
366 if ((le16_to_cpu(path->usDeviceTag) ==
367 ATOM_DEVICE_TV1_SUPPORT) ||
368 (le16_to_cpu(path->usDeviceTag) ==
369 ATOM_DEVICE_CV_SUPPORT))
370 continue;
371
372 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) {
373 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n",
374 con_obj_id, le16_to_cpu(path->usDeviceTag));
375 continue;
376 }
377
378 connector_type =
379 object_connector_convert[con_obj_id];
380 connector_object_id = con_obj_id;
381
382 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
383 continue;
384
385 router.ddc_valid = false;
386 router.cd_valid = false;
387 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
388 uint8_t grph_obj_type =
389 (le16_to_cpu(path->usGraphicObjIds[j]) &
390 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
391
392 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
393 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
394 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
395 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
396 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
397 (ctx->bios + data_offset +
398 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
399 ATOM_ENCODER_CAP_RECORD *cap_record;
400 u16 caps = 0;
401
402 while (record->ucRecordSize > 0 &&
403 record->ucRecordType > 0 &&
404 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
405 switch (record->ucRecordType) {
406 case ATOM_ENCODER_CAP_RECORD_TYPE:
407 cap_record =(ATOM_ENCODER_CAP_RECORD *)
408 record;
409 caps = le16_to_cpu(cap_record->usEncoderCap);
410 break;
411 }
412 record = (ATOM_COMMON_RECORD_HEADER *)
413 ((char *)record + record->ucRecordSize);
414 }
415 amdgpu_display_add_encoder(adev, encoder_obj,
416 le16_to_cpu(path->usDeviceTag),
417 caps);
418 }
419 }
420 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
421 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
422 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
423 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
424 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
425 (ctx->bios + data_offset +
426 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
427 ATOM_I2C_RECORD *i2c_record;
428 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
429 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
430 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
431 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
432 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
433 (ctx->bios + data_offset +
434 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
435 u8 *num_dst_objs = (u8 *)
436 ((u8 *)router_src_dst_table + 1 +
437 (router_src_dst_table->ucNumberOfSrc * 2));
438 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
439 int enum_id;
440
441 router.router_id = router_obj_id;
442 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
443 if (le16_to_cpu(path->usConnObjectId) ==
444 le16_to_cpu(dst_objs[enum_id]))
445 break;
446 }
447
448 while (record->ucRecordSize > 0 &&
449 record->ucRecordType > 0 &&
450 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
451 switch (record->ucRecordType) {
452 case ATOM_I2C_RECORD_TYPE:
453 i2c_record =
454 (ATOM_I2C_RECORD *)
455 record;
456 i2c_config =
457 (ATOM_I2C_ID_CONFIG_ACCESS *)
458 &i2c_record->sucI2cId;
459 router.i2c_info =
460 amdgpu_atombios_lookup_i2c_gpio(adev,
461 i2c_config->
462 ucAccess);
463 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
464 break;
465 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
466 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
467 record;
468 router.ddc_valid = true;
469 router.ddc_mux_type = ddc_path->ucMuxType;
470 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
471 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
472 break;
473 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
474 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
475 record;
476 router.cd_valid = true;
477 router.cd_mux_type = cd_path->ucMuxType;
478 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
479 router.cd_mux_state = cd_path->ucMuxState[enum_id];
480 break;
481 }
482 record = (ATOM_COMMON_RECORD_HEADER *)
483 ((char *)record + record->ucRecordSize);
484 }
485 }
486 }
487 }
488 }
489
490 /* look up gpio for ddc, hpd */
491 ddc_bus.valid = false;
492 hpd.hpd = AMDGPU_HPD_NONE;
493 if ((le16_to_cpu(path->usDeviceTag) &
494 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
495 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
496 if (le16_to_cpu(path->usConnObjectId) ==
497 le16_to_cpu(con_obj->asObjects[j].
498 usObjectID)) {
499 ATOM_COMMON_RECORD_HEADER
500 *record =
501 (ATOM_COMMON_RECORD_HEADER
502 *)
503 (ctx->bios + data_offset +
504 le16_to_cpu(con_obj->
505 asObjects[j].
506 usRecordOffset));
507 ATOM_I2C_RECORD *i2c_record;
508 ATOM_HPD_INT_RECORD *hpd_record;
509 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
510
511 while (record->ucRecordSize > 0 &&
512 record->ucRecordType > 0 &&
513 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
514 switch (record->ucRecordType) {
515 case ATOM_I2C_RECORD_TYPE:
516 i2c_record =
517 (ATOM_I2C_RECORD *)
518 record;
519 i2c_config =
520 (ATOM_I2C_ID_CONFIG_ACCESS *)
521 &i2c_record->sucI2cId;
522 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev,
523 i2c_config->
524 ucAccess);
525 break;
526 case ATOM_HPD_INT_RECORD_TYPE:
527 hpd_record =
528 (ATOM_HPD_INT_RECORD *)
529 record;
530 gpio = amdgpu_atombios_lookup_gpio(adev,
531 hpd_record->ucHPDIntGPIOID);
532 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio);
533 hpd.plugged_state = hpd_record->ucPlugged_PinState;
534 break;
535 }
536 record =
537 (ATOM_COMMON_RECORD_HEADER
538 *) ((char *)record
539 +
540 record->
541 ucRecordSize);
542 }
543 break;
544 }
545 }
546 }
547
548 /* needed for aux chan transactions */
549 ddc_bus.hpd = hpd.hpd;
550
551 conn_id = le16_to_cpu(path->usConnObjectId);
552
553 amdgpu_display_add_connector(adev,
554 conn_id,
555 le16_to_cpu(path->usDeviceTag),
556 connector_type, &ddc_bus,
557 connector_object_id,
558 &hpd,
559 &router);
560
561 }
562 }
563
564 amdgpu_link_encoder_connector(adev_to_drm(adev));
565
566 return true;
567 }
568
569 union firmware_info {
570 ATOM_FIRMWARE_INFO info;
571 ATOM_FIRMWARE_INFO_V1_2 info_12;
572 ATOM_FIRMWARE_INFO_V1_3 info_13;
573 ATOM_FIRMWARE_INFO_V1_4 info_14;
574 ATOM_FIRMWARE_INFO_V2_1 info_21;
575 ATOM_FIRMWARE_INFO_V2_2 info_22;
576 };
577
amdgpu_atombios_get_clock_info(struct amdgpu_device * adev)578 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
579 {
580 struct amdgpu_mode_info *mode_info = &adev->mode_info;
581 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
582 uint8_t frev, crev;
583 uint16_t data_offset;
584 int ret = -EINVAL;
585
586 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
587 &frev, &crev, &data_offset)) {
588 int i;
589 struct amdgpu_pll *ppll = &adev->clock.ppll[0];
590 struct amdgpu_pll *spll = &adev->clock.spll;
591 struct amdgpu_pll *mpll = &adev->clock.mpll;
592 union firmware_info *firmware_info =
593 (union firmware_info *)(mode_info->atom_context->bios +
594 data_offset);
595 /* pixel clocks */
596 ppll->reference_freq =
597 le16_to_cpu(firmware_info->info.usReferenceClock);
598 ppll->reference_div = 0;
599
600 ppll->pll_out_min =
601 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
602 ppll->pll_out_max =
603 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
604
605 ppll->lcd_pll_out_min =
606 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
607 if (ppll->lcd_pll_out_min == 0)
608 ppll->lcd_pll_out_min = ppll->pll_out_min;
609 ppll->lcd_pll_out_max =
610 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
611 if (ppll->lcd_pll_out_max == 0)
612 ppll->lcd_pll_out_max = ppll->pll_out_max;
613
614 if (ppll->pll_out_min == 0)
615 ppll->pll_out_min = 64800;
616
617 ppll->pll_in_min =
618 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
619 ppll->pll_in_max =
620 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
621
622 ppll->min_post_div = 2;
623 ppll->max_post_div = 0x7f;
624 ppll->min_frac_feedback_div = 0;
625 ppll->max_frac_feedback_div = 9;
626 ppll->min_ref_div = 2;
627 ppll->max_ref_div = 0x3ff;
628 ppll->min_feedback_div = 4;
629 ppll->max_feedback_div = 0xfff;
630 ppll->best_vco = 0;
631
632 for (i = 1; i < AMDGPU_MAX_PPLL; i++)
633 adev->clock.ppll[i] = *ppll;
634
635 /* system clock */
636 spll->reference_freq =
637 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
638 spll->reference_div = 0;
639
640 spll->pll_out_min =
641 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
642 spll->pll_out_max =
643 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
644
645 /* ??? */
646 if (spll->pll_out_min == 0)
647 spll->pll_out_min = 64800;
648
649 spll->pll_in_min =
650 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
651 spll->pll_in_max =
652 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
653
654 spll->min_post_div = 1;
655 spll->max_post_div = 1;
656 spll->min_ref_div = 2;
657 spll->max_ref_div = 0xff;
658 spll->min_feedback_div = 4;
659 spll->max_feedback_div = 0xff;
660 spll->best_vco = 0;
661
662 /* memory clock */
663 mpll->reference_freq =
664 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
665 mpll->reference_div = 0;
666
667 mpll->pll_out_min =
668 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
669 mpll->pll_out_max =
670 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
671
672 /* ??? */
673 if (mpll->pll_out_min == 0)
674 mpll->pll_out_min = 64800;
675
676 mpll->pll_in_min =
677 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
678 mpll->pll_in_max =
679 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
680
681 adev->clock.default_sclk =
682 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
683 adev->clock.default_mclk =
684 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
685
686 mpll->min_post_div = 1;
687 mpll->max_post_div = 1;
688 mpll->min_ref_div = 2;
689 mpll->max_ref_div = 0xff;
690 mpll->min_feedback_div = 4;
691 mpll->max_feedback_div = 0xff;
692 mpll->best_vco = 0;
693
694 /* disp clock */
695 adev->clock.default_dispclk =
696 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
697 /* set a reasonable default for DP */
698 if (adev->clock.default_dispclk < 53900) {
699 DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n",
700 adev->clock.default_dispclk / 100);
701 adev->clock.default_dispclk = 60000;
702 } else if (adev->clock.default_dispclk <= 60000) {
703 DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n",
704 adev->clock.default_dispclk / 100);
705 adev->clock.default_dispclk = 62500;
706 }
707 adev->clock.dp_extclk =
708 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
709 adev->clock.current_dispclk = adev->clock.default_dispclk;
710
711 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
712 if (adev->clock.max_pixel_clock == 0)
713 adev->clock.max_pixel_clock = 40000;
714
715 /* not technically a clock, but... */
716 adev->mode_info.firmware_flags =
717 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
718
719 ret = 0;
720 }
721
722 adev->pm.current_sclk = adev->clock.default_sclk;
723 adev->pm.current_mclk = adev->clock.default_mclk;
724
725 return ret;
726 }
727
728 union gfx_info {
729 ATOM_GFX_INFO_V2_1 info;
730 };
731
amdgpu_atombios_get_gfx_info(struct amdgpu_device * adev)732 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
733 {
734 struct amdgpu_mode_info *mode_info = &adev->mode_info;
735 int index = GetIndexIntoMasterTable(DATA, GFX_Info);
736 uint8_t frev, crev;
737 uint16_t data_offset;
738 int ret = -EINVAL;
739
740 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
741 &frev, &crev, &data_offset)) {
742 union gfx_info *gfx_info = (union gfx_info *)
743 (mode_info->atom_context->bios + data_offset);
744
745 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
746 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
747 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
748 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
749 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
750 adev->gfx.config.max_texture_channel_caches =
751 gfx_info->info.max_texture_channel_caches;
752
753 ret = 0;
754 }
755 return ret;
756 }
757
758 union igp_info {
759 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
760 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
761 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
762 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
763 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
764 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
765 };
766
767 /*
768 * Return vram width from integrated system info table, if available,
769 * or 0 if not.
770 */
amdgpu_atombios_get_vram_width(struct amdgpu_device * adev)771 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev)
772 {
773 struct amdgpu_mode_info *mode_info = &adev->mode_info;
774 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
775 u16 data_offset, size;
776 union igp_info *igp_info;
777 u8 frev, crev;
778
779 /* get any igp specific overrides */
780 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
781 &frev, &crev, &data_offset)) {
782 igp_info = (union igp_info *)
783 (mode_info->atom_context->bios + data_offset);
784 switch (crev) {
785 case 8:
786 case 9:
787 return igp_info->info_8.ucUMAChannelNumber * 64;
788 default:
789 return 0;
790 }
791 }
792
793 return 0;
794 }
795
amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device * adev,struct amdgpu_atom_ss * ss,int id)796 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev,
797 struct amdgpu_atom_ss *ss,
798 int id)
799 {
800 struct amdgpu_mode_info *mode_info = &adev->mode_info;
801 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
802 u16 data_offset, size;
803 union igp_info *igp_info;
804 u8 frev, crev;
805 u16 percentage = 0, rate = 0;
806
807 /* get any igp specific overrides */
808 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
809 &frev, &crev, &data_offset)) {
810 igp_info = (union igp_info *)
811 (mode_info->atom_context->bios + data_offset);
812 switch (crev) {
813 case 6:
814 switch (id) {
815 case ASIC_INTERNAL_SS_ON_TMDS:
816 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
817 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
818 break;
819 case ASIC_INTERNAL_SS_ON_HDMI:
820 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
821 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
822 break;
823 case ASIC_INTERNAL_SS_ON_LVDS:
824 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
825 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
826 break;
827 }
828 break;
829 case 7:
830 switch (id) {
831 case ASIC_INTERNAL_SS_ON_TMDS:
832 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
833 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
834 break;
835 case ASIC_INTERNAL_SS_ON_HDMI:
836 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
837 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
838 break;
839 case ASIC_INTERNAL_SS_ON_LVDS:
840 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
841 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
842 break;
843 }
844 break;
845 case 8:
846 switch (id) {
847 case ASIC_INTERNAL_SS_ON_TMDS:
848 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
849 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
850 break;
851 case ASIC_INTERNAL_SS_ON_HDMI:
852 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
853 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
854 break;
855 case ASIC_INTERNAL_SS_ON_LVDS:
856 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
857 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
858 break;
859 }
860 break;
861 case 9:
862 switch (id) {
863 case ASIC_INTERNAL_SS_ON_TMDS:
864 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage);
865 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz);
866 break;
867 case ASIC_INTERNAL_SS_ON_HDMI:
868 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage);
869 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz);
870 break;
871 case ASIC_INTERNAL_SS_ON_LVDS:
872 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage);
873 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz);
874 break;
875 }
876 break;
877 default:
878 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
879 break;
880 }
881 if (percentage)
882 ss->percentage = percentage;
883 if (rate)
884 ss->rate = rate;
885 }
886 }
887
888 union asic_ss_info {
889 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
890 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
891 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
892 };
893
894 union asic_ss_assignment {
895 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
896 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
897 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
898 };
899
amdgpu_atombios_get_asic_ss_info(struct amdgpu_device * adev,struct amdgpu_atom_ss * ss,int id,u32 clock)900 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
901 struct amdgpu_atom_ss *ss,
902 int id, u32 clock)
903 {
904 struct amdgpu_mode_info *mode_info = &adev->mode_info;
905 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
906 uint16_t data_offset, size;
907 union asic_ss_info *ss_info;
908 union asic_ss_assignment *ss_assign;
909 uint8_t frev, crev;
910 int i, num_indices;
911
912 if (id == ASIC_INTERNAL_MEMORY_SS) {
913 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
914 return false;
915 }
916 if (id == ASIC_INTERNAL_ENGINE_SS) {
917 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
918 return false;
919 }
920
921 memset(ss, 0, sizeof(struct amdgpu_atom_ss));
922 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
923 &frev, &crev, &data_offset)) {
924
925 ss_info =
926 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
927
928 switch (frev) {
929 case 1:
930 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
931 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
932
933 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
934 for (i = 0; i < num_indices; i++) {
935 if ((ss_assign->v1.ucClockIndication == id) &&
936 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
937 ss->percentage =
938 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
939 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
940 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
941 ss->percentage_divider = 100;
942 return true;
943 }
944 ss_assign = (union asic_ss_assignment *)
945 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
946 }
947 break;
948 case 2:
949 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
950 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
951 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
952 for (i = 0; i < num_indices; i++) {
953 if ((ss_assign->v2.ucClockIndication == id) &&
954 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
955 ss->percentage =
956 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
957 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
958 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
959 ss->percentage_divider = 100;
960 if ((crev == 2) &&
961 ((id == ASIC_INTERNAL_ENGINE_SS) ||
962 (id == ASIC_INTERNAL_MEMORY_SS)))
963 ss->rate /= 100;
964 return true;
965 }
966 ss_assign = (union asic_ss_assignment *)
967 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
968 }
969 break;
970 case 3:
971 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
972 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
973 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
974 for (i = 0; i < num_indices; i++) {
975 if ((ss_assign->v3.ucClockIndication == id) &&
976 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
977 ss->percentage =
978 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
979 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
980 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
981 if (ss_assign->v3.ucSpreadSpectrumMode &
982 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
983 ss->percentage_divider = 1000;
984 else
985 ss->percentage_divider = 100;
986 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
987 (id == ASIC_INTERNAL_MEMORY_SS))
988 ss->rate /= 100;
989 if (adev->flags & AMD_IS_APU)
990 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
991 return true;
992 }
993 ss_assign = (union asic_ss_assignment *)
994 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
995 }
996 break;
997 default:
998 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
999 break;
1000 }
1001
1002 }
1003 return false;
1004 }
1005
1006 union get_clock_dividers {
1007 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
1008 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
1009 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
1010 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
1011 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
1012 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
1013 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
1014 };
1015
amdgpu_atombios_get_clock_dividers(struct amdgpu_device * adev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)1016 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
1017 u8 clock_type,
1018 u32 clock,
1019 bool strobe_mode,
1020 struct atom_clock_dividers *dividers)
1021 {
1022 union get_clock_dividers args;
1023 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
1024 u8 frev, crev;
1025
1026 memset(&args, 0, sizeof(args));
1027 memset(dividers, 0, sizeof(struct atom_clock_dividers));
1028
1029 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1030 return -EINVAL;
1031
1032 switch (crev) {
1033 case 2:
1034 case 3:
1035 case 5:
1036 /* r6xx, r7xx, evergreen, ni, si.
1037 * TODO: add support for asic_type <= CHIP_RV770*/
1038 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
1039 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1040
1041 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1042 index, (uint32_t *)&args, sizeof(args)))
1043 return -EINVAL;
1044
1045 dividers->post_div = args.v3.ucPostDiv;
1046 dividers->enable_post_div = (args.v3.ucCntlFlag &
1047 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1048 dividers->enable_dithen = (args.v3.ucCntlFlag &
1049 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1050 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
1051 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
1052 dividers->ref_div = args.v3.ucRefDiv;
1053 dividers->vco_mode = (args.v3.ucCntlFlag &
1054 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1055 } else {
1056 /* for SI we use ComputeMemoryClockParam for memory plls */
1057 if (adev->asic_type >= CHIP_TAHITI)
1058 return -EINVAL;
1059 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
1060 if (strobe_mode)
1061 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
1062
1063 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1064 index, (uint32_t *)&args, sizeof(args)))
1065 return -EINVAL;
1066
1067 dividers->post_div = args.v5.ucPostDiv;
1068 dividers->enable_post_div = (args.v5.ucCntlFlag &
1069 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
1070 dividers->enable_dithen = (args.v5.ucCntlFlag &
1071 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
1072 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
1073 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
1074 dividers->ref_div = args.v5.ucRefDiv;
1075 dividers->vco_mode = (args.v5.ucCntlFlag &
1076 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
1077 }
1078 break;
1079 case 4:
1080 /* fusion */
1081 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
1082
1083 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1084 index, (uint32_t *)&args, sizeof(args)))
1085 return -EINVAL;
1086
1087 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
1088 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
1089 break;
1090 case 6:
1091 /* CI */
1092 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
1093 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
1094 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
1095
1096 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1097 index, (uint32_t *)&args, sizeof(args)))
1098 return -EINVAL;
1099
1100 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
1101 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
1102 dividers->ref_div = args.v6_out.ucPllRefDiv;
1103 dividers->post_div = args.v6_out.ucPllPostDiv;
1104 dividers->flags = args.v6_out.ucPllCntlFlag;
1105 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
1106 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
1107 break;
1108 default:
1109 return -EINVAL;
1110 }
1111 return 0;
1112 }
1113
1114 #ifdef CONFIG_DRM_AMDGPU_SI
amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device * adev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)1115 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
1116 u32 clock,
1117 bool strobe_mode,
1118 struct atom_mpll_param *mpll_param)
1119 {
1120 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
1121 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
1122 u8 frev, crev;
1123
1124 memset(&args, 0, sizeof(args));
1125 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
1126
1127 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1128 return -EINVAL;
1129
1130 switch (frev) {
1131 case 2:
1132 switch (crev) {
1133 case 1:
1134 /* SI */
1135 args.ulClock = cpu_to_le32(clock); /* 10 khz */
1136 args.ucInputFlag = 0;
1137 if (strobe_mode)
1138 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
1139
1140 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1141 index, (uint32_t *)&args, sizeof(args)))
1142 return -EINVAL;
1143
1144 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
1145 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
1146 mpll_param->post_div = args.ucPostDiv;
1147 mpll_param->dll_speed = args.ucDllSpeed;
1148 mpll_param->bwcntl = args.ucBWCntl;
1149 mpll_param->vco_mode =
1150 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
1151 mpll_param->yclk_sel =
1152 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
1153 mpll_param->qdr =
1154 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
1155 mpll_param->half_rate =
1156 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161 break;
1162 default:
1163 return -EINVAL;
1164 }
1165 return 0;
1166 }
1167
amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device * adev,u32 eng_clock,u32 mem_clock)1168 int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev,
1169 u32 eng_clock, u32 mem_clock)
1170 {
1171 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1172 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
1173 u32 tmp;
1174
1175 memset(&args, 0, sizeof(args));
1176
1177 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
1178 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
1179
1180 args.ulTargetEngineClock = cpu_to_le32(tmp);
1181 if (mem_clock)
1182 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
1183
1184 return amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
1185 (uint32_t *)&args, sizeof(args));
1186 }
1187
amdgpu_atombios_get_default_voltages(struct amdgpu_device * adev,u16 * vddc,u16 * vddci,u16 * mvdd)1188 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
1189 u16 *vddc, u16 *vddci, u16 *mvdd)
1190 {
1191 struct amdgpu_mode_info *mode_info = &adev->mode_info;
1192 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1193 u8 frev, crev;
1194 u16 data_offset;
1195 union firmware_info *firmware_info;
1196
1197 *vddc = 0;
1198 *vddci = 0;
1199 *mvdd = 0;
1200
1201 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
1202 &frev, &crev, &data_offset)) {
1203 firmware_info =
1204 (union firmware_info *)(mode_info->atom_context->bios +
1205 data_offset);
1206 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
1207 if ((frev == 2) && (crev >= 2)) {
1208 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
1209 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
1210 }
1211 }
1212 }
1213
1214 union set_voltage {
1215 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
1216 struct _SET_VOLTAGE_PARAMETERS v1;
1217 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
1218 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
1219 };
1220
amdgpu_atombios_get_max_vddc(struct amdgpu_device * adev,u8 voltage_type,u16 voltage_id,u16 * voltage)1221 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
1222 u16 voltage_id, u16 *voltage)
1223 {
1224 union set_voltage args;
1225 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
1226 u8 frev, crev;
1227
1228 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
1229 return -EINVAL;
1230
1231 switch (crev) {
1232 case 1:
1233 return -EINVAL;
1234 case 2:
1235 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
1236 args.v2.ucVoltageMode = 0;
1237 args.v2.usVoltageLevel = 0;
1238
1239 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1240 index, (uint32_t *)&args, sizeof(args)))
1241 return -EINVAL;
1242
1243 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
1244 break;
1245 case 3:
1246 args.v3.ucVoltageType = voltage_type;
1247 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
1248 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
1249
1250 if (amdgpu_atom_execute_table(adev->mode_info.atom_context,
1251 index, (uint32_t *)&args, sizeof(args)))
1252 return -EINVAL;
1253
1254 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
1255 break;
1256 default:
1257 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1258 return -EINVAL;
1259 }
1260
1261 return 0;
1262 }
1263
amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device * adev,u16 * voltage,u16 leakage_idx)1264 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
1265 u16 *voltage,
1266 u16 leakage_idx)
1267 {
1268 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
1269 }
1270
1271 union voltage_object_info {
1272 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
1273 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
1274 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
1275 };
1276
1277 union voltage_object {
1278 struct _ATOM_VOLTAGE_OBJECT v1;
1279 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
1280 union _ATOM_VOLTAGE_OBJECT_V3 v3;
1281 };
1282
1283
amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)1284 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
1285 u8 voltage_type, u8 voltage_mode)
1286 {
1287 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
1288 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
1289 u8 *start = (u8 *)v3;
1290
1291 while (offset < size) {
1292 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
1293 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
1294 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
1295 return vo;
1296 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
1297 }
1298 return NULL;
1299 }
1300
amdgpu_atombios_get_svi2_info(struct amdgpu_device * adev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)1301 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
1302 u8 voltage_type,
1303 u8 *svd_gpio_id, u8 *svc_gpio_id)
1304 {
1305 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1306 u8 frev, crev;
1307 u16 data_offset, size;
1308 union voltage_object_info *voltage_info;
1309 union voltage_object *voltage_object = NULL;
1310
1311 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1312 &frev, &crev, &data_offset)) {
1313 voltage_info = (union voltage_object_info *)
1314 (adev->mode_info.atom_context->bios + data_offset);
1315
1316 switch (frev) {
1317 case 3:
1318 switch (crev) {
1319 case 1:
1320 voltage_object = (union voltage_object *)
1321 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1322 voltage_type,
1323 VOLTAGE_OBJ_SVID2);
1324 if (voltage_object) {
1325 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
1326 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
1327 } else {
1328 return -EINVAL;
1329 }
1330 break;
1331 default:
1332 DRM_ERROR("unknown voltage object table\n");
1333 return -EINVAL;
1334 }
1335 break;
1336 default:
1337 DRM_ERROR("unknown voltage object table\n");
1338 return -EINVAL;
1339 }
1340
1341 }
1342 return 0;
1343 }
1344
1345 bool
amdgpu_atombios_is_voltage_gpio(struct amdgpu_device * adev,u8 voltage_type,u8 voltage_mode)1346 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,
1347 u8 voltage_type, u8 voltage_mode)
1348 {
1349 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1350 u8 frev, crev;
1351 u16 data_offset, size;
1352 union voltage_object_info *voltage_info;
1353
1354 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1355 &frev, &crev, &data_offset)) {
1356 voltage_info = (union voltage_object_info *)
1357 (adev->mode_info.atom_context->bios + data_offset);
1358
1359 switch (frev) {
1360 case 3:
1361 switch (crev) {
1362 case 1:
1363 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1364 voltage_type, voltage_mode))
1365 return true;
1366 break;
1367 default:
1368 DRM_ERROR("unknown voltage object table\n");
1369 return false;
1370 }
1371 break;
1372 default:
1373 DRM_ERROR("unknown voltage object table\n");
1374 return false;
1375 }
1376
1377 }
1378 return false;
1379 }
1380
amdgpu_atombios_get_voltage_table(struct amdgpu_device * adev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)1381 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev,
1382 u8 voltage_type, u8 voltage_mode,
1383 struct atom_voltage_table *voltage_table)
1384 {
1385 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
1386 u8 frev, crev;
1387 u16 data_offset, size;
1388 int i;
1389 union voltage_object_info *voltage_info;
1390 union voltage_object *voltage_object = NULL;
1391
1392 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1393 &frev, &crev, &data_offset)) {
1394 voltage_info = (union voltage_object_info *)
1395 (adev->mode_info.atom_context->bios + data_offset);
1396
1397 switch (frev) {
1398 case 3:
1399 switch (crev) {
1400 case 1:
1401 voltage_object = (union voltage_object *)
1402 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,
1403 voltage_type, voltage_mode);
1404 if (voltage_object) {
1405 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
1406 &voltage_object->v3.asGpioVoltageObj;
1407 VOLTAGE_LUT_ENTRY_V2 *lut;
1408 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
1409 return -EINVAL;
1410 lut = &gpio->asVolGpioLut[0];
1411 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
1412 voltage_table->entries[i].value =
1413 le16_to_cpu(lut->usVoltageValue);
1414 voltage_table->entries[i].smio_low =
1415 le32_to_cpu(lut->ulVoltageId);
1416 lut = (VOLTAGE_LUT_ENTRY_V2 *)
1417 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
1418 }
1419 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
1420 voltage_table->count = gpio->ucGpioEntryNum;
1421 voltage_table->phase_delay = gpio->ucPhaseDelay;
1422 return 0;
1423 }
1424 break;
1425 default:
1426 DRM_ERROR("unknown voltage object table\n");
1427 return -EINVAL;
1428 }
1429 break;
1430 default:
1431 DRM_ERROR("unknown voltage object table\n");
1432 return -EINVAL;
1433 }
1434 }
1435 return -EINVAL;
1436 }
1437
1438 union vram_info {
1439 struct _ATOM_VRAM_INFO_V3 v1_3;
1440 struct _ATOM_VRAM_INFO_V4 v1_4;
1441 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
1442 };
1443
1444 #define MEM_ID_MASK 0xff000000
1445 #define MEM_ID_SHIFT 24
1446 #define CLOCK_RANGE_MASK 0x00ffffff
1447 #define CLOCK_RANGE_SHIFT 0
1448 #define LOW_NIBBLE_MASK 0xf
1449 #define DATA_EQU_PREV 0
1450 #define DATA_FROM_TABLE 4
1451
amdgpu_atombios_init_mc_reg_table(struct amdgpu_device * adev,u8 module_index,struct atom_mc_reg_table * reg_table)1452 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
1453 u8 module_index,
1454 struct atom_mc_reg_table *reg_table)
1455 {
1456 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
1457 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
1458 u32 i = 0, j;
1459 u16 data_offset, size;
1460 union vram_info *vram_info;
1461
1462 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
1463
1464 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1465 &frev, &crev, &data_offset)) {
1466 vram_info = (union vram_info *)
1467 (adev->mode_info.atom_context->bios + data_offset);
1468 switch (frev) {
1469 case 1:
1470 DRM_ERROR("old table version %d, %d\n", frev, crev);
1471 return -EINVAL;
1472 case 2:
1473 switch (crev) {
1474 case 1:
1475 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
1476 ATOM_INIT_REG_BLOCK *reg_block =
1477 (ATOM_INIT_REG_BLOCK *)
1478 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
1479 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
1480 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1481 ((u8 *)reg_block + (2 * sizeof(u16)) +
1482 le16_to_cpu(reg_block->usRegIndexTblSize));
1483 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
1484 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
1485 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
1486 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
1487 return -EINVAL;
1488 while (i < num_entries) {
1489 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
1490 break;
1491 reg_table->mc_reg_address[i].s1 =
1492 (u16)(le16_to_cpu(format->usRegIndex));
1493 reg_table->mc_reg_address[i].pre_reg_data =
1494 (u8)(format->ucPreRegDataLength);
1495 i++;
1496 format = (ATOM_INIT_REG_INDEX_FORMAT *)
1497 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
1498 }
1499 reg_table->last = i;
1500 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
1501 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
1502 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
1503 >> MEM_ID_SHIFT);
1504 if (module_index == t_mem_id) {
1505 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
1506 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
1507 >> CLOCK_RANGE_SHIFT);
1508 for (i = 0, j = 1; i < reg_table->last; i++) {
1509 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
1510 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1511 (u32)le32_to_cpu(*((u32 *)reg_data + j));
1512 j++;
1513 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
1514 if (i == 0)
1515 continue;
1516 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
1517 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
1518 }
1519 }
1520 num_ranges++;
1521 }
1522 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
1523 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
1524 }
1525 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
1526 return -EINVAL;
1527 reg_table->num_entries = num_ranges;
1528 } else
1529 return -EINVAL;
1530 break;
1531 default:
1532 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1533 return -EINVAL;
1534 }
1535 break;
1536 default:
1537 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1538 return -EINVAL;
1539 }
1540 return 0;
1541 }
1542 return -EINVAL;
1543 }
1544 #endif
1545
amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device * adev)1546 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
1547 {
1548 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo);
1549 u8 frev, crev;
1550 u16 data_offset, size;
1551
1552 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
1553 &frev, &crev, &data_offset))
1554 return true;
1555
1556 return false;
1557 }
1558
amdgpu_atombios_scratch_regs_lock(struct amdgpu_device * adev,bool lock)1559 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock)
1560 {
1561 uint32_t bios_6_scratch;
1562
1563 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1564
1565 if (lock) {
1566 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
1567 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
1568 } else {
1569 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
1570 bios_6_scratch |= ATOM_S6_ACC_MODE;
1571 }
1572
1573 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1574 }
1575
amdgpu_atombios_scratch_regs_init(struct amdgpu_device * adev)1576 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev)
1577 {
1578 uint32_t bios_2_scratch, bios_6_scratch;
1579
1580 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0;
1581
1582 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
1583 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
1584
1585 /* let the bios control the backlight */
1586 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1587
1588 /* tell the bios not to handle mode switching */
1589 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
1590
1591 /* clear the vbios dpms state */
1592 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
1593
1594 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);
1595 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);
1596 }
1597
amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device * adev,bool hung)1598 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev,
1599 bool hung)
1600 {
1601 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
1602
1603 if (hung)
1604 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1605 else
1606 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1607
1608 WREG32(adev->bios_scratch_reg_offset + 3, tmp);
1609 }
1610
amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device * adev,u32 backlight_level)1611 void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev,
1612 u32 backlight_level)
1613 {
1614 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 2);
1615
1616 tmp &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
1617 tmp |= (backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
1618 ATOM_S2_CURRENT_BL_LEVEL_MASK;
1619
1620 WREG32(adev->bios_scratch_reg_offset + 2, tmp);
1621 }
1622
amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device * adev)1623 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev)
1624 {
1625 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
1626
1627 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK)
1628 return false;
1629 else
1630 return true;
1631 }
1632
1633 /* Atom needs data in little endian format so swap as appropriate when copying
1634 * data to or from atom. Note that atom operates on dw units.
1635 *
1636 * Use to_le=true when sending data to atom and provide at least
1637 * ALIGN(num_bytes,4) bytes in the dst buffer.
1638 *
1639 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4)
1640 * byes in the src buffer.
1641 */
amdgpu_atombios_copy_swap(u8 * dst,u8 * src,u8 num_bytes,bool to_le)1642 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
1643 {
1644 #ifdef __BIG_ENDIAN
1645 u32 src_tmp[5], dst_tmp[5];
1646 int i;
1647 u8 align_num_bytes = ALIGN(num_bytes, 4);
1648
1649 if (to_le) {
1650 memcpy(src_tmp, src, num_bytes);
1651 for (i = 0; i < align_num_bytes / 4; i++)
1652 dst_tmp[i] = cpu_to_le32(src_tmp[i]);
1653 memcpy(dst, dst_tmp, align_num_bytes);
1654 } else {
1655 memcpy(src_tmp, src, align_num_bytes);
1656 for (i = 0; i < align_num_bytes / 4; i++)
1657 dst_tmp[i] = le32_to_cpu(src_tmp[i]);
1658 memcpy(dst, dst_tmp, num_bytes);
1659 }
1660 #else
1661 memcpy(dst, src, num_bytes);
1662 #endif
1663 }
1664
amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device * adev)1665 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)
1666 {
1667 struct atom_context *ctx = adev->mode_info.atom_context;
1668 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
1669 uint16_t data_offset;
1670 int usage_bytes = 0;
1671 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
1672 u64 start_addr;
1673 u64 size;
1674
1675 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
1676 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
1677
1678 DRM_DEBUG("atom firmware requested %08x %dkb\n",
1679 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
1680 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
1681
1682 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware;
1683 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb;
1684
1685 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
1686 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
1687 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
1688 /* Firmware request VRAM reservation for SR-IOV */
1689 adev->mman.fw_vram_usage_start_offset = (start_addr &
1690 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
1691 adev->mman.fw_vram_usage_size = size << 10;
1692 /* Use the default scratch size */
1693 usage_bytes = 0;
1694 } else {
1695 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
1696 }
1697 }
1698 ctx->scratch_size_bytes = 0;
1699 if (usage_bytes == 0)
1700 usage_bytes = 20 * 1024;
1701 /* allocate some scratch memory */
1702 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
1703 if (!ctx->scratch)
1704 return -ENOMEM;
1705 ctx->scratch_size_bytes = usage_bytes;
1706 return 0;
1707 }
1708
1709 /* ATOM accessor methods */
1710 /*
1711 * ATOM is an interpreted byte code stored in tables in the vbios. The
1712 * driver registers callbacks to access registers and the interpreter
1713 * in the driver parses the tables and executes then to program specific
1714 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
1715 * atombios.h, and atom.c
1716 */
1717
1718 /**
1719 * cail_pll_read - read PLL register
1720 *
1721 * @info: atom card_info pointer
1722 * @reg: PLL register offset
1723 *
1724 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1725 * Returns the value of the PLL register.
1726 */
cail_pll_read(struct card_info * info,uint32_t reg)1727 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
1728 {
1729 return 0;
1730 }
1731
1732 /**
1733 * cail_pll_write - write PLL register
1734 *
1735 * @info: atom card_info pointer
1736 * @reg: PLL register offset
1737 * @val: value to write to the pll register
1738 *
1739 * Provides a PLL register accessor for the atom interpreter (r4xx+).
1740 */
cail_pll_write(struct card_info * info,uint32_t reg,uint32_t val)1741 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
1742 {
1743
1744 }
1745
1746 /**
1747 * cail_mc_read - read MC (Memory Controller) register
1748 *
1749 * @info: atom card_info pointer
1750 * @reg: MC register offset
1751 *
1752 * Provides an MC register accessor for the atom interpreter (r4xx+).
1753 * Returns the value of the MC register.
1754 */
cail_mc_read(struct card_info * info,uint32_t reg)1755 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
1756 {
1757 return 0;
1758 }
1759
1760 /**
1761 * cail_mc_write - write MC (Memory Controller) register
1762 *
1763 * @info: atom card_info pointer
1764 * @reg: MC register offset
1765 * @val: value to write to the pll register
1766 *
1767 * Provides a MC register accessor for the atom interpreter (r4xx+).
1768 */
cail_mc_write(struct card_info * info,uint32_t reg,uint32_t val)1769 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
1770 {
1771
1772 }
1773
1774 /**
1775 * cail_reg_write - write MMIO register
1776 *
1777 * @info: atom card_info pointer
1778 * @reg: MMIO register offset
1779 * @val: value to write to the pll register
1780 *
1781 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
1782 */
cail_reg_write(struct card_info * info,uint32_t reg,uint32_t val)1783 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
1784 {
1785 struct amdgpu_device *adev = drm_to_adev(info->dev);
1786
1787 WREG32(reg, val);
1788 }
1789
1790 /**
1791 * cail_reg_read - read MMIO register
1792 *
1793 * @info: atom card_info pointer
1794 * @reg: MMIO register offset
1795 *
1796 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
1797 * Returns the value of the MMIO register.
1798 */
cail_reg_read(struct card_info * info,uint32_t reg)1799 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
1800 {
1801 struct amdgpu_device *adev = drm_to_adev(info->dev);
1802 uint32_t r;
1803
1804 r = RREG32(reg);
1805 return r;
1806 }
1807
amdgpu_atombios_get_vbios_version(struct device * dev,struct device_attribute * attr,char * buf)1808 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1809 struct device_attribute *attr,
1810 char *buf)
1811 {
1812 struct drm_device *ddev = dev_get_drvdata(dev);
1813 struct amdgpu_device *adev = drm_to_adev(ddev);
1814 struct atom_context *ctx = adev->mode_info.atom_context;
1815
1816 return sysfs_emit(buf, "%s\n", ctx->vbios_pn);
1817 }
1818
1819 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1820 NULL);
1821
1822 static struct attribute *amdgpu_vbios_version_attrs[] = {
1823 &dev_attr_vbios_version.attr,
1824 NULL
1825 };
1826
1827 const struct attribute_group amdgpu_vbios_version_attr_group = {
1828 .attrs = amdgpu_vbios_version_attrs
1829 };
1830
amdgpu_atombios_sysfs_init(struct amdgpu_device * adev)1831 int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev)
1832 {
1833 if (adev->mode_info.atom_context)
1834 return devm_device_add_group(adev->dev,
1835 &amdgpu_vbios_version_attr_group);
1836
1837 return 0;
1838 }
1839
1840 /**
1841 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1842 *
1843 * @adev: amdgpu_device pointer
1844 *
1845 * Frees the driver info and register access callbacks for the ATOM
1846 * interpreter (r4xx+).
1847 * Called at driver shutdown.
1848 */
amdgpu_atombios_fini(struct amdgpu_device * adev)1849 void amdgpu_atombios_fini(struct amdgpu_device *adev)
1850 {
1851 if (adev->mode_info.atom_context) {
1852 kfree(adev->mode_info.atom_context->scratch);
1853 kfree(adev->mode_info.atom_context->iio);
1854 }
1855 kfree(adev->mode_info.atom_context);
1856 adev->mode_info.atom_context = NULL;
1857 kfree(adev->mode_info.atom_card_info);
1858 adev->mode_info.atom_card_info = NULL;
1859 }
1860
1861 /**
1862 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1863 *
1864 * @adev: amdgpu_device pointer
1865 *
1866 * Initializes the driver info and register access callbacks for the
1867 * ATOM interpreter (r4xx+).
1868 * Returns 0 on sucess, -ENOMEM on failure.
1869 * Called at driver startup.
1870 */
amdgpu_atombios_init(struct amdgpu_device * adev)1871 int amdgpu_atombios_init(struct amdgpu_device *adev)
1872 {
1873 struct card_info *atom_card_info =
1874 kzalloc(sizeof(struct card_info), GFP_KERNEL);
1875
1876 if (!atom_card_info)
1877 return -ENOMEM;
1878
1879 adev->mode_info.atom_card_info = atom_card_info;
1880 atom_card_info->dev = adev_to_drm(adev);
1881 atom_card_info->reg_read = cail_reg_read;
1882 atom_card_info->reg_write = cail_reg_write;
1883 atom_card_info->mc_read = cail_mc_read;
1884 atom_card_info->mc_write = cail_mc_write;
1885 atom_card_info->pll_read = cail_pll_read;
1886 atom_card_info->pll_write = cail_pll_write;
1887
1888 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1889 if (!adev->mode_info.atom_context) {
1890 amdgpu_atombios_fini(adev);
1891 return -ENOMEM;
1892 }
1893
1894 mutex_init(&adev->mode_info.atom_context->mutex);
1895 if (adev->is_atom_fw) {
1896 amdgpu_atomfirmware_scratch_regs_init(adev);
1897 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1898 /* cached firmware_flags for further usage */
1899 adev->mode_info.firmware_flags =
1900 amdgpu_atomfirmware_query_firmware_capability(adev);
1901 } else {
1902 amdgpu_atombios_scratch_regs_init(adev);
1903 amdgpu_atombios_allocate_fb_scratch(adev);
1904 }
1905
1906 return 0;
1907 }
1908
amdgpu_atombios_get_data_table(struct amdgpu_device * adev,uint32_t table,uint16_t * size,uint8_t * frev,uint8_t * crev,uint8_t ** addr)1909 int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
1910 uint32_t table,
1911 uint16_t *size,
1912 uint8_t *frev,
1913 uint8_t *crev,
1914 uint8_t **addr)
1915 {
1916 uint16_t data_start;
1917
1918 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, table,
1919 size, frev, crev, &data_start))
1920 return -EINVAL;
1921
1922 *addr = (uint8_t *)adev->mode_info.atom_context->bios + data_start;
1923
1924 return 0;
1925 }
1926