1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
4 * Author: Sugar <shuge@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dmapool.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_dma.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/string_choices.h>
23 #include <linux/types.h>
24
25 #include "virt-dma.h"
26
27 /*
28 * Common registers
29 */
30 #define DMA_IRQ_EN(x) ((x) * 0x04)
31 #define DMA_IRQ_HALF BIT(0)
32 #define DMA_IRQ_PKG BIT(1)
33 #define DMA_IRQ_QUEUE BIT(2)
34
35 #define DMA_IRQ_CHAN_NR 8
36 #define DMA_IRQ_CHAN_WIDTH 4
37
38
39 #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10)
40
41 #define DMA_STAT 0x30
42
43 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */
44 #define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4)
45
46 /*
47 * sun8i specific registers
48 */
49 #define SUN8I_DMA_GATE 0x20
50 #define SUN8I_DMA_GATE_ENABLE 0x4
51
52 #define SUNXI_H3_SECURE_REG 0x20
53 #define SUNXI_H3_DMA_GATE 0x28
54 #define SUNXI_H3_DMA_GATE_ENABLE 0x4
55 /*
56 * Channels specific registers
57 */
58 #define DMA_CHAN_ENABLE 0x00
59 #define DMA_CHAN_ENABLE_START BIT(0)
60 #define DMA_CHAN_ENABLE_STOP 0
61
62 #define DMA_CHAN_PAUSE 0x04
63 #define DMA_CHAN_PAUSE_PAUSE BIT(1)
64 #define DMA_CHAN_PAUSE_RESUME 0
65
66 #define DMA_CHAN_LLI_ADDR 0x08
67
68 #define DMA_CHAN_CUR_CFG 0x0c
69 #define DMA_CHAN_MAX_DRQ_A31 0x1f
70 #define DMA_CHAN_MAX_DRQ_H6 0x3f
71 #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31)
72 #define DMA_CHAN_CFG_SRC_DRQ_H6(x) ((x) & DMA_CHAN_MAX_DRQ_H6)
73 #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5)
74 #define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8)
75 #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7)
76 #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6)
77 #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9)
78
79 #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16)
80 #define DMA_CHAN_CFG_DST_DRQ_H6(x) (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16)
81 #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16)
82 #define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16)
83 #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)
84 #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)
85 #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16)
86
87 #define DMA_CHAN_CUR_SRC 0x10
88
89 #define DMA_CHAN_CUR_DST 0x14
90
91 #define DMA_CHAN_CUR_CNT 0x18
92
93 #define DMA_CHAN_CUR_PARA 0x1c
94
95 /*
96 * LLI address mangling
97 *
98 * The LLI link physical address is also mangled, but we avoid dealing
99 * with that by allocating LLIs from the DMA32 zone.
100 */
101 #define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16)
102 #define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18)
103
104 /*
105 * Various hardware related defines
106 */
107 #define LLI_LAST_ITEM 0xfffff800
108 #define NORMAL_WAIT 8
109 #define DRQ_SDRAM 1
110 #define LINEAR_MODE 0
111 #define IO_MODE 1
112
113 /* forward declaration */
114 struct sun6i_dma_dev;
115
116 /*
117 * Hardware channels / ports representation
118 *
119 * The hardware is used in several SoCs, with differing numbers
120 * of channels and endpoints. This structure ties those numbers
121 * to a certain compatible string.
122 */
123 struct sun6i_dma_config {
124 u32 nr_max_channels;
125 u32 nr_max_requests;
126 u32 nr_max_vchans;
127 /*
128 * In the datasheets/user manuals of newer Allwinner SoCs, a special
129 * bit (bit 2 at register 0x20) is present.
130 * It's named "DMA MCLK interface circuit auto gating bit" in the
131 * documents, and the footnote of this register says that this bit
132 * should be set up when initializing the DMA controller.
133 * Allwinner A23/A33 user manuals do not have this bit documented,
134 * however these SoCs really have and need this bit, as seen in the
135 * BSP kernel source code.
136 */
137 void (*clock_autogate_enable)(struct sun6i_dma_dev *);
138 void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
139 void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
140 void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
141 u32 src_burst_lengths;
142 u32 dst_burst_lengths;
143 u32 src_addr_widths;
144 u32 dst_addr_widths;
145 bool has_high_addr;
146 bool has_mbus_clk;
147 };
148
149 /*
150 * Hardware representation of the LLI
151 *
152 * The hardware will be fed the physical address of this structure,
153 * and read its content in order to start the transfer.
154 */
155 struct sun6i_dma_lli {
156 u32 cfg;
157 u32 src;
158 u32 dst;
159 u32 len;
160 u32 para;
161 u32 p_lli_next;
162
163 /*
164 * This field is not used by the DMA controller, but will be
165 * used by the CPU to go through the list (mostly for dumping
166 * or freeing it).
167 */
168 struct sun6i_dma_lli *v_lli_next;
169 };
170
171
172 struct sun6i_desc {
173 struct virt_dma_desc vd;
174 dma_addr_t p_lli;
175 struct sun6i_dma_lli *v_lli;
176 };
177
178 struct sun6i_pchan {
179 u32 idx;
180 void __iomem *base;
181 struct sun6i_vchan *vchan;
182 struct sun6i_desc *desc;
183 struct sun6i_desc *done;
184 };
185
186 struct sun6i_vchan {
187 struct virt_dma_chan vc;
188 struct list_head node;
189 struct dma_slave_config cfg;
190 struct sun6i_pchan *phy;
191 u8 port;
192 u8 irq_type;
193 bool cyclic;
194 };
195
196 struct sun6i_dma_dev {
197 struct dma_device slave;
198 void __iomem *base;
199 struct clk *clk;
200 struct clk *clk_mbus;
201 int irq;
202 spinlock_t lock;
203 struct reset_control *rstc;
204 struct tasklet_struct task;
205 atomic_t tasklet_shutdown;
206 struct list_head pending;
207 struct dma_pool *pool;
208 struct sun6i_pchan *pchans;
209 struct sun6i_vchan *vchans;
210 const struct sun6i_dma_config *cfg;
211 u32 num_pchans;
212 u32 num_vchans;
213 u32 max_request;
214 };
215
chan2dev(struct dma_chan * chan)216 static struct device *chan2dev(struct dma_chan *chan)
217 {
218 return &chan->dev->device;
219 }
220
to_sun6i_dma_dev(struct dma_device * d)221 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d)
222 {
223 return container_of(d, struct sun6i_dma_dev, slave);
224 }
225
to_sun6i_vchan(struct dma_chan * chan)226 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan)
227 {
228 return container_of(chan, struct sun6i_vchan, vc.chan);
229 }
230
231 static inline struct sun6i_desc *
to_sun6i_desc(struct dma_async_tx_descriptor * tx)232 to_sun6i_desc(struct dma_async_tx_descriptor *tx)
233 {
234 return container_of(tx, struct sun6i_desc, vd.tx);
235 }
236
sun6i_dma_dump_com_regs(struct sun6i_dma_dev * sdev)237 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev)
238 {
239 dev_dbg(sdev->slave.dev, "Common register:\n"
240 "\tmask0(%04x): 0x%08x\n"
241 "\tmask1(%04x): 0x%08x\n"
242 "\tpend0(%04x): 0x%08x\n"
243 "\tpend1(%04x): 0x%08x\n"
244 "\tstats(%04x): 0x%08x\n",
245 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)),
246 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)),
247 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)),
248 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)),
249 DMA_STAT, readl(sdev->base + DMA_STAT));
250 }
251
sun6i_dma_dump_chan_regs(struct sun6i_dma_dev * sdev,struct sun6i_pchan * pchan)252 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev,
253 struct sun6i_pchan *pchan)
254 {
255 dev_dbg(sdev->slave.dev, "Chan %d reg:\n"
256 "\t___en(%04x): \t0x%08x\n"
257 "\tpause(%04x): \t0x%08x\n"
258 "\tstart(%04x): \t0x%08x\n"
259 "\t__cfg(%04x): \t0x%08x\n"
260 "\t__src(%04x): \t0x%08x\n"
261 "\t__dst(%04x): \t0x%08x\n"
262 "\tcount(%04x): \t0x%08x\n"
263 "\t_para(%04x): \t0x%08x\n\n",
264 pchan->idx,
265 DMA_CHAN_ENABLE,
266 readl(pchan->base + DMA_CHAN_ENABLE),
267 DMA_CHAN_PAUSE,
268 readl(pchan->base + DMA_CHAN_PAUSE),
269 DMA_CHAN_LLI_ADDR,
270 readl(pchan->base + DMA_CHAN_LLI_ADDR),
271 DMA_CHAN_CUR_CFG,
272 readl(pchan->base + DMA_CHAN_CUR_CFG),
273 DMA_CHAN_CUR_SRC,
274 readl(pchan->base + DMA_CHAN_CUR_SRC),
275 DMA_CHAN_CUR_DST,
276 readl(pchan->base + DMA_CHAN_CUR_DST),
277 DMA_CHAN_CUR_CNT,
278 readl(pchan->base + DMA_CHAN_CUR_CNT),
279 DMA_CHAN_CUR_PARA,
280 readl(pchan->base + DMA_CHAN_CUR_PARA));
281 }
282
convert_burst(u32 maxburst)283 static inline s8 convert_burst(u32 maxburst)
284 {
285 switch (maxburst) {
286 case 1:
287 return 0;
288 case 4:
289 return 1;
290 case 8:
291 return 2;
292 case 16:
293 return 3;
294 default:
295 return -EINVAL;
296 }
297 }
298
convert_buswidth(enum dma_slave_buswidth addr_width)299 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
300 {
301 return ilog2(addr_width);
302 }
303
sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev * sdev)304 static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev)
305 {
306 writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
307 }
308
sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev * sdev)309 static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev)
310 {
311 writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
312 }
313
sun6i_set_burst_length_a31(u32 * p_cfg,s8 src_burst,s8 dst_burst)314 static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst)
315 {
316 *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |
317 DMA_CHAN_CFG_DST_BURST_A31(dst_burst);
318 }
319
sun6i_set_burst_length_h3(u32 * p_cfg,s8 src_burst,s8 dst_burst)320 static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst)
321 {
322 *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |
323 DMA_CHAN_CFG_DST_BURST_H3(dst_burst);
324 }
325
sun6i_set_drq_a31(u32 * p_cfg,s8 src_drq,s8 dst_drq)326 static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq)
327 {
328 *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) |
329 DMA_CHAN_CFG_DST_DRQ_A31(dst_drq);
330 }
331
sun6i_set_drq_h6(u32 * p_cfg,s8 src_drq,s8 dst_drq)332 static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq)
333 {
334 *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) |
335 DMA_CHAN_CFG_DST_DRQ_H6(dst_drq);
336 }
337
sun6i_set_mode_a31(u32 * p_cfg,s8 src_mode,s8 dst_mode)338 static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode)
339 {
340 *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) |
341 DMA_CHAN_CFG_DST_MODE_A31(dst_mode);
342 }
343
sun6i_set_mode_h6(u32 * p_cfg,s8 src_mode,s8 dst_mode)344 static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode)
345 {
346 *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) |
347 DMA_CHAN_CFG_DST_MODE_H6(dst_mode);
348 }
349
sun6i_get_chan_size(struct sun6i_pchan * pchan)350 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
351 {
352 struct sun6i_desc *txd = pchan->desc;
353 struct sun6i_dma_lli *lli;
354 size_t bytes;
355 dma_addr_t pos;
356
357 pos = readl(pchan->base + DMA_CHAN_LLI_ADDR);
358 bytes = readl(pchan->base + DMA_CHAN_CUR_CNT);
359
360 if (pos == LLI_LAST_ITEM)
361 return bytes;
362
363 for (lli = txd->v_lli; lli; lli = lli->v_lli_next) {
364 if (lli->p_lli_next == pos) {
365 for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next)
366 bytes += lli->len;
367 break;
368 }
369 }
370
371 return bytes;
372 }
373
sun6i_dma_lli_add(struct sun6i_dma_lli * prev,struct sun6i_dma_lli * next,dma_addr_t next_phy,struct sun6i_desc * txd)374 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev,
375 struct sun6i_dma_lli *next,
376 dma_addr_t next_phy,
377 struct sun6i_desc *txd)
378 {
379 if ((!prev && !txd) || !next)
380 return NULL;
381
382 if (!prev) {
383 txd->p_lli = next_phy;
384 txd->v_lli = next;
385 } else {
386 prev->p_lli_next = next_phy;
387 prev->v_lli_next = next;
388 }
389
390 next->p_lli_next = LLI_LAST_ITEM;
391 next->v_lli_next = NULL;
392
393 return next;
394 }
395
sun6i_dma_dump_lli(struct sun6i_vchan * vchan,struct sun6i_dma_lli * v_lli,dma_addr_t p_lli)396 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan,
397 struct sun6i_dma_lli *v_lli,
398 dma_addr_t p_lli)
399 {
400 dev_dbg(chan2dev(&vchan->vc.chan),
401 "\n\tdesc:\tp - %pad v - 0x%p\n"
402 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n"
403 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n",
404 &p_lli, v_lli,
405 v_lli->cfg, v_lli->src, v_lli->dst,
406 v_lli->len, v_lli->para, v_lli->p_lli_next);
407 }
408
sun6i_dma_free_desc(struct virt_dma_desc * vd)409 static void sun6i_dma_free_desc(struct virt_dma_desc *vd)
410 {
411 struct sun6i_desc *txd = to_sun6i_desc(&vd->tx);
412 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device);
413 struct sun6i_dma_lli *v_lli, *v_next;
414 dma_addr_t p_lli, p_next;
415
416 if (unlikely(!txd))
417 return;
418
419 p_lli = txd->p_lli;
420 v_lli = txd->v_lli;
421
422 while (v_lli) {
423 v_next = v_lli->v_lli_next;
424 p_next = v_lli->p_lli_next;
425
426 dma_pool_free(sdev->pool, v_lli, p_lli);
427
428 v_lli = v_next;
429 p_lli = p_next;
430 }
431
432 kfree(txd);
433 }
434
sun6i_dma_start_desc(struct sun6i_vchan * vchan)435 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan)
436 {
437 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device);
438 struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc);
439 struct sun6i_pchan *pchan = vchan->phy;
440 u32 irq_val, irq_reg, irq_offset;
441
442 if (!pchan)
443 return -EAGAIN;
444
445 if (!desc) {
446 pchan->desc = NULL;
447 pchan->done = NULL;
448 return -EAGAIN;
449 }
450
451 list_del(&desc->node);
452
453 pchan->desc = to_sun6i_desc(&desc->tx);
454 pchan->done = NULL;
455
456 sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli);
457
458 irq_reg = pchan->idx / DMA_IRQ_CHAN_NR;
459 irq_offset = pchan->idx % DMA_IRQ_CHAN_NR;
460
461 vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE;
462
463 irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg));
464 irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) <<
465 (irq_offset * DMA_IRQ_CHAN_WIDTH));
466 irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH);
467 writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg));
468
469 writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR);
470 writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE);
471
472 sun6i_dma_dump_com_regs(sdev);
473 sun6i_dma_dump_chan_regs(sdev, pchan);
474
475 return 0;
476 }
477
sun6i_dma_tasklet(struct tasklet_struct * t)478 static void sun6i_dma_tasklet(struct tasklet_struct *t)
479 {
480 struct sun6i_dma_dev *sdev = from_tasklet(sdev, t, task);
481 struct sun6i_vchan *vchan;
482 struct sun6i_pchan *pchan;
483 unsigned int pchan_alloc = 0;
484 unsigned int pchan_idx;
485
486 list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) {
487 spin_lock_irq(&vchan->vc.lock);
488
489 pchan = vchan->phy;
490
491 if (pchan && pchan->done) {
492 if (sun6i_dma_start_desc(vchan)) {
493 /*
494 * No current txd associated with this channel
495 */
496 dev_dbg(sdev->slave.dev, "pchan %u: free\n",
497 pchan->idx);
498
499 /* Mark this channel free */
500 vchan->phy = NULL;
501 pchan->vchan = NULL;
502 }
503 }
504 spin_unlock_irq(&vchan->vc.lock);
505 }
506
507 spin_lock_irq(&sdev->lock);
508 for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
509 pchan = &sdev->pchans[pchan_idx];
510
511 if (pchan->vchan || list_empty(&sdev->pending))
512 continue;
513
514 vchan = list_first_entry(&sdev->pending,
515 struct sun6i_vchan, node);
516
517 /* Remove from pending channels */
518 list_del_init(&vchan->node);
519 pchan_alloc |= BIT(pchan_idx);
520
521 /* Mark this channel allocated */
522 pchan->vchan = vchan;
523 vchan->phy = pchan;
524 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n",
525 pchan->idx, &vchan->vc);
526 }
527 spin_unlock_irq(&sdev->lock);
528
529 for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) {
530 if (!(pchan_alloc & BIT(pchan_idx)))
531 continue;
532
533 pchan = sdev->pchans + pchan_idx;
534 vchan = pchan->vchan;
535 if (vchan) {
536 spin_lock_irq(&vchan->vc.lock);
537 sun6i_dma_start_desc(vchan);
538 spin_unlock_irq(&vchan->vc.lock);
539 }
540 }
541 }
542
sun6i_dma_interrupt(int irq,void * dev_id)543 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
544 {
545 struct sun6i_dma_dev *sdev = dev_id;
546 struct sun6i_vchan *vchan;
547 struct sun6i_pchan *pchan;
548 int i, j, ret = IRQ_NONE;
549 u32 status;
550
551 for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) {
552 status = readl(sdev->base + DMA_IRQ_STAT(i));
553 if (!status)
554 continue;
555
556 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
557 str_high_low(i), status);
558
559 writel(status, sdev->base + DMA_IRQ_STAT(i));
560
561 for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) {
562 pchan = sdev->pchans + j;
563 vchan = pchan->vchan;
564 if (vchan && (status & vchan->irq_type)) {
565 if (vchan->cyclic) {
566 vchan_cyclic_callback(&pchan->desc->vd);
567 } else {
568 spin_lock(&vchan->vc.lock);
569 vchan_cookie_complete(&pchan->desc->vd);
570 pchan->done = pchan->desc;
571 spin_unlock(&vchan->vc.lock);
572 }
573 }
574
575 status = status >> DMA_IRQ_CHAN_WIDTH;
576 }
577
578 if (!atomic_read(&sdev->tasklet_shutdown))
579 tasklet_schedule(&sdev->task);
580 ret = IRQ_HANDLED;
581 }
582
583 return ret;
584 }
585
set_config(struct sun6i_dma_dev * sdev,struct dma_slave_config * sconfig,enum dma_transfer_direction direction,u32 * p_cfg)586 static int set_config(struct sun6i_dma_dev *sdev,
587 struct dma_slave_config *sconfig,
588 enum dma_transfer_direction direction,
589 u32 *p_cfg)
590 {
591 enum dma_slave_buswidth src_addr_width, dst_addr_width;
592 u32 src_maxburst, dst_maxburst;
593 s8 src_width, dst_width, src_burst, dst_burst;
594
595 src_addr_width = sconfig->src_addr_width;
596 dst_addr_width = sconfig->dst_addr_width;
597 src_maxburst = sconfig->src_maxburst;
598 dst_maxburst = sconfig->dst_maxburst;
599
600 switch (direction) {
601 case DMA_MEM_TO_DEV:
602 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
603 src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
604 src_maxburst = src_maxburst ? src_maxburst : 8;
605 break;
606 case DMA_DEV_TO_MEM:
607 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
608 dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
609 dst_maxburst = dst_maxburst ? dst_maxburst : 8;
610 break;
611 default:
612 return -EINVAL;
613 }
614
615 if (!(BIT(src_addr_width) & sdev->slave.src_addr_widths))
616 return -EINVAL;
617 if (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths))
618 return -EINVAL;
619 if (!(BIT(src_maxburst) & sdev->cfg->src_burst_lengths))
620 return -EINVAL;
621 if (!(BIT(dst_maxburst) & sdev->cfg->dst_burst_lengths))
622 return -EINVAL;
623
624 src_width = convert_buswidth(src_addr_width);
625 dst_width = convert_buswidth(dst_addr_width);
626 dst_burst = convert_burst(dst_maxburst);
627 src_burst = convert_burst(src_maxburst);
628
629 *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |
630 DMA_CHAN_CFG_DST_WIDTH(dst_width);
631
632 sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst);
633
634 return 0;
635 }
636
sun6i_dma_set_addr(struct sun6i_dma_dev * sdev,struct sun6i_dma_lli * v_lli,dma_addr_t src,dma_addr_t dst)637 static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev,
638 struct sun6i_dma_lli *v_lli,
639 dma_addr_t src, dma_addr_t dst)
640 {
641 v_lli->src = lower_32_bits(src);
642 v_lli->dst = lower_32_bits(dst);
643
644 if (sdev->cfg->has_high_addr)
645 v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) |
646 DST_HIGH_ADDR(upper_32_bits(dst));
647 }
648
sun6i_dma_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)649 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
650 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
651 size_t len, unsigned long flags)
652 {
653 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
654 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
655 struct sun6i_dma_lli *v_lli;
656 struct sun6i_desc *txd;
657 dma_addr_t p_lli;
658 s8 burst, width;
659
660 dev_dbg(chan2dev(chan),
661 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n",
662 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags);
663
664 if (!len)
665 return NULL;
666
667 txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
668 if (!txd)
669 return NULL;
670
671 v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli);
672 if (!v_lli) {
673 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
674 goto err_txd_free;
675 }
676
677 v_lli->len = len;
678 v_lli->para = NORMAL_WAIT;
679 sun6i_dma_set_addr(sdev, v_lli, src, dest);
680
681 burst = convert_burst(8);
682 width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES);
683 v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) |
684 DMA_CHAN_CFG_DST_WIDTH(width);
685
686 sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst);
687 sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM);
688 sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE);
689
690 sun6i_dma_lli_add(NULL, v_lli, p_lli, txd);
691
692 sun6i_dma_dump_lli(vchan, v_lli, p_lli);
693
694 return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
695
696 err_txd_free:
697 kfree(txd);
698 return NULL;
699 }
700
sun6i_dma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction dir,unsigned long flags,void * context)701 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg(
702 struct dma_chan *chan, struct scatterlist *sgl,
703 unsigned int sg_len, enum dma_transfer_direction dir,
704 unsigned long flags, void *context)
705 {
706 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
707 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
708 struct dma_slave_config *sconfig = &vchan->cfg;
709 struct sun6i_dma_lli *v_lli, *prev = NULL;
710 struct sun6i_desc *txd;
711 struct scatterlist *sg;
712 dma_addr_t p_lli;
713 u32 lli_cfg;
714 int i, ret;
715
716 if (!sgl)
717 return NULL;
718
719 ret = set_config(sdev, sconfig, dir, &lli_cfg);
720 if (ret) {
721 dev_err(chan2dev(chan), "Invalid DMA configuration\n");
722 return NULL;
723 }
724
725 txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
726 if (!txd)
727 return NULL;
728
729 for_each_sg(sgl, sg, sg_len, i) {
730 v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli);
731 if (!v_lli)
732 goto err_lli_free;
733
734 v_lli->len = sg_dma_len(sg);
735 v_lli->para = NORMAL_WAIT;
736
737 if (dir == DMA_MEM_TO_DEV) {
738 sun6i_dma_set_addr(sdev, v_lli,
739 sg_dma_address(sg),
740 sconfig->dst_addr);
741 v_lli->cfg = lli_cfg;
742 sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
743 sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
744
745 dev_dbg(chan2dev(chan),
746 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
747 __func__, vchan->vc.chan.chan_id,
748 &sconfig->dst_addr, &sg_dma_address(sg),
749 sg_dma_len(sg), flags);
750
751 } else {
752 sun6i_dma_set_addr(sdev, v_lli,
753 sconfig->src_addr,
754 sg_dma_address(sg));
755 v_lli->cfg = lli_cfg;
756 sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
757 sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
758
759 dev_dbg(chan2dev(chan),
760 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n",
761 __func__, vchan->vc.chan.chan_id,
762 &sg_dma_address(sg), &sconfig->src_addr,
763 sg_dma_len(sg), flags);
764 }
765
766 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
767 }
768
769 dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli);
770 for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli;
771 p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next)
772 sun6i_dma_dump_lli(vchan, v_lli, p_lli);
773
774 return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
775
776 err_lli_free:
777 for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli;
778 p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next)
779 dma_pool_free(sdev->pool, v_lli, p_lli);
780 kfree(txd);
781 return NULL;
782 }
783
sun6i_dma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction dir,unsigned long flags)784 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic(
785 struct dma_chan *chan,
786 dma_addr_t buf_addr,
787 size_t buf_len,
788 size_t period_len,
789 enum dma_transfer_direction dir,
790 unsigned long flags)
791 {
792 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
793 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
794 struct dma_slave_config *sconfig = &vchan->cfg;
795 struct sun6i_dma_lli *v_lli, *prev = NULL;
796 struct sun6i_desc *txd;
797 dma_addr_t p_lli;
798 u32 lli_cfg;
799 unsigned int i, periods = buf_len / period_len;
800 int ret;
801
802 ret = set_config(sdev, sconfig, dir, &lli_cfg);
803 if (ret) {
804 dev_err(chan2dev(chan), "Invalid DMA configuration\n");
805 return NULL;
806 }
807
808 txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
809 if (!txd)
810 return NULL;
811
812 for (i = 0; i < periods; i++) {
813 v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli);
814 if (!v_lli) {
815 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n");
816 goto err_lli_free;
817 }
818
819 v_lli->len = period_len;
820 v_lli->para = NORMAL_WAIT;
821
822 if (dir == DMA_MEM_TO_DEV) {
823 sun6i_dma_set_addr(sdev, v_lli,
824 buf_addr + period_len * i,
825 sconfig->dst_addr);
826 v_lli->cfg = lli_cfg;
827 sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port);
828 sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE);
829 } else {
830 sun6i_dma_set_addr(sdev, v_lli,
831 sconfig->src_addr,
832 buf_addr + period_len * i);
833 v_lli->cfg = lli_cfg;
834 sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM);
835 sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE);
836 }
837
838 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd);
839 }
840
841 prev->p_lli_next = txd->p_lli; /* cyclic list */
842
843 vchan->cyclic = true;
844
845 return vchan_tx_prep(&vchan->vc, &txd->vd, flags);
846
847 err_lli_free:
848 for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli;
849 p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next)
850 dma_pool_free(sdev->pool, v_lli, p_lli);
851 kfree(txd);
852 return NULL;
853 }
854
sun6i_dma_config(struct dma_chan * chan,struct dma_slave_config * config)855 static int sun6i_dma_config(struct dma_chan *chan,
856 struct dma_slave_config *config)
857 {
858 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
859
860 memcpy(&vchan->cfg, config, sizeof(*config));
861
862 return 0;
863 }
864
sun6i_dma_pause(struct dma_chan * chan)865 static int sun6i_dma_pause(struct dma_chan *chan)
866 {
867 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
868 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
869 struct sun6i_pchan *pchan = vchan->phy;
870
871 dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc);
872
873 if (pchan) {
874 writel(DMA_CHAN_PAUSE_PAUSE,
875 pchan->base + DMA_CHAN_PAUSE);
876 } else {
877 spin_lock(&sdev->lock);
878 list_del_init(&vchan->node);
879 spin_unlock(&sdev->lock);
880 }
881
882 return 0;
883 }
884
sun6i_dma_resume(struct dma_chan * chan)885 static int sun6i_dma_resume(struct dma_chan *chan)
886 {
887 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
888 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
889 struct sun6i_pchan *pchan = vchan->phy;
890 unsigned long flags;
891
892 dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc);
893
894 spin_lock_irqsave(&vchan->vc.lock, flags);
895
896 if (pchan) {
897 writel(DMA_CHAN_PAUSE_RESUME,
898 pchan->base + DMA_CHAN_PAUSE);
899 } else if (!list_empty(&vchan->vc.desc_issued)) {
900 spin_lock(&sdev->lock);
901 list_add_tail(&vchan->node, &sdev->pending);
902 spin_unlock(&sdev->lock);
903 }
904
905 spin_unlock_irqrestore(&vchan->vc.lock, flags);
906
907 return 0;
908 }
909
sun6i_dma_terminate_all(struct dma_chan * chan)910 static int sun6i_dma_terminate_all(struct dma_chan *chan)
911 {
912 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
913 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
914 struct sun6i_pchan *pchan = vchan->phy;
915 unsigned long flags;
916 LIST_HEAD(head);
917
918 spin_lock(&sdev->lock);
919 list_del_init(&vchan->node);
920 spin_unlock(&sdev->lock);
921
922 spin_lock_irqsave(&vchan->vc.lock, flags);
923
924 if (vchan->cyclic) {
925 vchan->cyclic = false;
926 if (pchan && pchan->desc) {
927 struct virt_dma_desc *vd = &pchan->desc->vd;
928 struct virt_dma_chan *vc = &vchan->vc;
929
930 list_add_tail(&vd->node, &vc->desc_completed);
931 }
932 }
933
934 vchan_get_all_descriptors(&vchan->vc, &head);
935
936 if (pchan) {
937 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE);
938 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE);
939
940 vchan->phy = NULL;
941 pchan->vchan = NULL;
942 pchan->desc = NULL;
943 pchan->done = NULL;
944 }
945
946 spin_unlock_irqrestore(&vchan->vc.lock, flags);
947
948 vchan_dma_desc_free_list(&vchan->vc, &head);
949
950 return 0;
951 }
952
sun6i_dma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * state)953 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan,
954 dma_cookie_t cookie,
955 struct dma_tx_state *state)
956 {
957 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
958 struct sun6i_pchan *pchan = vchan->phy;
959 struct sun6i_dma_lli *lli;
960 struct virt_dma_desc *vd;
961 struct sun6i_desc *txd;
962 enum dma_status ret;
963 unsigned long flags;
964 size_t bytes = 0;
965
966 ret = dma_cookie_status(chan, cookie, state);
967 if (ret == DMA_COMPLETE || !state)
968 return ret;
969
970 spin_lock_irqsave(&vchan->vc.lock, flags);
971
972 vd = vchan_find_desc(&vchan->vc, cookie);
973 txd = to_sun6i_desc(&vd->tx);
974
975 if (vd) {
976 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next)
977 bytes += lli->len;
978 } else if (!pchan || !pchan->desc) {
979 bytes = 0;
980 } else {
981 bytes = sun6i_get_chan_size(pchan);
982 }
983
984 spin_unlock_irqrestore(&vchan->vc.lock, flags);
985
986 dma_set_residue(state, bytes);
987
988 return ret;
989 }
990
sun6i_dma_issue_pending(struct dma_chan * chan)991 static void sun6i_dma_issue_pending(struct dma_chan *chan)
992 {
993 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
994 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
995 unsigned long flags;
996
997 spin_lock_irqsave(&vchan->vc.lock, flags);
998
999 if (vchan_issue_pending(&vchan->vc)) {
1000 spin_lock(&sdev->lock);
1001
1002 if (!vchan->phy && list_empty(&vchan->node)) {
1003 list_add_tail(&vchan->node, &sdev->pending);
1004 tasklet_schedule(&sdev->task);
1005 dev_dbg(chan2dev(chan), "vchan %p: issued\n",
1006 &vchan->vc);
1007 }
1008
1009 spin_unlock(&sdev->lock);
1010 } else {
1011 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n",
1012 &vchan->vc);
1013 }
1014
1015 spin_unlock_irqrestore(&vchan->vc.lock, flags);
1016 }
1017
sun6i_dma_free_chan_resources(struct dma_chan * chan)1018 static void sun6i_dma_free_chan_resources(struct dma_chan *chan)
1019 {
1020 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device);
1021 struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
1022 unsigned long flags;
1023
1024 spin_lock_irqsave(&sdev->lock, flags);
1025 list_del_init(&vchan->node);
1026 spin_unlock_irqrestore(&sdev->lock, flags);
1027
1028 vchan_free_chan_resources(&vchan->vc);
1029 }
1030
sun6i_dma_of_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1031 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec,
1032 struct of_dma *ofdma)
1033 {
1034 struct sun6i_dma_dev *sdev = ofdma->of_dma_data;
1035 struct sun6i_vchan *vchan;
1036 struct dma_chan *chan;
1037 u8 port = dma_spec->args[0];
1038
1039 if (port > sdev->max_request)
1040 return NULL;
1041
1042 chan = dma_get_any_slave_channel(&sdev->slave);
1043 if (!chan)
1044 return NULL;
1045
1046 vchan = to_sun6i_vchan(chan);
1047 vchan->port = port;
1048
1049 return chan;
1050 }
1051
sun6i_kill_tasklet(struct sun6i_dma_dev * sdev)1052 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev)
1053 {
1054 /* Disable all interrupts from DMA */
1055 writel(0, sdev->base + DMA_IRQ_EN(0));
1056 writel(0, sdev->base + DMA_IRQ_EN(1));
1057
1058 /* Prevent spurious interrupts from scheduling the tasklet */
1059 atomic_inc(&sdev->tasklet_shutdown);
1060
1061 /* Make sure we won't have any further interrupts */
1062 devm_free_irq(sdev->slave.dev, sdev->irq, sdev);
1063
1064 /* Actually prevent the tasklet from being scheduled */
1065 tasklet_kill(&sdev->task);
1066 }
1067
sun6i_dma_free(struct sun6i_dma_dev * sdev)1068 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev)
1069 {
1070 int i;
1071
1072 for (i = 0; i < sdev->num_vchans; i++) {
1073 struct sun6i_vchan *vchan = &sdev->vchans[i];
1074
1075 list_del(&vchan->vc.chan.device_node);
1076 tasklet_kill(&vchan->vc.task);
1077 }
1078 }
1079
1080 /*
1081 * For A31:
1082 *
1083 * There's 16 physical channels that can work in parallel.
1084 *
1085 * However we have 30 different endpoints for our requests.
1086 *
1087 * Since the channels are able to handle only an unidirectional
1088 * transfer, we need to allocate more virtual channels so that
1089 * everyone can grab one channel.
1090 *
1091 * Some devices can't work in both direction (mostly because it
1092 * wouldn't make sense), so we have a bit fewer virtual channels than
1093 * 2 channels per endpoints.
1094 */
1095
1096 static struct sun6i_dma_config sun6i_a31_dma_cfg = {
1097 .nr_max_channels = 16,
1098 .nr_max_requests = 30,
1099 .nr_max_vchans = 53,
1100 .set_burst_length = sun6i_set_burst_length_a31,
1101 .set_drq = sun6i_set_drq_a31,
1102 .set_mode = sun6i_set_mode_a31,
1103 .src_burst_lengths = BIT(1) | BIT(8),
1104 .dst_burst_lengths = BIT(1) | BIT(8),
1105 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1106 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1107 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1108 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1109 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1110 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1111 };
1112
1113 /*
1114 * The A23 only has 8 physical channels, a maximum DRQ port id of 24,
1115 * and a total of 37 usable source and destination endpoints.
1116 */
1117
1118 static struct sun6i_dma_config sun8i_a23_dma_cfg = {
1119 .nr_max_channels = 8,
1120 .nr_max_requests = 24,
1121 .nr_max_vchans = 37,
1122 .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1123 .set_burst_length = sun6i_set_burst_length_a31,
1124 .set_drq = sun6i_set_drq_a31,
1125 .set_mode = sun6i_set_mode_a31,
1126 .src_burst_lengths = BIT(1) | BIT(8),
1127 .dst_burst_lengths = BIT(1) | BIT(8),
1128 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1129 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1130 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1131 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1132 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1133 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1134 };
1135
1136 static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
1137 .nr_max_channels = 8,
1138 .nr_max_requests = 28,
1139 .nr_max_vchans = 39,
1140 .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1141 .set_burst_length = sun6i_set_burst_length_a31,
1142 .set_drq = sun6i_set_drq_a31,
1143 .set_mode = sun6i_set_mode_a31,
1144 .src_burst_lengths = BIT(1) | BIT(8),
1145 .dst_burst_lengths = BIT(1) | BIT(8),
1146 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1147 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1148 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1149 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1150 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1151 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1152 };
1153
1154 /*
1155 * The H3 has 12 physical channels, a maximum DRQ port id of 27,
1156 * and a total of 34 usable source and destination endpoints.
1157 * It also supports additional burst lengths and bus widths,
1158 * and the burst length fields have different offsets.
1159 */
1160
1161 static struct sun6i_dma_config sun8i_h3_dma_cfg = {
1162 .nr_max_channels = 12,
1163 .nr_max_requests = 27,
1164 .nr_max_vchans = 34,
1165 .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1166 .set_burst_length = sun6i_set_burst_length_h3,
1167 .set_drq = sun6i_set_drq_a31,
1168 .set_mode = sun6i_set_mode_a31,
1169 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1170 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1171 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1172 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1173 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1174 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1175 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1176 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1177 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1178 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1179 };
1180
1181 /*
1182 * The A64 binding uses the number of dma channels from the
1183 * device tree node.
1184 */
1185 static struct sun6i_dma_config sun50i_a64_dma_cfg = {
1186 .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1187 .set_burst_length = sun6i_set_burst_length_h3,
1188 .set_drq = sun6i_set_drq_a31,
1189 .set_mode = sun6i_set_mode_a31,
1190 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1191 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1192 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1193 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1194 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1195 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1196 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1197 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1198 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1199 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1200 };
1201
1202 /*
1203 * The A100 binding uses the number of dma channels from the
1204 * device tree node.
1205 */
1206 static struct sun6i_dma_config sun50i_a100_dma_cfg = {
1207 .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1208 .set_burst_length = sun6i_set_burst_length_h3,
1209 .set_drq = sun6i_set_drq_h6,
1210 .set_mode = sun6i_set_mode_h6,
1211 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1212 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1213 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1214 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1215 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1216 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1217 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1218 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1219 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1220 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1221 .has_high_addr = true,
1222 .has_mbus_clk = true,
1223 };
1224
1225 /*
1226 * The H6 binding uses the number of dma channels from the
1227 * device tree node.
1228 */
1229 static struct sun6i_dma_config sun50i_h6_dma_cfg = {
1230 .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
1231 .set_burst_length = sun6i_set_burst_length_h3,
1232 .set_drq = sun6i_set_drq_h6,
1233 .set_mode = sun6i_set_mode_h6,
1234 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1235 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
1236 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1237 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1238 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1239 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1240 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1241 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1242 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1243 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
1244 .has_mbus_clk = true,
1245 };
1246
1247 /*
1248 * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
1249 * and a total of 24 usable source and destination endpoints.
1250 */
1251
1252 static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
1253 .nr_max_channels = 8,
1254 .nr_max_requests = 23,
1255 .nr_max_vchans = 24,
1256 .clock_autogate_enable = sun6i_enable_clock_autogate_a23,
1257 .set_burst_length = sun6i_set_burst_length_a31,
1258 .set_drq = sun6i_set_drq_a31,
1259 .set_mode = sun6i_set_mode_a31,
1260 .src_burst_lengths = BIT(1) | BIT(8),
1261 .dst_burst_lengths = BIT(1) | BIT(8),
1262 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1263 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1264 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1265 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1266 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1267 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
1268 };
1269
1270 static const struct of_device_id sun6i_dma_match[] = {
1271 { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg },
1272 { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg },
1273 { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg },
1274 { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg },
1275 { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg },
1276 { .compatible = "allwinner,sun20i-d1-dma", .data = &sun50i_a100_dma_cfg },
1277 { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
1278 { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg },
1279 { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
1280 { /* sentinel */ }
1281 };
1282 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
1283
sun6i_dma_probe(struct platform_device * pdev)1284 static int sun6i_dma_probe(struct platform_device *pdev)
1285 {
1286 struct device_node *np = pdev->dev.of_node;
1287 struct sun6i_dma_dev *sdc;
1288 int ret, i;
1289
1290 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
1291 if (!sdc)
1292 return -ENOMEM;
1293
1294 sdc->cfg = of_device_get_match_data(&pdev->dev);
1295 if (!sdc->cfg)
1296 return -ENODEV;
1297
1298 sdc->base = devm_platform_ioremap_resource(pdev, 0);
1299 if (IS_ERR(sdc->base))
1300 return PTR_ERR(sdc->base);
1301
1302 sdc->irq = platform_get_irq(pdev, 0);
1303 if (sdc->irq < 0)
1304 return sdc->irq;
1305
1306 sdc->clk = devm_clk_get(&pdev->dev, NULL);
1307 if (IS_ERR(sdc->clk)) {
1308 dev_err(&pdev->dev, "No clock specified\n");
1309 return PTR_ERR(sdc->clk);
1310 }
1311
1312 if (sdc->cfg->has_mbus_clk) {
1313 sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus");
1314 if (IS_ERR(sdc->clk_mbus)) {
1315 dev_err(&pdev->dev, "No mbus clock specified\n");
1316 return PTR_ERR(sdc->clk_mbus);
1317 }
1318 }
1319
1320 sdc->rstc = devm_reset_control_get(&pdev->dev, NULL);
1321 if (IS_ERR(sdc->rstc)) {
1322 dev_err(&pdev->dev, "No reset controller specified\n");
1323 return PTR_ERR(sdc->rstc);
1324 }
1325
1326 sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1327 sizeof(struct sun6i_dma_lli), 4, 0);
1328 if (!sdc->pool) {
1329 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1330 return -ENOMEM;
1331 }
1332
1333 platform_set_drvdata(pdev, sdc);
1334 INIT_LIST_HEAD(&sdc->pending);
1335 spin_lock_init(&sdc->lock);
1336
1337 dma_set_max_seg_size(&pdev->dev, SZ_32M - 1);
1338
1339 dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
1340 dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
1341 dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask);
1342 dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask);
1343
1344 INIT_LIST_HEAD(&sdc->slave.channels);
1345 sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources;
1346 sdc->slave.device_tx_status = sun6i_dma_tx_status;
1347 sdc->slave.device_issue_pending = sun6i_dma_issue_pending;
1348 sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg;
1349 sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy;
1350 sdc->slave.device_prep_dma_cyclic = sun6i_dma_prep_dma_cyclic;
1351 sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES;
1352 sdc->slave.device_config = sun6i_dma_config;
1353 sdc->slave.device_pause = sun6i_dma_pause;
1354 sdc->slave.device_resume = sun6i_dma_resume;
1355 sdc->slave.device_terminate_all = sun6i_dma_terminate_all;
1356 sdc->slave.src_addr_widths = sdc->cfg->src_addr_widths;
1357 sdc->slave.dst_addr_widths = sdc->cfg->dst_addr_widths;
1358 sdc->slave.directions = BIT(DMA_DEV_TO_MEM) |
1359 BIT(DMA_MEM_TO_DEV);
1360 sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1361 sdc->slave.dev = &pdev->dev;
1362
1363 sdc->num_pchans = sdc->cfg->nr_max_channels;
1364 sdc->num_vchans = sdc->cfg->nr_max_vchans;
1365 sdc->max_request = sdc->cfg->nr_max_requests;
1366
1367 ret = of_property_read_u32(np, "dma-channels", &sdc->num_pchans);
1368 if (ret && !sdc->num_pchans) {
1369 dev_err(&pdev->dev, "Can't get dma-channels.\n");
1370 return ret;
1371 }
1372
1373 ret = of_property_read_u32(np, "dma-requests", &sdc->max_request);
1374 if (ret && !sdc->max_request) {
1375 dev_info(&pdev->dev, "Missing dma-requests, using %u.\n",
1376 DMA_CHAN_MAX_DRQ_A31);
1377 sdc->max_request = DMA_CHAN_MAX_DRQ_A31;
1378 }
1379
1380 /*
1381 * If the number of vchans is not specified, derive it from the
1382 * highest port number, at most one channel per port and direction.
1383 */
1384 if (!sdc->num_vchans)
1385 sdc->num_vchans = 2 * (sdc->max_request + 1);
1386
1387 sdc->pchans = devm_kcalloc(&pdev->dev, sdc->num_pchans,
1388 sizeof(struct sun6i_pchan), GFP_KERNEL);
1389 if (!sdc->pchans)
1390 return -ENOMEM;
1391
1392 sdc->vchans = devm_kcalloc(&pdev->dev, sdc->num_vchans,
1393 sizeof(struct sun6i_vchan), GFP_KERNEL);
1394 if (!sdc->vchans)
1395 return -ENOMEM;
1396
1397 tasklet_setup(&sdc->task, sun6i_dma_tasklet);
1398
1399 for (i = 0; i < sdc->num_pchans; i++) {
1400 struct sun6i_pchan *pchan = &sdc->pchans[i];
1401
1402 pchan->idx = i;
1403 pchan->base = sdc->base + 0x100 + i * 0x40;
1404 }
1405
1406 for (i = 0; i < sdc->num_vchans; i++) {
1407 struct sun6i_vchan *vchan = &sdc->vchans[i];
1408
1409 INIT_LIST_HEAD(&vchan->node);
1410 vchan->vc.desc_free = sun6i_dma_free_desc;
1411 vchan_init(&vchan->vc, &sdc->slave);
1412 }
1413
1414 ret = reset_control_deassert(sdc->rstc);
1415 if (ret) {
1416 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n");
1417 goto err_chan_free;
1418 }
1419
1420 ret = clk_prepare_enable(sdc->clk);
1421 if (ret) {
1422 dev_err(&pdev->dev, "Couldn't enable the clock\n");
1423 goto err_reset_assert;
1424 }
1425
1426 if (sdc->cfg->has_mbus_clk) {
1427 ret = clk_prepare_enable(sdc->clk_mbus);
1428 if (ret) {
1429 dev_err(&pdev->dev, "Couldn't enable mbus clock\n");
1430 goto err_clk_disable;
1431 }
1432 }
1433
1434 ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0,
1435 dev_name(&pdev->dev), sdc);
1436 if (ret) {
1437 dev_err(&pdev->dev, "Cannot request IRQ\n");
1438 goto err_mbus_clk_disable;
1439 }
1440
1441 ret = dma_async_device_register(&sdc->slave);
1442 if (ret) {
1443 dev_warn(&pdev->dev, "Failed to register DMA engine device\n");
1444 goto err_irq_disable;
1445 }
1446
1447 ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate,
1448 sdc);
1449 if (ret) {
1450 dev_err(&pdev->dev, "of_dma_controller_register failed\n");
1451 goto err_dma_unregister;
1452 }
1453
1454 if (sdc->cfg->clock_autogate_enable)
1455 sdc->cfg->clock_autogate_enable(sdc);
1456
1457 return 0;
1458
1459 err_dma_unregister:
1460 dma_async_device_unregister(&sdc->slave);
1461 err_irq_disable:
1462 sun6i_kill_tasklet(sdc);
1463 err_mbus_clk_disable:
1464 clk_disable_unprepare(sdc->clk_mbus);
1465 err_clk_disable:
1466 clk_disable_unprepare(sdc->clk);
1467 err_reset_assert:
1468 reset_control_assert(sdc->rstc);
1469 err_chan_free:
1470 sun6i_dma_free(sdc);
1471 return ret;
1472 }
1473
sun6i_dma_remove(struct platform_device * pdev)1474 static void sun6i_dma_remove(struct platform_device *pdev)
1475 {
1476 struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev);
1477
1478 of_dma_controller_free(pdev->dev.of_node);
1479 dma_async_device_unregister(&sdc->slave);
1480
1481 sun6i_kill_tasklet(sdc);
1482
1483 clk_disable_unprepare(sdc->clk_mbus);
1484 clk_disable_unprepare(sdc->clk);
1485 reset_control_assert(sdc->rstc);
1486
1487 sun6i_dma_free(sdc);
1488 }
1489
1490 static struct platform_driver sun6i_dma_driver = {
1491 .probe = sun6i_dma_probe,
1492 .remove = sun6i_dma_remove,
1493 .driver = {
1494 .name = "sun6i-dma",
1495 .of_match_table = sun6i_dma_match,
1496 },
1497 };
1498 module_platform_driver(sun6i_dma_driver);
1499
1500 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver");
1501 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>");
1502 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1503 MODULE_LICENSE("GPL");
1504