1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * intel_pstate.c: Native P state management for Intel processors
4  *
5  * (C) Copyright 2012 Intel Corporation
6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7  */
8 
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/sched/smt.h>
20 #include <linux/list.h>
21 #include <linux/cpu.h>
22 #include <linux/cpufreq.h>
23 #include <linux/sysfs.h>
24 #include <linux/types.h>
25 #include <linux/fs.h>
26 #include <linux/acpi.h>
27 #include <linux/vmalloc.h>
28 #include <linux/pm_qos.h>
29 #include <linux/bitfield.h>
30 #include <trace/events/power.h>
31 #include <linux/units.h>
32 
33 #include <asm/cpu.h>
34 #include <asm/div64.h>
35 #include <asm/msr.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
39 #include "../drivers/thermal/intel/thermal_interrupt.h"
40 
41 #define INTEL_PSTATE_SAMPLING_INTERVAL	(10 * NSEC_PER_MSEC)
42 
43 #define INTEL_CPUFREQ_TRANSITION_LATENCY	20000
44 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP	5000
45 #define INTEL_CPUFREQ_TRANSITION_DELAY		500
46 
47 #ifdef CONFIG_ACPI
48 #include <acpi/processor.h>
49 #include <acpi/cppc_acpi.h>
50 #endif
51 
52 #define FRAC_BITS 8
53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
54 #define fp_toint(X) ((X) >> FRAC_BITS)
55 
56 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
57 
58 #define EXT_BITS 6
59 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
60 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
61 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
62 
mul_fp(int32_t x,int32_t y)63 static inline int32_t mul_fp(int32_t x, int32_t y)
64 {
65 	return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
66 }
67 
div_fp(s64 x,s64 y)68 static inline int32_t div_fp(s64 x, s64 y)
69 {
70 	return div64_s64((int64_t)x << FRAC_BITS, y);
71 }
72 
ceiling_fp(int32_t x)73 static inline int ceiling_fp(int32_t x)
74 {
75 	int mask, ret;
76 
77 	ret = fp_toint(x);
78 	mask = (1 << FRAC_BITS) - 1;
79 	if (x & mask)
80 		ret += 1;
81 	return ret;
82 }
83 
mul_ext_fp(u64 x,u64 y)84 static inline u64 mul_ext_fp(u64 x, u64 y)
85 {
86 	return (x * y) >> EXT_FRAC_BITS;
87 }
88 
div_ext_fp(u64 x,u64 y)89 static inline u64 div_ext_fp(u64 x, u64 y)
90 {
91 	return div64_u64(x << EXT_FRAC_BITS, y);
92 }
93 
94 /**
95  * struct sample -	Store performance sample
96  * @core_avg_perf:	Ratio of APERF/MPERF which is the actual average
97  *			performance during last sample period
98  * @busy_scaled:	Scaled busy value which is used to calculate next
99  *			P state. This can be different than core_avg_perf
100  *			to account for cpu idle period
101  * @aperf:		Difference of actual performance frequency clock count
102  *			read from APERF MSR between last and current sample
103  * @mperf:		Difference of maximum performance frequency clock count
104  *			read from MPERF MSR between last and current sample
105  * @tsc:		Difference of time stamp counter between last and
106  *			current sample
107  * @time:		Current time from scheduler
108  *
109  * This structure is used in the cpudata structure to store performance sample
110  * data for choosing next P State.
111  */
112 struct sample {
113 	int32_t core_avg_perf;
114 	int32_t busy_scaled;
115 	u64 aperf;
116 	u64 mperf;
117 	u64 tsc;
118 	u64 time;
119 };
120 
121 /**
122  * struct pstate_data - Store P state data
123  * @current_pstate:	Current requested P state
124  * @min_pstate:		Min P state possible for this platform
125  * @max_pstate:		Max P state possible for this platform
126  * @max_pstate_physical:This is physical Max P state for a processor
127  *			This can be higher than the max_pstate which can
128  *			be limited by platform thermal design power limits
129  * @perf_ctl_scaling:	PERF_CTL P-state to frequency scaling factor
130  * @scaling:		Scaling factor between performance and frequency
131  * @turbo_pstate:	Max Turbo P state possible for this platform
132  * @min_freq:		@min_pstate frequency in cpufreq units
133  * @max_freq:		@max_pstate frequency in cpufreq units
134  * @turbo_freq:		@turbo_pstate frequency in cpufreq units
135  *
136  * Stores the per cpu model P state limits and current P state.
137  */
138 struct pstate_data {
139 	int	current_pstate;
140 	int	min_pstate;
141 	int	max_pstate;
142 	int	max_pstate_physical;
143 	int	perf_ctl_scaling;
144 	int	scaling;
145 	int	turbo_pstate;
146 	unsigned int min_freq;
147 	unsigned int max_freq;
148 	unsigned int turbo_freq;
149 };
150 
151 /**
152  * struct vid_data -	Stores voltage information data
153  * @min:		VID data for this platform corresponding to
154  *			the lowest P state
155  * @max:		VID data corresponding to the highest P State.
156  * @turbo:		VID data for turbo P state
157  * @ratio:		Ratio of (vid max - vid min) /
158  *			(max P state - Min P State)
159  *
160  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
161  * This data is used in Atom platforms, where in addition to target P state,
162  * the voltage data needs to be specified to select next P State.
163  */
164 struct vid_data {
165 	int min;
166 	int max;
167 	int turbo;
168 	int32_t ratio;
169 };
170 
171 /**
172  * struct global_params - Global parameters, mostly tunable via sysfs.
173  * @no_turbo:		Whether or not to use turbo P-states.
174  * @turbo_disabled:	Whether or not turbo P-states are available at all,
175  *			based on the MSR_IA32_MISC_ENABLE value and whether or
176  *			not the maximum reported turbo P-state is different from
177  *			the maximum reported non-turbo one.
178  * @min_perf_pct:	Minimum capacity limit in percent of the maximum turbo
179  *			P-state capacity.
180  * @max_perf_pct:	Maximum capacity limit in percent of the maximum turbo
181  *			P-state capacity.
182  */
183 struct global_params {
184 	bool no_turbo;
185 	bool turbo_disabled;
186 	int max_perf_pct;
187 	int min_perf_pct;
188 };
189 
190 /**
191  * struct cpudata -	Per CPU instance data storage
192  * @cpu:		CPU number for this instance data
193  * @policy:		CPUFreq policy value
194  * @update_util:	CPUFreq utility callback information
195  * @update_util_set:	CPUFreq utility callback is set
196  * @iowait_boost:	iowait-related boost fraction
197  * @last_update:	Time of the last update.
198  * @pstate:		Stores P state limits for this CPU
199  * @vid:		Stores VID limits for this CPU
200  * @last_sample_time:	Last Sample time
201  * @aperf_mperf_shift:	APERF vs MPERF counting frequency difference
202  * @prev_aperf:		Last APERF value read from APERF MSR
203  * @prev_mperf:		Last MPERF value read from MPERF MSR
204  * @prev_tsc:		Last timestamp counter (TSC) value
205  * @sample:		Storage for storing last Sample data
206  * @min_perf_ratio:	Minimum capacity in terms of PERF or HWP ratios
207  * @max_perf_ratio:	Maximum capacity in terms of PERF or HWP ratios
208  * @acpi_perf_data:	Stores ACPI perf information read from _PSS
209  * @valid_pss_table:	Set to true for valid ACPI _PSS entries found
210  * @epp_powersave:	Last saved HWP energy performance preference
211  *			(EPP) or energy performance bias (EPB),
212  *			when policy switched to performance
213  * @epp_policy:		Last saved policy used to set EPP/EPB
214  * @epp_default:	Power on default HWP energy performance
215  *			preference/bias
216  * @epp_cached:		Cached HWP energy-performance preference value
217  * @hwp_req_cached:	Cached value of the last HWP Request MSR
218  * @hwp_cap_cached:	Cached value of the last HWP Capabilities MSR
219  * @last_io_update:	Last time when IO wake flag was set
220  * @capacity_perf:	Highest perf used for scale invariance
221  * @sched_flags:	Store scheduler flags for possible cross CPU update
222  * @hwp_boost_min:	Last HWP boosted min performance
223  * @suspended:		Whether or not the driver has been suspended.
224  * @hwp_notify_work:	workqueue for HWP notifications.
225  *
226  * This structure stores per CPU instance data for all CPUs.
227  */
228 struct cpudata {
229 	int cpu;
230 
231 	unsigned int policy;
232 	struct update_util_data update_util;
233 	bool   update_util_set;
234 
235 	struct pstate_data pstate;
236 	struct vid_data vid;
237 
238 	u64	last_update;
239 	u64	last_sample_time;
240 	u64	aperf_mperf_shift;
241 	u64	prev_aperf;
242 	u64	prev_mperf;
243 	u64	prev_tsc;
244 	struct sample sample;
245 	int32_t	min_perf_ratio;
246 	int32_t	max_perf_ratio;
247 #ifdef CONFIG_ACPI
248 	struct acpi_processor_performance acpi_perf_data;
249 	bool valid_pss_table;
250 #endif
251 	unsigned int iowait_boost;
252 	s16 epp_powersave;
253 	s16 epp_policy;
254 	s16 epp_default;
255 	s16 epp_cached;
256 	u64 hwp_req_cached;
257 	u64 hwp_cap_cached;
258 	u64 last_io_update;
259 	unsigned int capacity_perf;
260 	unsigned int sched_flags;
261 	u32 hwp_boost_min;
262 	bool suspended;
263 	struct delayed_work hwp_notify_work;
264 };
265 
266 static struct cpudata **all_cpu_data;
267 
268 /**
269  * struct pstate_funcs - Per CPU model specific callbacks
270  * @get_max:		Callback to get maximum non turbo effective P state
271  * @get_max_physical:	Callback to get maximum non turbo physical P state
272  * @get_min:		Callback to get minimum P state
273  * @get_turbo:		Callback to get turbo P state
274  * @get_scaling:	Callback to get frequency scaling factor
275  * @get_cpu_scaling:	Get frequency scaling factor for a given cpu
276  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277  * @get_val:		Callback to convert P state to actual MSR write value
278  * @get_vid:		Callback to get VID data for Atom platforms
279  *
280  * Core and Atom CPU models have different way to get P State limits. This
281  * structure is used to store those callbacks.
282  */
283 struct pstate_funcs {
284 	int (*get_max)(int cpu);
285 	int (*get_max_physical)(int cpu);
286 	int (*get_min)(int cpu);
287 	int (*get_turbo)(int cpu);
288 	int (*get_scaling)(void);
289 	int (*get_cpu_scaling)(int cpu);
290 	int (*get_aperf_mperf_shift)(void);
291 	u64 (*get_val)(struct cpudata*, int pstate);
292 	void (*get_vid)(struct cpudata *);
293 };
294 
295 static struct pstate_funcs pstate_funcs __read_mostly;
296 
297 static bool hwp_active __ro_after_init;
298 static int hwp_mode_bdw __ro_after_init;
299 static bool per_cpu_limits __ro_after_init;
300 static bool hwp_forced __ro_after_init;
301 static bool hwp_boost __read_mostly;
302 static bool hwp_is_hybrid;
303 
304 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
305 
306 #define HYBRID_SCALING_FACTOR_ADL	78741
307 #define HYBRID_SCALING_FACTOR_MTL	80000
308 #define HYBRID_SCALING_FACTOR_LNL	86957
309 
310 static int hybrid_scaling_factor;
311 
core_get_scaling(void)312 static inline int core_get_scaling(void)
313 {
314 	return 100000;
315 }
316 
317 #ifdef CONFIG_ACPI
318 static bool acpi_ppc;
319 #endif
320 
321 static struct global_params global;
322 
323 static DEFINE_MUTEX(intel_pstate_driver_lock);
324 static DEFINE_MUTEX(intel_pstate_limits_lock);
325 
326 #ifdef CONFIG_ACPI
327 
intel_pstate_acpi_pm_profile_server(void)328 static bool intel_pstate_acpi_pm_profile_server(void)
329 {
330 	if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
331 	    acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
332 		return true;
333 
334 	return false;
335 }
336 
intel_pstate_get_ppc_enable_status(void)337 static bool intel_pstate_get_ppc_enable_status(void)
338 {
339 	if (intel_pstate_acpi_pm_profile_server())
340 		return true;
341 
342 	return acpi_ppc;
343 }
344 
345 #ifdef CONFIG_ACPI_CPPC_LIB
346 
347 /* The work item is needed to avoid CPU hotplug locking issues */
intel_pstste_sched_itmt_work_fn(struct work_struct * work)348 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
349 {
350 	sched_set_itmt_support();
351 }
352 
353 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
354 
355 #define CPPC_MAX_PERF	U8_MAX
356 
intel_pstate_set_itmt_prio(int cpu)357 static void intel_pstate_set_itmt_prio(int cpu)
358 {
359 	struct cppc_perf_caps cppc_perf;
360 	static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
361 	int ret;
362 
363 	ret = cppc_get_perf_caps(cpu, &cppc_perf);
364 	/*
365 	 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0].
366 	 *
367 	 * Also, on some systems with overclocking enabled, CPPC.highest_perf is
368 	 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT.
369 	 * Fall back to MSR_HWP_CAPABILITIES then too.
370 	 */
371 	if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF)
372 		cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
373 
374 	/*
375 	 * The priorities can be set regardless of whether or not
376 	 * sched_set_itmt_support(true) has been called and it is valid to
377 	 * update them at any time after it has been called.
378 	 */
379 	sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
380 
381 	if (max_highest_perf <= min_highest_perf) {
382 		if (cppc_perf.highest_perf > max_highest_perf)
383 			max_highest_perf = cppc_perf.highest_perf;
384 
385 		if (cppc_perf.highest_perf < min_highest_perf)
386 			min_highest_perf = cppc_perf.highest_perf;
387 
388 		if (max_highest_perf > min_highest_perf) {
389 			/*
390 			 * This code can be run during CPU online under the
391 			 * CPU hotplug locks, so sched_set_itmt_support()
392 			 * cannot be called from here.  Queue up a work item
393 			 * to invoke it.
394 			 */
395 			schedule_work(&sched_itmt_work);
396 		}
397 	}
398 }
399 
intel_pstate_get_cppc_guaranteed(int cpu)400 static int intel_pstate_get_cppc_guaranteed(int cpu)
401 {
402 	struct cppc_perf_caps cppc_perf;
403 	int ret;
404 
405 	ret = cppc_get_perf_caps(cpu, &cppc_perf);
406 	if (ret)
407 		return ret;
408 
409 	if (cppc_perf.guaranteed_perf)
410 		return cppc_perf.guaranteed_perf;
411 
412 	return cppc_perf.nominal_perf;
413 }
414 
intel_pstate_cppc_get_scaling(int cpu)415 static int intel_pstate_cppc_get_scaling(int cpu)
416 {
417 	struct cppc_perf_caps cppc_perf;
418 
419 	/*
420 	 * Compute the perf-to-frequency scaling factor for the given CPU if
421 	 * possible, unless it would be 0.
422 	 */
423 	if (!cppc_get_perf_caps(cpu, &cppc_perf) &&
424 	    cppc_perf.nominal_perf && cppc_perf.nominal_freq)
425 		return div_u64(cppc_perf.nominal_freq * KHZ_PER_MHZ,
426 			       cppc_perf.nominal_perf);
427 
428 	return core_get_scaling();
429 }
430 
431 #else /* CONFIG_ACPI_CPPC_LIB */
intel_pstate_set_itmt_prio(int cpu)432 static inline void intel_pstate_set_itmt_prio(int cpu)
433 {
434 }
435 #endif /* CONFIG_ACPI_CPPC_LIB */
436 
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)437 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
438 {
439 	struct cpudata *cpu;
440 	int ret;
441 	int i;
442 
443 	if (hwp_active) {
444 		intel_pstate_set_itmt_prio(policy->cpu);
445 		return;
446 	}
447 
448 	if (!intel_pstate_get_ppc_enable_status())
449 		return;
450 
451 	cpu = all_cpu_data[policy->cpu];
452 
453 	ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
454 						  policy->cpu);
455 	if (ret)
456 		return;
457 
458 	/*
459 	 * Check if the control value in _PSS is for PERF_CTL MSR, which should
460 	 * guarantee that the states returned by it map to the states in our
461 	 * list directly.
462 	 */
463 	if (cpu->acpi_perf_data.control_register.space_id !=
464 						ACPI_ADR_SPACE_FIXED_HARDWARE)
465 		goto err;
466 
467 	/*
468 	 * If there is only one entry _PSS, simply ignore _PSS and continue as
469 	 * usual without taking _PSS into account
470 	 */
471 	if (cpu->acpi_perf_data.state_count < 2)
472 		goto err;
473 
474 	pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
475 	for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
476 		pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
477 			 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
478 			 (u32) cpu->acpi_perf_data.states[i].core_frequency,
479 			 (u32) cpu->acpi_perf_data.states[i].power,
480 			 (u32) cpu->acpi_perf_data.states[i].control);
481 	}
482 
483 	cpu->valid_pss_table = true;
484 	pr_debug("_PPC limits will be enforced\n");
485 
486 	return;
487 
488  err:
489 	cpu->valid_pss_table = false;
490 	acpi_processor_unregister_performance(policy->cpu);
491 }
492 
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)493 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
494 {
495 	struct cpudata *cpu;
496 
497 	cpu = all_cpu_data[policy->cpu];
498 	if (!cpu->valid_pss_table)
499 		return;
500 
501 	acpi_processor_unregister_performance(policy->cpu);
502 }
503 #else /* CONFIG_ACPI */
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)504 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
505 {
506 }
507 
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)508 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
509 {
510 }
511 
intel_pstate_acpi_pm_profile_server(void)512 static inline bool intel_pstate_acpi_pm_profile_server(void)
513 {
514 	return false;
515 }
516 #endif /* CONFIG_ACPI */
517 
518 #ifndef CONFIG_ACPI_CPPC_LIB
intel_pstate_get_cppc_guaranteed(int cpu)519 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
520 {
521 	return -ENOTSUPP;
522 }
523 
intel_pstate_cppc_get_scaling(int cpu)524 static int intel_pstate_cppc_get_scaling(int cpu)
525 {
526 	return core_get_scaling();
527 }
528 #endif /* CONFIG_ACPI_CPPC_LIB */
529 
intel_pstate_freq_to_hwp_rel(struct cpudata * cpu,int freq,unsigned int relation)530 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
531 					unsigned int relation)
532 {
533 	if (freq == cpu->pstate.turbo_freq)
534 		return cpu->pstate.turbo_pstate;
535 
536 	if (freq == cpu->pstate.max_freq)
537 		return cpu->pstate.max_pstate;
538 
539 	switch (relation) {
540 	case CPUFREQ_RELATION_H:
541 		return freq / cpu->pstate.scaling;
542 	case CPUFREQ_RELATION_C:
543 		return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
544 	}
545 
546 	return DIV_ROUND_UP(freq, cpu->pstate.scaling);
547 }
548 
intel_pstate_freq_to_hwp(struct cpudata * cpu,int freq)549 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
550 {
551 	return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
552 }
553 
554 /**
555  * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
556  * @cpu: Target CPU.
557  *
558  * On hybrid processors, HWP may expose more performance levels than there are
559  * P-states accessible through the PERF_CTL interface.  If that happens, the
560  * scaling factor between HWP performance levels and CPU frequency will be less
561  * than the scaling factor between P-state values and CPU frequency.
562  *
563  * In that case, adjust the CPU parameters used in computations accordingly.
564  */
intel_pstate_hybrid_hwp_adjust(struct cpudata * cpu)565 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
566 {
567 	int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
568 	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
569 	int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
570 	int scaling = cpu->pstate.scaling;
571 	int freq;
572 
573 	pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
574 	pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
575 	pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
576 	pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
577 	pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
578 	pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
579 
580 	cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
581 					   perf_ctl_scaling);
582 	cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
583 					 perf_ctl_scaling);
584 
585 	freq = perf_ctl_max_phys * perf_ctl_scaling;
586 	cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
587 
588 	freq = cpu->pstate.min_pstate * perf_ctl_scaling;
589 	cpu->pstate.min_freq = freq;
590 	/*
591 	 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
592 	 * the effective range of HWP performance levels.
593 	 */
594 	cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
595 }
596 
turbo_is_disabled(void)597 static bool turbo_is_disabled(void)
598 {
599 	u64 misc_en;
600 
601 	if (!cpu_feature_enabled(X86_FEATURE_IDA))
602 		return true;
603 
604 	rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
605 
606 	return !!(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
607 }
608 
min_perf_pct_min(void)609 static int min_perf_pct_min(void)
610 {
611 	struct cpudata *cpu = all_cpu_data[0];
612 	int turbo_pstate = cpu->pstate.turbo_pstate;
613 
614 	return turbo_pstate ?
615 		(cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
616 }
617 
intel_pstate_get_epb(struct cpudata * cpu_data)618 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
619 {
620 	u64 epb;
621 	int ret;
622 
623 	if (!boot_cpu_has(X86_FEATURE_EPB))
624 		return -ENXIO;
625 
626 	ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
627 	if (ret)
628 		return (s16)ret;
629 
630 	return (s16)(epb & 0x0f);
631 }
632 
intel_pstate_get_epp(struct cpudata * cpu_data,u64 hwp_req_data)633 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
634 {
635 	s16 epp;
636 
637 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
638 		/*
639 		 * When hwp_req_data is 0, means that caller didn't read
640 		 * MSR_HWP_REQUEST, so need to read and get EPP.
641 		 */
642 		if (!hwp_req_data) {
643 			epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
644 					    &hwp_req_data);
645 			if (epp)
646 				return epp;
647 		}
648 		epp = (hwp_req_data >> 24) & 0xff;
649 	} else {
650 		/* When there is no EPP present, HWP uses EPB settings */
651 		epp = intel_pstate_get_epb(cpu_data);
652 	}
653 
654 	return epp;
655 }
656 
intel_pstate_set_epb(int cpu,s16 pref)657 static int intel_pstate_set_epb(int cpu, s16 pref)
658 {
659 	u64 epb;
660 	int ret;
661 
662 	if (!boot_cpu_has(X86_FEATURE_EPB))
663 		return -ENXIO;
664 
665 	ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
666 	if (ret)
667 		return ret;
668 
669 	epb = (epb & ~0x0f) | pref;
670 	wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
671 
672 	return 0;
673 }
674 
675 /*
676  * EPP/EPB display strings corresponding to EPP index in the
677  * energy_perf_strings[]
678  *	index		String
679  *-------------------------------------
680  *	0		default
681  *	1		performance
682  *	2		balance_performance
683  *	3		balance_power
684  *	4		power
685  */
686 
687 enum energy_perf_value_index {
688 	EPP_INDEX_DEFAULT = 0,
689 	EPP_INDEX_PERFORMANCE,
690 	EPP_INDEX_BALANCE_PERFORMANCE,
691 	EPP_INDEX_BALANCE_POWERSAVE,
692 	EPP_INDEX_POWERSAVE,
693 };
694 
695 static const char * const energy_perf_strings[] = {
696 	[EPP_INDEX_DEFAULT] = "default",
697 	[EPP_INDEX_PERFORMANCE] = "performance",
698 	[EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
699 	[EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
700 	[EPP_INDEX_POWERSAVE] = "power",
701 	NULL
702 };
703 static unsigned int epp_values[] = {
704 	[EPP_INDEX_DEFAULT] = 0, /* Unused index */
705 	[EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
706 	[EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
707 	[EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
708 	[EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
709 };
710 
intel_pstate_get_energy_pref_index(struct cpudata * cpu_data,int * raw_epp)711 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
712 {
713 	s16 epp;
714 	int index = -EINVAL;
715 
716 	*raw_epp = 0;
717 	epp = intel_pstate_get_epp(cpu_data, 0);
718 	if (epp < 0)
719 		return epp;
720 
721 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
722 		if (epp == epp_values[EPP_INDEX_PERFORMANCE])
723 			return EPP_INDEX_PERFORMANCE;
724 		if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
725 			return EPP_INDEX_BALANCE_PERFORMANCE;
726 		if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
727 			return EPP_INDEX_BALANCE_POWERSAVE;
728 		if (epp == epp_values[EPP_INDEX_POWERSAVE])
729 			return EPP_INDEX_POWERSAVE;
730 		*raw_epp = epp;
731 		return 0;
732 	} else if (boot_cpu_has(X86_FEATURE_EPB)) {
733 		/*
734 		 * Range:
735 		 *	0x00-0x03	:	Performance
736 		 *	0x04-0x07	:	Balance performance
737 		 *	0x08-0x0B	:	Balance power
738 		 *	0x0C-0x0F	:	Power
739 		 * The EPB is a 4 bit value, but our ranges restrict the
740 		 * value which can be set. Here only using top two bits
741 		 * effectively.
742 		 */
743 		index = (epp >> 2) + 1;
744 	}
745 
746 	return index;
747 }
748 
intel_pstate_set_epp(struct cpudata * cpu,u32 epp)749 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
750 {
751 	int ret;
752 
753 	/*
754 	 * Use the cached HWP Request MSR value, because in the active mode the
755 	 * register itself may be updated by intel_pstate_hwp_boost_up() or
756 	 * intel_pstate_hwp_boost_down() at any time.
757 	 */
758 	u64 value = READ_ONCE(cpu->hwp_req_cached);
759 
760 	value &= ~GENMASK_ULL(31, 24);
761 	value |= (u64)epp << 24;
762 	/*
763 	 * The only other updater of hwp_req_cached in the active mode,
764 	 * intel_pstate_hwp_set(), is called under the same lock as this
765 	 * function, so it cannot run in parallel with the update below.
766 	 */
767 	WRITE_ONCE(cpu->hwp_req_cached, value);
768 	ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
769 	if (!ret)
770 		cpu->epp_cached = epp;
771 
772 	return ret;
773 }
774 
intel_pstate_set_energy_pref_index(struct cpudata * cpu_data,int pref_index,bool use_raw,u32 raw_epp)775 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
776 					      int pref_index, bool use_raw,
777 					      u32 raw_epp)
778 {
779 	int epp = -EINVAL;
780 	int ret;
781 
782 	if (!pref_index)
783 		epp = cpu_data->epp_default;
784 
785 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
786 		if (use_raw)
787 			epp = raw_epp;
788 		else if (epp == -EINVAL)
789 			epp = epp_values[pref_index];
790 
791 		/*
792 		 * To avoid confusion, refuse to set EPP to any values different
793 		 * from 0 (performance) if the current policy is "performance",
794 		 * because those values would be overridden.
795 		 */
796 		if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
797 			return -EBUSY;
798 
799 		ret = intel_pstate_set_epp(cpu_data, epp);
800 	} else {
801 		if (epp == -EINVAL)
802 			epp = (pref_index - 1) << 2;
803 		ret = intel_pstate_set_epb(cpu_data->cpu, epp);
804 	}
805 
806 	return ret;
807 }
808 
show_energy_performance_available_preferences(struct cpufreq_policy * policy,char * buf)809 static ssize_t show_energy_performance_available_preferences(
810 				struct cpufreq_policy *policy, char *buf)
811 {
812 	int i = 0;
813 	int ret = 0;
814 
815 	while (energy_perf_strings[i] != NULL)
816 		ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
817 
818 	ret += sprintf(&buf[ret], "\n");
819 
820 	return ret;
821 }
822 
823 cpufreq_freq_attr_ro(energy_performance_available_preferences);
824 
825 static struct cpufreq_driver intel_pstate;
826 
store_energy_performance_preference(struct cpufreq_policy * policy,const char * buf,size_t count)827 static ssize_t store_energy_performance_preference(
828 		struct cpufreq_policy *policy, const char *buf, size_t count)
829 {
830 	struct cpudata *cpu = all_cpu_data[policy->cpu];
831 	char str_preference[21];
832 	bool raw = false;
833 	ssize_t ret;
834 	u32 epp = 0;
835 
836 	ret = sscanf(buf, "%20s", str_preference);
837 	if (ret != 1)
838 		return -EINVAL;
839 
840 	ret = match_string(energy_perf_strings, -1, str_preference);
841 	if (ret < 0) {
842 		if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
843 			return ret;
844 
845 		ret = kstrtouint(buf, 10, &epp);
846 		if (ret)
847 			return ret;
848 
849 		if (epp > 255)
850 			return -EINVAL;
851 
852 		raw = true;
853 	}
854 
855 	/*
856 	 * This function runs with the policy R/W semaphore held, which
857 	 * guarantees that the driver pointer will not change while it is
858 	 * running.
859 	 */
860 	if (!intel_pstate_driver)
861 		return -EAGAIN;
862 
863 	mutex_lock(&intel_pstate_limits_lock);
864 
865 	if (intel_pstate_driver == &intel_pstate) {
866 		ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
867 	} else {
868 		/*
869 		 * In the passive mode the governor needs to be stopped on the
870 		 * target CPU before the EPP update and restarted after it,
871 		 * which is super-heavy-weight, so make sure it is worth doing
872 		 * upfront.
873 		 */
874 		if (!raw)
875 			epp = ret ? epp_values[ret] : cpu->epp_default;
876 
877 		if (cpu->epp_cached != epp) {
878 			int err;
879 
880 			cpufreq_stop_governor(policy);
881 			ret = intel_pstate_set_epp(cpu, epp);
882 			err = cpufreq_start_governor(policy);
883 			if (!ret)
884 				ret = err;
885 		} else {
886 			ret = 0;
887 		}
888 	}
889 
890 	mutex_unlock(&intel_pstate_limits_lock);
891 
892 	return ret ?: count;
893 }
894 
show_energy_performance_preference(struct cpufreq_policy * policy,char * buf)895 static ssize_t show_energy_performance_preference(
896 				struct cpufreq_policy *policy, char *buf)
897 {
898 	struct cpudata *cpu_data = all_cpu_data[policy->cpu];
899 	int preference, raw_epp;
900 
901 	preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
902 	if (preference < 0)
903 		return preference;
904 
905 	if (raw_epp)
906 		return  sprintf(buf, "%d\n", raw_epp);
907 	else
908 		return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
909 }
910 
911 cpufreq_freq_attr_rw(energy_performance_preference);
912 
show_base_frequency(struct cpufreq_policy * policy,char * buf)913 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
914 {
915 	struct cpudata *cpu = all_cpu_data[policy->cpu];
916 	int ratio, freq;
917 
918 	ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
919 	if (ratio <= 0) {
920 		u64 cap;
921 
922 		rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
923 		ratio = HWP_GUARANTEED_PERF(cap);
924 	}
925 
926 	freq = ratio * cpu->pstate.scaling;
927 	if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
928 		freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
929 
930 	return sprintf(buf, "%d\n", freq);
931 }
932 
933 cpufreq_freq_attr_ro(base_frequency);
934 
935 static struct freq_attr *hwp_cpufreq_attrs[] = {
936 	&energy_performance_preference,
937 	&energy_performance_available_preferences,
938 	&base_frequency,
939 	NULL,
940 };
941 
942 static bool no_cas __ro_after_init;
943 
944 static struct cpudata *hybrid_max_perf_cpu __read_mostly;
945 /*
946  * Protects hybrid_max_perf_cpu, the capacity_perf fields in struct cpudata,
947  * and the x86 arch scale-invariance information from concurrent updates.
948  */
949 static DEFINE_MUTEX(hybrid_capacity_lock);
950 
hybrid_set_cpu_capacity(struct cpudata * cpu)951 static void hybrid_set_cpu_capacity(struct cpudata *cpu)
952 {
953 	arch_set_cpu_capacity(cpu->cpu, cpu->capacity_perf,
954 			      hybrid_max_perf_cpu->capacity_perf,
955 			      cpu->capacity_perf,
956 			      cpu->pstate.max_pstate_physical);
957 
958 	pr_debug("CPU%d: perf = %u, max. perf = %u, base perf = %d\n", cpu->cpu,
959 		 cpu->capacity_perf, hybrid_max_perf_cpu->capacity_perf,
960 		 cpu->pstate.max_pstate_physical);
961 }
962 
hybrid_clear_cpu_capacity(unsigned int cpunum)963 static void hybrid_clear_cpu_capacity(unsigned int cpunum)
964 {
965 	arch_set_cpu_capacity(cpunum, 1, 1, 1, 1);
966 }
967 
hybrid_get_capacity_perf(struct cpudata * cpu)968 static void hybrid_get_capacity_perf(struct cpudata *cpu)
969 {
970 	if (READ_ONCE(global.no_turbo)) {
971 		cpu->capacity_perf = cpu->pstate.max_pstate_physical;
972 		return;
973 	}
974 
975 	cpu->capacity_perf = HWP_HIGHEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
976 }
977 
hybrid_set_capacity_of_cpus(void)978 static void hybrid_set_capacity_of_cpus(void)
979 {
980 	int cpunum;
981 
982 	for_each_online_cpu(cpunum) {
983 		struct cpudata *cpu = all_cpu_data[cpunum];
984 
985 		if (cpu)
986 			hybrid_set_cpu_capacity(cpu);
987 	}
988 }
989 
hybrid_update_cpu_capacity_scaling(void)990 static void hybrid_update_cpu_capacity_scaling(void)
991 {
992 	struct cpudata *max_perf_cpu = NULL;
993 	unsigned int max_cap_perf = 0;
994 	int cpunum;
995 
996 	for_each_online_cpu(cpunum) {
997 		struct cpudata *cpu = all_cpu_data[cpunum];
998 
999 		if (!cpu)
1000 			continue;
1001 
1002 		/*
1003 		 * During initialization, CPU performance at full capacity needs
1004 		 * to be determined.
1005 		 */
1006 		if (!hybrid_max_perf_cpu)
1007 			hybrid_get_capacity_perf(cpu);
1008 
1009 		/*
1010 		 * If hybrid_max_perf_cpu is not NULL at this point, it is
1011 		 * being replaced, so don't take it into account when looking
1012 		 * for the new one.
1013 		 */
1014 		if (cpu == hybrid_max_perf_cpu)
1015 			continue;
1016 
1017 		if (cpu->capacity_perf > max_cap_perf) {
1018 			max_cap_perf = cpu->capacity_perf;
1019 			max_perf_cpu = cpu;
1020 		}
1021 	}
1022 
1023 	if (max_perf_cpu) {
1024 		hybrid_max_perf_cpu = max_perf_cpu;
1025 		hybrid_set_capacity_of_cpus();
1026 	} else {
1027 		pr_info("Found no CPUs with nonzero maximum performance\n");
1028 		/* Revert to the flat CPU capacity structure. */
1029 		for_each_online_cpu(cpunum)
1030 			hybrid_clear_cpu_capacity(cpunum);
1031 	}
1032 }
1033 
__hybrid_refresh_cpu_capacity_scaling(void)1034 static void __hybrid_refresh_cpu_capacity_scaling(void)
1035 {
1036 	hybrid_max_perf_cpu = NULL;
1037 	hybrid_update_cpu_capacity_scaling();
1038 }
1039 
hybrid_refresh_cpu_capacity_scaling(void)1040 static void hybrid_refresh_cpu_capacity_scaling(void)
1041 {
1042 	guard(mutex)(&hybrid_capacity_lock);
1043 
1044 	__hybrid_refresh_cpu_capacity_scaling();
1045 }
1046 
hybrid_init_cpu_capacity_scaling(bool refresh)1047 static void hybrid_init_cpu_capacity_scaling(bool refresh)
1048 {
1049 	/* Bail out if enabling capacity-aware scheduling is prohibited. */
1050 	if (no_cas)
1051 		return;
1052 
1053 	/*
1054 	 * If hybrid_max_perf_cpu is set at this point, the hybrid CPU capacity
1055 	 * scaling has been enabled already and the driver is just changing the
1056 	 * operation mode.
1057 	 */
1058 	if (refresh) {
1059 		hybrid_refresh_cpu_capacity_scaling();
1060 		return;
1061 	}
1062 
1063 	/*
1064 	 * On hybrid systems, use asym capacity instead of ITMT, but because
1065 	 * the capacity of SMT threads is not deterministic even approximately,
1066 	 * do not do that when SMT is in use.
1067 	 */
1068 	if (hwp_is_hybrid && !sched_smt_active() && arch_enable_hybrid_capacity_scale()) {
1069 		hybrid_refresh_cpu_capacity_scaling();
1070 		/*
1071 		 * Disabling ITMT causes sched domains to be rebuilt to disable asym
1072 		 * packing and enable asym capacity.
1073 		 */
1074 		sched_clear_itmt_support();
1075 	}
1076 }
1077 
hybrid_clear_max_perf_cpu(void)1078 static bool hybrid_clear_max_perf_cpu(void)
1079 {
1080 	bool ret;
1081 
1082 	guard(mutex)(&hybrid_capacity_lock);
1083 
1084 	ret = !!hybrid_max_perf_cpu;
1085 	hybrid_max_perf_cpu = NULL;
1086 
1087 	return ret;
1088 }
1089 
__intel_pstate_get_hwp_cap(struct cpudata * cpu)1090 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
1091 {
1092 	u64 cap;
1093 
1094 	rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
1095 	WRITE_ONCE(cpu->hwp_cap_cached, cap);
1096 	cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
1097 	cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
1098 }
1099 
intel_pstate_get_hwp_cap(struct cpudata * cpu)1100 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
1101 {
1102 	int scaling = cpu->pstate.scaling;
1103 
1104 	__intel_pstate_get_hwp_cap(cpu);
1105 
1106 	cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
1107 	cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
1108 	if (scaling != cpu->pstate.perf_ctl_scaling) {
1109 		int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
1110 
1111 		cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
1112 						 perf_ctl_scaling);
1113 		cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
1114 						   perf_ctl_scaling);
1115 	}
1116 }
1117 
hybrid_update_capacity(struct cpudata * cpu)1118 static void hybrid_update_capacity(struct cpudata *cpu)
1119 {
1120 	unsigned int max_cap_perf;
1121 
1122 	mutex_lock(&hybrid_capacity_lock);
1123 
1124 	if (!hybrid_max_perf_cpu)
1125 		goto unlock;
1126 
1127 	/*
1128 	 * The maximum performance of the CPU may have changed, but assume
1129 	 * that the performance of the other CPUs has not changed.
1130 	 */
1131 	max_cap_perf = hybrid_max_perf_cpu->capacity_perf;
1132 
1133 	intel_pstate_get_hwp_cap(cpu);
1134 
1135 	hybrid_get_capacity_perf(cpu);
1136 	/* Should hybrid_max_perf_cpu be replaced by this CPU? */
1137 	if (cpu->capacity_perf > max_cap_perf) {
1138 		hybrid_max_perf_cpu = cpu;
1139 		hybrid_set_capacity_of_cpus();
1140 		goto unlock;
1141 	}
1142 
1143 	/* If this CPU is hybrid_max_perf_cpu, should it be replaced? */
1144 	if (cpu == hybrid_max_perf_cpu && cpu->capacity_perf < max_cap_perf) {
1145 		hybrid_update_cpu_capacity_scaling();
1146 		goto unlock;
1147 	}
1148 
1149 	hybrid_set_cpu_capacity(cpu);
1150 
1151 unlock:
1152 	mutex_unlock(&hybrid_capacity_lock);
1153 }
1154 
intel_pstate_hwp_set(unsigned int cpu)1155 static void intel_pstate_hwp_set(unsigned int cpu)
1156 {
1157 	struct cpudata *cpu_data = all_cpu_data[cpu];
1158 	int max, min;
1159 	u64 value;
1160 	s16 epp;
1161 
1162 	max = cpu_data->max_perf_ratio;
1163 	min = cpu_data->min_perf_ratio;
1164 
1165 	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
1166 		min = max;
1167 
1168 	rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
1169 
1170 	value &= ~HWP_MIN_PERF(~0L);
1171 	value |= HWP_MIN_PERF(min);
1172 
1173 	value &= ~HWP_MAX_PERF(~0L);
1174 	value |= HWP_MAX_PERF(max);
1175 
1176 	if (cpu_data->epp_policy == cpu_data->policy)
1177 		goto skip_epp;
1178 
1179 	cpu_data->epp_policy = cpu_data->policy;
1180 
1181 	if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
1182 		epp = intel_pstate_get_epp(cpu_data, value);
1183 		cpu_data->epp_powersave = epp;
1184 		/* If EPP read was failed, then don't try to write */
1185 		if (epp < 0)
1186 			goto skip_epp;
1187 
1188 		epp = 0;
1189 	} else {
1190 		/* skip setting EPP, when saved value is invalid */
1191 		if (cpu_data->epp_powersave < 0)
1192 			goto skip_epp;
1193 
1194 		/*
1195 		 * No need to restore EPP when it is not zero. This
1196 		 * means:
1197 		 *  - Policy is not changed
1198 		 *  - user has manually changed
1199 		 *  - Error reading EPB
1200 		 */
1201 		epp = intel_pstate_get_epp(cpu_data, value);
1202 		if (epp)
1203 			goto skip_epp;
1204 
1205 		epp = cpu_data->epp_powersave;
1206 	}
1207 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1208 		value &= ~GENMASK_ULL(31, 24);
1209 		value |= (u64)epp << 24;
1210 	} else {
1211 		intel_pstate_set_epb(cpu, epp);
1212 	}
1213 skip_epp:
1214 	WRITE_ONCE(cpu_data->hwp_req_cached, value);
1215 	wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1216 }
1217 
1218 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1219 
intel_pstate_hwp_offline(struct cpudata * cpu)1220 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1221 {
1222 	u64 value = READ_ONCE(cpu->hwp_req_cached);
1223 	int min_perf;
1224 
1225 	intel_pstate_disable_hwp_interrupt(cpu);
1226 
1227 	if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1228 		/*
1229 		 * In case the EPP has been set to "performance" by the
1230 		 * active mode "performance" scaling algorithm, replace that
1231 		 * temporary value with the cached EPP one.
1232 		 */
1233 		value &= ~GENMASK_ULL(31, 24);
1234 		value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1235 		/*
1236 		 * However, make sure that EPP will be set to "performance" when
1237 		 * the CPU is brought back online again and the "performance"
1238 		 * scaling algorithm is still in effect.
1239 		 */
1240 		cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1241 	}
1242 
1243 	/*
1244 	 * Clear the desired perf field in the cached HWP request value to
1245 	 * prevent nonzero desired values from being leaked into the active
1246 	 * mode.
1247 	 */
1248 	value &= ~HWP_DESIRED_PERF(~0L);
1249 	WRITE_ONCE(cpu->hwp_req_cached, value);
1250 
1251 	value &= ~GENMASK_ULL(31, 0);
1252 	min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1253 
1254 	/* Set hwp_max = hwp_min */
1255 	value |= HWP_MAX_PERF(min_perf);
1256 	value |= HWP_MIN_PERF(min_perf);
1257 
1258 	/* Set EPP to min */
1259 	if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1260 		value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1261 
1262 	wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1263 
1264 	mutex_lock(&hybrid_capacity_lock);
1265 
1266 	if (!hybrid_max_perf_cpu) {
1267 		mutex_unlock(&hybrid_capacity_lock);
1268 
1269 		return;
1270 	}
1271 
1272 	if (hybrid_max_perf_cpu == cpu)
1273 		hybrid_update_cpu_capacity_scaling();
1274 
1275 	mutex_unlock(&hybrid_capacity_lock);
1276 
1277 	/* Reset the capacity of the CPU going offline to the initial value. */
1278 	hybrid_clear_cpu_capacity(cpu->cpu);
1279 }
1280 
1281 #define POWER_CTL_EE_ENABLE	1
1282 #define POWER_CTL_EE_DISABLE	2
1283 
1284 static int power_ctl_ee_state;
1285 
set_power_ctl_ee_state(bool input)1286 static void set_power_ctl_ee_state(bool input)
1287 {
1288 	u64 power_ctl;
1289 
1290 	mutex_lock(&intel_pstate_driver_lock);
1291 	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1292 	if (input) {
1293 		power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1294 		power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1295 	} else {
1296 		power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1297 		power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1298 	}
1299 	wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1300 	mutex_unlock(&intel_pstate_driver_lock);
1301 }
1302 
1303 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1304 
intel_pstate_hwp_reenable(struct cpudata * cpu)1305 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1306 {
1307 	intel_pstate_hwp_enable(cpu);
1308 	wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1309 }
1310 
intel_pstate_suspend(struct cpufreq_policy * policy)1311 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1312 {
1313 	struct cpudata *cpu = all_cpu_data[policy->cpu];
1314 
1315 	pr_debug("CPU %d suspending\n", cpu->cpu);
1316 
1317 	cpu->suspended = true;
1318 
1319 	/* disable HWP interrupt and cancel any pending work */
1320 	intel_pstate_disable_hwp_interrupt(cpu);
1321 
1322 	return 0;
1323 }
1324 
intel_pstate_resume(struct cpufreq_policy * policy)1325 static int intel_pstate_resume(struct cpufreq_policy *policy)
1326 {
1327 	struct cpudata *cpu = all_cpu_data[policy->cpu];
1328 
1329 	pr_debug("CPU %d resuming\n", cpu->cpu);
1330 
1331 	/* Only restore if the system default is changed */
1332 	if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1333 		set_power_ctl_ee_state(true);
1334 	else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1335 		set_power_ctl_ee_state(false);
1336 
1337 	if (cpu->suspended && hwp_active) {
1338 		mutex_lock(&intel_pstate_limits_lock);
1339 
1340 		/* Re-enable HWP, because "online" has not done that. */
1341 		intel_pstate_hwp_reenable(cpu);
1342 
1343 		mutex_unlock(&intel_pstate_limits_lock);
1344 	}
1345 
1346 	cpu->suspended = false;
1347 
1348 	return 0;
1349 }
1350 
intel_pstate_update_policies(void)1351 static void intel_pstate_update_policies(void)
1352 {
1353 	int cpu;
1354 
1355 	for_each_possible_cpu(cpu)
1356 		cpufreq_update_policy(cpu);
1357 }
1358 
__intel_pstate_update_max_freq(struct cpudata * cpudata,struct cpufreq_policy * policy)1359 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1360 					   struct cpufreq_policy *policy)
1361 {
1362 	if (hwp_active)
1363 		intel_pstate_get_hwp_cap(cpudata);
1364 
1365 	policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
1366 			cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1367 
1368 	refresh_frequency_limits(policy);
1369 }
1370 
intel_pstate_update_limits(unsigned int cpu)1371 static void intel_pstate_update_limits(unsigned int cpu)
1372 {
1373 	struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1374 	struct cpudata *cpudata;
1375 
1376 	if (!policy)
1377 		return;
1378 
1379 	cpudata = all_cpu_data[cpu];
1380 
1381 	__intel_pstate_update_max_freq(cpudata, policy);
1382 
1383 	/* Prevent the driver from being unregistered now. */
1384 	mutex_lock(&intel_pstate_driver_lock);
1385 
1386 	cpufreq_cpu_release(policy);
1387 
1388 	hybrid_update_capacity(cpudata);
1389 
1390 	mutex_unlock(&intel_pstate_driver_lock);
1391 }
1392 
intel_pstate_update_limits_for_all(void)1393 static void intel_pstate_update_limits_for_all(void)
1394 {
1395 	int cpu;
1396 
1397 	for_each_possible_cpu(cpu) {
1398 		struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1399 
1400 		if (!policy)
1401 			continue;
1402 
1403 		__intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1404 
1405 		cpufreq_cpu_release(policy);
1406 	}
1407 
1408 	mutex_lock(&hybrid_capacity_lock);
1409 
1410 	if (hybrid_max_perf_cpu)
1411 		__hybrid_refresh_cpu_capacity_scaling();
1412 
1413 	mutex_unlock(&hybrid_capacity_lock);
1414 }
1415 
1416 /************************** sysfs begin ************************/
1417 #define show_one(file_name, object)					\
1418 	static ssize_t show_##file_name					\
1419 	(struct kobject *kobj, struct kobj_attribute *attr, char *buf)	\
1420 	{								\
1421 		return sprintf(buf, "%u\n", global.object);		\
1422 	}
1423 
1424 static ssize_t intel_pstate_show_status(char *buf);
1425 static int intel_pstate_update_status(const char *buf, size_t size);
1426 
show_status(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1427 static ssize_t show_status(struct kobject *kobj,
1428 			   struct kobj_attribute *attr, char *buf)
1429 {
1430 	ssize_t ret;
1431 
1432 	mutex_lock(&intel_pstate_driver_lock);
1433 	ret = intel_pstate_show_status(buf);
1434 	mutex_unlock(&intel_pstate_driver_lock);
1435 
1436 	return ret;
1437 }
1438 
store_status(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1439 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1440 			    const char *buf, size_t count)
1441 {
1442 	char *p = memchr(buf, '\n', count);
1443 	int ret;
1444 
1445 	mutex_lock(&intel_pstate_driver_lock);
1446 	ret = intel_pstate_update_status(buf, p ? p - buf : count);
1447 	mutex_unlock(&intel_pstate_driver_lock);
1448 
1449 	return ret < 0 ? ret : count;
1450 }
1451 
show_turbo_pct(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1452 static ssize_t show_turbo_pct(struct kobject *kobj,
1453 				struct kobj_attribute *attr, char *buf)
1454 {
1455 	struct cpudata *cpu;
1456 	int total, no_turbo, turbo_pct;
1457 	uint32_t turbo_fp;
1458 
1459 	mutex_lock(&intel_pstate_driver_lock);
1460 
1461 	if (!intel_pstate_driver) {
1462 		mutex_unlock(&intel_pstate_driver_lock);
1463 		return -EAGAIN;
1464 	}
1465 
1466 	cpu = all_cpu_data[0];
1467 
1468 	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1469 	no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1470 	turbo_fp = div_fp(no_turbo, total);
1471 	turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1472 
1473 	mutex_unlock(&intel_pstate_driver_lock);
1474 
1475 	return sprintf(buf, "%u\n", turbo_pct);
1476 }
1477 
show_num_pstates(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1478 static ssize_t show_num_pstates(struct kobject *kobj,
1479 				struct kobj_attribute *attr, char *buf)
1480 {
1481 	struct cpudata *cpu;
1482 	int total;
1483 
1484 	mutex_lock(&intel_pstate_driver_lock);
1485 
1486 	if (!intel_pstate_driver) {
1487 		mutex_unlock(&intel_pstate_driver_lock);
1488 		return -EAGAIN;
1489 	}
1490 
1491 	cpu = all_cpu_data[0];
1492 	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1493 
1494 	mutex_unlock(&intel_pstate_driver_lock);
1495 
1496 	return sprintf(buf, "%u\n", total);
1497 }
1498 
show_no_turbo(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1499 static ssize_t show_no_turbo(struct kobject *kobj,
1500 			     struct kobj_attribute *attr, char *buf)
1501 {
1502 	ssize_t ret;
1503 
1504 	mutex_lock(&intel_pstate_driver_lock);
1505 
1506 	if (!intel_pstate_driver) {
1507 		mutex_unlock(&intel_pstate_driver_lock);
1508 		return -EAGAIN;
1509 	}
1510 
1511 	ret = sprintf(buf, "%u\n", global.no_turbo);
1512 
1513 	mutex_unlock(&intel_pstate_driver_lock);
1514 
1515 	return ret;
1516 }
1517 
store_no_turbo(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1518 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1519 			      const char *buf, size_t count)
1520 {
1521 	unsigned int input;
1522 	bool no_turbo;
1523 
1524 	if (sscanf(buf, "%u", &input) != 1)
1525 		return -EINVAL;
1526 
1527 	mutex_lock(&intel_pstate_driver_lock);
1528 
1529 	if (!intel_pstate_driver) {
1530 		count = -EAGAIN;
1531 		goto unlock_driver;
1532 	}
1533 
1534 	no_turbo = !!clamp_t(int, input, 0, 1);
1535 
1536 	WRITE_ONCE(global.turbo_disabled, turbo_is_disabled());
1537 	if (global.turbo_disabled && !no_turbo) {
1538 		pr_notice("Turbo disabled by BIOS or unavailable on processor\n");
1539 		count = -EPERM;
1540 		if (global.no_turbo)
1541 			goto unlock_driver;
1542 		else
1543 			no_turbo = 1;
1544 	}
1545 
1546 	if (no_turbo == global.no_turbo) {
1547 		goto unlock_driver;
1548 	}
1549 
1550 	WRITE_ONCE(global.no_turbo, no_turbo);
1551 
1552 	mutex_lock(&intel_pstate_limits_lock);
1553 
1554 	if (no_turbo) {
1555 		struct cpudata *cpu = all_cpu_data[0];
1556 		int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1557 
1558 		/* Squash the global minimum into the permitted range. */
1559 		if (global.min_perf_pct > pct)
1560 			global.min_perf_pct = pct;
1561 	}
1562 
1563 	mutex_unlock(&intel_pstate_limits_lock);
1564 
1565 	intel_pstate_update_limits_for_all();
1566 	arch_set_max_freq_ratio(no_turbo);
1567 
1568 unlock_driver:
1569 	mutex_unlock(&intel_pstate_driver_lock);
1570 
1571 	return count;
1572 }
1573 
update_qos_request(enum freq_qos_req_type type)1574 static void update_qos_request(enum freq_qos_req_type type)
1575 {
1576 	struct freq_qos_request *req;
1577 	struct cpufreq_policy *policy;
1578 	int i;
1579 
1580 	for_each_possible_cpu(i) {
1581 		struct cpudata *cpu = all_cpu_data[i];
1582 		unsigned int freq, perf_pct;
1583 
1584 		policy = cpufreq_cpu_get(i);
1585 		if (!policy)
1586 			continue;
1587 
1588 		req = policy->driver_data;
1589 		cpufreq_cpu_put(policy);
1590 
1591 		if (!req)
1592 			continue;
1593 
1594 		if (hwp_active)
1595 			intel_pstate_get_hwp_cap(cpu);
1596 
1597 		if (type == FREQ_QOS_MIN) {
1598 			perf_pct = global.min_perf_pct;
1599 		} else {
1600 			req++;
1601 			perf_pct = global.max_perf_pct;
1602 		}
1603 
1604 		freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1605 
1606 		if (freq_qos_update_request(req, freq) < 0)
1607 			pr_warn("Failed to update freq constraint: CPU%d\n", i);
1608 	}
1609 }
1610 
store_max_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1611 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1612 				  const char *buf, size_t count)
1613 {
1614 	unsigned int input;
1615 	int ret;
1616 
1617 	ret = sscanf(buf, "%u", &input);
1618 	if (ret != 1)
1619 		return -EINVAL;
1620 
1621 	mutex_lock(&intel_pstate_driver_lock);
1622 
1623 	if (!intel_pstate_driver) {
1624 		mutex_unlock(&intel_pstate_driver_lock);
1625 		return -EAGAIN;
1626 	}
1627 
1628 	mutex_lock(&intel_pstate_limits_lock);
1629 
1630 	global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1631 
1632 	mutex_unlock(&intel_pstate_limits_lock);
1633 
1634 	if (intel_pstate_driver == &intel_pstate)
1635 		intel_pstate_update_policies();
1636 	else
1637 		update_qos_request(FREQ_QOS_MAX);
1638 
1639 	mutex_unlock(&intel_pstate_driver_lock);
1640 
1641 	return count;
1642 }
1643 
store_min_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1644 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1645 				  const char *buf, size_t count)
1646 {
1647 	unsigned int input;
1648 	int ret;
1649 
1650 	ret = sscanf(buf, "%u", &input);
1651 	if (ret != 1)
1652 		return -EINVAL;
1653 
1654 	mutex_lock(&intel_pstate_driver_lock);
1655 
1656 	if (!intel_pstate_driver) {
1657 		mutex_unlock(&intel_pstate_driver_lock);
1658 		return -EAGAIN;
1659 	}
1660 
1661 	mutex_lock(&intel_pstate_limits_lock);
1662 
1663 	global.min_perf_pct = clamp_t(int, input,
1664 				      min_perf_pct_min(), global.max_perf_pct);
1665 
1666 	mutex_unlock(&intel_pstate_limits_lock);
1667 
1668 	if (intel_pstate_driver == &intel_pstate)
1669 		intel_pstate_update_policies();
1670 	else
1671 		update_qos_request(FREQ_QOS_MIN);
1672 
1673 	mutex_unlock(&intel_pstate_driver_lock);
1674 
1675 	return count;
1676 }
1677 
show_hwp_dynamic_boost(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1678 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1679 				struct kobj_attribute *attr, char *buf)
1680 {
1681 	return sprintf(buf, "%u\n", hwp_boost);
1682 }
1683 
store_hwp_dynamic_boost(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1684 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1685 				       struct kobj_attribute *b,
1686 				       const char *buf, size_t count)
1687 {
1688 	unsigned int input;
1689 	int ret;
1690 
1691 	ret = kstrtouint(buf, 10, &input);
1692 	if (ret)
1693 		return ret;
1694 
1695 	mutex_lock(&intel_pstate_driver_lock);
1696 	hwp_boost = !!input;
1697 	intel_pstate_update_policies();
1698 	mutex_unlock(&intel_pstate_driver_lock);
1699 
1700 	return count;
1701 }
1702 
show_energy_efficiency(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1703 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1704 				      char *buf)
1705 {
1706 	u64 power_ctl;
1707 	int enable;
1708 
1709 	rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1710 	enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1711 	return sprintf(buf, "%d\n", !enable);
1712 }
1713 
store_energy_efficiency(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1714 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1715 				       const char *buf, size_t count)
1716 {
1717 	bool input;
1718 	int ret;
1719 
1720 	ret = kstrtobool(buf, &input);
1721 	if (ret)
1722 		return ret;
1723 
1724 	set_power_ctl_ee_state(input);
1725 
1726 	return count;
1727 }
1728 
1729 show_one(max_perf_pct, max_perf_pct);
1730 show_one(min_perf_pct, min_perf_pct);
1731 
1732 define_one_global_rw(status);
1733 define_one_global_rw(no_turbo);
1734 define_one_global_rw(max_perf_pct);
1735 define_one_global_rw(min_perf_pct);
1736 define_one_global_ro(turbo_pct);
1737 define_one_global_ro(num_pstates);
1738 define_one_global_rw(hwp_dynamic_boost);
1739 define_one_global_rw(energy_efficiency);
1740 
1741 static struct attribute *intel_pstate_attributes[] = {
1742 	&status.attr,
1743 	&no_turbo.attr,
1744 	NULL
1745 };
1746 
1747 static const struct attribute_group intel_pstate_attr_group = {
1748 	.attrs = intel_pstate_attributes,
1749 };
1750 
1751 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1752 
1753 static struct kobject *intel_pstate_kobject;
1754 
intel_pstate_sysfs_expose_params(void)1755 static void __init intel_pstate_sysfs_expose_params(void)
1756 {
1757 	struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1758 	int rc;
1759 
1760 	if (dev_root) {
1761 		intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1762 		put_device(dev_root);
1763 	}
1764 	if (WARN_ON(!intel_pstate_kobject))
1765 		return;
1766 
1767 	rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1768 	if (WARN_ON(rc))
1769 		return;
1770 
1771 	if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1772 		rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1773 		WARN_ON(rc);
1774 
1775 		rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1776 		WARN_ON(rc);
1777 	}
1778 
1779 	/*
1780 	 * If per cpu limits are enforced there are no global limits, so
1781 	 * return without creating max/min_perf_pct attributes
1782 	 */
1783 	if (per_cpu_limits)
1784 		return;
1785 
1786 	rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1787 	WARN_ON(rc);
1788 
1789 	rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1790 	WARN_ON(rc);
1791 
1792 	if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1793 		rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1794 		WARN_ON(rc);
1795 	}
1796 }
1797 
intel_pstate_sysfs_remove(void)1798 static void __init intel_pstate_sysfs_remove(void)
1799 {
1800 	if (!intel_pstate_kobject)
1801 		return;
1802 
1803 	sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1804 
1805 	if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1806 		sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1807 		sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1808 	}
1809 
1810 	if (!per_cpu_limits) {
1811 		sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1812 		sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1813 
1814 		if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1815 			sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1816 	}
1817 
1818 	kobject_put(intel_pstate_kobject);
1819 }
1820 
intel_pstate_sysfs_expose_hwp_dynamic_boost(void)1821 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1822 {
1823 	int rc;
1824 
1825 	if (!hwp_active)
1826 		return;
1827 
1828 	rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1829 	WARN_ON_ONCE(rc);
1830 }
1831 
intel_pstate_sysfs_hide_hwp_dynamic_boost(void)1832 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1833 {
1834 	if (!hwp_active)
1835 		return;
1836 
1837 	sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1838 }
1839 
1840 /************************** sysfs end ************************/
1841 
intel_pstate_notify_work(struct work_struct * work)1842 static void intel_pstate_notify_work(struct work_struct *work)
1843 {
1844 	struct cpudata *cpudata =
1845 		container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1846 	struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1847 
1848 	if (policy) {
1849 		__intel_pstate_update_max_freq(cpudata, policy);
1850 
1851 		cpufreq_cpu_release(policy);
1852 
1853 		/*
1854 		 * The driver will not be unregistered while this function is
1855 		 * running, so update the capacity without acquiring the driver
1856 		 * lock.
1857 		 */
1858 		hybrid_update_capacity(cpudata);
1859 	}
1860 
1861 	wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1862 }
1863 
1864 static DEFINE_RAW_SPINLOCK(hwp_notify_lock);
1865 static cpumask_t hwp_intr_enable_mask;
1866 
1867 #define HWP_GUARANTEED_PERF_CHANGE_STATUS      BIT(0)
1868 #define HWP_HIGHEST_PERF_CHANGE_STATUS         BIT(3)
1869 
notify_hwp_interrupt(void)1870 void notify_hwp_interrupt(void)
1871 {
1872 	unsigned int this_cpu = smp_processor_id();
1873 	u64 value, status_mask;
1874 	unsigned long flags;
1875 
1876 	if (!hwp_active || !cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1877 		return;
1878 
1879 	status_mask = HWP_GUARANTEED_PERF_CHANGE_STATUS;
1880 	if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1881 		status_mask |= HWP_HIGHEST_PERF_CHANGE_STATUS;
1882 
1883 	rdmsrl_safe(MSR_HWP_STATUS, &value);
1884 	if (!(value & status_mask))
1885 		return;
1886 
1887 	raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1888 
1889 	if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1890 		goto ack_intr;
1891 
1892 	schedule_delayed_work(&all_cpu_data[this_cpu]->hwp_notify_work,
1893 			      msecs_to_jiffies(10));
1894 
1895 	raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1896 
1897 	return;
1898 
1899 ack_intr:
1900 	wrmsrl_safe(MSR_HWP_STATUS, 0);
1901 	raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1902 }
1903 
intel_pstate_disable_hwp_interrupt(struct cpudata * cpudata)1904 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1905 {
1906 	bool cancel_work;
1907 
1908 	if (!cpu_feature_enabled(X86_FEATURE_HWP_NOTIFY))
1909 		return;
1910 
1911 	/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1912 	wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1913 
1914 	raw_spin_lock_irq(&hwp_notify_lock);
1915 	cancel_work = cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1916 	raw_spin_unlock_irq(&hwp_notify_lock);
1917 
1918 	if (cancel_work)
1919 		cancel_delayed_work_sync(&cpudata->hwp_notify_work);
1920 }
1921 
1922 #define HWP_GUARANTEED_PERF_CHANGE_REQ BIT(0)
1923 #define HWP_HIGHEST_PERF_CHANGE_REQ    BIT(2)
1924 
intel_pstate_enable_hwp_interrupt(struct cpudata * cpudata)1925 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1926 {
1927 	/* Enable HWP notification interrupt for performance change */
1928 	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1929 		u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ;
1930 
1931 		raw_spin_lock_irq(&hwp_notify_lock);
1932 		INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1933 		cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1934 		raw_spin_unlock_irq(&hwp_notify_lock);
1935 
1936 		if (cpu_feature_enabled(X86_FEATURE_HWP_HIGHEST_PERF_CHANGE))
1937 			interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ;
1938 
1939 		/* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1940 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask);
1941 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1942 	}
1943 }
1944 
intel_pstate_update_epp_defaults(struct cpudata * cpudata)1945 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1946 {
1947 	cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1948 
1949 	/*
1950 	 * If the EPP is set by firmware, which means that firmware enabled HWP
1951 	 * - Is equal or less than 0x80 (default balance_perf EPP)
1952 	 * - But less performance oriented than performance EPP
1953 	 *   then use this as new balance_perf EPP.
1954 	 */
1955 	if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1956 	    cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1957 		epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1958 		return;
1959 	}
1960 
1961 	/*
1962 	 * If this CPU gen doesn't call for change in balance_perf
1963 	 * EPP return.
1964 	 */
1965 	if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1966 		return;
1967 
1968 	/*
1969 	 * Use hard coded value per gen to update the balance_perf
1970 	 * and default EPP.
1971 	 */
1972 	cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1973 	intel_pstate_set_epp(cpudata, cpudata->epp_default);
1974 }
1975 
intel_pstate_hwp_enable(struct cpudata * cpudata)1976 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1977 {
1978 	/* First disable HWP notification interrupt till we activate again */
1979 	if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1980 		wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1981 
1982 	wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1983 
1984 	intel_pstate_enable_hwp_interrupt(cpudata);
1985 
1986 	if (cpudata->epp_default >= 0)
1987 		return;
1988 
1989 	intel_pstate_update_epp_defaults(cpudata);
1990 }
1991 
atom_get_min_pstate(int not_used)1992 static int atom_get_min_pstate(int not_used)
1993 {
1994 	u64 value;
1995 
1996 	rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1997 	return (value >> 8) & 0x7F;
1998 }
1999 
atom_get_max_pstate(int not_used)2000 static int atom_get_max_pstate(int not_used)
2001 {
2002 	u64 value;
2003 
2004 	rdmsrl(MSR_ATOM_CORE_RATIOS, value);
2005 	return (value >> 16) & 0x7F;
2006 }
2007 
atom_get_turbo_pstate(int not_used)2008 static int atom_get_turbo_pstate(int not_used)
2009 {
2010 	u64 value;
2011 
2012 	rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
2013 	return value & 0x7F;
2014 }
2015 
atom_get_val(struct cpudata * cpudata,int pstate)2016 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
2017 {
2018 	u64 val;
2019 	int32_t vid_fp;
2020 	u32 vid;
2021 
2022 	val = (u64)pstate << 8;
2023 	if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled))
2024 		val |= (u64)1 << 32;
2025 
2026 	vid_fp = cpudata->vid.min + mul_fp(
2027 		int_tofp(pstate - cpudata->pstate.min_pstate),
2028 		cpudata->vid.ratio);
2029 
2030 	vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
2031 	vid = ceiling_fp(vid_fp);
2032 
2033 	if (pstate > cpudata->pstate.max_pstate)
2034 		vid = cpudata->vid.turbo;
2035 
2036 	return val | vid;
2037 }
2038 
silvermont_get_scaling(void)2039 static int silvermont_get_scaling(void)
2040 {
2041 	u64 value;
2042 	int i;
2043 	/* Defined in Table 35-6 from SDM (Sept 2015) */
2044 	static int silvermont_freq_table[] = {
2045 		83300, 100000, 133300, 116700, 80000};
2046 
2047 	rdmsrl(MSR_FSB_FREQ, value);
2048 	i = value & 0x7;
2049 	WARN_ON(i > 4);
2050 
2051 	return silvermont_freq_table[i];
2052 }
2053 
airmont_get_scaling(void)2054 static int airmont_get_scaling(void)
2055 {
2056 	u64 value;
2057 	int i;
2058 	/* Defined in Table 35-10 from SDM (Sept 2015) */
2059 	static int airmont_freq_table[] = {
2060 		83300, 100000, 133300, 116700, 80000,
2061 		93300, 90000, 88900, 87500};
2062 
2063 	rdmsrl(MSR_FSB_FREQ, value);
2064 	i = value & 0xF;
2065 	WARN_ON(i > 8);
2066 
2067 	return airmont_freq_table[i];
2068 }
2069 
atom_get_vid(struct cpudata * cpudata)2070 static void atom_get_vid(struct cpudata *cpudata)
2071 {
2072 	u64 value;
2073 
2074 	rdmsrl(MSR_ATOM_CORE_VIDS, value);
2075 	cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
2076 	cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
2077 	cpudata->vid.ratio = div_fp(
2078 		cpudata->vid.max - cpudata->vid.min,
2079 		int_tofp(cpudata->pstate.max_pstate -
2080 			cpudata->pstate.min_pstate));
2081 
2082 	rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
2083 	cpudata->vid.turbo = value & 0x7f;
2084 }
2085 
core_get_min_pstate(int cpu)2086 static int core_get_min_pstate(int cpu)
2087 {
2088 	u64 value;
2089 
2090 	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2091 	return (value >> 40) & 0xFF;
2092 }
2093 
core_get_max_pstate_physical(int cpu)2094 static int core_get_max_pstate_physical(int cpu)
2095 {
2096 	u64 value;
2097 
2098 	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
2099 	return (value >> 8) & 0xFF;
2100 }
2101 
core_get_tdp_ratio(int cpu,u64 plat_info)2102 static int core_get_tdp_ratio(int cpu, u64 plat_info)
2103 {
2104 	/* Check how many TDP levels present */
2105 	if (plat_info & 0x600000000) {
2106 		u64 tdp_ctrl;
2107 		u64 tdp_ratio;
2108 		int tdp_msr;
2109 		int err;
2110 
2111 		/* Get the TDP level (0, 1, 2) to get ratios */
2112 		err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
2113 		if (err)
2114 			return err;
2115 
2116 		/* TDP MSR are continuous starting at 0x648 */
2117 		tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
2118 		err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
2119 		if (err)
2120 			return err;
2121 
2122 		/* For level 1 and 2, bits[23:16] contain the ratio */
2123 		if (tdp_ctrl & 0x03)
2124 			tdp_ratio >>= 16;
2125 
2126 		tdp_ratio &= 0xff; /* ratios are only 8 bits long */
2127 		pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
2128 
2129 		return (int)tdp_ratio;
2130 	}
2131 
2132 	return -ENXIO;
2133 }
2134 
core_get_max_pstate(int cpu)2135 static int core_get_max_pstate(int cpu)
2136 {
2137 	u64 tar;
2138 	u64 plat_info;
2139 	int max_pstate;
2140 	int tdp_ratio;
2141 	int err;
2142 
2143 	rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
2144 	max_pstate = (plat_info >> 8) & 0xFF;
2145 
2146 	tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
2147 	if (tdp_ratio <= 0)
2148 		return max_pstate;
2149 
2150 	if (hwp_active) {
2151 		/* Turbo activation ratio is not used on HWP platforms */
2152 		return tdp_ratio;
2153 	}
2154 
2155 	err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
2156 	if (!err) {
2157 		int tar_levels;
2158 
2159 		/* Do some sanity checking for safety */
2160 		tar_levels = tar & 0xff;
2161 		if (tdp_ratio - 1 == tar_levels) {
2162 			max_pstate = tar_levels;
2163 			pr_debug("max_pstate=TAC %x\n", max_pstate);
2164 		}
2165 	}
2166 
2167 	return max_pstate;
2168 }
2169 
core_get_turbo_pstate(int cpu)2170 static int core_get_turbo_pstate(int cpu)
2171 {
2172 	u64 value;
2173 	int nont, ret;
2174 
2175 	rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2176 	nont = core_get_max_pstate(cpu);
2177 	ret = (value) & 255;
2178 	if (ret <= nont)
2179 		ret = nont;
2180 	return ret;
2181 }
2182 
core_get_val(struct cpudata * cpudata,int pstate)2183 static u64 core_get_val(struct cpudata *cpudata, int pstate)
2184 {
2185 	u64 val;
2186 
2187 	val = (u64)pstate << 8;
2188 	if (READ_ONCE(global.no_turbo) && !READ_ONCE(global.turbo_disabled))
2189 		val |= (u64)1 << 32;
2190 
2191 	return val;
2192 }
2193 
knl_get_aperf_mperf_shift(void)2194 static int knl_get_aperf_mperf_shift(void)
2195 {
2196 	return 10;
2197 }
2198 
knl_get_turbo_pstate(int cpu)2199 static int knl_get_turbo_pstate(int cpu)
2200 {
2201 	u64 value;
2202 	int nont, ret;
2203 
2204 	rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
2205 	nont = core_get_max_pstate(cpu);
2206 	ret = (((value) >> 8) & 0xFF);
2207 	if (ret <= nont)
2208 		ret = nont;
2209 	return ret;
2210 }
2211 
hwp_get_cpu_scaling(int cpu)2212 static int hwp_get_cpu_scaling(int cpu)
2213 {
2214 	if (hybrid_scaling_factor) {
2215 		struct cpuinfo_x86 *c = &cpu_data(cpu);
2216 		u8 cpu_type = c->topo.intel_type;
2217 
2218 		/*
2219 		 * Return the hybrid scaling factor for P-cores and use the
2220 		 * default core scaling for E-cores.
2221 		 */
2222 		if (cpu_type == INTEL_CPU_TYPE_CORE)
2223 			return hybrid_scaling_factor;
2224 
2225 		if (cpu_type == INTEL_CPU_TYPE_ATOM)
2226 			return core_get_scaling();
2227 	}
2228 
2229 	/* Use core scaling on non-hybrid systems. */
2230 	if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
2231 		return core_get_scaling();
2232 
2233 	/*
2234 	 * The system is hybrid, but the hybrid scaling factor is not known or
2235 	 * the CPU type is not one of the above, so use CPPC to compute the
2236 	 * scaling factor for this CPU.
2237 	 */
2238 	return intel_pstate_cppc_get_scaling(cpu);
2239 }
2240 
intel_pstate_set_pstate(struct cpudata * cpu,int pstate)2241 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2242 {
2243 	trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2244 	cpu->pstate.current_pstate = pstate;
2245 	/*
2246 	 * Generally, there is no guarantee that this code will always run on
2247 	 * the CPU being updated, so force the register update to run on the
2248 	 * right CPU.
2249 	 */
2250 	wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2251 		      pstate_funcs.get_val(cpu, pstate));
2252 }
2253 
intel_pstate_set_min_pstate(struct cpudata * cpu)2254 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2255 {
2256 	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2257 }
2258 
intel_pstate_get_cpu_pstates(struct cpudata * cpu)2259 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2260 {
2261 	int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2262 	int perf_ctl_scaling = pstate_funcs.get_scaling();
2263 
2264 	cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2265 	cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2266 	cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2267 
2268 	if (hwp_active && !hwp_mode_bdw) {
2269 		__intel_pstate_get_hwp_cap(cpu);
2270 
2271 		if (pstate_funcs.get_cpu_scaling) {
2272 			cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2273 			if (cpu->pstate.scaling != perf_ctl_scaling) {
2274 				intel_pstate_hybrid_hwp_adjust(cpu);
2275 				hwp_is_hybrid = true;
2276 			}
2277 		} else {
2278 			cpu->pstate.scaling = perf_ctl_scaling;
2279 		}
2280 		/*
2281 		 * If the CPU is going online for the first time and it was
2282 		 * offline initially, asym capacity scaling needs to be updated.
2283 		 */
2284 		hybrid_update_capacity(cpu);
2285 	} else {
2286 		cpu->pstate.scaling = perf_ctl_scaling;
2287 		cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2288 		cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2289 	}
2290 
2291 	if (cpu->pstate.scaling == perf_ctl_scaling) {
2292 		cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2293 		cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2294 		cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2295 	}
2296 
2297 	if (pstate_funcs.get_aperf_mperf_shift)
2298 		cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2299 
2300 	if (pstate_funcs.get_vid)
2301 		pstate_funcs.get_vid(cpu);
2302 
2303 	intel_pstate_set_min_pstate(cpu);
2304 }
2305 
2306 /*
2307  * Long hold time will keep high perf limits for long time,
2308  * which negatively impacts perf/watt for some workloads,
2309  * like specpower. 3ms is based on experiements on some
2310  * workoads.
2311  */
2312 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2313 
intel_pstate_hwp_boost_up(struct cpudata * cpu)2314 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2315 {
2316 	u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2317 	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2318 	u32 max_limit = (hwp_req & 0xff00) >> 8;
2319 	u32 min_limit = (hwp_req & 0xff);
2320 	u32 boost_level1;
2321 
2322 	/*
2323 	 * Cases to consider (User changes via sysfs or boot time):
2324 	 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2325 	 *	No boost, return.
2326 	 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2327 	 *     Should result in one level boost only for P0.
2328 	 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2329 	 *     Should result in two level boost:
2330 	 *         (min + p1)/2 and P1.
2331 	 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2332 	 *     Should result in three level boost:
2333 	 *        (min + p1)/2, P1 and P0.
2334 	 */
2335 
2336 	/* If max and min are equal or already at max, nothing to boost */
2337 	if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2338 		return;
2339 
2340 	if (!cpu->hwp_boost_min)
2341 		cpu->hwp_boost_min = min_limit;
2342 
2343 	/* level at half way mark between min and guranteed */
2344 	boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2345 
2346 	if (cpu->hwp_boost_min < boost_level1)
2347 		cpu->hwp_boost_min = boost_level1;
2348 	else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2349 		cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2350 	else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2351 		 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2352 		cpu->hwp_boost_min = max_limit;
2353 	else
2354 		return;
2355 
2356 	hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2357 	wrmsrl(MSR_HWP_REQUEST, hwp_req);
2358 	cpu->last_update = cpu->sample.time;
2359 }
2360 
intel_pstate_hwp_boost_down(struct cpudata * cpu)2361 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2362 {
2363 	if (cpu->hwp_boost_min) {
2364 		bool expired;
2365 
2366 		/* Check if we are idle for hold time to boost down */
2367 		expired = time_after64(cpu->sample.time, cpu->last_update +
2368 				       hwp_boost_hold_time_ns);
2369 		if (expired) {
2370 			wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2371 			cpu->hwp_boost_min = 0;
2372 		}
2373 	}
2374 	cpu->last_update = cpu->sample.time;
2375 }
2376 
intel_pstate_update_util_hwp_local(struct cpudata * cpu,u64 time)2377 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2378 						      u64 time)
2379 {
2380 	cpu->sample.time = time;
2381 
2382 	if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2383 		bool do_io = false;
2384 
2385 		cpu->sched_flags = 0;
2386 		/*
2387 		 * Set iowait_boost flag and update time. Since IO WAIT flag
2388 		 * is set all the time, we can't just conclude that there is
2389 		 * some IO bound activity is scheduled on this CPU with just
2390 		 * one occurrence. If we receive at least two in two
2391 		 * consecutive ticks, then we treat as boost candidate.
2392 		 */
2393 		if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2394 			do_io = true;
2395 
2396 		cpu->last_io_update = time;
2397 
2398 		if (do_io)
2399 			intel_pstate_hwp_boost_up(cpu);
2400 
2401 	} else {
2402 		intel_pstate_hwp_boost_down(cpu);
2403 	}
2404 }
2405 
intel_pstate_update_util_hwp(struct update_util_data * data,u64 time,unsigned int flags)2406 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2407 						u64 time, unsigned int flags)
2408 {
2409 	struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2410 
2411 	cpu->sched_flags |= flags;
2412 
2413 	if (smp_processor_id() == cpu->cpu)
2414 		intel_pstate_update_util_hwp_local(cpu, time);
2415 }
2416 
intel_pstate_calc_avg_perf(struct cpudata * cpu)2417 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2418 {
2419 	struct sample *sample = &cpu->sample;
2420 
2421 	sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2422 }
2423 
intel_pstate_sample(struct cpudata * cpu,u64 time)2424 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2425 {
2426 	u64 aperf, mperf;
2427 	unsigned long flags;
2428 	u64 tsc;
2429 
2430 	local_irq_save(flags);
2431 	rdmsrl(MSR_IA32_APERF, aperf);
2432 	rdmsrl(MSR_IA32_MPERF, mperf);
2433 	tsc = rdtsc();
2434 	if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2435 		local_irq_restore(flags);
2436 		return false;
2437 	}
2438 	local_irq_restore(flags);
2439 
2440 	cpu->last_sample_time = cpu->sample.time;
2441 	cpu->sample.time = time;
2442 	cpu->sample.aperf = aperf;
2443 	cpu->sample.mperf = mperf;
2444 	cpu->sample.tsc =  tsc;
2445 	cpu->sample.aperf -= cpu->prev_aperf;
2446 	cpu->sample.mperf -= cpu->prev_mperf;
2447 	cpu->sample.tsc -= cpu->prev_tsc;
2448 
2449 	cpu->prev_aperf = aperf;
2450 	cpu->prev_mperf = mperf;
2451 	cpu->prev_tsc = tsc;
2452 	/*
2453 	 * First time this function is invoked in a given cycle, all of the
2454 	 * previous sample data fields are equal to zero or stale and they must
2455 	 * be populated with meaningful numbers for things to work, so assume
2456 	 * that sample.time will always be reset before setting the utilization
2457 	 * update hook and make the caller skip the sample then.
2458 	 */
2459 	if (cpu->last_sample_time) {
2460 		intel_pstate_calc_avg_perf(cpu);
2461 		return true;
2462 	}
2463 	return false;
2464 }
2465 
get_avg_frequency(struct cpudata * cpu)2466 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2467 {
2468 	return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2469 }
2470 
get_avg_pstate(struct cpudata * cpu)2471 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2472 {
2473 	return mul_ext_fp(cpu->pstate.max_pstate_physical,
2474 			  cpu->sample.core_avg_perf);
2475 }
2476 
get_target_pstate(struct cpudata * cpu)2477 static inline int32_t get_target_pstate(struct cpudata *cpu)
2478 {
2479 	struct sample *sample = &cpu->sample;
2480 	int32_t busy_frac;
2481 	int target, avg_pstate;
2482 
2483 	busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2484 			   sample->tsc);
2485 
2486 	if (busy_frac < cpu->iowait_boost)
2487 		busy_frac = cpu->iowait_boost;
2488 
2489 	sample->busy_scaled = busy_frac * 100;
2490 
2491 	target = READ_ONCE(global.no_turbo) ?
2492 			cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2493 	target += target >> 2;
2494 	target = mul_fp(target, busy_frac);
2495 	if (target < cpu->pstate.min_pstate)
2496 		target = cpu->pstate.min_pstate;
2497 
2498 	/*
2499 	 * If the average P-state during the previous cycle was higher than the
2500 	 * current target, add 50% of the difference to the target to reduce
2501 	 * possible performance oscillations and offset possible performance
2502 	 * loss related to moving the workload from one CPU to another within
2503 	 * a package/module.
2504 	 */
2505 	avg_pstate = get_avg_pstate(cpu);
2506 	if (avg_pstate > target)
2507 		target += (avg_pstate - target) >> 1;
2508 
2509 	return target;
2510 }
2511 
intel_pstate_prepare_request(struct cpudata * cpu,int pstate)2512 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2513 {
2514 	int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2515 	int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2516 
2517 	return clamp_t(int, pstate, min_pstate, max_pstate);
2518 }
2519 
intel_pstate_update_pstate(struct cpudata * cpu,int pstate)2520 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2521 {
2522 	if (pstate == cpu->pstate.current_pstate)
2523 		return;
2524 
2525 	cpu->pstate.current_pstate = pstate;
2526 	wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2527 }
2528 
intel_pstate_adjust_pstate(struct cpudata * cpu)2529 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2530 {
2531 	int from = cpu->pstate.current_pstate;
2532 	struct sample *sample;
2533 	int target_pstate;
2534 
2535 	target_pstate = get_target_pstate(cpu);
2536 	target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2537 	trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2538 	intel_pstate_update_pstate(cpu, target_pstate);
2539 
2540 	sample = &cpu->sample;
2541 	trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2542 		fp_toint(sample->busy_scaled),
2543 		from,
2544 		cpu->pstate.current_pstate,
2545 		sample->mperf,
2546 		sample->aperf,
2547 		sample->tsc,
2548 		get_avg_frequency(cpu),
2549 		fp_toint(cpu->iowait_boost * 100));
2550 }
2551 
intel_pstate_update_util(struct update_util_data * data,u64 time,unsigned int flags)2552 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2553 				     unsigned int flags)
2554 {
2555 	struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2556 	u64 delta_ns;
2557 
2558 	/* Don't allow remote callbacks */
2559 	if (smp_processor_id() != cpu->cpu)
2560 		return;
2561 
2562 	delta_ns = time - cpu->last_update;
2563 	if (flags & SCHED_CPUFREQ_IOWAIT) {
2564 		/* Start over if the CPU may have been idle. */
2565 		if (delta_ns > TICK_NSEC) {
2566 			cpu->iowait_boost = ONE_EIGHTH_FP;
2567 		} else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2568 			cpu->iowait_boost <<= 1;
2569 			if (cpu->iowait_boost > int_tofp(1))
2570 				cpu->iowait_boost = int_tofp(1);
2571 		} else {
2572 			cpu->iowait_boost = ONE_EIGHTH_FP;
2573 		}
2574 	} else if (cpu->iowait_boost) {
2575 		/* Clear iowait_boost if the CPU may have been idle. */
2576 		if (delta_ns > TICK_NSEC)
2577 			cpu->iowait_boost = 0;
2578 		else
2579 			cpu->iowait_boost >>= 1;
2580 	}
2581 	cpu->last_update = time;
2582 	delta_ns = time - cpu->sample.time;
2583 	if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2584 		return;
2585 
2586 	if (intel_pstate_sample(cpu, time))
2587 		intel_pstate_adjust_pstate(cpu);
2588 }
2589 
2590 static struct pstate_funcs core_funcs = {
2591 	.get_max = core_get_max_pstate,
2592 	.get_max_physical = core_get_max_pstate_physical,
2593 	.get_min = core_get_min_pstate,
2594 	.get_turbo = core_get_turbo_pstate,
2595 	.get_scaling = core_get_scaling,
2596 	.get_val = core_get_val,
2597 };
2598 
2599 static const struct pstate_funcs silvermont_funcs = {
2600 	.get_max = atom_get_max_pstate,
2601 	.get_max_physical = atom_get_max_pstate,
2602 	.get_min = atom_get_min_pstate,
2603 	.get_turbo = atom_get_turbo_pstate,
2604 	.get_val = atom_get_val,
2605 	.get_scaling = silvermont_get_scaling,
2606 	.get_vid = atom_get_vid,
2607 };
2608 
2609 static const struct pstate_funcs airmont_funcs = {
2610 	.get_max = atom_get_max_pstate,
2611 	.get_max_physical = atom_get_max_pstate,
2612 	.get_min = atom_get_min_pstate,
2613 	.get_turbo = atom_get_turbo_pstate,
2614 	.get_val = atom_get_val,
2615 	.get_scaling = airmont_get_scaling,
2616 	.get_vid = atom_get_vid,
2617 };
2618 
2619 static const struct pstate_funcs knl_funcs = {
2620 	.get_max = core_get_max_pstate,
2621 	.get_max_physical = core_get_max_pstate_physical,
2622 	.get_min = core_get_min_pstate,
2623 	.get_turbo = knl_get_turbo_pstate,
2624 	.get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2625 	.get_scaling = core_get_scaling,
2626 	.get_val = core_get_val,
2627 };
2628 
2629 #define X86_MATCH(vfm, policy)					 \
2630 	X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_APERFMPERF, &policy)
2631 
2632 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2633 	X86_MATCH(INTEL_SANDYBRIDGE,		core_funcs),
2634 	X86_MATCH(INTEL_SANDYBRIDGE_X,		core_funcs),
2635 	X86_MATCH(INTEL_ATOM_SILVERMONT,	silvermont_funcs),
2636 	X86_MATCH(INTEL_IVYBRIDGE,		core_funcs),
2637 	X86_MATCH(INTEL_HASWELL,		core_funcs),
2638 	X86_MATCH(INTEL_BROADWELL,		core_funcs),
2639 	X86_MATCH(INTEL_IVYBRIDGE_X,		core_funcs),
2640 	X86_MATCH(INTEL_HASWELL_X,		core_funcs),
2641 	X86_MATCH(INTEL_HASWELL_L,		core_funcs),
2642 	X86_MATCH(INTEL_HASWELL_G,		core_funcs),
2643 	X86_MATCH(INTEL_BROADWELL_G,		core_funcs),
2644 	X86_MATCH(INTEL_ATOM_AIRMONT,		airmont_funcs),
2645 	X86_MATCH(INTEL_SKYLAKE_L,		core_funcs),
2646 	X86_MATCH(INTEL_BROADWELL_X,		core_funcs),
2647 	X86_MATCH(INTEL_SKYLAKE,		core_funcs),
2648 	X86_MATCH(INTEL_BROADWELL_D,		core_funcs),
2649 	X86_MATCH(INTEL_XEON_PHI_KNL,		knl_funcs),
2650 	X86_MATCH(INTEL_XEON_PHI_KNM,		knl_funcs),
2651 	X86_MATCH(INTEL_ATOM_GOLDMONT,		core_funcs),
2652 	X86_MATCH(INTEL_ATOM_GOLDMONT_PLUS,	core_funcs),
2653 	X86_MATCH(INTEL_SKYLAKE_X,		core_funcs),
2654 	X86_MATCH(INTEL_COMETLAKE,		core_funcs),
2655 	X86_MATCH(INTEL_ICELAKE_X,		core_funcs),
2656 	X86_MATCH(INTEL_TIGERLAKE,		core_funcs),
2657 	X86_MATCH(INTEL_SAPPHIRERAPIDS_X,	core_funcs),
2658 	X86_MATCH(INTEL_EMERALDRAPIDS_X,	core_funcs),
2659 	{}
2660 };
2661 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2662 
2663 #ifdef CONFIG_ACPI
2664 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2665 	X86_MATCH(INTEL_BROADWELL_D,		core_funcs),
2666 	X86_MATCH(INTEL_BROADWELL_X,		core_funcs),
2667 	X86_MATCH(INTEL_SKYLAKE_X,		core_funcs),
2668 	X86_MATCH(INTEL_ICELAKE_X,		core_funcs),
2669 	X86_MATCH(INTEL_SAPPHIRERAPIDS_X,	core_funcs),
2670 	X86_MATCH(INTEL_EMERALDRAPIDS_X,	core_funcs),
2671 	X86_MATCH(INTEL_GRANITERAPIDS_D,	core_funcs),
2672 	X86_MATCH(INTEL_GRANITERAPIDS_X,	core_funcs),
2673 	X86_MATCH(INTEL_ATOM_CRESTMONT,		core_funcs),
2674 	X86_MATCH(INTEL_ATOM_CRESTMONT_X,	core_funcs),
2675 	{}
2676 };
2677 #endif
2678 
2679 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2680 	X86_MATCH(INTEL_KABYLAKE,		core_funcs),
2681 	{}
2682 };
2683 
intel_pstate_init_cpu(unsigned int cpunum)2684 static int intel_pstate_init_cpu(unsigned int cpunum)
2685 {
2686 	struct cpudata *cpu;
2687 
2688 	cpu = all_cpu_data[cpunum];
2689 
2690 	if (!cpu) {
2691 		cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2692 		if (!cpu)
2693 			return -ENOMEM;
2694 
2695 		WRITE_ONCE(all_cpu_data[cpunum], cpu);
2696 
2697 		cpu->cpu = cpunum;
2698 
2699 		cpu->epp_default = -EINVAL;
2700 
2701 		if (hwp_active) {
2702 			intel_pstate_hwp_enable(cpu);
2703 
2704 			if (intel_pstate_acpi_pm_profile_server())
2705 				hwp_boost = true;
2706 		}
2707 	} else if (hwp_active) {
2708 		/*
2709 		 * Re-enable HWP in case this happens after a resume from ACPI
2710 		 * S3 if the CPU was offline during the whole system/resume
2711 		 * cycle.
2712 		 */
2713 		intel_pstate_hwp_reenable(cpu);
2714 	}
2715 
2716 	cpu->epp_powersave = -EINVAL;
2717 	cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
2718 
2719 	intel_pstate_get_cpu_pstates(cpu);
2720 
2721 	pr_debug("controlling: cpu %d\n", cpunum);
2722 
2723 	return 0;
2724 }
2725 
intel_pstate_set_update_util_hook(unsigned int cpu_num)2726 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2727 {
2728 	struct cpudata *cpu = all_cpu_data[cpu_num];
2729 
2730 	if (hwp_active && !hwp_boost)
2731 		return;
2732 
2733 	if (cpu->update_util_set)
2734 		return;
2735 
2736 	/* Prevent intel_pstate_update_util() from using stale data. */
2737 	cpu->sample.time = 0;
2738 	cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2739 				     (hwp_active ?
2740 				      intel_pstate_update_util_hwp :
2741 				      intel_pstate_update_util));
2742 	cpu->update_util_set = true;
2743 }
2744 
intel_pstate_clear_update_util_hook(unsigned int cpu)2745 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2746 {
2747 	struct cpudata *cpu_data = all_cpu_data[cpu];
2748 
2749 	if (!cpu_data->update_util_set)
2750 		return;
2751 
2752 	cpufreq_remove_update_util_hook(cpu);
2753 	cpu_data->update_util_set = false;
2754 	synchronize_rcu();
2755 }
2756 
intel_pstate_get_max_freq(struct cpudata * cpu)2757 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2758 {
2759 	return READ_ONCE(global.no_turbo) ?
2760 			cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2761 }
2762 
intel_pstate_update_perf_limits(struct cpudata * cpu,unsigned int policy_min,unsigned int policy_max)2763 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2764 					    unsigned int policy_min,
2765 					    unsigned int policy_max)
2766 {
2767 	int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2768 	int32_t max_policy_perf, min_policy_perf;
2769 
2770 	max_policy_perf = policy_max / perf_ctl_scaling;
2771 	if (policy_max == policy_min) {
2772 		min_policy_perf = max_policy_perf;
2773 	} else {
2774 		min_policy_perf = policy_min / perf_ctl_scaling;
2775 		min_policy_perf = clamp_t(int32_t, min_policy_perf,
2776 					  0, max_policy_perf);
2777 	}
2778 
2779 	/*
2780 	 * HWP needs some special consideration, because HWP_REQUEST uses
2781 	 * abstract values to represent performance rather than pure ratios.
2782 	 */
2783 	if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2784 		int freq;
2785 
2786 		freq = max_policy_perf * perf_ctl_scaling;
2787 		max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2788 		freq = min_policy_perf * perf_ctl_scaling;
2789 		min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2790 	}
2791 
2792 	pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2793 		 cpu->cpu, min_policy_perf, max_policy_perf);
2794 
2795 	/* Normalize user input to [min_perf, max_perf] */
2796 	if (per_cpu_limits) {
2797 		cpu->min_perf_ratio = min_policy_perf;
2798 		cpu->max_perf_ratio = max_policy_perf;
2799 	} else {
2800 		int turbo_max = cpu->pstate.turbo_pstate;
2801 		int32_t global_min, global_max;
2802 
2803 		/* Global limits are in percent of the maximum turbo P-state. */
2804 		global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2805 		global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2806 		global_min = clamp_t(int32_t, global_min, 0, global_max);
2807 
2808 		pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2809 			 global_min, global_max);
2810 
2811 		cpu->min_perf_ratio = max(min_policy_perf, global_min);
2812 		cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2813 		cpu->max_perf_ratio = min(max_policy_perf, global_max);
2814 		cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2815 
2816 		/* Make sure min_perf <= max_perf */
2817 		cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2818 					  cpu->max_perf_ratio);
2819 
2820 	}
2821 	pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2822 		 cpu->max_perf_ratio,
2823 		 cpu->min_perf_ratio);
2824 }
2825 
intel_pstate_set_policy(struct cpufreq_policy * policy)2826 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2827 {
2828 	struct cpudata *cpu;
2829 
2830 	if (!policy->cpuinfo.max_freq)
2831 		return -ENODEV;
2832 
2833 	pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2834 		 policy->cpuinfo.max_freq, policy->max);
2835 
2836 	cpu = all_cpu_data[policy->cpu];
2837 	cpu->policy = policy->policy;
2838 
2839 	mutex_lock(&intel_pstate_limits_lock);
2840 
2841 	intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2842 
2843 	if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2844 		int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2845 
2846 		/*
2847 		 * NOHZ_FULL CPUs need this as the governor callback may not
2848 		 * be invoked on them.
2849 		 */
2850 		intel_pstate_clear_update_util_hook(policy->cpu);
2851 		intel_pstate_set_pstate(cpu, pstate);
2852 	} else {
2853 		intel_pstate_set_update_util_hook(policy->cpu);
2854 	}
2855 
2856 	if (hwp_active) {
2857 		/*
2858 		 * When hwp_boost was active before and dynamically it
2859 		 * was turned off, in that case we need to clear the
2860 		 * update util hook.
2861 		 */
2862 		if (!hwp_boost)
2863 			intel_pstate_clear_update_util_hook(policy->cpu);
2864 		intel_pstate_hwp_set(policy->cpu);
2865 	}
2866 	/*
2867 	 * policy->cur is never updated with the intel_pstate driver, but it
2868 	 * is used as a stale frequency value. So, keep it within limits.
2869 	 */
2870 	policy->cur = policy->min;
2871 
2872 	mutex_unlock(&intel_pstate_limits_lock);
2873 
2874 	return 0;
2875 }
2876 
intel_pstate_adjust_policy_max(struct cpudata * cpu,struct cpufreq_policy_data * policy)2877 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2878 					   struct cpufreq_policy_data *policy)
2879 {
2880 	if (!hwp_active &&
2881 	    cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2882 	    policy->max < policy->cpuinfo.max_freq &&
2883 	    policy->max > cpu->pstate.max_freq) {
2884 		pr_debug("policy->max > max non turbo frequency\n");
2885 		policy->max = policy->cpuinfo.max_freq;
2886 	}
2887 }
2888 
intel_pstate_verify_cpu_policy(struct cpudata * cpu,struct cpufreq_policy_data * policy)2889 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2890 					   struct cpufreq_policy_data *policy)
2891 {
2892 	int max_freq;
2893 
2894 	if (hwp_active) {
2895 		intel_pstate_get_hwp_cap(cpu);
2896 		max_freq = READ_ONCE(global.no_turbo) ?
2897 				cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2898 	} else {
2899 		max_freq = intel_pstate_get_max_freq(cpu);
2900 	}
2901 	cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2902 
2903 	intel_pstate_adjust_policy_max(cpu, policy);
2904 }
2905 
intel_pstate_verify_policy(struct cpufreq_policy_data * policy)2906 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2907 {
2908 	intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2909 
2910 	return 0;
2911 }
2912 
intel_cpufreq_cpu_offline(struct cpufreq_policy * policy)2913 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2914 {
2915 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2916 
2917 	pr_debug("CPU %d going offline\n", cpu->cpu);
2918 
2919 	if (cpu->suspended)
2920 		return 0;
2921 
2922 	/*
2923 	 * If the CPU is an SMT thread and it goes offline with the performance
2924 	 * settings different from the minimum, it will prevent its sibling
2925 	 * from getting to lower performance levels, so force the minimum
2926 	 * performance on CPU offline to prevent that from happening.
2927 	 */
2928 	if (hwp_active)
2929 		intel_pstate_hwp_offline(cpu);
2930 	else
2931 		intel_pstate_set_min_pstate(cpu);
2932 
2933 	intel_pstate_exit_perf_limits(policy);
2934 
2935 	return 0;
2936 }
2937 
intel_pstate_cpu_online(struct cpufreq_policy * policy)2938 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2939 {
2940 	struct cpudata *cpu = all_cpu_data[policy->cpu];
2941 
2942 	pr_debug("CPU %d going online\n", cpu->cpu);
2943 
2944 	intel_pstate_init_acpi_perf_limits(policy);
2945 
2946 	if (hwp_active) {
2947 		/*
2948 		 * Re-enable HWP and clear the "suspended" flag to let "resume"
2949 		 * know that it need not do that.
2950 		 */
2951 		intel_pstate_hwp_reenable(cpu);
2952 		cpu->suspended = false;
2953 
2954 		hybrid_update_capacity(cpu);
2955 	}
2956 
2957 	return 0;
2958 }
2959 
intel_pstate_cpu_offline(struct cpufreq_policy * policy)2960 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2961 {
2962 	intel_pstate_clear_update_util_hook(policy->cpu);
2963 
2964 	return intel_cpufreq_cpu_offline(policy);
2965 }
2966 
intel_pstate_cpu_exit(struct cpufreq_policy * policy)2967 static void intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2968 {
2969 	pr_debug("CPU %d exiting\n", policy->cpu);
2970 
2971 	policy->fast_switch_possible = false;
2972 }
2973 
__intel_pstate_cpu_init(struct cpufreq_policy * policy)2974 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2975 {
2976 	struct cpudata *cpu;
2977 	int rc;
2978 
2979 	rc = intel_pstate_init_cpu(policy->cpu);
2980 	if (rc)
2981 		return rc;
2982 
2983 	cpu = all_cpu_data[policy->cpu];
2984 
2985 	cpu->max_perf_ratio = 0xFF;
2986 	cpu->min_perf_ratio = 0;
2987 
2988 	/* cpuinfo and default policy values */
2989 	policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2990 	policy->cpuinfo.max_freq = READ_ONCE(global.no_turbo) ?
2991 			cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2992 
2993 	policy->min = policy->cpuinfo.min_freq;
2994 	policy->max = policy->cpuinfo.max_freq;
2995 
2996 	intel_pstate_init_acpi_perf_limits(policy);
2997 
2998 	policy->fast_switch_possible = true;
2999 
3000 	return 0;
3001 }
3002 
intel_pstate_cpu_init(struct cpufreq_policy * policy)3003 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
3004 {
3005 	int ret = __intel_pstate_cpu_init(policy);
3006 
3007 	if (ret)
3008 		return ret;
3009 
3010 	/*
3011 	 * Set the policy to powersave to provide a valid fallback value in case
3012 	 * the default cpufreq governor is neither powersave nor performance.
3013 	 */
3014 	policy->policy = CPUFREQ_POLICY_POWERSAVE;
3015 
3016 	if (hwp_active) {
3017 		struct cpudata *cpu = all_cpu_data[policy->cpu];
3018 
3019 		cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
3020 	}
3021 
3022 	return 0;
3023 }
3024 
3025 static struct cpufreq_driver intel_pstate = {
3026 	.flags		= CPUFREQ_CONST_LOOPS,
3027 	.verify		= intel_pstate_verify_policy,
3028 	.setpolicy	= intel_pstate_set_policy,
3029 	.suspend	= intel_pstate_suspend,
3030 	.resume		= intel_pstate_resume,
3031 	.init		= intel_pstate_cpu_init,
3032 	.exit		= intel_pstate_cpu_exit,
3033 	.offline	= intel_pstate_cpu_offline,
3034 	.online		= intel_pstate_cpu_online,
3035 	.update_limits	= intel_pstate_update_limits,
3036 	.name		= "intel_pstate",
3037 };
3038 
intel_cpufreq_verify_policy(struct cpufreq_policy_data * policy)3039 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
3040 {
3041 	struct cpudata *cpu = all_cpu_data[policy->cpu];
3042 
3043 	intel_pstate_verify_cpu_policy(cpu, policy);
3044 	intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
3045 
3046 	return 0;
3047 }
3048 
3049 /* Use of trace in passive mode:
3050  *
3051  * In passive mode the trace core_busy field (also known as the
3052  * performance field, and lablelled as such on the graphs; also known as
3053  * core_avg_perf) is not needed and so is re-assigned to indicate if the
3054  * driver call was via the normal or fast switch path. Various graphs
3055  * output from the intel_pstate_tracer.py utility that include core_busy
3056  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
3057  * so we use 10 to indicate the normal path through the driver, and
3058  * 90 to indicate the fast switch path through the driver.
3059  * The scaled_busy field is not used, and is set to 0.
3060  */
3061 
3062 #define	INTEL_PSTATE_TRACE_TARGET 10
3063 #define	INTEL_PSTATE_TRACE_FAST_SWITCH 90
3064 
intel_cpufreq_trace(struct cpudata * cpu,unsigned int trace_type,int old_pstate)3065 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
3066 {
3067 	struct sample *sample;
3068 
3069 	if (!trace_pstate_sample_enabled())
3070 		return;
3071 
3072 	if (!intel_pstate_sample(cpu, ktime_get()))
3073 		return;
3074 
3075 	sample = &cpu->sample;
3076 	trace_pstate_sample(trace_type,
3077 		0,
3078 		old_pstate,
3079 		cpu->pstate.current_pstate,
3080 		sample->mperf,
3081 		sample->aperf,
3082 		sample->tsc,
3083 		get_avg_frequency(cpu),
3084 		fp_toint(cpu->iowait_boost * 100));
3085 }
3086 
intel_cpufreq_hwp_update(struct cpudata * cpu,u32 min,u32 max,u32 desired,bool fast_switch)3087 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
3088 				     u32 desired, bool fast_switch)
3089 {
3090 	u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
3091 
3092 	value &= ~HWP_MIN_PERF(~0L);
3093 	value |= HWP_MIN_PERF(min);
3094 
3095 	value &= ~HWP_MAX_PERF(~0L);
3096 	value |= HWP_MAX_PERF(max);
3097 
3098 	value &= ~HWP_DESIRED_PERF(~0L);
3099 	value |= HWP_DESIRED_PERF(desired);
3100 
3101 	if (value == prev)
3102 		return;
3103 
3104 	WRITE_ONCE(cpu->hwp_req_cached, value);
3105 	if (fast_switch)
3106 		wrmsrl(MSR_HWP_REQUEST, value);
3107 	else
3108 		wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3109 }
3110 
intel_cpufreq_perf_ctl_update(struct cpudata * cpu,u32 target_pstate,bool fast_switch)3111 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
3112 					  u32 target_pstate, bool fast_switch)
3113 {
3114 	if (fast_switch)
3115 		wrmsrl(MSR_IA32_PERF_CTL,
3116 		       pstate_funcs.get_val(cpu, target_pstate));
3117 	else
3118 		wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
3119 			      pstate_funcs.get_val(cpu, target_pstate));
3120 }
3121 
intel_cpufreq_update_pstate(struct cpufreq_policy * policy,int target_pstate,bool fast_switch)3122 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
3123 				       int target_pstate, bool fast_switch)
3124 {
3125 	struct cpudata *cpu = all_cpu_data[policy->cpu];
3126 	int old_pstate = cpu->pstate.current_pstate;
3127 
3128 	target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
3129 	if (hwp_active) {
3130 		int max_pstate = policy->strict_target ?
3131 					target_pstate : cpu->max_perf_ratio;
3132 
3133 		intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
3134 					 fast_switch);
3135 	} else if (target_pstate != old_pstate) {
3136 		intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
3137 	}
3138 
3139 	cpu->pstate.current_pstate = target_pstate;
3140 
3141 	intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
3142 			    INTEL_PSTATE_TRACE_TARGET, old_pstate);
3143 
3144 	return target_pstate;
3145 }
3146 
intel_cpufreq_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)3147 static int intel_cpufreq_target(struct cpufreq_policy *policy,
3148 				unsigned int target_freq,
3149 				unsigned int relation)
3150 {
3151 	struct cpudata *cpu = all_cpu_data[policy->cpu];
3152 	struct cpufreq_freqs freqs;
3153 	int target_pstate;
3154 
3155 	freqs.old = policy->cur;
3156 	freqs.new = target_freq;
3157 
3158 	cpufreq_freq_transition_begin(policy, &freqs);
3159 
3160 	target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
3161 	target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
3162 
3163 	freqs.new = target_pstate * cpu->pstate.scaling;
3164 
3165 	cpufreq_freq_transition_end(policy, &freqs, false);
3166 
3167 	return 0;
3168 }
3169 
intel_cpufreq_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)3170 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
3171 					      unsigned int target_freq)
3172 {
3173 	struct cpudata *cpu = all_cpu_data[policy->cpu];
3174 	int target_pstate;
3175 
3176 	target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
3177 
3178 	target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
3179 
3180 	return target_pstate * cpu->pstate.scaling;
3181 }
3182 
intel_cpufreq_adjust_perf(unsigned int cpunum,unsigned long min_perf,unsigned long target_perf,unsigned long capacity)3183 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
3184 				      unsigned long min_perf,
3185 				      unsigned long target_perf,
3186 				      unsigned long capacity)
3187 {
3188 	struct cpudata *cpu = all_cpu_data[cpunum];
3189 	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
3190 	int old_pstate = cpu->pstate.current_pstate;
3191 	int cap_pstate, min_pstate, max_pstate, target_pstate;
3192 
3193 	cap_pstate = READ_ONCE(global.no_turbo) ?
3194 					HWP_GUARANTEED_PERF(hwp_cap) :
3195 					HWP_HIGHEST_PERF(hwp_cap);
3196 
3197 	/* Optimization: Avoid unnecessary divisions. */
3198 
3199 	target_pstate = cap_pstate;
3200 	if (target_perf < capacity)
3201 		target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
3202 
3203 	min_pstate = cap_pstate;
3204 	if (min_perf < capacity)
3205 		min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
3206 
3207 	if (min_pstate < cpu->pstate.min_pstate)
3208 		min_pstate = cpu->pstate.min_pstate;
3209 
3210 	if (min_pstate < cpu->min_perf_ratio)
3211 		min_pstate = cpu->min_perf_ratio;
3212 
3213 	if (min_pstate > cpu->max_perf_ratio)
3214 		min_pstate = cpu->max_perf_ratio;
3215 
3216 	max_pstate = min(cap_pstate, cpu->max_perf_ratio);
3217 	if (max_pstate < min_pstate)
3218 		max_pstate = min_pstate;
3219 
3220 	target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
3221 
3222 	intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
3223 
3224 	cpu->pstate.current_pstate = target_pstate;
3225 	intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3226 }
3227 
intel_cpufreq_cpu_init(struct cpufreq_policy * policy)3228 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3229 {
3230 	struct freq_qos_request *req;
3231 	struct cpudata *cpu;
3232 	struct device *dev;
3233 	int ret, freq;
3234 
3235 	dev = get_cpu_device(policy->cpu);
3236 	if (!dev)
3237 		return -ENODEV;
3238 
3239 	ret = __intel_pstate_cpu_init(policy);
3240 	if (ret)
3241 		return ret;
3242 
3243 	policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3244 	/* This reflects the intel_pstate_get_cpu_pstates() setting. */
3245 	policy->cur = policy->cpuinfo.min_freq;
3246 
3247 	req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3248 	if (!req) {
3249 		ret = -ENOMEM;
3250 		goto pstate_exit;
3251 	}
3252 
3253 	cpu = all_cpu_data[policy->cpu];
3254 
3255 	if (hwp_active) {
3256 		u64 value;
3257 
3258 		policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3259 
3260 		intel_pstate_get_hwp_cap(cpu);
3261 
3262 		rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3263 		WRITE_ONCE(cpu->hwp_req_cached, value);
3264 
3265 		cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3266 	} else {
3267 		policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3268 	}
3269 
3270 	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3271 
3272 	ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3273 				   freq);
3274 	if (ret < 0) {
3275 		dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3276 		goto free_req;
3277 	}
3278 
3279 	freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3280 
3281 	ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3282 				   freq);
3283 	if (ret < 0) {
3284 		dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3285 		goto remove_min_req;
3286 	}
3287 
3288 	policy->driver_data = req;
3289 
3290 	return 0;
3291 
3292 remove_min_req:
3293 	freq_qos_remove_request(req);
3294 free_req:
3295 	kfree(req);
3296 pstate_exit:
3297 	intel_pstate_exit_perf_limits(policy);
3298 
3299 	return ret;
3300 }
3301 
intel_cpufreq_cpu_exit(struct cpufreq_policy * policy)3302 static void intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3303 {
3304 	struct freq_qos_request *req;
3305 
3306 	req = policy->driver_data;
3307 
3308 	freq_qos_remove_request(req + 1);
3309 	freq_qos_remove_request(req);
3310 	kfree(req);
3311 
3312 	intel_pstate_cpu_exit(policy);
3313 }
3314 
intel_cpufreq_suspend(struct cpufreq_policy * policy)3315 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3316 {
3317 	intel_pstate_suspend(policy);
3318 
3319 	if (hwp_active) {
3320 		struct cpudata *cpu = all_cpu_data[policy->cpu];
3321 		u64 value = READ_ONCE(cpu->hwp_req_cached);
3322 
3323 		/*
3324 		 * Clear the desired perf field in MSR_HWP_REQUEST in case
3325 		 * intel_cpufreq_adjust_perf() is in use and the last value
3326 		 * written by it may not be suitable.
3327 		 */
3328 		value &= ~HWP_DESIRED_PERF(~0L);
3329 		wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3330 		WRITE_ONCE(cpu->hwp_req_cached, value);
3331 	}
3332 
3333 	return 0;
3334 }
3335 
3336 static struct cpufreq_driver intel_cpufreq = {
3337 	.flags		= CPUFREQ_CONST_LOOPS,
3338 	.verify		= intel_cpufreq_verify_policy,
3339 	.target		= intel_cpufreq_target,
3340 	.fast_switch	= intel_cpufreq_fast_switch,
3341 	.init		= intel_cpufreq_cpu_init,
3342 	.exit		= intel_cpufreq_cpu_exit,
3343 	.offline	= intel_cpufreq_cpu_offline,
3344 	.online		= intel_pstate_cpu_online,
3345 	.suspend	= intel_cpufreq_suspend,
3346 	.resume		= intel_pstate_resume,
3347 	.update_limits	= intel_pstate_update_limits,
3348 	.name		= "intel_cpufreq",
3349 };
3350 
3351 static struct cpufreq_driver *default_driver;
3352 
intel_pstate_driver_cleanup(void)3353 static void intel_pstate_driver_cleanup(void)
3354 {
3355 	unsigned int cpu;
3356 
3357 	cpus_read_lock();
3358 	for_each_online_cpu(cpu) {
3359 		if (all_cpu_data[cpu]) {
3360 			if (intel_pstate_driver == &intel_pstate)
3361 				intel_pstate_clear_update_util_hook(cpu);
3362 
3363 			kfree(all_cpu_data[cpu]);
3364 			WRITE_ONCE(all_cpu_data[cpu], NULL);
3365 		}
3366 	}
3367 	cpus_read_unlock();
3368 
3369 	intel_pstate_driver = NULL;
3370 }
3371 
intel_pstate_register_driver(struct cpufreq_driver * driver)3372 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3373 {
3374 	bool refresh_cpu_cap_scaling;
3375 	int ret;
3376 
3377 	if (driver == &intel_pstate)
3378 		intel_pstate_sysfs_expose_hwp_dynamic_boost();
3379 
3380 	memset(&global, 0, sizeof(global));
3381 	global.max_perf_pct = 100;
3382 	global.turbo_disabled = turbo_is_disabled();
3383 	global.no_turbo = global.turbo_disabled;
3384 
3385 	arch_set_max_freq_ratio(global.turbo_disabled);
3386 
3387 	refresh_cpu_cap_scaling = hybrid_clear_max_perf_cpu();
3388 
3389 	intel_pstate_driver = driver;
3390 	ret = cpufreq_register_driver(intel_pstate_driver);
3391 	if (ret) {
3392 		intel_pstate_driver_cleanup();
3393 		return ret;
3394 	}
3395 
3396 	global.min_perf_pct = min_perf_pct_min();
3397 
3398 	hybrid_init_cpu_capacity_scaling(refresh_cpu_cap_scaling);
3399 
3400 	return 0;
3401 }
3402 
intel_pstate_show_status(char * buf)3403 static ssize_t intel_pstate_show_status(char *buf)
3404 {
3405 	if (!intel_pstate_driver)
3406 		return sprintf(buf, "off\n");
3407 
3408 	return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3409 					"active" : "passive");
3410 }
3411 
intel_pstate_update_status(const char * buf,size_t size)3412 static int intel_pstate_update_status(const char *buf, size_t size)
3413 {
3414 	if (size == 3 && !strncmp(buf, "off", size)) {
3415 		if (!intel_pstate_driver)
3416 			return -EINVAL;
3417 
3418 		if (hwp_active)
3419 			return -EBUSY;
3420 
3421 		cpufreq_unregister_driver(intel_pstate_driver);
3422 		intel_pstate_driver_cleanup();
3423 		return 0;
3424 	}
3425 
3426 	if (size == 6 && !strncmp(buf, "active", size)) {
3427 		if (intel_pstate_driver) {
3428 			if (intel_pstate_driver == &intel_pstate)
3429 				return 0;
3430 
3431 			cpufreq_unregister_driver(intel_pstate_driver);
3432 		}
3433 
3434 		return intel_pstate_register_driver(&intel_pstate);
3435 	}
3436 
3437 	if (size == 7 && !strncmp(buf, "passive", size)) {
3438 		if (intel_pstate_driver) {
3439 			if (intel_pstate_driver == &intel_cpufreq)
3440 				return 0;
3441 
3442 			cpufreq_unregister_driver(intel_pstate_driver);
3443 			intel_pstate_sysfs_hide_hwp_dynamic_boost();
3444 		}
3445 
3446 		return intel_pstate_register_driver(&intel_cpufreq);
3447 	}
3448 
3449 	return -EINVAL;
3450 }
3451 
3452 static int no_load __initdata;
3453 static int no_hwp __initdata;
3454 static int hwp_only __initdata;
3455 static unsigned int force_load __initdata;
3456 
intel_pstate_msrs_not_valid(void)3457 static int __init intel_pstate_msrs_not_valid(void)
3458 {
3459 	if (!pstate_funcs.get_max(0) ||
3460 	    !pstate_funcs.get_min(0) ||
3461 	    !pstate_funcs.get_turbo(0))
3462 		return -ENODEV;
3463 
3464 	return 0;
3465 }
3466 
copy_cpu_funcs(struct pstate_funcs * funcs)3467 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3468 {
3469 	pstate_funcs.get_max   = funcs->get_max;
3470 	pstate_funcs.get_max_physical = funcs->get_max_physical;
3471 	pstate_funcs.get_min   = funcs->get_min;
3472 	pstate_funcs.get_turbo = funcs->get_turbo;
3473 	pstate_funcs.get_scaling = funcs->get_scaling;
3474 	pstate_funcs.get_val   = funcs->get_val;
3475 	pstate_funcs.get_vid   = funcs->get_vid;
3476 	pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3477 }
3478 
3479 #ifdef CONFIG_ACPI
3480 
intel_pstate_no_acpi_pss(void)3481 static bool __init intel_pstate_no_acpi_pss(void)
3482 {
3483 	int i;
3484 
3485 	for_each_possible_cpu(i) {
3486 		acpi_status status;
3487 		union acpi_object *pss;
3488 		struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3489 		struct acpi_processor *pr = per_cpu(processors, i);
3490 
3491 		if (!pr)
3492 			continue;
3493 
3494 		status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3495 		if (ACPI_FAILURE(status))
3496 			continue;
3497 
3498 		pss = buffer.pointer;
3499 		if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3500 			kfree(pss);
3501 			return false;
3502 		}
3503 
3504 		kfree(pss);
3505 	}
3506 
3507 	pr_debug("ACPI _PSS not found\n");
3508 	return true;
3509 }
3510 
intel_pstate_no_acpi_pcch(void)3511 static bool __init intel_pstate_no_acpi_pcch(void)
3512 {
3513 	acpi_status status;
3514 	acpi_handle handle;
3515 
3516 	status = acpi_get_handle(NULL, "\\_SB", &handle);
3517 	if (ACPI_FAILURE(status))
3518 		goto not_found;
3519 
3520 	if (acpi_has_method(handle, "PCCH"))
3521 		return false;
3522 
3523 not_found:
3524 	pr_debug("ACPI PCCH not found\n");
3525 	return true;
3526 }
3527 
intel_pstate_has_acpi_ppc(void)3528 static bool __init intel_pstate_has_acpi_ppc(void)
3529 {
3530 	int i;
3531 
3532 	for_each_possible_cpu(i) {
3533 		struct acpi_processor *pr = per_cpu(processors, i);
3534 
3535 		if (!pr)
3536 			continue;
3537 		if (acpi_has_method(pr->handle, "_PPC"))
3538 			return true;
3539 	}
3540 	pr_debug("ACPI _PPC not found\n");
3541 	return false;
3542 }
3543 
3544 enum {
3545 	PSS,
3546 	PPC,
3547 };
3548 
3549 /* Hardware vendor-specific info that has its own power management modes */
3550 static struct acpi_platform_list plat_info[] __initdata = {
3551 	{"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3552 	{"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3553 	{"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3554 	{"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3555 	{"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3556 	{"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3557 	{"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3558 	{"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3559 	{"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3560 	{"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3561 	{"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3562 	{"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3563 	{"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3564 	{"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3565 	{"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3566 	{ } /* End */
3567 };
3568 
3569 #define BITMASK_OOB	(BIT(8) | BIT(18))
3570 
intel_pstate_platform_pwr_mgmt_exists(void)3571 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3572 {
3573 	const struct x86_cpu_id *id;
3574 	u64 misc_pwr;
3575 	int idx;
3576 
3577 	id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3578 	if (id) {
3579 		rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3580 		if (misc_pwr & BITMASK_OOB) {
3581 			pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3582 			pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3583 			return true;
3584 		}
3585 	}
3586 
3587 	idx = acpi_match_platform_list(plat_info);
3588 	if (idx < 0)
3589 		return false;
3590 
3591 	switch (plat_info[idx].data) {
3592 	case PSS:
3593 		if (!intel_pstate_no_acpi_pss())
3594 			return false;
3595 
3596 		return intel_pstate_no_acpi_pcch();
3597 	case PPC:
3598 		return intel_pstate_has_acpi_ppc() && !force_load;
3599 	}
3600 
3601 	return false;
3602 }
3603 
intel_pstate_request_control_from_smm(void)3604 static void intel_pstate_request_control_from_smm(void)
3605 {
3606 	/*
3607 	 * It may be unsafe to request P-states control from SMM if _PPC support
3608 	 * has not been enabled.
3609 	 */
3610 	if (acpi_ppc)
3611 		acpi_processor_pstate_control();
3612 }
3613 #else /* CONFIG_ACPI not enabled */
intel_pstate_platform_pwr_mgmt_exists(void)3614 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
intel_pstate_has_acpi_ppc(void)3615 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
intel_pstate_request_control_from_smm(void)3616 static inline void intel_pstate_request_control_from_smm(void) {}
3617 #endif /* CONFIG_ACPI */
3618 
3619 #define INTEL_PSTATE_HWP_BROADWELL	0x01
3620 
3621 #define X86_MATCH_HWP(vfm, hwp_mode)				\
3622 	X86_MATCH_VFM_FEATURE(vfm, X86_FEATURE_HWP, hwp_mode)
3623 
3624 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3625 	X86_MATCH_HWP(INTEL_BROADWELL_X,	INTEL_PSTATE_HWP_BROADWELL),
3626 	X86_MATCH_HWP(INTEL_BROADWELL_D,	INTEL_PSTATE_HWP_BROADWELL),
3627 	X86_MATCH_HWP(INTEL_ANY,		0),
3628 	{}
3629 };
3630 
intel_pstate_hwp_is_enabled(void)3631 static bool intel_pstate_hwp_is_enabled(void)
3632 {
3633 	u64 value;
3634 
3635 	rdmsrl(MSR_PM_ENABLE, value);
3636 	return !!(value & 0x1);
3637 }
3638 
3639 #define POWERSAVE_MASK			GENMASK(7, 0)
3640 #define BALANCE_POWER_MASK		GENMASK(15, 8)
3641 #define BALANCE_PERFORMANCE_MASK	GENMASK(23, 16)
3642 #define PERFORMANCE_MASK		GENMASK(31, 24)
3643 
3644 #define HWP_SET_EPP_VALUES(powersave, balance_power, balance_perf, performance) \
3645 	(FIELD_PREP_CONST(POWERSAVE_MASK, powersave) |\
3646 	 FIELD_PREP_CONST(BALANCE_POWER_MASK, balance_power) |\
3647 	 FIELD_PREP_CONST(BALANCE_PERFORMANCE_MASK, balance_perf) |\
3648 	 FIELD_PREP_CONST(PERFORMANCE_MASK, performance))
3649 
3650 #define HWP_SET_DEF_BALANCE_PERF_EPP(balance_perf) \
3651 	(HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE, HWP_EPP_BALANCE_POWERSAVE,\
3652 	 balance_perf, HWP_EPP_PERFORMANCE))
3653 
3654 static const struct x86_cpu_id intel_epp_default[] = {
3655 	/*
3656 	 * Set EPP value as 102, this is the max suggested EPP
3657 	 * which can result in one core turbo frequency for
3658 	 * AlderLake Mobile CPUs.
3659 	 */
3660 	X86_MATCH_VFM(INTEL_ALDERLAKE_L, HWP_SET_DEF_BALANCE_PERF_EPP(102)),
3661 	X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3662 	X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3663 	X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3664 	X86_MATCH_VFM(INTEL_GRANITERAPIDS_D, HWP_SET_DEF_BALANCE_PERF_EPP(32)),
3665 	X86_MATCH_VFM(INTEL_METEORLAKE_L, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3666 		      179, 64, 16)),
3667 	X86_MATCH_VFM(INTEL_ARROWLAKE, HWP_SET_EPP_VALUES(HWP_EPP_POWERSAVE,
3668 		      179, 64, 16)),
3669 	{}
3670 };
3671 
3672 static const struct x86_cpu_id intel_hybrid_scaling_factor[] = {
3673 	X86_MATCH_VFM(INTEL_ALDERLAKE, HYBRID_SCALING_FACTOR_ADL),
3674 	X86_MATCH_VFM(INTEL_ALDERLAKE_L, HYBRID_SCALING_FACTOR_ADL),
3675 	X86_MATCH_VFM(INTEL_RAPTORLAKE, HYBRID_SCALING_FACTOR_ADL),
3676 	X86_MATCH_VFM(INTEL_RAPTORLAKE_P, HYBRID_SCALING_FACTOR_ADL),
3677 	X86_MATCH_VFM(INTEL_RAPTORLAKE_S, HYBRID_SCALING_FACTOR_ADL),
3678 	X86_MATCH_VFM(INTEL_METEORLAKE_L, HYBRID_SCALING_FACTOR_MTL),
3679 	X86_MATCH_VFM(INTEL_LUNARLAKE_M, HYBRID_SCALING_FACTOR_LNL),
3680 	{}
3681 };
3682 
intel_pstate_init(void)3683 static int __init intel_pstate_init(void)
3684 {
3685 	static struct cpudata **_all_cpu_data;
3686 	const struct x86_cpu_id *id;
3687 	int rc;
3688 
3689 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3690 		return -ENODEV;
3691 
3692 	/*
3693 	 * The Intel pstate driver will be ignored if the platform
3694 	 * firmware has its own power management modes.
3695 	 */
3696 	if (intel_pstate_platform_pwr_mgmt_exists()) {
3697 		pr_info("P-states controlled by the platform\n");
3698 		return -ENODEV;
3699 	}
3700 
3701 	id = x86_match_cpu(hwp_support_ids);
3702 	if (id) {
3703 		hwp_forced = intel_pstate_hwp_is_enabled();
3704 
3705 		if (hwp_forced)
3706 			pr_info("HWP enabled by BIOS\n");
3707 		else if (no_load)
3708 			return -ENODEV;
3709 
3710 		copy_cpu_funcs(&core_funcs);
3711 		/*
3712 		 * Avoid enabling HWP for processors without EPP support,
3713 		 * because that means incomplete HWP implementation which is a
3714 		 * corner case and supporting it is generally problematic.
3715 		 *
3716 		 * If HWP is enabled already, though, there is no choice but to
3717 		 * deal with it.
3718 		 */
3719 		if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3720 			hwp_active = true;
3721 			hwp_mode_bdw = id->driver_data;
3722 			intel_pstate.attr = hwp_cpufreq_attrs;
3723 			intel_cpufreq.attr = hwp_cpufreq_attrs;
3724 			intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3725 			intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3726 			if (!default_driver)
3727 				default_driver = &intel_pstate;
3728 
3729 			pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3730 
3731 			goto hwp_cpu_matched;
3732 		}
3733 		pr_info("HWP not enabled\n");
3734 	} else {
3735 		if (no_load)
3736 			return -ENODEV;
3737 
3738 		id = x86_match_cpu(intel_pstate_cpu_ids);
3739 		if (!id) {
3740 			pr_info("CPU model not supported\n");
3741 			return -ENODEV;
3742 		}
3743 
3744 		copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3745 	}
3746 
3747 	if (intel_pstate_msrs_not_valid()) {
3748 		pr_info("Invalid MSRs\n");
3749 		return -ENODEV;
3750 	}
3751 	/* Without HWP start in the passive mode. */
3752 	if (!default_driver)
3753 		default_driver = &intel_cpufreq;
3754 
3755 hwp_cpu_matched:
3756 	if (!hwp_active && hwp_only)
3757 		return -ENOTSUPP;
3758 
3759 	pr_info("Intel P-state driver initializing\n");
3760 
3761 	_all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3762 	if (!_all_cpu_data)
3763 		return -ENOMEM;
3764 
3765 	WRITE_ONCE(all_cpu_data, _all_cpu_data);
3766 
3767 	intel_pstate_request_control_from_smm();
3768 
3769 	intel_pstate_sysfs_expose_params();
3770 
3771 	if (hwp_active) {
3772 		const struct x86_cpu_id *id = x86_match_cpu(intel_epp_default);
3773 		const struct x86_cpu_id *hybrid_id = x86_match_cpu(intel_hybrid_scaling_factor);
3774 
3775 		if (id) {
3776 			epp_values[EPP_INDEX_POWERSAVE] =
3777 					FIELD_GET(POWERSAVE_MASK, id->driver_data);
3778 			epp_values[EPP_INDEX_BALANCE_POWERSAVE] =
3779 					FIELD_GET(BALANCE_POWER_MASK, id->driver_data);
3780 			epp_values[EPP_INDEX_BALANCE_PERFORMANCE] =
3781 					FIELD_GET(BALANCE_PERFORMANCE_MASK, id->driver_data);
3782 			epp_values[EPP_INDEX_PERFORMANCE] =
3783 					FIELD_GET(PERFORMANCE_MASK, id->driver_data);
3784 			pr_debug("Updated EPPs powersave:%x balanced power:%x balanced perf:%x performance:%x\n",
3785 				 epp_values[EPP_INDEX_POWERSAVE],
3786 				 epp_values[EPP_INDEX_BALANCE_POWERSAVE],
3787 				 epp_values[EPP_INDEX_BALANCE_PERFORMANCE],
3788 				 epp_values[EPP_INDEX_PERFORMANCE]);
3789 		}
3790 
3791 		if (hybrid_id) {
3792 			hybrid_scaling_factor = hybrid_id->driver_data;
3793 			pr_debug("hybrid scaling factor: %d\n", hybrid_scaling_factor);
3794 		}
3795 
3796 	}
3797 
3798 	mutex_lock(&intel_pstate_driver_lock);
3799 	rc = intel_pstate_register_driver(default_driver);
3800 	mutex_unlock(&intel_pstate_driver_lock);
3801 	if (rc) {
3802 		intel_pstate_sysfs_remove();
3803 		return rc;
3804 	}
3805 
3806 	if (hwp_active) {
3807 		const struct x86_cpu_id *id;
3808 
3809 		id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3810 		if (id) {
3811 			set_power_ctl_ee_state(false);
3812 			pr_info("Disabling energy efficiency optimization\n");
3813 		}
3814 
3815 		pr_info("HWP enabled\n");
3816 	} else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3817 		pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3818 	}
3819 
3820 	return 0;
3821 }
3822 device_initcall(intel_pstate_init);
3823 
intel_pstate_setup(char * str)3824 static int __init intel_pstate_setup(char *str)
3825 {
3826 	if (!str)
3827 		return -EINVAL;
3828 
3829 	if (!strcmp(str, "disable"))
3830 		no_load = 1;
3831 	else if (!strcmp(str, "active"))
3832 		default_driver = &intel_pstate;
3833 	else if (!strcmp(str, "passive"))
3834 		default_driver = &intel_cpufreq;
3835 
3836 	if (!strcmp(str, "no_hwp"))
3837 		no_hwp = 1;
3838 
3839 	if (!strcmp(str, "no_cas"))
3840 		no_cas = true;
3841 
3842 	if (!strcmp(str, "force"))
3843 		force_load = 1;
3844 	if (!strcmp(str, "hwp_only"))
3845 		hwp_only = 1;
3846 	if (!strcmp(str, "per_cpu_perf_limits"))
3847 		per_cpu_limits = true;
3848 
3849 #ifdef CONFIG_ACPI
3850 	if (!strcmp(str, "support_acpi_ppc"))
3851 		acpi_ppc = true;
3852 #endif
3853 
3854 	return 0;
3855 }
3856 early_param("intel_pstate", intel_pstate_setup);
3857 
3858 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3859 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3860